CY62157EV18LL-55BVXI [INFINEON]
Asynchronous SRAM;
| 型号： | CY62157EV18LL-55BVXI |
| 厂家： | 
Infineon |
| 描述： | Asynchronous SRAM 静态存储器 内存集成电路 |
| 文件： | 总22页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY62157EV18 MoBL
8-Mbit (512K × 16) Static RAM
8-bit (512K
x 16) Static RAM
consumption when addresses are not toggling. The device can
also be put into standby mode when deselected (CE1 HIGH or
CE2 LOW or both BHE and BLE are HIGH). The input and output
pins (I/O0 through I/O15) are placed in a high impedance state
when:
Features
■ Very high speed: 55 ns
■ Wide voltage range: 1.65 V–2.25 V
■ Pin compatible with CY62157DV18 and CY62157DV20
■ Deselected (CE1 HIGH or CE2 LOW)
■ Outputs are disabled (OE HIGH)
■ Ultra low standby power
❐ Typical Standby current: 2 A
❐ Maximum Standby current: 8 A
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH) or
■ Ultra low active power
❐ Typical active current: 6 mA at f = 1 MHz
■ Write operation is active (CE1 LOW, CE2 HIGH and WE LOW).
Write to the device by taking Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
■ Easy memory expansion with CE1, CE2 and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) package
Read from the device by taking Chip Enables (CE1 LOW and
CE2 HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
13 for a complete description of read and write modes.
Functional Description
The CY62157EV18 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
For a complete list of related documentation, click here.
Product Portfolio
Power Dissipation
Operating ICC, (mA)
VCC Range (V)
Speed
(ns)
Standby, ISB2 (A)
Product
f = fmax
f = 1MHz
Typ [1]
Typ [1]
Typ [1]
18
Typ [1]
Min
Max
Max
Max
Max
CY62157EV18
1.65
1.8
2.25
55
6
7
25
2
8
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Cypress Semiconductor Corporation
Document Number: 38-05490 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2020
CY62157EV18 MoBL
Logic Block Diagram
DATA IN DRIVERS
A
10
A
A
9
8
7
A
A
A
A
A
6
5
4
3
512K x 16
RAM Array
I/O –I/O
0
7
I/O –I/O
8
15
A
A
A
2
1
0
COLUMN DECODER
BHE
WE
CE
CE
2
1
OE
BLE
POWER DOWN
CIRCUIT
CE
CE
BHE
BLE
2
1
Document Number: 38-05490 Rev. *N
Page 2 of 21
CY62157EV18 MoBL
Contents
Pin Configuration .............................................................4
Maximum Ratings .............................................................5
Operating Range ...............................................................5
Electrical Characteristics .................................................5
Capacitance ......................................................................6
Thermal Resistance ..........................................................6
AC Test Loads and Waveforms .......................................6
Data Retention Characteristics .......................................7
Data Retention Waveform ................................................7
Switching Characteristics ................................................8
Switching Waveforms ......................................................9
Truth Table ......................................................................13
Ordering Information ......................................................14
Ordering Code Definitions .........................................14
Package Diagram ............................................................15
Acronyms ........................................................................16
Document Conventions .................................................16
Units of Measure .......................................................16
Document History Page .................................................17
Sales, Solutions, and Legal Information ......................21
Worldwide Sales and Design Support .......................21
Products ....................................................................21
PSoC® Solutions ......................................................21
Cypress Developer Community .................................21
Technical Support .....................................................21
Document Number: 38-05490 Rev. *N
Page 3 of 21
CY62157EV18 MoBL
Pin Configuration
Figure 1. 48-ball VFBGA pinout (Top View) [2]
1
2
3
4
5
6
A0
A2
A1
CE2
A
B
C
OE
BLE
A3
A5
A4
A6
CE1
I/O8 BHE
I/O0
I/O10
I/O11
I/O1 I/O2
I/O9
VSS
VCC
VCC
A7 I/O3
D
E
F
A17
A16 I/O4 VSS
I/O12 NC
A14
A15
I/O5 I/O6
I/O14 I/O13
A12 A13
I/O15
A18
NC
A8
I/O7
NC
WE
G
H
A9
A10 A11
Note
2. NC pins are not connected on the die.
Document Number: 38-05490 Rev. *N
Page 4 of 21
CY62157EV18 MoBL
DC input voltage [3, 4] ....... –0.2 V to 2.45 V (VCCmax + 0.2 V)
Output current into outputs (LOW) ............................. 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage (in accordance
with MIL-STD-883, Method 3015) ......................... > 2001 V
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Latch-up current ....................................................> 200 mA
Operating Range
Supply voltage
to ground potential ...........–0.2 V to 2.45 V (VCCmax + 0.2 V)
Ambient
Temperature
[5]
Device
Range
VCC
DC voltage applied to outputs
CY62157EV18LL Industrial –40 °C to +85 °C 1.65 V to
2.25 V
in High-Z state [3, 4] ..........–0.2 V to 2.45 V (VCCmax + 0.2 V)
Electrical Characteristics
Over the Operating Range
55 ns
Parameter
VOH
Description
Test Conditions
Unit
Typ [6]
Min
1.4
–
Max
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
IOH = –0.1 mA VCC = 1.65 V
–
–
V
V
VOL
VIH
VIL
IIX
IOL = 0.1 mA
VCC = 1.65 V
–
–
0.2
VCC = 1.65 V to 2.25 V
VCC = 1.65 V to 2.25 V
GND < VI < VCC
1.4
–0.2
–1
–1
–
VCC + 0.2 V
V
Input LOW voltage
–
0.4
+1
+1
25
7
V
Input leakage current
Output leakage current
VCC operating supply current
–
A
A
mA
mA
IOZ
ICC
GND < VO < VCC, output disabled
–
f = fmax = 1/tRC VCC = VCC(max)
,
18
6
IOUT = 0 mA
f = 1 MHz
–
CMOS levels
[7]
Automatic CE power down
current – CMOS inputs
CE1 > VCC0.2 V or
CE2 < 0.2 V,
–
2
2
8
A
ISB1
VIN > VCC – 0.2 V, VIN < 0.2 V),
f = fmax (address and data only),
V
f = 0 (OE, WE, BHE and BLE),
= VCC(max)
CC
.
[7]
Automatic CE power down
current – CMOS Inputs
CE1 > VCC – 0.2 V or
CE2 < 0.2 V,
–
8
A
ISB2
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
.
Notes
3.
V
= –2.0 V for pulse durations less than 20 ns.
IL(min)
4.
V
= V + 0.5 V for pulse durations less than 20 ns.
IH(max)
CC
5. Full Device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
7. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/I
/I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
Document Number: 38-05490 Rev. *N
Page 5 of 21
CY62157EV18 MoBL
Capacitance
Parameter [8]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [8]
Description
Test Conditions
BGA
Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
36.92
C/W
JC
Thermal resistance
(junction to case)
13.55
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
90%
VCC
OUTPUT
3V
10%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
RTH
V
Parameters
Value
13500
10800
6000
Unit
R1
R2
RTH
VTH
0.80
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05490 Rev. *N
Page 6 of 21
CY62157EV18 MoBL
Data Retention Characteristics
Over the Operating Range
Typ [9]
Parameter
VDR
Description
VCC for data retention
Data retention current
Conditions
Min
1.0
–
Max
–
Unit
V
–
[10]
1.2 V < VCC < VCC (max)
CE1 > VCC – 0.2 V,
CE2 < 0.2 V,
,
5
9
A
ICCDR
VIN > VCC – 0.2 V or VIN < 0.2 V
[11]
Chip deselect to data retention
time
0
–
–
–
–
ns
ns
tCDR
[12]
Operation recovery time
55
tR
Data Retention Waveform
Figure 3. Data Retention Waveform [13]
DATA RETENTION MODE
VCC(min)
VCC(min)
tCDR
> 1.0V
VDR
VCC
tR
CE1 or
BHE.BLE
or
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
10. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the I
/I
/I
spec. Other inputs can be left floating.
SB1 SB2 CCDR
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V ramp from V to V
> 100 s or stable at V > 100 s.
CC(min)
CC
DR
CC(min)
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
Document Number: 38-05490 Rev. *N
Page 7 of 21
CY62157EV18 MoBL
Switching Characteristics
Over the Operating Range
55 ns
Unit
]
Parameter [14,
Description
15
Min
Max
Read Cycle
tRC
Read cycle time
55
–
–
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to data valid
Data hold from address change
tOHA
tACE
10
–
CE1 LOW and CE2 HIGH to data valid
OE LOW to data valid
OE LOW to Low-Z [16]
55
25
–
–
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
–
OE HIGH to High-Z [16, 17]
18
–
CE1 LOW and CE2 HIGH to Low-Z [16]
CE1 HIGH and CE2 LOW to High-Z [16, 17]
CE1 LOW and CE2 HIGH to power up
CE1 HIGH and CE2 LOW to power down
BLE/BHE LOW to data valid
10
–
18
–
0
–
–
tPD
55
55
–
tDBE
[18]
tLZBE
BLE/BHE LOW to Low-Z [16]
BLE/BHE HIGH to High-Z [16, 17]
10
–
tHZBE
18
Write Cycle [19, 20]
tWC
Write cycle time
55
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
CE1 LOW and CE2 HIGH to write end
Address setup to write end
40
40
0
ns
ns
ns
ns
Address hold from write end
Address setup to write start
tSA
0
tPWE
tBW
tSD
WE pulse width
40
40
25
0
ns
ns
ns
ns
ns
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High-Z [16, 17]
WE HIGH to Low-Z [16]
tHD
–
tHZWE
tLZWE
20
–
10
ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the Figure 2 on page 6.
CC(typ)
OL OH
15. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip
enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application
Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has
been in production.
16. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any given
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
device.
17. t
, t
, t
, and t
transitions are measured when the output enters a high impedance state.
HZOE HZCE HZBE
HZWE
18. If both byte enables are toggled together, this value is 10 ns.
19. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a write
IL
IL
2
IH
and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
20. The minimum write cycle time for Write Cycle No. 3 (WE Controlled, OE LOW) is the sum of t
and t .
SD
HZWE
Document Number: 38-05490 Rev. *N
Page 8 of 21
CY62157EV18 MoBL
Switching Waveforms
Figure 4. Read Cycle 1 (Address Transition Controlled) [21, 22]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle 2 (OE Controlled) [22, 23]
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
21. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
IH
1
IL
IL
2
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document Number: 38-05490 Rev. *N
Page 9 of 21
CY62157EV18 MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle 1 (WE Controlled) [24, 25, 26]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 27
VALID DATA
tHZOE
Notes
24. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a
IL
IL
2
IH
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
25. Data I/O is high impedance if OE = V
.
IH
26. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
27. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05490 Rev. *N
Page 10 of 21
CY62157EV18 MoBL
Switching Waveforms (continued)
Figure 7. Write Cycle 2 (CE1 or CE2 Controlled) [28, 29, 30]
t
WC
ADDRESS
t
SCE
CE
CE
1
2
t
SA
t
t
HA
AW
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
DATA I/O
NOTE 31
VALID DATA
t
HZOE
Notes
28. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate a
IL
IL
2
IH
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
29. Data I/O is high impedance if OE = V
.
IH
30. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
31. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 38-05490 Rev. *N
Page 11 of 21
CY62157EV18 MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle 3 (WE Controlled, OE LOW) [32, 33]
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 34
DATA I/O
VALID DATA
tLZWE
tHZWE
Figure 9. Write Cycle 4 (BHE/BLE Controlled, OE LOW) [32]
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
NOTE 34
DATA I/O
VALID DATA
Notes
32. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
33. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
34. During this period, the I/Os are in output state and input signals must not be applied.
and t .
SD
HZWE
Document Number: 38-05490 Rev. *N
Page 12 of 21
CY62157EV18 MoBL
Truth Table
CE1
CE2
WE
OE
BHE
BLE
Inputs/Outputs
High-Z
Mode
Power
X[35]
L
X[35]
X[35]
H
X
X
Deselect/Power down
Deselect/Power down
Deselect/Power down
Read
Standby (ISB
)
)
)
X[35]
X[35]
H
X[35]
H
X
X
H
H
X
X
L
L
High-Z
Standby (ISB
Standby (ISB
X[35]
L
X[35]
H
High-Z
L
L
L
Data out (I/O0–I/O15
)
Active (ICC
Active (ICC
)
)
L
H
H
Data out (I/O0–I/O7);
High-Z (I/O8–I/O15
Read
)
L
H
H
L
L
H
High-Z (I/O0–I/O7);
Data out (I/O8–I/O15
Read
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High-Z
High-Z
High-Z
Output disabled
Output disabled
Output disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data in (I/O0–I/O15
Data in (I/O0–I/O7);
High-Z (I/O8–I/O15
)
L
H
Write
)
L
H
L
X
L
H
High-Z (I/O0–I/O7);
Data in (I/O8–I/O15
Write
Active (ICC
)
)
Note
35. The ‘X’ (Don’t care) state for the Chip enables and Byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 38-05490 Rev. *N
Page 13 of 21
CY62157EV18 MoBL
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
55
CY62157EV18LL-55BVXI 51-85150 48-ball VFBGA (Pb-free)
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
E
V18 LL - 55 BV
X
I
5
621
CY
7
Temperature Range: I = Industrial
Pb-free
Package Type: BV = 48-ball VFBGA
Speed Grade: 55 ns
Low Power
Voltage Range: V18 = 1.8 V typical
Process Technology: E = 90 nm Technology
Datawidth: 7 = × 16
Density: 5 = 8-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
Document Number: 38-05490 Rev. *N
Page 14 of 21
CY62157EV18 MoBL
Package Diagram
Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *I
Document Number: 38-05490 Rev. *N
Page 15 of 21
CY62157EV18 MoBL
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
BHE
BLE
Byte High Enable
Unit of Measure
Byte Low Enable
Chip Enable
°C
A
mA
MHz
ns
degrees Celsius
microampere
milliampere
megahertz
nanosecond
ohm
CE
CMOS
I/O
Complementary Metal Oxide Semiconductor
Input/Output
OE
Output Enable
SRAM
VFBGA
WE
Static Random Access Memory
Very Fine-Pitch Ball Grid Array
Write Enable
pF
V
picofarad
volt
W
watt
Document Number: 38-05490 Rev. *N
Page 16 of 21
CY62157EV18 MoBL
Document History Page
Document Title: CY62157EV18 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05490
Submission
Rev.
ECN No.
Description of Change
Date
**
202862
291272
01/27/2004 New data sheet.
*A
11/19/2004 Changed status from Advance Information to Preliminary.
Updated Features:
Updated description.
Updated Operating Range:
Updated Note 5 (Replaced “100 µs wait time” with “200 µs wait time”).
Updated Data Retention Characteristics:
Changed maximum value of ICCDR parameter from 4 µA to 4.5 µA.
Updated Switching Characteristics:
Changed minimum value of tOHA parameter from 6 ns to 10 ns corresponding to both 35 ns
and 45 ns speed bins.
Changed maximum value of tDOE parameter from 15 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE parameter from 12 ns to 15 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZOE parameter from 15 ns to 18 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZCE parameter from 12 ns to 18 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZCE parameter from 15 ns to 22 ns corresponding to 45 ns
speed bin.
Changed maximum value of tHZBE parameter from 12 ns to 15 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZBE parameter from 15 ns to 18 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSCE parameter from 25 ns to 30 ns corresponding to 35 ns
speed bin.
Changed minimum value of tSCE parameter from 40 ns to 35 ns corresponding to 45 ns
speed bin.
Changed minimum value of tAW parameter from 25 ns to 30 ns corresponding to 35 ns speed
bin.
Changed minimum value of tAW parameter from 40 ns to 35 ns corresponding to 45 ns speed
bin.
Changed minimum value of tBW parameter from 25 ns to 30 ns corresponding to 35 ns
speed bin.
Changed minimum value of tBW parameter from 40 ns to 35 ns corresponding to 45 ns
speed bin.
Changed minimum value of tSD parameter from 15 ns to 18 ns corresponding to 35 ns speed
bin.
Changed minimum value of tSD parameter from 20 ns to 22 ns corresponding to 45 ns speed
bin.
Changed maximum value of tHZWE parameter from 12 ns to 15 ns corresponding to 35 ns
speed bin.
Changed maximum value of tHZWE parameter from 15 ns to 18 ns corresponding to 45 ns
speed bin.
Updated Ordering Information:
Updated part numbers.
Document Number: 38-05490 Rev. *N
Page 17 of 21
CY62157EV18 MoBL
Document History Page (continued)
Document Title: CY62157EV18 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05490
Submission
Rev.
ECN No.
Description of Change
Date
*B
444306
04/13/2006 Changed status from Preliminary to Final.
Removed 35 ns Speed Bin related information in all instances across the document.
Removed “L” from the part numbers across the document.
Updated Pin Configuration:
Updated Figure 1 (Changed ball E3 from DNU to NC).
Removed Note “DNU pins have to be left floating or tied to Vss to ensure proper application.”
and its reference.
Updated Maximum Ratings:
Updated ratings corresponding to “Supply Voltage to Ground Potential”, “DC Voltage
Applied to Outputs in High Z State”, “DC Input Voltage” (Replaced “2.4 V” with “2.45 V”).
Updated Electrical Characteristics:
Changed typical value of ICC parameter from 16 mA to 18 mA corresponding to Test
Condition “f = fMAX = 1/tRC”.
Changed maximum value of ICC parameter from 28 mA to 25 mA corresponding to Test
Condition “f = fMAX = 1/tRC”.
Changed maximum value of ICC parameter from 2.3 mA to 3 mA corresponding to Test
Condition “f = 1 MHz”.
Changed typical value of ISB1 parameter from 0.9 µA to 2 µA.
Changed maximum value of ISB1 parameter from 4.5 µA to 8 µA.
Changed typical value of ISB2 parameter from 0.9 µA to 2 µA.
Changed maximum value of ISB2 parameter from 4.5 µA to 8 µA.
Updated Thermal Resistance:
Updated values of JA, JC parameters corresponding to BGA package.
Updated AC Test Loads and Waveforms:
Updated Figure 2 (Changed Test Load Capacitance from 50 pF to 30 pF).
Updated Data Retention Characteristics:
Added 1 µA as typical value for ICCDR parameter.
Changed maximum value of ICCDR parameter from 4.5 µA to 3 µA.
Changed minimum value of tR parameter from 100 µs to tRC ns.
Updated Switching Characteristics:
Changed minimum value of tLZOE parameter from 3 ns to 5 ns.
Changed minimum value of tLZCE parameter from 6 ns to 10 ns.
Changed maximum value of tHZCE parameter from 22 ns to 18 ns.
Changed minimum value of tLZBE parameter from 6 ns to 5 ns.
Changed minimum value of tPWE parameter from 30 ns to 35 ns.
Changed minimum value of tSD parameter from 22 ns to 25 ns.
Changed minimum value of tLZWE parameter from 6 ns to 10 ns.
Added Note 18 and referred the same note in tLZBE parameter.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
Updated Package Diagram:
spec 51-85150 – Changed revision from *B to *D.
Updated to new template.
*C
*D
571786
908120
12/01/2006 Removed 45 ns Speed Bin related information in all instances across the document.
Added 55 ns Speed Bin related information in all instances across the document.
Updated Ordering Information:
Updated part numbers.
04/04/2007 Updated Electrical Characteristics:
Added Note 7 and referred the same note in ISB2 parameter.
Updated Switching Characteristics:
Added Note 15 and referred the same note in “Parameter” column.
Document Number: 38-05490 Rev. *N
Page 18 of 21
CY62157EV18 MoBL
Document History Page (continued)
Document Title: CY62157EV18 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05490
Submission
Rev.
ECN No.
Description of Change
Date
06/03/2010 Updated Switching Characteristics:
Added Note 35 and referred the same note in “X” under CE1 and CE2 columns.
*E
2934396
Updated Package Diagram:
spec 51-85150 – Changed revision from *D to *E.
Updated to new template.
*F
3110053
12/14/2010 Changed Table Footnotes to Notes.
Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagram:
spec 51-85150 – Changed revision from *E to *F.
*G
*H
3243545
3295175
04/28/2011 Added Acronyms and Units of Measure.
Updated to new template.
Completing Sunset Review.
06/29/2011 Updated Electrical Characteristics:
Updated Note 7.
Referred Note 7 in ISB1 parameter.
Updated Data Retention Characteristics:
Added Note 10 and referred the same note in ICCDR parameter.
Updated Truth Table:
Updated Note 35.
*I
4102022
4384935
08/22/2013 Updated Switching Characteristics:
Updated Note 15.
Updated Package Diagram:
spec 51-85150 – Changed revision from *F to *H.
Updated to new template.
*J
05/20/2014 Updated Switching Characteristics:
Added Note 20 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 33 and referred the same note in Figure 8.
Completing Sunset Review.
*K
*L
4576526
5759379
11/21/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
06/01/2017 Updated Thermal Resistance values.
Updated to new template.
Completing Sunset Review.
*M
6819840
02/28/2020 Updated Features:
Updated description.
Updated Product Portfolio:
Updated all values of “Operating ICC” corresponding to “f = 1 MHz”.
Updated Electrical Characteristics:
Updated all values of ICC parameter corresponding to “55 ns” and “f = 1 MHz”.
Updated Thermal Resistance:
Updated values of JA, JC parameters corresponding to BGA package.
Updated Data Retention Characteristics:
Updated details in “Conditions” column and updated all values of
Updated Package Diagram:
parameter.
ICCDR
spec 51-85150 – Changed revision from *H to *I.
Updated to new template.
Document Number: 38-05490 Rev. *N
Page 19 of 21
CY62157EV18 MoBL
Document History Page (continued)
Document Title: CY62157EV18 MoBL, 8-Mbit (512K × 16) Static RAM
Document Number: 38-05490
Submission
Rev.
ECN No.
Description of Change
Date
11/13/2020 Updated Switching Characteristics:
Changed minimum value of tWC parameter from 45 ns to 55 ns.
*N
7023434
Changed minimum value of tSCE parameter from 35 ns to 40 ns.
Changed minimum value of tAW parameter from 35 ns to 40 ns.
Changed minimum value of tPWE parameter from 35 ns to 40 ns.
Changed minimum value of tBW parameter from 35 ns to 40 ns.
Changed maximum value of tHZWE parameter from 18 ns to 20 ns.
Document Number: 38-05490 Rev. *N
Page 20 of 21
CY62157EV18 MoBL
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Internet of Things
Memory
Technical Support
cypress.com/memory
cypress.com/mcu
cypress.com/support
Microcontrollers
PSoC
cypress.com/psoc
cypress.com/pmic
cypress.com/touch
cypress.com/usb
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004–2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries (“Cypress”). This document, including any software or
firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILLBE FREE FROM CORRUPTION,ATTACK, VIRUSES, INTERFERENCE, HACKING, DATALOSS OR THEFT, OR OTHER SECURITYINTRUSION (collectively, “Security
Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05490 Rev. *N
Revised November 13, 2020
Page 21 of 21
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor.
相关型号：
CY62157EV18LL-55BVXIT
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
©2020 ICPDF网 联系我们和版权申明