CY62157ELL-55BVXET [CYPRESS]
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| 型号： | CY62157ELL-55BVXET |
| 厂家： | 
CYPRESS |
| 描述： | 暂无描述 内存集成电路 静态存储器 |
| 文件： | 总12页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157E MoBL®
8-Mbit (512K x 16) Static RAM
also has an automatic power-down feature that significantly
reduces power consumption when addresses are not toggling.
The device can also be put into standby mode when
deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are
HIGH). The input/output pins (IO0 through IO15) are placed in
a high-impedance state when: deselected (CE1HIGH or CE2
LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
Features
• Very high speed: 45 ns
• Wide voltage range: 4.5V–5.5V
• Ultra-low standby power
—Typical Standby current: 2 µA
—Maximum Standby current: 8 µA (Industrial)
• Ultra-low active power
— Typical active current: 1.8 mA @ f = 1 MHz
• Ultra-low standby power
Writing to the device is accomplished by taking Chip Enable
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.
If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0
through IO7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from IO pins (IO8 through IO15) is written into
the location specified on the address pins (A0 through A18).
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP II and 48-ball VFBGA
package
Reading from the device is accomplished by taking Chip
Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE)
LOW while forcing the Write Enable (WE) HIGH. If Byte Low
Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on IO0 to IO7. If Byte
High Enable (BHE) is LOW, then data from memory will appear
on IO8 to IO15. See the truth table at the back of this data sheet
for a complete description of read and write modes.
Functional Description[1]
The CY62157E is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
Logic Block Diagram
DATA IN DRIVERS
A
10
A
A
9
8
7
A
A
A
A
A
6
5
4
3
512K x 16
RAM Array
IO –IO
0
7
IO –IO
8
15
A
A
A
2
1
0
COLUMN DECODER
BHE
WE
CE
CE
2
1
OE
BLE
POWER-DOWN
CIRCUIT
CE
CE
BHE
BLE
2
1
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05695 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 21, 2006
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CY62157E MoBL®
Pin Configuration[2, 3]
TSOP II
VFBGA
Top View
Top View
1
4
3
2
5
6
A
A
A
7
OE
BHE
BLE
IO
15
IO
A
1
2
3
4
5
6
7
8
44
5
6
4
A
43
42
41
40
39
38
37
3
A
A
A
2
CE2
OE
BLE
A
2
0
1
A
B
C
A
1
A
0
A
4
A
IO
BHE
CE1 IO
3
0
2
8
CE
IO
0
A
A
6
IO
IO
IO
IO
5
10
1
9
IO
1
14
IO
IO
9
IO
13
IO
36
35
34
33
32
31
30
29
28
27
26
25
24
23
2
Vcc
A
V
IO
IO
3
A17
NC
D
E
F
SS
7
10
11
12
13
14
15
16
17
18
19
20
21
22
11
3
12
V
V
SS
CC
V
SS
V
CC
IO
A
V
CC
IO
Vss
IO
IO
IO
16
12
4
5
IO
4
11
10
IO
5
IO
A
A
15
IO
IO
IO
14
13
IO
9
14
6
6
IO
IO
A
7
8
A
A
WE
A
G
H
8
IO
IO
NC
WE
13
12
15
7
A
9
18
A
A
10
17
A
A
A
A
A18
NC
10
9
11
8
A
A
16
11
A
15
A
12
A
14
A
13
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1MHz f = fmax
Speed
(ns)
Standby, ISB2
VCC Range (V)
(µA)
Product
CY62157E-45
CY62157E-55[5]
Range
Min
4.5
4.5
Typ[4]
Max
5.5
Typ[4]
Max
3
Typ[4]
Max
25
Typ[4]
Max
8
Ind’l
5.0
45
55
1.8
1.8
18
18
2
2
Auto
5.0
5.5
4
35
30
Notes:
2. NC pins are not connected on the die.
3. The 44-pin TSOP II package has only one chip enable (CE) pin.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ)
5. Automotive product information is Preliminary.
Document #: 38-05695 Rev. *C
Page 2 of 12
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CY62157E MoBL®
DC Input Voltage[6, 7]........................................–0.5V to 6.0V
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ..........................................> 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................–65°C to + 150°C
Latch-Up Current ...................................................> 200 mA
Ambient Temperature with
Power Applied ...........................................–55°C to + 125°C
Operating Range
Supply Voltage to Ground
Ambient
Temperature
Potential .......................................................... –0.5V to 6.0V
[8]
Device
Range
VCC
DC Voltage Applied to Outputs
CY62157E
Industrial –40°C to +85°C
Automotive –40°C to +125°C
4.5V to 5.5V
in High Z State[6, 7] ........................................... –0.5V to 6.0V
Electrical Characteristics (Over the Operating Range)
45 ns (Industrial)
55 ns (Automotive)
Parameter
Description
Test Conditions
Min Typ[4]
Max
Min Typ[4]
Max
Unit
VOH
Output HIGH
Voltage
IOH = –1 mA
VCC = 4.5V
IOL = 2.1 mA VCC = 4.5V
VCC = 4.5V to 5.5V
2.4
2.4
V
VOL
VIH
VIL
IIX
Output LOW
Voltage
0.4
0.4
VCC + 0.5
0.8
V
V
Input HIGH
Voltage
2.2
–0.5
–1
VCC + 0.5 2.2
Input LOW
Voltage
VCC = 4.5V to 5.5V
0.8
+1
+1
–0.5
–1
V
Input Leakage
Current
GND < VI < VCC
+1
µA
µA
IOZ
ICC
Output Leakage GND < VO < VCC, Output Disabled –1
Current
–1
+1
VCC Operating
Supply
Current
f = fmax = 1/tRC VCC = VCCmax
18
25
3
18
35
4
IOUT = 0 mA
CMOS levels
mA
f = 1 MHz
1.8
1.8
ISB1
Automatic CE
Power-Down
Current —
2
8
2
30
µA
CE1 > VCC − 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V, VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
CMOS Inputs
V
CC = 3.60V
CE1 > VCC – 0.2V or CE2 < 0.2V,
IN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
ISB2
Automatic CE
Power-Down
Current —
2
8
2
30
µA
V
CMOS Inputs
Capacitance[9]
Parameter
Description
Test Conditions
Max
10
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz, VCC = VCC(typ)
pF
pF
COUT
10
Notes:
6. V
7. V
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL(min)
= V + 0.75V for pulse durations less than 20 ns.
IH(max)
CC
8. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.
CC
CC
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05695 Rev. *C
Page 3 of 12
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CY62157E MoBL®
Thermal Resistance[9]
Parameter
Description
Test Conditions
TSOP II VFBGA Unit
ΘJA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
77
72
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
13
8.86
°C/W
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
VCC
OUTPUT
3V
90%
10%
10%
GND
Rise Time = 1 V/ns
R2
30 pF
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
OUTPUT
THEVENIN EQUIVALENT
RTH
V
Parameters
Values
1800
990
Unit
Ω
R1
R2
Ω
RTH
VTH
639
Ω
1.77
V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Description
Conditions
Min Typ[4] Max Unit
VCC for Data Retention
Data Retention Current
2
V
ICCDR
Industrial
8
µA
VCC=2V, CE1> VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
Automotive
30
[9]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[10]
tR
Operation Recovery Time
tRC
Data Retention Waveform[11]
DATA RETENTION MODE
VCC(min)
VCC(min)
V
DR
> 2 V
VCC
t
t
R
CDR
CE1or
BHE.BLE
CE2
Notes:
10. Full device operation requires linear V ramp from V to V
> 100 µs or stable at V
> 100 µs.
CC(min)
CC
DR
CC(min)
11. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05695 Rev. *C
Page 4 of 12
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CY62157E MoBL®
Switching Characteristics Over the Operating Range [12]
45 ns
55 ns
Parameter
Description
Min
45
Max
Min
55
Max
Unit
Read Cycle
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
55
tAA
Address to Data Valid
10
10
tOHA
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[13]
OE HIGH to High Z[13, 14]
CE1 LOW and CE2 HIGH to Low Z[13]
CE1 HIGH and CE2 LOW to High Z[13, 14]
CE1 LOW and CE2 HIGH to Power-Up
CE1 HIGH and CE2 LOW to Power-Down
BLE/BHE LOW to Data Valid
tACE
45
22
55
25
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
18
18
20
20
tPD
45
45
55
55
tDBE
tLZBE
tHZBE
Write Cycle[15]
BLE/BHE LOW to Low Z[13]
BLE/BHE HIGH to HIGH Z[13, 14]
10
45
10
55
18
20
tWC
tSCE
tAW
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
35
35
40
40
tHA
0
0
0
0
tSA
tPWE
tBW
35
35
25
0
40
40
25
0
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High-Z[13, 14]
WE HIGH to Low-Z[13]
tSD
tHD
tHZWE
tLZWE
18
20
10
10
Notes:
12. Test conditions for all parameters other than Tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse
CC(typ)
levels of 0 to V
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” section.
CC(typ)
OL OH
13. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
given device.
14. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
15. The internal Write time of the memory is defined by the overlap of WE, CE = V , BHE and/or BLE = V , and CE = V . All signals must be ACTIVE to initiate
1
IL
IL
2
IH
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
Document #: 38-05695 Rev. *C
Page 5 of 12
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CY62157E MoBL®
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATA VALID
DATA VALID
DATA OUT
Read Cycle 2 (OE Controlled)[17, 18]
ADDRESS
CE1
tRC
tPD
tHZCE
CE2
tACE
BHE/BLE
tDBE
tHZBE
tLZBE
OE
tHZOE
tDOE
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
tPU
50%
50%
ISB
Notes:
16. The device is continuously selected. OE, CE = V , BHE and/or BLE = V , and CE = V .
1
IL
IL
2
IH
17. WE is HIGH for read cycle.
18. Address valid prior to or coincident with CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document #: 38-05695 Rev. *C
Page 6 of 12
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CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[15, 19, 20, 21]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tSD
tHD
VALID DATA
IO
See Note 21
DATA
tHZOE
Write Cycle 2 (CE1 or CE2 Controlled)[15, 19, 20, 21]
tWC
ADDRESS
tSCE
CE
CE
1
2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
tHD
VALID DATA
See Note 21
DATA IO
tHZOE
Notes:
19. Data IO is high impedance if OE = V
.
IH
20. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high-impedance state.
1
2
IH
21. During this period, the IOs are in output state and input signals should not be applied.
Document #: 38-05695 Rev. *C
Page 7 of 12
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CY62157E MoBL®
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[20, 21]
tWC
ADDRESS
tSCE
CE1
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
DATA IO
See Note 21
VALID DATA
tLZWE
tHZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[20, 21]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
See Note 21
DATA IO
VALID DATA
Document #: 38-05695 Rev. *C
Page 8 of 12
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CY62157E MoBL®
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
Standby (ISB
Standby (ISB
Standby (ISB
)
)
)
X
L
X
X
X
X
High Z
X
X
X
X
H
H
High Z
L
H
H
L
L
L
Data Out (IO0–IO15
)
Active (ICC
Active (ICC
)
)
L
H
H
L
H
L
Data Out (IO0–IO7);
High Z (IO8–IO15
Read
)
L
H
H
L
L
H
High Z (IO0–IO7);
Data Out (IO8–IO15
Read
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (IO0–IO15)
L
H
Data In (IO0–IO7);
High Z (IO8–IO15)
Write
L
H
L
X
L
H
High Z (IO0–IO7);
Data In (IO8–IO15)
Write
Active (ICC
)
Ordering Information
Speed
Package
Diagram
Operating
Range
(ns)
Ordering Code
CY62157ELL-45ZSXI
CY62157ELL-55ZSXE
Package Type
45
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Industrial
55
Automotive
CY62157ELL-55BVXE 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)
Document #: 38-05695 Rev. *C
Page 9 of 12
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CY62157E MoBL®
Package Diagrams
44-pin TSOP II (51-85087)
51-85087-*A
Document #: 38-05695 Rev. *C
Page 10 of 12
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CY62157E MoBL®
Package Diagrams (continued)
48-ball VFBGA (6 x 8 x 1 mm) (51-85150)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
Ø0.30 0.05ꢀ(48X
A1 CORNER
1
2
3
(
5
6
6
5
(
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.475
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15ꢀ(8X
51-85150-*D
SEATING PLANE
C
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05695 Rev. *C
Page 11 of 12
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62157E MoBL®
Document History Page
Document Title: CY62157E MoBL®, 8-Mbit (512K x 16) Static RAM
Document Number: 38-05695
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
291273
457689
See ECN
See ECN
PCI
New data sheet
*A
NXR
Added Automotive Product
Removed Industrial Product
Removed 35 ns and 45 ns speed bins
Removed “L” bin
Updated AC Test Loads table
Corrected tR in Data Retention Characteristics from 100 µs to tRC ns
Updated the Ordering Information and replaced the Package Name column
with Package Diagram
*B
*C
467033
569114
See ECN
See ECN
NXR
VKN
Added Industrial Product (Final Information)
Removed 48 ball VFBGA package and its relevant information
Changed the ICC(typ) value of Automotive from 2 mA to 1.8 mA for f = 1MHz
Changed the ISB2(typ) value of Automotive from 5 µA to 1.8 µA
Modified footnote #4 to include current limit
Updated the Ordering Information table
Added 48 ball VFBGA package
Updated Logic Block Diagram
Added footnote #3
Updated the Ordering Information table
Document #: 38-05695 Rev. *C
Page 12 of 12
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相关型号：
CY62157EV18LL-45BVXI
512KX16 STANDARD SRAM, 45ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
ROCHESTER
CY62157EV18LL-45BVXIT
Standard SRAM, 512KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CYPRESS
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