CY62148VNLL-70ZSXI [CYPRESS]
4 Mbit (512K x 8) Static RAM; 4兆位（ 512K ×8）静态RAM
| 型号： | CY62148VNLL-70ZSXI |
| 厂家： | 
CYPRESS |
| 描述： | 4 Mbit (512K x 8) Static RAM |
| 文件： | 总10页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62148VN MoBL®
4 Mbit (512K x 8) Static RAM
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can be put into standby mode when deselected (CE
HIGH).
Features
■ Wide Voltage Range: 2.7V to 3.6V
■ Ultra Low Active Power
■ Low Standby Power
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O0 through I/O7) is then written into the location specified on
the address pins (A0 through A18).
■ TTL-compatible Inputs and Outputs
■ Automatic Power Down when deselected
■ CMOS for optimum Speed and Power
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
■ Package available in a 32-Pin TSOP II and a 32-Pin SOIC
Package
The eight input/output pins (I/O0 through I/O7) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW and WE LOW).
Functional Description
The CY62148VN is a high performance CMOS static RAM
organized as 512K words by eight bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL) in portable
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
Data in Drivers
1
2
3
4
5
A
0
A
1
A
2
A
3
A
4
A
512K x 8
ARRAY
5
A
6
A
A
A
7
8
9
6
7
POWER
DOWN
COLUMN
DECODER
CE
I/O
WE
OE
Cypress Semiconductor Corporation
Document Number : 001-55636 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 6, 2010
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CY62148VN MoBL®
Pin Configuration
Figure 1. 32-Pin TSOP II/SOIC (Top View)
A
A
V
A
A
WE
A
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
32
31
30
29
1
17
CC
16
2
3
4
5
6
15
A
14
18
A
12
A
A
A
A
A
A
A
A
28
27
26
25
7
6
5
13
8
7
9
11
4
3
8
24
23
9
2
10
11
12
13
10
22
21
20
19
18
17
1
0
0
7
I/O
6
5
I/O
I/O
V
1
2
14
15
4
I/O
SS 16
3
Product Portfolio
Power Dissipation
VCC Range (V)
Typ[1]
Operating ICC, (mA)
Standby ISB2, (A)
Speed
(ns)
Product
Min
Max
Typ[1]
Max
Typ[1]
Max
CY62148VNLL
2.7
3.0
3.6
70
7
15
2
20
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25°C.
A
CC
CC(typ.)
Document Number : 001-55636 Rev. *A
Page 2 of 10
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CY62148VN MoBL®
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied .............................................. 55°C to +125°C
Operating Range
Supply Voltage to Ground Potential................–0.5V to +4.6V
Range
Ambient Temperature
VCC
DC Voltage Applied to Outputs
Industrial
–40°C to +85°C
2.7V to 3.6V
in High-Z State[2]....................................–0.5V to VCC + 0.5V
Electrical Characteristics
Over the Operating Range
CY62148VN-70
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min.
Typ.[1]
Max.
Unit
V
IOH = –1.0 mA
IOL = 2.1 mA
VCC = 2.7V
VCC = 2.7V
VCC = 3.6V
2.4
VOL
0.4
V
VIH
2.2
VCC
+
V
0.5V
VIL
IIX
Input LOW Voltage
Input Load Current
VCC = 2.7V
–0.5
–1
0.8
+1
+1
15
V
GND < VI < VCC
+1
+1
7
A
A
mA
IOZ
ICC
Output Leakage Current GND < VO < VCC, Output Disabled
–1
VCC Operating Supply
Current
IOUT = 0 mA, f = fMAX = 1/tRC
CMOS Levels
VCC = 3.6V
IOUT = 0 mA, f = 1 MHz CMOS Levels
1
2
2
mA
ISB1
Automatic CE
Power down Current—
CE > VCC 0.3V, VIN > VCC 0.3V or VIN < 0.3V,
f = fMAX
20
A
CMOS Inputs
ISB2
Automatic CE
Power down Current—
CMOS Inputs
CE > VCC 0.3V
VIN > VCC 0.3V
or VIN < 0.3V, f = 0
VCC = 3.6V
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
Max
6
Unit
pF
VCC = 3.0V
COUT
8
pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
TSOP II
SOIC
Unit
JA
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
four-layer printed circuit board
TBD
TBD
C/W
JC
Thermal Resistance
(Junction to Case)
TBD
TBD
C/W
Note
2.
V
= –2.0V for pulse durations less than 20 ns.
IL(min.)
Document Number : 001-55636 Rev. *A
Page 3 of 10
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CY62148VN MoBL®
Figure 2. AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
VCC TYP
GND
OUTPUT
90%
10%
90%
10%
R2
50 pF
Fall time: 1V/ns
Rise time: 1V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
Rth
OUTPUT
Vth
Parameters
3.0V
1105
1550
645
Unit
R1
R2
V
RTH
VTH
1.75V
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
Conditions
Min.
Typ.[1] Max. Unit
VCC for Data Retention
Data Retention Current
1.0
3.6
5.5
V
VCC = 1.0V, CE > VCC 0.3V, VIN > VCC 0.3V or
VIN < 0.3V; No input may exceed VCC + 0.3V
0.2
A
[3]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[4]
tR
Operation Recovery Time
tRC
Figure 3. Data Retention Waveform
DATA RETENTION MODE
1.0V
1.0V
V
DR
> 1.0 V
V
CC
t
t
R
CDR
CE
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. Full-device AC operation requires linear V ramp from V to V
> 10 s or stable at V
> 10 s.
CC
DR
CC(min.)
CC(min.)
Document Number : 001-55636 Rev. *A
Page 4 of 10
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CY62148VN MoBL®
Switching Characteristics
Over the Operating Range[5]
70 ns
Parameter
Description
Unit
Min
70
Max
Read Cycle
tRC
Read Cycle Time
ns
tAA
Address to Data Valid
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOHA
Data Hold from Address Change
CE LOW to Data Valid
10
tACE
70
35
tDOE
OE LOW to Data Valid
6
tLZOE
OE LOW to Low Z[ ]
5
10
0
7
tHZOE
OE HIGH to High Z[ ]
25
25
70
6
tLZCE
CE LOW and to Low Z[ ]
6, 7
]
tHZCE
CE HIGH to High Z[
tPU
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH and CE2 LOW to Power Down
tPD
Write Cycle[8, 9]
tWC
Write Cycle Time
70
ns
tSCE
tAW
tHA
tSA
tPWE
tSD
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
60
60
ns
ns
Address Hold from Write End
Address Setup to Write Start
0
0
ns
ns
WE Pulse Width
50
30
0
ns
ns
ns
Data Setup to Write End
tHD
Data Hold from Write End
6, 7
6
]
tHZWE
tLZWE
WE LOW to High Z[
WE HIGH to Low Z[ ]
25
ns
ns
10
Notes
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
, and output loading of the specified
CC(typ.)
I
/I and 30 pF load capacitance.
OL OH
6. At any given temperature and voltage condition, t
is less than t
, t
is less than t
, and t
is less than t
for any given device.
HZCE
LZCE HZOE
LZOE
HZWE
LZWE
7.
t
, t
, and t
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
HZOE HZCE
HZWE L
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
and t
.
HZWE
SD
Document Number : 001-55636 Rev. *A
Page 5 of 10
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CY62148VN MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1: Address Transition Controlled [10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [11, 12]
t
RC
CE
OE
t
ACE
t
t
HZOE
t
DOE
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
VCC
SUPPLY
CURRENT
ICC
ISB
50%
50%
Figure 6. Write Cycle No 1: WE Controlled [8, 13, 14]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
SD
t
HD
DATA VALID
DATA I/O
NOTE15
IN
t
HZOE
Notes
10. The device is continuously selected. OE, CE = V
11. WE is HIGH for read cycle.
.
IL
12. Address valid before or similar to CE transition LOW.
13. Data I/O is high impedance if OE = V
.
IH
14. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
Document Number : 001-55636 Rev. *A
Page 6 of 10
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CY62148VN MoBL®
Switching Waveforms (continued)
Figure 7. Write Cycle 2: CE Controlled [8, 13, 14]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
AW
HA
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Figure 8. Write Cycle 3: WE controlled, OE LOW [14]
t
WC
ADDRESS
CE
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 15
IN
t
t
LZWE
HZWE
Note
15. During this period, the I/Os are in output state. Do not apply input signals.
Document Number : 001-55636 Rev. *A
Page 7 of 10
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CY62148VN MoBL®
Typical DC and AC Characteristics
Standby Current vs. Supply Voltage
45
Normalized Operating Current
vs. Supply Voltage
1.4
1.2
40
35
30
25
1.0
0.8
0.6
20
0.4
15
10
0.2
0.0
1.0
3.7
2.8
1.9
SUPPLY VOLTAGE (V)
1.7
2.2
2.7
3.2
3.7
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
70
60
50
40
30
20
10
1.0
3.7
2.8
1.9
SUPPLY VOLTAGE (V)
Truth Table
CE
H
L
WE
X
OE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Active (ICC
Active (ICC
Active (ICC
High-Z
Deselect/Power down
Read
)
H
L
Data Out
Data In
High-Z
)
L
L
X
Write
)
L
H
H
Output Disabled
)
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
70
CY62148VNLL-70ZSXI
51-85095 32-Pin TSOP II
Industrial
Document Number : 001-55636 Rev. *A
Page 8 of 10
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CY62148VN MoBL®
Package Diagrams
Figure 9. 32-Pin TSOP II, 51-85095
51-85095 *A
Document Number : 001-55636 Rev. *A
Page 9 of 10
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CY62148VN MoBL®
Document History Page
Document Title: CY62148VN MoBL®, 4 Mbit (512K x 8) Static RAM
Document Number: 001-55636
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
**
2761558
2905443
VKN
09/09/2009 New data sheet
*A
VKN
06/04/2010 Removed inactive part CY62148VNLL-70SXI from ordering information.
Updated Package Diagrams.
Sales, Solutions, and Legal Information
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closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number : 001-55636 Rev. *A
Revised April 6, 2010
Page 10 of 10
MoBL is aregisteredtrademark andMore Battery Lifeis atrademark of Cypress Semiconductor. All product andcompany names mentioned in this document are the trademarks of their respective holders.
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