CY62156ESL [CYPRESS]
8-Mbit (512 K x 16) Static RAM; 8兆位（ 512K的×16 ）静态RAM
| 型号： | CY62156ESL |
| 厂家： | 
CYPRESS |
| 描述： | 8-Mbit (512 K x 16) Static RAM |
| 文件： | 总16页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62156ESL MoBL®
8-Mbit (512 K × 16) Static RAM
8-Mbit (512
K × 16) Static RAM
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
in standby mode when deselected (CE1 HIGH or CE2 LOW). The
input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or
a write operation is active (CE1 LOW, CE2 HIGH and WE LOW).
Features
■ High Speed: 45 ns
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■ Ultra Low Standby Power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A
■ Ultra Low Active Power
❐ Typical active current: 1.8 mA at f = 1 MHz
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
■ Easy Memory Expansion with CE1, CE2, and OE Features
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Available in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) packages
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
11 for a complete description of read and write modes.
Functional Description
The CY62156ESL is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
512 K × 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-54995 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2013
CY62156ESL MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................11
Ordering Information ......................................................12
Ordering Code Definitions .........................................12
Package Diagrams ..........................................................13
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................16
Worldwide Sales and Design Support .......................16
Products ....................................................................16
PSoC Solutions .........................................................16
Document Number: 001-54995 Rev. *D
Page 2 of 16
CY62156ESL MoBL®
Pin Configurations
Figure 1. 48-ball VFBGA pinout (Top View) [1]
1
2
3
4
5
6
A2
CE2
A0
A3
A5
A1
A4
A6
BLE OE
A
B
C
I/O8
I/O0
I/O2
CE1
I/O1
BHE
I/O9
I/O10
V
I/O11 A17
D
V
A7
I/O3
I/O4
I/O5
CC
SS
V
SS
I/O12
NC
A16
A15
A13
A10
V
CC
E
F
I/O14 I/O13
I/O6
I/O7
NC
A14
A12
A9
G
H
I/O15
A18
NC
A8
WE
A11
Product Portfolio
Power Dissipation
Operating ICC, (mA)
f = 1MHz f = fmax
Speed
(ns)
Standby, ISB2
Product
Range
VCC Range (V) [2]
(A)
Typ [3] Max Typ [3] Max Typ [3] Max
CY62156ESL
Industrial 2.2 V to 3.6 V and 4.5 V to 5.5 V
45
1.8
3
18
25
2
8
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for V in the range of 3.6 V to 4.5 V.
CC
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
Document Number: 001-54995 Rev. *D
Page 3 of 16
CY62156ESL MoBL®
Output Current into Outputs (LOW) ............................ 20 mA
Maximum Ratings
Static Discharge Voltage
(MIL-STD-883, Method 3015) .................................> 2,001V
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Latch Up Current ...................................................> 200 mA
Storage Temperature ............................... –65 °C to + 150°C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Operating Range
Ambient
[6]
Supply Voltage to Ground Potential ...............–0.5 V to 6.0 V
Device
Range
VCC
Temperature
DC Voltage Applied to Outputs
CY62156ESL
Industrial –40 °C to +85 °C 2.2Vto3.6V,
in High Z State [4, 5] ........................................–0.5 V to 6.0 V
and
4.5 V to 5.5 V
DC Input Voltage [4, 5] ....................................–0.5 V to 6.0 V
Electrical Characteristics
Over the Operating Range
45 ns
Unit
Parameter
VOH
Description
Test Conditions
Min
2.0
2.4
2.4
–
Typ [1]
Max
Output HIGH Voltage
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
2.2 < VCC < 2.7
2.7 < VCC < 3.6
4.5 < VCC < 5.5
GND < VI < VCC
IOH = –0.1 mA
IOH = –1.0 mA
IOH = –1.0 mA
IOL = 0.1 mA
IOL = 2.1mA
IOL = 2.1mA
–
–
–
V
V
V
V
–
–
–
VOL
VIH
VIL
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
–
0.4
–
–
0.4
–
–
0.4
1.8
2.2
2.2
–0.3
–0.3
–0.5
–1
–
VCC + 0.3
VCC + 0.3
VCC + 0.5
0.6
–
–
–
–
0.8
–
0.8
IIX
Input Leakage Current
–
+1
A
A
IOZ
ICC
Output Leakage Current
VCC Operating Supply Current
GND < VO < VCC, Output Disabled
–1
–
+1
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
OUT = 0 mA,
CMOS levels
,
–
18
1.8
25
mA
I
–
3
ISB1
ISB2
Notes
Automatic CE Power down
Current – CMOS Inputs
–
–
2
2
8
8
A
A
CE1 > VCC 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = VCC(max)
[7]
Automatic CE Power down
Current – CMOS Inputs
CE1 > VCC – 0.2 V or CE < 0.2 V
,
2
V
IN > VCC – 0.2 V or VIN < 0.2 V,
V
=
f = 0, VCC
CC(max)
4. V (min) = –2.0 V for pulse durations less than 20 ns.
IL
5.
V (max) = V + 0.75 V for pulse durations less than 20 ns.
IH CC
6. Full Device AC operation assumes a 100 s ramp time from 0 to V (min) and 200 s wait time after V stabilization.
CC
CC
7. Only chip enables (CE and CE ) need to be tied to CMOS levels to meet the I
/ I
spec. Other inputs can be left floating.
1
2
SB2 CCDR
Document Number: 001-54995 Rev. *D
Page 4 of 16
CY62156ESL MoBL®
Capacitance
Parameter [8]
Description
Input capacitance
Output capacitance
Test Conditions
Max
10
Unit
pF
CIN
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
COUT
10
pF
Thermal Resistance
Parameter [8]
Description
Test Conditions
48-ball BGA Unit
JA
Thermal resistance
(junction to ambient)
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
72
C/W
JC
Thermal resistance
(junction to case)
8.86
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
90%
90%
VCC
OUTPUT
10%
10%
Fall Time = 1 V/ns
GND
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
VTH
Parameters
2.5 V
16667
15385
8000
3.0 V
1103
1554
645
5.0 V
Unit
R1
R2
1800
990
RTH
VTH
639
1.20
1.75
1.77
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-54995 Rev. *D
Page 5 of 16
CY62156ESL MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min
1.5
–
Typ [9]
Max
–
Unit
V
–
2
[10]
CE1 > VCC – 0.2 V, CE < 0.2 V
5
A
,
VIN > VCC – 0.2 V or VI2N < 0.2 V,
VCC = 1.5 V
[11]
tCDR
Chip Deselect to Data Retention
Time
0
–
–
–
–
ns
ns
[12]
tR
Operation Recovery Time
45
Data Retention Waveform
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC(min)
VCC(min)
tCDR
> 1.5 V
VDR
VCC
CE1
tR
or
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V
, T = 25 °C.
A
CC
CC(typ)
10. Only chip enables (CE and CE ) need to be tied to CMOS levels to meet the I / I spec. Other inputs can be left floating.
1
2
SB2 CCDR
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear V ramp from V to V
> 100 s or stable at V
> 100 s.
CC
DR
CC(min)
CC(min)
Document Number: 001-54995 Rev. *D
Page 6 of 16
CY62156ESL MoBL®
Switching Characteristics
Over the Operating Range
45 ns
Unit
Parameter [13]
Description
Min
Max
Read Cycle
tRC
Read Cycle Time
45
–
–
45
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
10
–
tACE
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[14]
45
22
–
–
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
–
OE HIGH to High Z[14, 15]
18
–
CE1 LOW and CE2 HIGH to Low Z[14]
CE1 HIGH and CE2 LOW to High Z[14, 15]
CE1 LOW and CE2 HIGH to Power Up
CE1 HIGH and CE2 LOW to Power Down
BLE/BHE LOW to Data Valid
10
–
18
–
0
–
–
tPD
45
22
–
tDBE
tLZBE
tHZBE
Write Cycle[16]
tWC
BLE/BHE LOW to Low Z[14]
BLE/BHE HIGH to High Z[14, 15]
5
–
18
Write Cycle Time
45
–
–
–
–
–
–
–
–
–
ns
tSCE
tAW
tHA
tSA
CE1 LOW and CE2 HIGH to Write End
Address Setup to Write End
35
35
ns
ns
Address Hold from Write End
Address Setup to Write Start
0
0
ns
ns
tPWE
tBW
tSD
WE Pulse Width
35
35
25
0
ns
ns
ns
ns
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
tHD
WE LOW to High Z[14, 15]
WE HIGH to Low Z[14]
18
–
ns
ns
–
tHZWE
tLZWE
10
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of V
/2, input pulse levels
CC(typ)
of 0 to V
, and output loading of the specified I /I as shown in the Figure 2 on page 5.
CC(typ)
OL OH
14. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
LZWE
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
15. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
16. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be active to initiate a write
1
IL
IL
2
IH
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates
the write.
Document Number: 001-54995 Rev. *D
Page 7 of 16
CY62156ESL MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1: Address Transition Controlled [17, 18]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [18, 19]
ADDRESS
tRC
CE1
CE2
tPD
t
HZCE
tACE
BHE/BLE
OE
tDBE
tHZBE
tLZBE
tHZOE
tDOE
tLZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
VCC
SUPPLY
CURRENT
DATA VALID
tLZCE
ICC
ISB
tPU
50%
50%
Notes
17. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V , and CE = V .
IH
1
IL
IL
2
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE , BHE, BLE transition LOW and CE transition HIGH.
1
2
Document Number: 001-54995 Rev. *D
Page 8 of 16
CY62156ESL MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled [20, 21, 22]
tWC
ADDRESS
CE1
tSCE
CE2
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
NOTE 23
DATA I/O
VALID DATA
tHZOE
Figure 7. Write Cycle 2: CE Controlled [20, 21, 22]
tWC
ADDRESS
CE1
tSCE
CE2
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 23
VALID DATA
tHZOE
Notes
20. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V , and CE = V . All signals must be active to initiate a write
1
IL
IL
2
IH
and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the
write.
21. Data I/O is high impedance if OE = V
.
IH
22. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
23. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-54995 Rev. *D
Page 9 of 16
CY62156ESL MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE controlled, OE LOW [24]
tWC
ADDRESS
CE1
tSCE
CE2
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
tHD
NOTE 25
DATA I/O
VALID DATA
tLZWE
tHZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [24]
tWC
ADDRESS
CE1
CE2
tSCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
NOTE 25
DATA I/O
VALID DATA
Notes
24. If CE goes HIGH and CE goes LOW simultaneously with WE = V , the output remains in a high impedance state.
1
2
IH
25. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-54995 Rev. *D
Page 10 of 16
CY62156ESL MoBL®
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
Deselect/Power Down
Deselect/Power Down
Output Disabled
Read
Standby (ISB
)
)
X
L
X
X
X
X
High Z
Standby (ISB
L
H
X
X
H
H
High Z
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
High Z (I/O8–I/O15
Read
)
L
H
H
L
L
H
High Z (I/O0–I/O7);
Data Out (I/O8–I/O15
Read
Active (ICC
)
)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
High Z
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
)
)
L
Data In (I/O0–I/O15)
L
H
Data In (I/O0–I/O7);
High Z (I/O8–I/O15)
Write
L
H
L
X
L
H
High Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write
Active (ICC
)
Document Number: 001-54995 Rev. *D
Page 11 of 16
CY62156ESL MoBL®
Ordering Information
Speed
Package
Diagram
Operating
Range
Ordering Code
(ns)
Package Type
45
CY62156ESL-45BVXI
51-85150 48-ball VFBGA (Pb-free)
Industrial
Ordering Code Definitions
-
SL
45 BV
X
I
5
621
E
CY
6
Temperature Range:
I = Industrial
Pb-free
Package Type:
BV = 48-ball VFBGA
Speed Grade: 45 ns
Low Power
Process Technology: E = 90 nm
Buswidth: 6 = × 16
Density: 5 = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document Number: 001-54995 Rev. *D
Page 12 of 16
CY62156ESL MoBL®
Package Diagrams
Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-54995 Rev. *D
Page 13 of 16
CY62156ESL MoBL®
Acronyms
Document Conventions
Units of Measure
Symbol
Acronym
Description
CE
chip enable
Unit of Measure
CMOS
I/O
complementary metal oxide semiconductor
input/output
°C
MHz
µA
µs
mA
mm
ns
degree Celsius
megahertz
microampere
microsecond
milliampere
millimeter
nanosecond
ohm
OE
output enable
RAM
SRAM
VFBGA
WE
random access memory
static random access memory
very fine-pitch ball grid array
write enable
%
percent
pF
V
picofarad
volt
W
watt
Document Number: 001-54995 Rev. *D
Page 14 of 16
CY62156ESL MoBL®
Document History Page
Document Title: CY62156ESL MoBL®, 8-Mbit (512 K × 16) Static RAM
Document Number: 001-54995
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
2751673
2899866
VKN
AJU
08/13/09
03/26/10
New data sheet
*A
Removed inactive parts from Ordering Information.
Updated Package Diagram
*B
*C
3109032
3903222
AJU
AJU
12/13/2010 Obsolete document.
02/19/2013 Changed from Obsolete to Active.
Removed all references of TSOP packages across the document and added
48-ball VFBGA package related information in the corresponding places.
Updated Features.
Updated Functional Description.
Updated Logic Block Diagram.
Updated Ordering Information (Updated part numbers) and added Ordering
Code Definitions.
Updated Package Diagrams:
Removed spec 51-85087 and spec 51-85183.
Added spec 51-85150.
Added Acronyms and Units of Measure.
Updated in new template.
*D
3996550
MEMJ
05/13/2013 Changed status from Preliminary to Final.
Document Number: 001-54995 Rev. *D
Page 15 of 16
CY62156ESL MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54995 Rev. *D
Revised May 13, 2013
Page 16 of 16
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective
holders.
相关型号：
CY62157CV25LL-55BAI
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
CY62157CV25LL-70BAIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
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