CY62157CV18LL-70BAI [CYPRESS]
512K x 16 Static RAM; 512K ×16静态RAM
| 型号： | CY62157CV18LL-70BAI |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 16 Static RAM |
| 文件： | 总11页 (文件大小：267K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157CV18 MoBL2™
512K x 16 Static RAM
The device can also be put into standby mode when deselect-
ed (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected (CE1 HIGH or CE2
LOW), outputs are disabled (OE HIGH), both Byte High Enable
and Byte Low Enable are disabled (BHE, BLE HIGH), or during
a write operation (CE1 LOW, CE2 HIGH and WE LOW).
Features
• High Speed
— 55 ns and 70 ns availability
• Low voltage range:
— CY62157CV18: 1.65V–1.95V
• Ultra-low active power
Writing to the device is accomplished by taking Chip Enables
(CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs
LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins
(I/O0 through I/O7), is written into the location specified on the
address pins (A0 through A18). If Byte High Enable (BHE) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A18).
— Typical Active Current: 0.5 mA @ f = 1 MHz
— Typical Active Current: 4 mA @ f = fmax (70 ns speed)
• Low standby power
• Easy memory expansion with CE1, CE2 and OEfeatures
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip En-
able (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW
while forcing the Write Enable (WE) HIGH. If Byte Low Enable
(BLE) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory will appear on
I/O8 to I/O15. See the truth table at the back of this datasheet
for a complete description of read and write modes.
Functional Description
The CY62157CV18 is a high-performance CMOS static RAM
organized as 512K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that significantly reduces
power consumption by 99% when addresses are not toggling.
The CY62157CV18 is available in a 48-ball FBGA package.
Logic Block Diagram
DATA IN DRIVERS
A
A
10
9
A
A
A
8
7
6
512K x 16
A
A
A
5
4
3
2
RAM Array
2048 X 4096
I/O –I/O
0
7
I/O –I/O
8
15
A
A
A
1
0
COLUMN DECODER
BHE
WE
CE2
CE1
OE
BLE
Power -Down
Circuit
CE2
CE1
BHE
BLE
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05012 Rev. *C
Revised October 31, 2001
CY62157CV18 MoBL2™
Pin Configuration[1, 2]
FBGA
Top View
1
2
4
3
5
6
A
A
A
2
CE
OE
BLE
0
1
2
A
B
C
A
A
I/O BHE
CE
I/O
I/O
0
3
4
8
1
A
A
6
I/O
I/O
2
I/O
5
10
1
9
Vccq
Vssq
A
V
I/O
I/O
3
A
D
E
F
SS
7
11
17
DNU
A
16
V
CC
I/O
I/O
12
4
A
A
15
I/O
I/O
5
I/O
I/O
6
14
13
14
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
8
A
NC
10
11
18
DC Voltage Applied to Outputs
Maximum Ratings
in High Z State[3.............................................]–0.2V to VCC + 0.2V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V
Output Current into Outputs (LOW)............................. 20 mA
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Latch-Up Current .....................................................>200 mA
Supply Voltage to Ground Potential............... –0.2V to +2.4V
Operating Range
Device
Range
Ambient Temperature
VCC
CY62157CV18
Industrial
–40°C to +85°C
1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC
)
VCC Range
f = 1 MHz
f = fmax
Standby (ISB2)
Product
Min.
1.65V
Typ.[4]
Max.
Speed
55 ns
70 ns
Typ.[4]
Max.
3 mA
3 mA
Typ.[4]
Max.
15 mA
12 mA
Typ.[4]
Max.
CY62157CV18
1.8V
1.95V
0.5 mA
0.5 mA
5 mA
4 mA
1.5 µA
20 µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. IL(min.) = –2.0V for pulse durations less than 20 ns.
V
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05012 Rev. *C
Page 2 of 11
CY62157CV18 MoBL2™
Electrical Characteristics Over the Operating Range
CY62157CV18-55
CY62157CV18-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
IOH = –0.1 mA
IOL = 0.1 mA
VCC = 1.65V
VCC = 1.65V
1.4
1.4
1.4
V
V
V
VOL
0.2
0.2
VIH
VCC
1.4
VCC
+0.2V
+0.2V
VIL
IIX
Input LOW Voltage
–0.2
–1
0.4
+1
+1
–0.2
–1
0.4
+1
+1
V
Input Leakage Current GND < VI < VCC
µA
µA
IOZ
Output Leakage
Current
GND <VO<VCC,Output Disabled –1
–1
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 1.95V
IOUT = 0 mA
CMOS levels
5
15
3
4
12
3
mA
mA
ICC
0.5
0.5
Automatic CE
CE1 > VCC − 0.2V, CE2< 0.2V
1.5
20
1.5
20
µA
Power-DownCurrent— VIN > VCC – 0.2V, VIN < 0.2V)
ISB1
CMOS Inputs
f =fMAX(Address andDataOnly),
f = 0 (OE, WE, BHE, and BLE)
Automatic CE
CE1 > VCC – 0.2V or CE2 < 0.2V,
ISB2
Power-DownCurrent— VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs f = 0, VCC = 1.95V
Capacitance[5]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
6
8
COUT
pF
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Unit
Thermal Resistance
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
ΘJA
55
°C/W
(Junction to Ambient)[5]
Thermal Resistance
(Junction to Case)[5]
ΘJC
16
°C/W
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05012 Rev. *C
Page 3 of 11
CY62157CV18 MoBL2™
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
OUTPUT
V
Typ
CC
90%
10%
10%
R2
30 pF
GND
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
1.8V
Unit
R1
13500
10800
6000
0.80
Ohms
Ohms
R2
RTH
VTH
Ohms
Volts
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[4]
Max.
Unit
V
1.0
1.95
10
VCC= 1.0V
CE1 > VCC – 0.2V, CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
1
µA
[5]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[6]
tR
Operation Recovery Time
tRC
Data Retention Waveform[7]
DATA RETENTION MODE
V
, min.
V
DR
> 1.0 V
V
CC
V
, min.
CC
CC
t
t
R
CDR
CE or
1
BHE,BLE
or
CE
2
Notes:
6. Full Device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us or stable at VCC(min.) > 100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05012 Rev. *C
Page 4 of 11
CY62157CV18 MoBL2™
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
READ CYCLE
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[9]
OE HIGH to High Z[9, 10]
CE1 LOW and CE2 HIGH to Low Z[9]
CE1 HIGH and CE2 LOW to High Z[9, 10]
CE1 LOW and CE2 HIGH to Power-Up
CE1 HIGH and CE2 LOW to Power-Down
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[9]
10
10
55
25
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
20
20
25
25
tPD
55
55
70
70
tDBE
tLZBE
tHZBE
WRITE CYCLE[11]
tWC
5
5
BLE / BHE HIGH to HIGH Z[9, 10]
20
25
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
tBW
45
45
25
0
50
60
30
0
BLE / BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[9, 10]
WE HIGH to Low Z[9]
tSD
tHD
tHZWE
20
25
tLZWE
5
10
Notes:
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device
10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the write.
Document #: 38-05012 Rev. *C
Page 5 of 11
CY62157CV18 MoBL2™
Switching Waveforms
Read Cycle No. 1 (Address Transition controlled)[12, 13]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE controlled)[13, 14]
ADDRESS
t
RC
CE
1
t
PD
t
HZCE
CE
2
t
ACE
BHE/BLE
t
DBE
t
HZBE
t
LZBE
OE
t
HZOE
t
DOE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
12. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH
.
13. WE is HIGH for read cycle.
14. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05012 Rev. *C
Page 6 of 11
CY62157CV18 MoBL2™
Switching Waveforms (continued)
[11, 15, 16]
Write Cycle No. 1(WE Controlled)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATA
DATA I/O
VALID
IN
NOTE 17
t
HZOE
[11, 15, 16]
Write Cycle No. 2 (CE1 or CE2 Controlled)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
tSA
t
t
HA
AW
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATA
DATA I/O
IN
NOTE 17
t
HZOE
Notes:
15. Data I/O is high impedance if OE = VIH
.
16. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05012 Rev. *C
Page 7 of 11
CY62157CV18 MoBL2™
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[16]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 17
DATAI/O
DATA VALID
IN
t
LZWE
t
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [16]
t
WC
ADDRESS
CE
1
CE
2
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
t
t
HD
SD
DATA I/O
VALID
DATAIN
NOTE 17
Document #: 38-05012 Rev. *C
Page 8 of 11
CY62157CV18 MoBL2™
Typical DC and AC Characteristics
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C)
Standby Current vs. Supply Voltage
Operating Current vs. Supply Voltage
MoBL2
3.0
6.0
(f = f
, 55 ns)
max
MoBL2
2.5
2.0
5.0
4.0
3.0
(f = f
, 70 ns)
max
1.5
1.0
0.5
0
2.0
1.0
0.0
(f = 1 MHz)
1.80
1.65
1.95
1.65
1.80
SUPPLY VOLTAGE (V)
1.95
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
MoBL2
40
35
30
25
20
15
10
1.65
1.95
1.80
SUPPLY VOLTAGE (V)
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
High Z
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
)
X
L
X
X
X
X
High Z
)
X
X
X
X
H
H
High Z
)
L
H
H
L
L
L
Data Out (I/O0–I/O15)
)
L
H
H
L
H
L
Data Out (I/O0–I/O7);
Read
)
High Z
High Z
(I/O8–I/O15)
(I/O0–I/O7);
L
H
H
L
L
H
Read
Active (ICC)
Data Out (I/O8–I/O15)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
H
L
L
L
L
High Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
High Z
)
High Z
)
L
Data In (I/O0–I/O15)
)
L
H
Data In (I/O0–I/O7);
High Z
High Z
Write
)
(I/O8–I/O15)
(I/O0–I/O7);
L
H
L
X
L
H
Write
Active (ICC)
Data In (I/O8–I/O15)
Document #: 38-05012 Rev. *C
Page 9 of 11
CY62157CV18 MoBL2™
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
48-Ball Fine Pitch BGA
55
CY62157CV18LL-55BAI
CY62157CV18LL-70BAI
BA48F
Industrial
70
Package Diagram
48-Ball (6 mm x 10 mm x 1.2 mm) Fine Pitch BGA BA48F
51-85128-*A
Document #: 38-05012 Rev. *C
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62157CV18 MoBL2™
Document Title:CY62157CV18 MoBL2™ 512K x 16 Static RAM
Document Number: 38-05012
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106158
107242
109231
110574
Description of Change
04/06/01
07/31/01
08/31/01
11/02/01
MGN
MGN
MGN
MGN
New Data Sheet, replaces CY62157BV18.
Changing from Preliminary to Final.
*A
*B
Add comment on front page about Active Current at different frequencies.
*C
Improved tDOE from 35 ns to 25 ns (@55 ns). Added Typical DC & AC
Characteristics. Format standardization
Document #: 38-05012 Rev. *C
Page 11 of 11
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