CY62157CV25 [CYPRESS]
512K x 16 Static RAM; 512K ×16静态RAM
| 型号： | CY62157CV25 |
| 厂家： | 
CYPRESS |
| 描述： | 512K x 16 Static RAM |
| 文件： | 总13页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157CV25/30/33
MoBL™
512K x 16 Static RAM
reducing power consumption by more than 99% when dese-
lected (CE1 HIGH or CE2 LOW or both BLE and BHE are
HIGH). The input/output pins (I/O0 through I/O15) are placed
in a high-impedance state when: deselected (CE1 HIGH or
CE2 LOW), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE1 LOW and CE2 HIGH and WE
LOW).
Features
• High speed
— 55 ns and 70 ns availability
• Voltage range:
— CY62157CV25: 2.2V–2.7V
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O0 through I/O7), is written into the location speci-
fied on the address pins (A0 through A18). If Byte High Enable
(BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is
written into the location specified on the address pins (A0
through A18).
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)
• Low standby power
• Easy memory expansion with CE1, CE2 and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable
2 (CE2) HIGH while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O0 to
I/O7. If Byte High Enable (BHE) is LOW, then data from mem-
ory will appear on I/O8 to I/O15. See the truth table at the back
of this data sheet for a complete description of read and write
modes.
Functional Description
The CY62157CV25/30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This is ideal for providing More Battery Life™ (MoBL™)
in portable applications such as cellular telephones. The de-
vices also have an automatic power-down feature that signifi-
cantly reduces power consumption by 80% when addresses
are not toggling. The device can also be put into standby mode
The CY62157CV25/30/33 are available in a 48-ball FBGA
package.
Logic Block Diagram
DATA IN DRIVERS
A
A
A
A
A
A
A
A
A
10
9
8
7
6
512K × 16
5
4
3
2
RAM Array
2048 × 4096
I/O –I/O
0
7
I/O –I/O
8
15
A
A
1
0
COLUMN DECODER
BHE
WE
CE
2
CE
1
OE
BLE
Power-down
Circuit
CE
2
BHE
BLE
CE
1
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05014 Rev. *C
Revised April 23, 2002
CY62157CV25/30/33
MoBL™
Pin Configurations[1, 2]
FBGA (Top View)
1
2
3
4
5
6
CE
A
A
A
OE
2
BLE
0
1
2
A
B
C
A
A
I/O BHE
8
CE
I/O
I/O
0
4
3
1
A
A
6
I/O I/O
I/O
2
5
10
1
9
V
A
V
I/O
I/O
3
A
CC
D
E
F
SS
7
11
17
V
SS
A
V
CC
I/O
DNU
I/O
16
12
4
A
A
15
I/O
I/O
5
I/O
I/O
14
13
14
6
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
A
NC
10
11
8
18
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Operating Range
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Temperature
Device
Range
VCC
Supply Voltage to Ground Potential...–0.5V to Vccmax + 0.5V
CY62157CV25 Industrial –40°Cto+85°C 2.2V to 2.7V
DC Voltage Applied to Outputs
CY62157CV30
CY62157CV33
2.7V to 3.3V
3.0V to 3.6V
in High-Z State[3]....................................–0.5V to VCC + 0.3V
DC Input Voltage[3].................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW) .............................20 mA
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC
f = 1 MHz f = fmax
Typ.[4] Max. Typ.[4] Max.
55 ns 1.5 mA 3 mA 7 mA 15 mA
70 ns 1.5 mA 3 mA 5.5 mA 12 mA
55 ns 1.5 mA 3 mA 7 mA 15 mA
70 ns 1.5 mA 3 mA 5.5 mA 12 mA
55 ns 1.5 mA 3 mA 7 mA 15 mA
70 ns 1.5 mA 3 mA 5.5 mA 12 mA
)
V
CC Range
Speed
Standby (ISB2
)
[4]
Product
VCC(min.) VCC(typ.)
VCC(max.)
Typ.[4]
Max.
25 µA
CY62157CV25
2.2V
2.7V
3.0V
2.5V
3.0V
3.3V
2.7V
6 µA
CY62157CV30
3.3V
3.6V
8 µA
25 µA
30 µA
CY62157CV33
10 µA
Notes:
1. NC pins are not connected to the die.
2. E3 (DNU) can be left as NC or VSS to ensure proper application.
3. IL(min.) = –2.0V for pulse durations less than 20 ns.
V
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Document #: 38-05014 Rev. *C
Page 2 of 13
CY62157CV25/30/33
MoBL™
Electrical Characteristics Over the Operating Range
CY62157CV25-55
CY62157CV25-70
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
IOH = –0.1 mA
VCC = 2.2V
VCC = 2.2V
2.0
2.0
V
V
V
VOL
VIH
IOL = 0.1 mA
0.4
0.4
1.8
VCC
+
1.8
VCC +
0.3V
0.3V
0.6
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
0.6 –0.3
V
Input Leakage Current
GND < VI < VCC
+1
+1
–1
–1
µA
µA
IOZ
Output Leakage Current GND < VO < VCC
Output Disabled
,
–1
+1
ICC
VCC Operating Supply
Current
f = fMAX = 1/tRC VCC = 2.7V
7
15
3
5.5
1.5
12
3
mA
IOUT = 0 mA
f = 1 MHz
1.5
CMOS Levels
ISB1
Automatic CE
Power-Down Current—
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
6
25
6
25
µA
CMOS Inputs
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE and BLE)
ISB2
Automatic CE
Power-Down Current—
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
CMOS Inputs
f = 0, VCC = 2.7V
CY62157CV30-55 CY62157CV30-70
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Parameter
VOH
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Test Conditions
IOH = –1.0 mA
VCC = 2.7V
VCC = 2.7V
2.4
2.4
V
V
V
VOL
IOL = 2.1 mA
0.4
0.4
VIH
2.2
VCC
+
2.2
VCC
+
0.3V
0.3V
VIL
IIX
Input LOW Voltage
–0.3
–1
0.8 –0.3
0.8
+1
+1
V
Input Leakage Current
Output Leakage Current
GND < VI < VCC
+1
+1
15
3
–1
–1
µA
µA
IOZ
ICC
GND < VO < VCC, Output Disabled
–1
VCC Operating Supply
Current
f = fMAX = 1/tRC
f = 1 MHz
VCC = 3.3V
IOUT = 0 mA
CMOS Levels
7
5.5
1.5
12 mA
3
1.5
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE and BLE)
8
25
8
25
µA
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.3V
Document #: 38-05014 Rev. *C
Page 3 of 13
CY62157CV25/30/33
MoBL™
CY62157CV33-55
CY62157CV33-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[4] Max. Min. Typ.[4] Max. Unit
Output HIGH Voltage IOH = –1.0 mA VCC = 3.0V
2.4
2.4
V
V
V
VOL
Output LOW Voltage IOL = 2.1 mA
Input HIGH Voltage
VCC = 3.0V
0.4
0.4
VIH
2.2
VCC
+
2.2
VCC +
0.3V
0.8
+1
0.3V
0.8
+1
VIL
IIX
Input LOW Voltage
–0.3
–1
–0.3
–1
V
Input Leakage
Current
GND < VI < VCC
µA
IOZ
ICC
Output Leakage
Current
GND < VO < VCC, Output Disabled –1
+1
–1
+1
µA
VCC Operating Supply f = fMAX = 1/tRC VCC = 3.6V
Current
7
15
3
5.5
1.5
12
3
mA
IOUT = 0 mA
f = 1 MHz
1.5
CMOS Levels
ISB1
Automatic CE
Power-Down
Current—CMOS
Inputs
CE1 > VCC – 0.2V or CE2 < 0.2V
IN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f = 0 (OE,WE,BHE,and BLE)
10
30
10
30
µA
V
ISB2
Automatic CE
Power-Down Cur-
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
rent—CMOS Inputs f = 0, VCC = 3.6V
Capacitance[5]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
Max.
Unit
CIN
6
8
pF
pF
COUT
Thermal Resistance
Description
Test Conditions
Symbol
BGA
Unit
Thermal Resistance
Still Air, soldered on a 3 x 4.5 inch, two-layer printed
circuit board
ΘJA
55
°C/W
(Junction to Ambient)[5]
Thermal Resistance
ΘJC
16
°C/W
(Junction to Case)[5]
Note:
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05014 Rev. *C
Page 4 of 13
CY62157CV25/30/33
MoBL™
AC Test Loads and Waveforms
R1
V
CC
ALL INPUT PULSES
90%
V
Typ
OUTPUT
CC
90%
10%
10%
GND
Rise TIme: 1 V/ns
R2
30 pF
Fall Time: 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
2.5V
16.6
15.4
8.0
3.0V
1.105
1.550
0.645
1.75
3.3V
Unit
R1
R2
1.216
1.374
0.645
1.75
K Ohms
K Ohms
K Ohms
Volts
RTH
VTH
1.20
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
Conditions
Min.
Typ.[4]
Max.
Unit
V
VCC for Data Retention
Data Retention Current
1.5
Vccmax
20
VCC = 1.5V
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
4
µA
[5]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
[6]
tR
Operation Recovery Time
tRC
Data Retention Waveform[7]
DATA RETENTION MODE
V
V
DR
> 1.5 V
V
CC
V
CC(min.)
CC(min.)
t
t
R
CDR
CE or
1
BHE.BLE
or
CE
2
Note:
6. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) >100 µs.
7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05014 Rev. *C
Page 5 of 13
CY62157CV25/30/33
MoBL™
Switching Characteristics Over the Operating Range[8]
55 ns
70 ns
Parameter
Read Cycle
Description
Min.
55
Max.
Min.
70
Max.
Unit
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
Data Hold from Address Change
CE1 LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[9]
OE HIGH to High-Z[9, 10]
CE1 LOW and CE2 HIGH to Low-Z[9]
CE1 HIGH or CE2 LOW to High-Z[9, 10]
CE1 LOW and CE2 HIGH to Power-up
CE1 HIGH or CE2 LOW to Power-down
BHE/BLE LOW to Data Valid
BHE/BLE LOW to Low-Z[9]
10
10
55
25
70
35
5
10
0
5
10
0
20
20
25
25
tPD
55
55
70
70
tDBE
[11]
tLZBE
tHZBE
Write Cycle[12]
tWC
5
5
BHE/BLE HIGH to High-Z[9, 10]
20
25
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
tAW
tHA
tSA
0
0
tPWE
tBW
45
50
25
0
50
60
30
0
BHE/BLE Pulse Width
tSD
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9, 10]
WE HIGH to Low-Z[9]
tHD
tHZWE
20
25
tLZWE
5
5
Notes:
8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of
the specified IOL/IOH and 30-pF load capacitance.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
10.
tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. When both byte enables are toggled together this value is 10 ns.
12. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate
a Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the
signal that terminates the Write.
Document #: 38-05014 Rev. *C
Page 6 of 13
CY62157CV25/30/33
MoBL™
C
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
[14, 15]
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
HZBE
BHE/BLE
t
LZBE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
I
t
CC
PU
V
CC
50%
50%
SUPPLY
CURRENT
I
SB
Notes:
13. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH
.
14. WE is HIGH for Read cycle.
15. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH.
Document #: 38-05014 Rev. *C
Page 7 of 13
CY62157CV25/30/33
MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[12, 16, 17]
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE18
t
HZOE
[12, 16, 17]
Write Cycle No. 2 (CE1 or CE2 Controlled)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
tSA
t
t
HA
AW
t
PWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
VALID
DATA
DATA I/O
IN
NOTE
18
t
HZOE
Notes:
16. Data I/O is high-impedance if OE = VIH
.
17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05014 Rev. *C
Page 8 of 13
CY62157CV25/30/33
MoBL™
Switching Waveforms (continued)
[17]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
t
SCE
CE
1
CE
2
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 18
DATAI/O
DATA VALID
IN
t
LZWE
t
HZWE
[17]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
1
CE
2
t
SCE
tAW
tHA
tBW
BHE/BLE
WE
tSA
tPWE
tSD
tHD
DATA I/O
VALID
DATAIN
NOTE 18
Document #: 38-05014 Rev. *C
Page 9 of 13
CY62157CV25/30/33
MoBL™
Typical DC and AC Characteristics
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.)
Operating Current vs. Supply Voltage
14.0
12.0
10.0
14.0
12.0
10.0
14.0
12.0
MoBL
MoBL
MoBL
10.0
(f = f
(f = f
, 55ns)
, 70ns)
max
(f = f
, 55ns)
8.0
6.0
4.0
8.0
6.0
4.0
(f = f
, 55ns)
, 70ns)
8.0
6.0
4.0
max
max
(f = f
, 70ns)
max
max
(f = f
max
2.0
0.0
2.0
0.0
2.0
0.0
(f = 1 MHz)
(f = 1 MHz)
(f = 1 MHz)
3.0
2.7
3.3
2.7
2.2
2.5
3.3
3.0
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0
12.0
10.0
12.0
10.0
MoBL
10.0
8.0
MoBL
MoBL
8.0
8.0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
6.0
4.0
2.0
0
3.3
3.6
3.0
2.2
3.3
2.7
3.0
2.5
2.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60
60
60
MoBL
MoBL
MoBL
50
40
30
50
40
30
50
40
30
20
20
20
10
0
10
0
10
0
3.6
3.0
3.3
2.2
2.5
2.7
3.0
2.7
3.3
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Document #: 38-05014 Rev. *C
Page 10 of 13
CY62157CV25/30/33
MoBL™
Truth Table
CE1
H
CE2
X
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High Z
Mode
Power
Standby (ISB
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
Deselect/Power-Down
Deselect/Power-Down
Deselect/Power-Down
Read
)
X
L
X
X
X
X
High Z
)
X
X
X
X
H
H
High Z
)
L
H
H
L
L
L
Data Out (I/OO–I/O15
)
)
L
H
H
L
H
L
Data Out (I/OO–I/O7); Read
I/O8–I/O15 in High Z
)
L
H
H
L
L
H
Data Out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
Active (ICC)
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
Output Disabled
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
High Z
Output Disabled
Output Disabled
Write
)
High Z
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
)
L
H
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
Document #: 38-05014 Rev. *C
Page 11 of 13
CY62157CV25/30/33
MoBL™
Ordering Information
Speed (ns)
Ordering Code
Package Name
Package Type
48-ball Fine-pitch BGA
Operating Range
70
CY62157CV25LL-70BAI
CY62157CV30LL-70BAI
CY62157CV33LL-70BAI
CY62157CV30LL-55BAI
CY62157CV33LL-55BAI
BA48F
Industrial
55
Package Diagram
48-Ball (6 mm x 10 mm x 1.2 mm) FBGA BA48F
51-85128-*B
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names
mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05014 Rev. *C
Page 12 of 13
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62157CV25/30/33
MoBL™
Document Title: CY62157CV25/30/33 MoBL™ 512K x 16 STATIC RAM
Document Number: 38-05014
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
106184
107241
Description of Change
05/10/01 HRT/MGN New Datasheet – Advance Information
*A
07/24/01
MGN
Make Corrections to Advance Information.
Added 55 ns bin.
*B
*C
109621
114218
03/11/02
05/01/02
MGN
Change from Advance Information to Final
Improved Typical & Max ICC values
GUG/
MGN
Document #: 38-05014 Rev. *C
Page 13 of 13
相关型号：
CY62157CV25LL-55BAI
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
CY62157CV25LL-70BAIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
CY62157CV30LL-55BAI
512KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
ROCHESTER
CY62157CV30LL-70BAI
512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
ROCHESTER
CY62157CV30LL-70BAIT
512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
ROCHESTER
CY62157CV30LL-70BAIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
©2020 ICPDF网 联系我们和版权申明