CY62157BV18LL-70BAI [CYPRESS]
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, FBGA-48;
| 型号： | CY62157BV18LL-70BAI |
| 厂家： | 
CYPRESS |
| 描述： | Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, FBGA-48 静态存储器 |
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
512K x 16 Static RAM
through I/O ) are placed in a high-impedance state when:
Features
15
deselected (CE HIGH), outputs are disabled (OE HIGH), BHE
and BLE are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
• Low voltage range:
— CY62157BV18LL: 1.65V–1.95V
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is
0
7
written into the location specified on the address pins (A
0
through A ). If Byte High Enable (BHE) is LOW, then data
18
from I/O pins (I/O through I/O ) is written into the location
8
15
specified on the address pins (A through A ).
0
18
Functional Description
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
The CY62157BV18LL is a high-performance CMOS static
RAM organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in por-
table applications such as cellular telephones. The device also
has an automatic power-down feature that significantly reduc-
es power consumption by 99% when addresses are not tog-
gling. The device can also be put into standby mode when
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,
0
7
then data from memory will appear on I/O to I/O . See the
8
15
truth table at the back of this datasheet for a complete descrip-
tion of read and write modes.
The CY62157BV18LL is available in a 48-Ball FBGA package.
deselected (CE HIGH, CS2 LOW). The input/output pins (I/O
0
Logic Block Diagram
DATA IN DRIVERS
A9
A8
A7
A6
A5
A4
A3
A2
256K x 16
RAM Array
1024 X 4096
I/O0 – I/O7
I/O8 – I/O15
A1
A0
COLUMN DECODER
BHE
WE
CEx
OE
BLE
CEx is the combination of CE and CS2
62157V–1
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
March 23, 2000
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
Pin Configuration[1]
FBGA
Top View
4
1
2
3
5
6
A
A
2
A
CS2
OE
BLE
0
1
A
B
C
A
A
I/O BHE
8
CE
I/O
I/O
0
4
3
A
A
I/O I/O
I/O
2
5
6
9
10
1
A
V
V
I/O
I/O
3
A17
CC
D
E
F
SS
7
11
A
V
CC
V
I/O
I/O
SS
V
SS
16
12
4
A
A
15
I/O
I/O
5
I/O
I/O
6
14
13
14
A
A
G
H
I/O
NC
WE
I/O
7
13
12
15
A
A
9
A
A
A18
NC
10
11
8
62146V–3
DC Voltage Applied to Outputs
in High Z State ................................... –0.5V to V + 0.5V
Maximum Ratings
[2]
CC
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
[2]
DC Input Voltage ................................. -0.5V to V + 0.5V
CC
Output Current into Outputs (LOW)............................. 20 mA
Storage Temperature .................................–65°C to +150°C
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Latch-Up Current.................................................... >200 mA
Supply Voltage to Ground Potential ............... –0.5V to +4.6V
Operating Range
Device
Range
Ambient Temperature
V
CC
CY62157BV18 Industrial
–40°C to +85°C
1.65V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
Operating (I Standby (I
Product
V
Range
Speed
)
)
SB2
CC
CC
[3]
[3]
[3]
Min.
1.65V
Typ.
Max.
Typ
7 mA
Maximum
Typ
2 µA
Maximum
CY62157BV18
1.8V
1.95V
55, 70 ns
15 mA
20 µA
Notes:
1. NC pins are not connected to the die.
2. IL(min.) = –2.0V for pulse durations less than 20 ns.
V
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
2
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
Electrical Characteristics Over the Operating Range
CY62157BV18
[3]
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min.
Typ.
Max.
Unit
V
V
I
I
= –0.1 mA
V
V
V
V
= 1.65V
= 1.65V
= 1.95V
= 1.65V
1.5
OH
OH
CC
CC
CC
CC
V
= 0.1 mA
0.2
V
OL
OL
V
V
1.4
–0.5
–1
V
+ 0.3V
CC
V
IH
IL
0.4
+1
+1
V
I
I
GND < V < V
CC
±1
+1
µA
µA
IX
I
GND < V < V , Output
–1
OZ
O
CC
Disabled
I
V
Operating Supply
I
= 0 mA,
V
= 1.95V
7
1
15
mA
CC
CC
OUT
CC
Current
f = f
CMOS levels
= 1/t
,
MAX
RC
I
= 0 mA, f = 1 MHz, CMOS
2
mA
OUT
Levels
I
I
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V – 0.3V,
100
µA
SB1
CC
V
V
> V – 0.3V or
IN
IN
CC
< 0.3V, f = f
MAX
Automatic CE
CE > V – 0.3V
V
= 1.95V
CC
2
20
µA
SB2
CC
Power-Down Current—
CMOS Inputs
V
> V – 0.3V
IN CC
or V < 0.3V, f = 0
IN
Capacitance[4]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
C
C
Input Capacitance
Output Capacitance
6
8
pF
pF
IN
A
V
= 1.8V
CC
OUT
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
3
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
AC Test Loads and Waveforms
R1
VCC
ALL INPUT PULSES
OUTPUT
VCC Typ
90%
10%
fall time: 1 V/ns
90%
10%
R2
30 pF
GND
rise time: 1 V/ns
INCLUDING
JIG AND
SCOPE
62157V–4
62157V–5
Equivalent to:
THÉVENIN EQUIVALENT
RTH
OUTPUT
V
Parameters
1.8V
15294
11300
6500
0.85
UNIT
Ohms
Ohms
Ohms
Volts
R1
R2
R
V
TH
TH
(Over the Operating Range)
Data Retention Characteristics
[3]
Parameter
Description
Conditions
Min.
Typ.
Max.
1.95
5
Unit
V
V
V
for Data Retention
CC
1.0
DR
I
Data Retention Current
V
= 1.0V
CC
µA
CCDR
CE > V – 0.3V,
CC
V
V
> V – 0.3V or
IN
CC
< 0.3V
IN
No input may exceed
+ 0.3V
V
CC
[4]
t
t
Chip Deselect to Data
Retention Time
0
ns
CDR
[5]
R
Operation Recovery Time
100
µs
Note:
5. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) >10 µs or stable at VCC(min.) > 10 µs.
Data Retention Waveform
DATA RETENTION MODE
VCC(min.)
V
DR
> 1.0 V
V
CC
VCC(min.)
CDR
t
t
R
CE
62157V–6
4
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
[6]
Switching Characteristics Over the Operating Range
55 ns
70 ns
Parameter
Description
Min.
55
Max.
Min.
70
Max.
Unit
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
55
70
AA
Data Hold from Address Change
CE LOW to Data Valid
10
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
55
25
70
35
OE LOW to Data Valid
[7, ]
OE LOW to Low Z
5
10
0
5
10
0
[8]
OE HIGH to High Z
20
20
25
25
[7]
CE LOW to Low Z
[7, 8]
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
55
55
70
70
PD
DBE
LZBE
HZBE
5
5
20
25
[9, 10]
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
55
40
40
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
CE LOW to Write End
SCE
AW
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
HA
0
0
SA
40
25
0
50
30
0
PWE
SD
Data Set-Up to Write End
Data Hold from Write End
HD
[7, 8]
WE LOW to High Z
20
25
HZWE
LZWE
[7]
WE HIGH to Low Z
5
10
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, tHZCE is less than tLZCE and tHZWE
is less than tLZWE for any given device.
8. tHZOE, tHZCE, tHZBE and tHZWE are specified for with CL=5 pF. Transition is measured ± 200 mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
5
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
Switching Waveforms[11]
[12, 13]
Read Cycle No. 1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
62157V–7
[13, 14]
Read Cycle No. 2
t
RC
CEx
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
ICC
CC
SUPPLY
CURRENT
50%
50%
ISB
62157V–8
Notes:
11. CEx is the combination of CE and CE2
12. Device is continuously selected. OE, CE = VIL
13. WE is HIGH for read cycle.
.
14. Address valid prior to or coincident with CE transition LOW.
6
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
Switching Waveforms[11]
(continued)
[9, 15, 16]
Write Cycle No. 1 (WE Controlled)
t
WC
ADDRESS
CEx
t
t
AW
HA
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
17
DATA VALID
IN
DATA I/O
NOTE
t
HZOE
62157V–9
[9, 15, 16]
Write Cycle No. 2 (CE Controlled)
t
WC
ADDRESS
CEx
t
SCE
t
SA
t
t
HA
AW
t
BW
BHE/BLE
WE
t
PWE
t
t
HD
SD
DATA I/O
DATA VALID
IN
62157V–10
Notes:
15. Data I/O is high impedance if OE = VIH
.
16. If CEgoes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
7
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
Switching Waveforms[11]
(continued)
[12, 16]
Write Cycle No. 3 (WE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
C62157V–11
[12,16]
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 17
IN
t
t
LZWE
HZWE
C62157V–11
8
CY62157BV18LL
MoBL2™
ADVANCE INFORMATION
Truth Table
CS2
L
CE
H
WE
X
OE
X
BHE
X
BLE
Inputs/Outputs
High Z
Data Out (I/O –I/O
Mode
Power
X
L
L
Deselect/Power-Down Standby (I
)
SB
H
L
H
L
L
)
Read
Read
Active (I
Active (I
)
CC
0
15
H
L
H
L
H
Data Out (I/O –I/O );
)
CC
0
7
I/O –I/O in High Z
8
15
H
L
H
L
L
H
Data Out (I/O –I/O );
Read
Active (I
)
CC
8
15
I/O –I/O in High Z
0
7
H
H
H
H
L
L
L
L
H
H
L
L
H
X
X
H
X
L
H
X
L
High Z
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
)
CC
High Z
)
CC
Data In (I/O –I/O
)
)
CC
0
15
L
H
L
Data In (I/O –I/O );
Write
)
CC
0
7
I/O –I/O in High Z
8
15
H
H
L
L
L
L
X
X
L
H
H
Data In (I/O –I/O );
Write
Active (I
Active (I
)
CC
8
15
I/O –I/O in High Z
0
7
H
High Z
Output Disabled
)
CC
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
Name
Package Type
48-Ball Fine Pitch BGA
55
CY62157BV18LL-55BAI
CY62157BV18LL-70BAI
TBD
70
Industrial
Document #: 38-00908
Package Diagram
TBD
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
CY62157CV25LL-55BAI
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
CY62157CV25LL-70BAIT
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CYPRESS
CY62157CV30LL-55BAI
512KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
ROCHESTER
©2020 ICPDF网 联系我们和版权申明