CY3674 [CYPRESS]
EZ-USB FX1⑩ USB Microcontroller Full-speed USB Peripheral Controller; EZ- USB FX1⑩ USB微控制器全速USB外设控制器型号: | CY3674 |
厂家: | CYPRESS |
描述: | EZ-USB FX1⑩ USB Microcontroller Full-speed USB Peripheral Controller |
文件: | 总50页 (文件大小:758K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C64713/14
EZ-USB FX1™ USB Microcontroller
Full-speed USB Peripheral Controller
—Supports multiple Ready (RDY) inputs and Control
(CTL) outputs
• Integrated, industry standard 8051 with enhanced
features
1.0
Features
• Single-chip integrated USB transceiver, SIE, and
enhanced 8051 microprocessor
• Fit, form and function upgradable to the FX2LP
(CY7C68013A)
—Up to 48-MHz clock rate
—Four clocks per instruction cycle
—Two USARTS
—Three counter/timers
—Expanded interrupt system
—Two data pointers
— Pin-compatible
— Object-code-compatible
— Functionally-compatible (FX1 functionality is a
Subset of the FX2LP)
• Draws no morethan65 mA in any mode making theFX1
suitable for bus powered applications
• 3.3V operation with 5V tolerant inputs
• Smart SIE
• Software: 8051 runs from internal RAM, which is:
— Downloaded via USB
— Loaded from EEPROM
— Externalmemorydevice(128-pinconfigurationonly)
• 16 KBytes of on-chip Code/Data RAM
• Vectored USB interrupts
• Separate data buffers for the Setup and DATA portions
of a CONTROL transfer
• Integrated I2C controller, runs at 100 or 400 KHz
• 48-MHz, 24-MHz, or 12-MHz 8051 operation
• Four integrated FIFOs
• Four programmable BULK/INTERRUPT/ISOCH-
RONOUS endpoints
—Brings glue and FIFOs inside for lower system cost
—Automatic conversion to and from 16-bit buses
—Master or slave operation
— Buffering options: double, triple, and quad
• Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
• 8- or 16-bit external data interface
• Smart Media Standard ECC generation
• GPIF
—FIFOs can use externally supplied clock or
asynchronous strobes
—Easy interface to ASIC and DSP ICs
• Vectored for FIFO and GPIF interrupts
• Up to 40 general purpose I/Os
— Allowsdirect connection to most parallel interfaces;
8- and 16-bit
• Three package options—128-pin TQFP, 100-pin TQFP,
and 56-pin QFN Lead-free
— Programmable waveform descriptors and configu-
ration registers to define waveforms
High-performance micro
using standard tools
24 MHz
Ext. XTAL
with lower-power options
FX1
I2C
/0.5
/1.0
/2.0
8051 Core
x20
Master
VCC
12/24/48 MHz,
four clocks/cycle
PLL
Abundant I/O
Additional I/Os (24)
1.5k
connected for
enumeration
including two USARTS
General
ADDR (9)
programmable I/F
to ASIC/DSP or bus
standards such as
D+
GPIF
USB
CY
16 KB
RAM
RDY (6)
CTL (6)
ATAPI, EPP, etc.
D–
ECC
Smart
XCVR
USB
Engine
Integrated
full-speed XCVR
Up to 96 MBytes/s
burst rate
4 kB
FIFO
8/16
Enhanced USB core
Simplifies 8051 code
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08039 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised February 14, 2005
CY7C64713/14
4.2
8051 Microprocessor
2.0
Functional Description
The 8051 microprocessor embedded in the FX1 family has
256 bytes of register RAM, an expanded interrupt system,
three timer/counters, and two USARTs.
EZ-USB FX1 (CY7C64713/4) is
a full-speed highly
integrated, USB microcontroller. By integrating the USB trans-
ceiver, serial interface engine (SIE), enhanced 8051 microcon-
troller, and a programmable peripheral interface in a single
chip, Cypress has created a very cost-effective solution that
provides superior time-to-market advantages.
4.2.1
8051 Clock Frequency
FX1 has an on-chip oscillator circuit that uses an external 24-
MHz (±100 ppm) crystal with the following characteristics:
Because it incorporates the USB transceiver, the EZ-USB FX1
is more economical, providing a smaller footprint solution than
USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application-specific functions and decreasing development
time to ensure USB compatibility.
• Parallel resonant
• Fundamental mode
• 500-µW drive level
• 12-pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to 480
MHz, as required by the transceiver/PHY, and internal
counters divide it down for use as the 8051 clock. The default
8051 clock frequency is 12 MHz. The clock frequency of the
8051 can be changed by the 8051 through the CPUCS
register, dynamically.
The General Programmable Interface (GPIF) and Master/
Slave Endpoint FIFO (8- or 16-bit data bus) provides an easy
and glueless interface to popular interfaces such as ATA,
UTOPIA, EPP, PCMCIA, and most DSP/processors.
Three lead-free packages are defined for the family: 56 QFN,
100 TQFP, and 128 TQFP.
The CLKOUT pin, which can be three-stated and inverted
using internal control bits, outputs the 50% duty cycle 8051
clock, at the selected 8051 clock frequency—48, 24, or 12
MHz.
3.0
Applications
• DSL modems
4.2.2
USARTS
• ATA interface
FX1 contains two standard 8051 USARTs, addressed via
Special Function Register (SFR) bits. The USART interface
pins are available on separate I/O pins, and are not multi-
plexed with port pins.
• Memory card readers
• Legacy conversion devices
• Home PNA
• Wireless LAN
UART0 and UART1 can operate using an internal clock at 230
KBaud with no more than 1% baud rate error. 230-KBaud
operation is achieved by an internally derived clock source that
generates overflow pulses at the appropriate time. The
internal clock adjusts for the 8051 clock rate (48, 24, 12 MHz)
such that it always presents the correct frequency for 230-
KBaud operation.[1]
• MP3 players
• Networking
The “Reference Designs” section of the cypress website
provides additional tools for typical USB applications. Each
reference design comes complete with firmware source and
object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
4.2.3
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are
shown in Table 4-1. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with “0”
and “8” contain bit-addressable registers. The four I/O ports
A–D use the SFR addresses used in the standard 8051 for
ports 0–3, which are not implemented in FX1. Because of the
faster and more efficient SFR addressing, the FX1 I/O ports
are not addressable in external RAM space (using the MOVX
instruction).
4.0
4.1
Functional Overview
USB Signaling Speed
FX1 operates at one of the three rates defined in the USB
Specification Revision 2.0, dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbps.
FX1 does not support the low-speed signaling mode of 1.5
Mbps or the high-speed mode of 480 Mbps.
24 MHz
C1
C2
12 pf
12 pf
20 × PLL
12-pF capacitor values assumes a trace
capacitance of 3 pF per side on a four-layer FR4 PCA
Figure 4-1. Crystal Configuration
Note:
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1, respectively.
Document #: 38-08039 Rev. *B
Page 2 of 50
CY7C64713/14
4.3
I2C Bus
4.4
Buses
FX1 supports the I2C bus as a master only at 100/400 KHz.
SCL and SDA pins have open-drain outputs and hysteresis
inputs. These signals must be pulled up to 3.3V, even if no I2C
device is connected.
All packages: 8- or 16-bit “FIFO” bidirectional data bus, multi-
plexed on I/O ports B and D. 128-pin package: adds 16-bit
output-only 8051 address bus, 8-bit bidirectional data bus.
Table 4-1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
9x
IOB
Ax
Bx
Cx
Dx
Ex
Fx
IOC
IOD
SCON1
SBUF1
PSW
ACC
B
SP
EXIF
INT2CLR
INT4CLR
IOE
DPL0
DPH0
DPL1
DPH1
DPS
MPAGE
OEA
OEB
OEC
OED
OEE
PCON
TCON
TMOD
TL0
SCON0
SBUF0
IE
IP
T2CON
EICON
EIE
EIP
AUTOPTRH1
AUTOPTRL1
reserved
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
EP01STAT
GPIFTRIG
RCAP2L
RCAP2H
TL2
TL1
TH0
TH1
AUTOPTRH2
AUTOPTRL2
reserved
GPIFSGLDATH
GPIFSGLDATLX
TH2
CKCON
AUTOPTRSETUP GPIFSGLDATLNOX
a device defined by the downloaded information. This
patented two-step process, called ReNumeration, happens
instantly when the device is plugged in, with no hint that the
initial download step has occurred.
4.5
USB Boot Methods
During the power-up sequence, internal logic checks the I2C
port for the connection of an EEPROM whose first byte is
either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values
in the EEPROM in place of the internally stored values (0xC0),
or it boot-loads the EEPROM contents into internal RAM
(0xC2). If no EEPROM is detected, FX1 enumerates using
internally stored descriptors. The default ID values for FX1 are
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).[2]
Two control bits in the USBCS (USB Control and Status)
register control the ReNumeration process: DISCON and
RENUM. To simulate a USB disconnect, the firmware sets
DISCON to 1. To reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM
bit to indicate whether the firmware or the Default USB Device
will handle device requests over endpoint zero: if RENUM = 0,
the Default USB Device will handle device requests; if RENUM
= 1, the firmware will.
Table 4-2. Default ID Values for FX1
Default VID/PID/DID
Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x6473 EZ-USB FX1
4.7
Bus-powered Applications
The FX1 fully supports bus-powered designs by enumerating
with less than 100 mA as required by the USB specification.
Device
release
0xAnnn Depends chip revision (nnn = chip
revision where first silicon = 001)
4.8
Interrupt System
4.6
ReNumeration™
4.8.1
INT2 Interrupt Request and Enable Registers
Because the FX1’s configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
FX1 implements an autovector feature for INT2 and INT4.
There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)
vectors. See EZ-USB Technical Reference Manual (TRM) for
more details.
When first plugged into USB, the FX1 enumerates automati-
cally and downloads firmware and USB descriptor tables over
the USB cable. Next, the FX1 enumerates again, this time as
Note:
2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Document #: 38-08039 Rev. *B
Page 3 of 50
CY7C64713/14
4.8.2
USB-Interrupt Autovectors
the high byte (“page”) of a jump-table address is preloaded at
location 0x0044, the automatically-inserted INT2VEC byte at
0x0045 will direct the jump to the correct address out of the 27
addresses within the page.
The main USB interrupt is shared by 27 interrupt sources. To
save the code and processing time that normally would be
required to identify the individual USB interrupt source, the
FX1 provides a second level of interrupt vectoring, called
Autovectoring. When a USB interrupt is asserted, the FX1
pushes the program counter onto its stack then jumps to
address 0x0043, where it expects to find a “jump” instruction
to the USB Interrupt service routine.
4.8.3
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB-
interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like
the USB Interrupt, can employ autovectoring. Table 4-4 shows
the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
The FX1 jump instruction is encoded as shown in Table 4-3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if
Table 4-3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Source
Priority
1
INT2VEC Value
Notes
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
SUDAV
SOF
Setup Data Available
Start of Frame
2
3
SUTOK
Setup Token Received
USB Suspend request
Bus reset
4
SUSPEND
5
USB RESET
6
reserved
7
EP0ACK
FX1 ACK’d the CONTROL Handshake
reserved
8
9
EP0-IN
EP0-OUT
EP1-IN
EP1-OUT
EP2
EP0-IN ready to be loaded with data
EP0-OUT has USB data
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EP1-IN ready to be loaded with data
EP1-OUT has USB data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN-Bulk-NAK (any IN endpoint)
reserved
EP4
EP6
EP8
IBN
EP0PING
EP1PING
EP2PING
EP4PING
EP6PING
EP8PING
ERRLIMIT
EP0 OUT was Pinged and it NAK’d
EP1 OUT was Pinged and it NAK’d
EP2 OUT was Pinged and it NAK’d
EP4 OUT was Pinged and it NAK’d
EP6 OUT was Pinged and it NAK’d
EP8 OUT was Pinged and it NAK’d
Bus errors exceeded the programmed limit
reserved
reserved
EP2ISOERR
EP4ISOERR
EP6ISOERR
EP8ISOERR
ISO EP2 OUT PID sequence error
ISO EP4 OUT PID sequence error
ISO EP6 OUT PID sequence error
ISO EP8 OUT PID sequence error
Document #: 38-08039 Rev. *B
Page 4 of 50
CY7C64713/14
Table 4-4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
EP6FF
Notes
1
2
80
84
88
8C
90
94
98
9C
A0
A4
A8
AC
B0
B4
Endpoint 2 Programmable Flag
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
3
4
5
6
7
8
9
10
11
12
13
14
Endpoint 4 Full Flag
Endpoint 6 Full Flag
EP8FF
GPIFDONE
GPIFWF
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX1 substitutes its INT4VEC byte. Therefore, if
the high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically-inserted INT4VEC byte at
0x0055 will direct the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack then jumps to
address 0x0053, where it expects to find a “jump” instruction
to the ISR Interrupt service routine.
4.9
Reset and Wakeup
4.9.1
Reset Pin
The input pin, RESET#, will reset the FX1 when asserted. This
pin has hysteresis and is active LOW. When a crystal is used
with the CY7C64713/4 the reset period must allow for the
stabilization of the crystal and the PLL. This reset period
should be approximately 5 ms after VCC has reached 3.0
Volts. If the crystal input pin is driven by a clock signal the
internal PLL stabilizes in 200 µs after VCC has reached
3.0V[3]. Figure 4-2 shows a power on reset condition and a
reset applied during operation. A power on reset is defined as
the time reset is asserted while power is being applied to the
circuit. A powered reset is defined to be when the FX1 has
previously been powered on and operating and the RESET#
pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and can be found
on the Cypress web site. While the application note discusses
the FX2, the information provided applies also to the FX1. For
more information on reset implementation for the FX2 family
of products visit the http://www.cypress.com.
Note:
3. If the external clock is powered at the same time as the CY7C64713/4 and has a stabilization wait period, it must be added to the 200 µs.
Document #: 38-08039 Rev. *B
Page 5 of 50
CY7C64713/14
RESET#
RESET#
VIL
VIL
3.3V
3.0V
3.3V
VCC
VCC
0V
0V
TRESET
TRESET
Power on Reset
Powered Reset
Figure 4-2. Reset Timing Plots
Table 4-5. Reset Timing Values
access it as both program and data memory. No USB control
registers appear in this space.
Condition
TRESET
Two memory maps are shown in the following diagrams:
Figure 4-3 Internal Code Memory, EA = 0
Power-On Reset with crystal
5 ms
Power-On Reset with external 200 µs + Clock stability time
clock
Figure 4-4 External Code Memory, EA = 1.
Powered Reset
200 µs
4.10.2 Internal Code Memory, EA = 0
This mode implements the internal 16-KByte block of RAM
(starting at 0) as combined code and data memory. When
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside
the chip. This allows the user to connect a 64-KByte memory
without requiring address decodes to keep clear of internal
memory spaces.
4.9.2 Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external logic, the oscil-
lator restarts, after the PLL stabilizes, and then the 8051
receives a wakeup interrupt. This applies whether or not FX1
is connected to the USB.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
The FX1 exits the power-down (USB suspend) state using one
of the following methods:
• USB download
• USB bus activity (if D+/D– lines are left floating, noise on
these lines may indicate activity to the FX1 and initiate a
wakeup).
• USB upload
• Setup data pointer
• I2C interface boot load.
• External logic asserts the WAKEUP pin
• External logic asserts the PA3/WU2 pin.
4.10.3 External Code Memory, EA = 1
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active low.
The bottom 16 KBytes of program memory is external, and
therefore the bottom 16 KBytes of internal RAM is accessible
only as data memory.
4.10
Program/Data RAM
4.10.1 Size
The FX1 has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to allow the 8051 to
Document #: 38-08039 Rev. *B
Page 6 of 50
CY7C64713/14
Inside FX1
Outside FX1
FFFF
7.5 KBytes
USB regs and
4K FIFO buffers
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
(RD#,WR#)
E200
E1FF
0.5 KBytes RAM
Data (RD#,WR#)*
E000
48 KBytes
External
Code
Memory
(PSEN#)
40 KBytes
External
Data
Memory
(RD#,WR#)
3FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
0000
Data
Code
*SUDPTR, USB upload/download, I2C interface boot access
Figure 4-3. Internal Code Memory, EA = 0
Inside FX1
Outside FX1
FFFF
7.5 KBytes
(OK to populate
USB regs and
4K FIFO buffers
(RD#,WR#)
data memory
here—RD#/WR#
strobes are not
active)
E200
E1FF
0.5 KBytes RAM
Data (RD#,WR#)*
E000
40 KBytes
External
Data
Memory
(RD#,WR#)
64 KBytes
External
Code
Memory
(PSEN#)
3FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes
RAM
Data
(RD#,WR#)*
0000
Data
Code
*SUDPTR, USB upload/download, I2C interface boot access
Figure 4-4. External Code Memory, EA = 1
Document #: 38-08039 Rev. *B
Page 7 of 50
CY7C64713/14
4.11
Register Addresses
FFFF
4 KBytes EP2-EP8
buffers
(8 x 512)
Not all Space is available
for all transfer types
F000
EFFF
2 KBytes RESERVED
E800
E7FF
E7C0
64 Bytes EP1IN
E7BF
E780
E77F
E740
E73F
E700
E6FF
64 Bytes EP1OUT
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
(512)
E500
E4FF
E480
E47F
Reserved (128)
128 bytes GPIF Waveforms
Reserved (512)
E400
E3FF
E200
E1FF
512 bytes
8051 xdata RAM
E000
be either double, triple, or quad buffered. Regardless of the
physical size of the buffer, each endpoint buffer accommo-
dates only one full-speed packet. For bulk endpoints the
maximum number of bytes it can accommodate is 64, even
though the physical buffer size is 512 or 1024. For an
ISOCHRONOUS endpoint the maximum number of bytes
it can accommodate is 1023. For endpoint configuration
options, see Figure 4-5.
4.12
Endpoint RAM
4.12.1 Size
• 3 × 64 bytes (Endpoints 0 and 1)
• 8 × 512 bytes (Endpoints 2, 4, 6, 8)
4.12.2 Organization
• EP0—Bidirectional endpoint zero, 64-byte buffer
4.12.3 Setup Data Buffer
• EP1IN, EP1OUT—64-byte buffers, bulk or interrupt
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
• EP2,4,6,8—Eight 512-byte buffers, bulk, interrupt, or isoch-
ronous, of which only the transfer size is available.
EP4 and EP8 can be double buffered, while EP2 and 6 can
Document #: 38-08039 Rev. *B
Page 8 of 50
CY7C64713/14
4.12.4 Endpoint Configurations
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP0 IN&OUT
EP1 IN
64
64
EP1 OUT
EP2
64
EP2
EP2
EP2 EP2
EP2 EP2
EP2
64
EP2
EP2
EP2
64
EP2
64
64
64
64
64
64
64
1023
1023
1023
1023
64
64
64
64
64
1023
EP4
64
EP4 EP4
64
64
64
64
64
64
64
64
EP6
1023
1023
1023
1023
1023
64
64
64
64
EP6
64
EP6
64
EP6
EP6 EP6
EP6
EP6
EP6 EP6
64
64
1023
1023
64
64
64
64
64
64
1023
1023
1023
64
64
64
64
EP8
64
EP8
64
EP8
64
EP8
64
EP8
64
1023
64
64
64
64
64
64
1023
1023
1023
64
64
64
64
64
10
12
9
11
4
5
8
1
2
3
6
7
Figure 4-5. Endpoint Configuration
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical columns. In full-speed, BULK mode uses only the first
64 bytes of each buffer, even though memory exists for the
allocation of the isochronous transfers in BULK mode the
unused endpoint buffer space is not available for other opera-
tions. An example endpoint configuration would be:
are controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described
in Section 4.12.2.
In operation, some of the eight RAM blocks fill or empty from
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
EP2—1023 double buffered; EP6—64 quad buffered (column
8).
4.13.2 Master/Slave Control Signals
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between two domains, the USB (SIE) domain
and the 8051-I/O Unit domain. This switching is done virtually
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” Since they are physically the
same memory, no bytes are actually transferred between
buffers.
4.12.5 Default Alternate Settings
Table 4-6. Default Alternate Settings[4, 5]
Alternate
Setting
0
1
2
3
ep0
64 64
64
64
ep1out
ep1in
ep2
0 64 bulk
0 64 bulk
64 int
64 int
64 int
64 int
0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
ep4
ep6
ep8
4.13
External FIFO Interface
4.13.1 Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories, and
Notes:
4. “0” means “not implemented.”
5. “2×” means “double buffered.”
Document #: 38-08039 Rev. *B
Page 9 of 50
CY7C64713/14
At any given time, some RAM blocks are filling/emptying with
USB data under SIE control, while other RAM blocks are
available to the 8051 and/or the I/O control unit. The RAM
blocks operate as single-port in the USB domain, and dual-
port in the 8051-I/O domain. The blocks can be configured as
single, double, triple, or quad buffered as previously shown.
4.14.1 Six Control OUT Signals
The 100- and 128-pin packages bring out all six Control Output
pins (CTL0-CTL5). The 8051 programs the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of
these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock
(20.8 ns using a 48-MHz clock).
The I/O control unit implements either an internal-master (M
for master) or external-master (S for Slave) interface.
4.14.2 Six Ready IN Signals
In Master (M) mode, the GPIF internally controls
FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-
pin package, six in the 100-pin and 128-pin packages) can be
used as flag inputs from an external FIFO or other logic if
desired. The GPIF can be run from either an internally derived
clock or externally supplied clock (IFCLK), at a rate that
transfers data up to 96 Megabytes/s (48-MHz IFCLK with 16-
bit interface).
The 100- and 128-pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56-pin package brings out
two of these signals, RDY0–1.
4.14.3 Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100- and 128-pin
packages, GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512-byte block of RAM. If more
address lines are needed, I/O port pins can be used.
In Slave (S) mode, the FX1 accepts either an internally derived
clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals
from external logic. When using an external IFCLK, the
external clock must be present before switching to the external
clock with the IFCLKSRC bit. Each endpoint can individually
be selected for byte or word operation by an internal configu-
ration bit, and a Slave FIFO Output Enable signal SLOE
enables data of the selected width. External logic must insure
that the output enable signal is inactive when writing data to a
slave FIFO. The slave interface can also operate asynchro-
nously, where the SLRD and SLWR signals act directly as
strobes, rather than a clock qualifier as in synchronous mode.
The signals SLRD, SLWR, SLOE and PKTEND are gated by
the signal SLCS#.
4.14.4 Long Transfer Mode
In master mode, the 8051 appropriately sets GPIF transaction
count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
4.15
ECC Generation
The EZ-USB FX1 can calculate ECCs (Error-Correcting
Codes) on data that passes across its GPIF or Slave FIFO
interfaces. There are two ECC configurations: Two ECCs,
each calculated over 256 bytes (SmartMedia™ Standard); and
one ECC calculated over 512 bytes.
4.13.3 GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the
internally supplied interface clock: 30 MHz and 48 MHz. Alter-
natively, an externally supplied clock of 5 MHz–48 MHz
feeding the IFCLK pin can be used as the interface clock.
IFCLK can be configured to function as an output clock when
the GPIF and FIFOs are internally clocked. An output enable
bit in the IFCONFIG register turns this clock output off, if
desired. Another bit within the IFCONFIG register will invert
the IFCLK signal whether internally or externally sourced.
The ECC can correct any one-bit error or detect any two-bit
error.
Note: To use the ECC logic, the GPIF or Slave FIFO interface
must be configured for byte-wide operation.
4.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit:
4.14
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a
user-programmable finite state machine. It allows the
CY7C64713/4 to perform local bus mastering, and can
implement a wide variety of protocols such as ATA interface,
printer parallel port, and Utopia.
4.15.1.1 ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia
Standard.
Write any value to ECCRESET, then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 256 bytes
of data will be calculated and stored in ECC1. The ECC for the
next 256 bytes will be stored in ECC2. After the second ECC
is calculated, the values in the ECCx registers will not change
until ECCRESET is written again, even if more data is subse-
quently passed across the interface.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general-purpose ready
inputs (RDY). The data bus width can be 8 or 16 bits. Each
GPIF vector defines the state of the control outputs, and deter-
mines what state a ready input (or multiple inputs) must be
before proceeding. The GPIF vector can be programmed to
advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the FX1 and the external device.
4.15.1.2 ECCM=1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the
GPIF or Slave FIFO interface. The ECC for the first 512 bytes
of data will be calculated and stored in ECC1; ECC2 is unused.
After the ECC is calculated, the value in ECC1 will not change
Document #: 38-08039 Rev. *B
Page 10 of 50
CY7C64713/14
until ECCRESET is written again, even if more data is subse-
quently passed across the interface
4.18.2 I2C Interface Boot Load Access
At power-on reset the I2C interface boot loader will load the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The
8051 will be in reset. I2C interface boot loads only occur after
power-on reset.
4.16
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16 KByte RAM and of the internal 512-byte scratch
pad RAM via a vendor-specific command. This capability is
normally used when “soft” downloading user code and is
available only to and from internal RAM, only when the 8051
is held in reset. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF (code/data) and 512 bytes from
0xE000–0xE1FF (scratch pad data RAM).[6]
4.18.3 I2C Interface General Purpose Access
The 8051 can control peripherals connected to the I2C bus
using the I2CTL and I2DAT registers. FX1 provides I2C master
control only, it is never an I2C slave.
4.17
Autopointer Access
4.19
Compatible with Previous Generation
EZ-USB FX2
FX1 provides two identical autopointers. They are similar to
the internal 8051 data pointers, but with an additional feature:
they can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external FX1 registers,
under control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopointer access (at 0xE67B – 0xE67C) allows
the autopointer to access all RAM, internal and external to the
part. Also, the autopointers can point to any FX1 register or
endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDATA
and code space cannot be used.
The EZ-USB FX1 is fit/form/function-upgradable to the EZ-
USB FX2LP. This makes for a easy transition for designers
wanting to upgrade their systems from full-speed to the high-
speed designs. The pinout and package selection are
identical, and all of the firmware developed for the FX1 will
function in the FX2LP with proper addition of High Speed
descriptors and speed switching code.
5.0
Pin Assignments
Figure 5-1 identifies all signals for the three package types.
The following pages illustrate the individual pin diagrams, plus
a combination diagram showing which of the full set of signals
are available in the 128-, 100-, and 56-pin packages.
4.18
I2C Controller
FX1 has one I2C port that is driven by two internal controllers,
one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that
the 8051, once running, uses to control external I2C devices.
The I2C port operates in master mode only.
The signals on the left edge of the 56-pin package in Figure 5-
1 are common to all versions in the FX1 family. Three modes
are available in all package versions: Port, GPIF master, and
Slave FIFO. These modes define the signals on the right edge
of the diagram. The 8051 selects the interface mode using the
IFCONFIG[1:0] register bits. Port mode is the power-on default
configuration.
4.18.1 I2C Port Pins
The I2C- pins SCL and SDA must have external 2.2-kΩ pull-
up resistors even if no EEPROM is connected to the FX1.
External EEPROM device address pins must be configured
properly. See Table 4-7 for configuring the device address
pins.
The 100-pin package adds functionality to the 56-pin package
by adding these pins:
• PORTC or alternate GPIFADR[7:0] address signals
• PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
Table 4-7. Strap Boot EEPROM Address Lines to These
Values
• Three GPIF Control signals
• Four GPIF Ready signals
Bytes
16
Example EEPROM
24LC00[7]
24LC01
A2
N/A
0
A1
N/A
0
A0
N/A
0
• Nine 8051 signals (two USARTs, three timer inputs,
INT4,and INT5#)
128
256
4K
• BKPT, RD#, WR#.
24LC02
0
0
0
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version. In the 100-pin
and 128-pin versions, an 8051 control bit can be set to pulse
the RD# and WR# pins when the 8051 reads from/writes to
PORTC.
24LC32
0
0
1
8K
24LC64
0
0
1
16K
24LC128
0
0
1
Notes:
6. After the data has been downloaded from the host, a “loader” can execute from internal RAM in order to transfer downloaded data to external memory.
7. This EEPROM does not have address pins.
Document #: 38-08039 Rev. *B
Page 11 of 50
CY7C64713/14
Port
GPIF Master
Slave FIFO
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
56
SLRD
SLWR
RDY0
RDY1
FLAGA
FLAGB
FLAGC
CTL0
CTL1
CTL2
T0OUT
T1OUT
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
INT0#/ PA0
INT1#/ PA1
SLOE
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
IFCLK
CLKOUT
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
DPLUS
DMINUS
PA5
PA6
PA7
PA7/FLAGD/SLCS#
PA7
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
100
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
T1
T0
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
128
A8
A7
A6
A5
A4
A3
EA
A2
A1
A0
Figure 5-1. Signals
Document #: 38-08039 Rev. *B
Page 12 of 50
CY7C64713/14
1
102
CLKOUT
VCC
GND
PD0/FD8
*WAKEUP
VCC
RESET#
2
101
3
100
4
99
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
5
98
CTL5
6
97
A3
A2
A1
A0
7
96
8
95
9
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
93
GND
92
PA7/*FLAGD/SLCS#
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
NC
NC
D6
D5
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
CY7C64713/4
128-pin TQFP
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
CTL4
CTL3
GND
OE#
Figure 5-2. CY7C64713/4 128-pin TQFP Pin Assignment
* denotes programmable polarity
Document #: 38-08039 Rev. *B
Page 13 of 50
CY7C64713/14
1
80
VCC
PD0/FD8
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
*WAKEUP
VCC
RESET#
3
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
4
5
CTL5
GND
6
7
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PA2/*SLOE
PA1/INT1#
PA0/INT0#
NC
NC
CY7C64713/4
100-pin TQFP
VCC
GND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
T2
*IFCLK
RESERVED
BKPT
SCL
CTL4
CTL3
SDA
Figure 5-3. CY7C64713/4 100-pin TQFP Pin Assignment
* denotes programmable polarity
Document #: 38-08039 Rev. *B
Page 14 of 50
CY7C64713/14
RESET#
RDY0/*SLRD
RDY1/*SLWR
AVCC
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
3
XTALOUT
XTALIN
4
5
AGND
6
CY7C64713/4
56-pin QFN
AVCC
7
PA2/*SLOE
PA1/INT1#
DPLUS
8
DMINUS
9
PA0/INT0#
AGND
10
11
12
13
14
VCC
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
*IFCLK/**PE0/T0OUT
RESERVED
Figure 5-4. CY7C64713/4 56-pin QFN Pin Assignment
* denotes programmable polarity
Document #: 38-08039 Rev. *B
Page 15 of 50
CY7C64713/14
5.1
CY7C64713/4 Pin Definitions
[8]
Table 5-1. FX1 Pin Definitions
128 100 56
TQFP TQFP QFN
Name
Type
Description
Default
10
17
9
3
7
6
AVCC
Power
N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides
power to the analog section of the chip.
16
AVCC
AGND
Power
N/A Analog VCC. Connect this pin to 3.3V power source. This signal provides
power to the analog section of the chip.
13
20
12
19
18
17
Ground
Ground
I/O/Z
N/A Analog Ground. Connect to ground with as short a path as possible.
N/A Analog Ground. Connect to ground with as short a path as possible.
10 AGND
19
9
8
DMINUS
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
H
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
18
DPLUS
A0
I/O/Z
94
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O/Z
8051 Address Bus. This bus is driven at all times. When the 8051 is
addressing internal RAM it reflects the internal address.
95
A1
96
A2
97
A3
117
118
119
120
126
127
128
21
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
22
23
24
25
59
8051 Data Bus. This bidirectional bus is high-impedance when inactive,
input for bus reads, and output for bus writes. The data bus is used for
external 8051 program and data memory. The data bus is active only for
external bus accesses, and is driven LOW in suspend.
60
D1
I/O/Z
61
D2
I/O/Z
62
D3
I/O/Z
63
D4
I/O/Z
86
D5
I/O/Z
87
D6
I/O/Z
88
D7
I/O/Z
39
PSEN#
Output
Program Store Enable. This active-LOW signal indicates an 8051 code
fetch from external memory. It is active for program memory fetches from
0x4000–0xFFFF when the EA pin is LOW, or from 0x0000–0xFFFF when
the EA pin is HIGH.
34
28
BKPT
Output
L
Breakpoint. This pin goes active (HIGH) when the 8051 address bus
matches the BPADDRH/L registers and breakpoints are enabled in the
BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT
register is HIGH, this signal pulses HIGH for eight 12-/24-/48-MHz clocks.
If the BPPULSE bit is LOW, the signal remains HIGH until the 8051 clears
the BREAK bit (by writing 1 to it) in the BREAKPT register.
Note:
8. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up
and in standby. Note also that no pins should be driven while the device is powered down.
Document #: 38-08039 Rev. *B
Page 16 of 50
CY7C64713/14
Table 5-1. FX1 Pin Definitions (continued)[8]
128 100
56
TQFP TQFP QFN
Name
Type
Description
Default
99
35
77
42 RESET#
EA
Input
N/A Active LOW Reset. Resets the entire chip. See section 4.9 ”Reset and
Wakeup” on page 5 for more details.
Input
Input
N/A External Access. This pin determines where the 8051 fetches code
between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches this
code from its internal RAM. IF EA = 1 the 8051 fetches this code from
external memory.
12
11
5
4
XTALIN
N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square wave
derived from another clock source. When driving from an external source,
the driving signal should be a 3.3V square wave.
11
1
10
XTALOUT Output
N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant, funda-
mental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
100
54 CLKOUT O/Z
12 CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input
MHz clock. The 8051 defaults to 12-MHz operation. The 8051 may three-state
this output by setting CPUCS.1 = 1.
Port A
82
67
68
33 PA0 or
INT0#
I/O/Z
I
Multiplexed pin whose function is selected by PORTACFG.0
(PA0) PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is either
edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83
84
85
34 PA1 or
INT1#
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA1) PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is either
edge triggered (IT1 = 1) or level triggered (IT1 = 0).
69
70
35 PA2 or
SLOE
I
Multiplexed pin whose function is selected by two bits:
(PA2) IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity (FIFOPIN-
POLAR.4) for the slave FIFOs connected to FD[7..0] or FD[15..0].
36 PA3 or
WU2
I
Multiplexed pin whose function is selected by:
(PA3) WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN bit
(WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the 8051 is in
suspend and WU2EN = 1, a transition on this pin starts up the oscillator
and interrupts the 8051 to allow it to exit the suspend mode. Asserting this
pin inhibits the chip from suspending, if WU2EN=1.
89
90
91
71
72
73
37 PA4 or
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA4) IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0
FIFOADR0 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
38 PA5 or
FIFOADR1
I
Multiplexed pin whose function is selected by:
(PA5) IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs connected
to FD[7..0] or FD[15..0].
39 PA6 or
PKTEND
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.
(PA6) PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the endpoint
and whose polarity is programmable via FIFOPINPOLAR.5.
Document #: 38-08039 Rev. *B
Page 17 of 50
CY7C64713/14
Table 5-1. FX1 Pin Definitions (continued)[8]
128 100
56
TQFP TQFP QFN
Name
Type
Description
Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
Default
92
74
40 PA7 or
I/O/Z
I
FLAGD or
SLCS#
(PA7) PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
Port B
44
34
35
36
37
44
45
46
47
18 PB0 or
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
FD[0]
(PB0) IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
45
46
47
54
55
56
57
19 PB1 or
FD[1]
I
Multiplexed pin whose function is selected by the following bits:
(PB1) IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
20 PB2 or
FD[2]
I
Multiplexed pin whose function is selected by the following bits:
(PB2) IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
21 PB3 or
FD[3]
I
Multiplexed pin whose function is selected by the following bits:
(PB3) IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
22 PB4 or
FD[4]
I
Multiplexed pin whose function is selected by the following bits:
(PB4) IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
23 PB5 or
FD[5]
I
Multiplexed pin whose function is selected by the following bits:
(PB5) IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
24 PB6 or
FD[6]
I
Multiplexed pin whose function is selected by the following bits:
(PB6) IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
25 PB7 or
FD[7]
I
Multiplexed pin whose function is selected by the following bits:
(PB7) IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
PORT C
72
57
58
59
60
61
PC0 or
GPIFADR0
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.0
(PC0) PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73
74
75
76
PC1 or
GPIFADR1
I
Multiplexed pin whose function is selected by PORTCCFG.1
(PC1) PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
PC2 or
GPIFADR2
I
Multiplexed pin whose function is selected by PORTCCFG.2
(PC2) PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
PC3 or
GPIFADR3
I
Multiplexed pin whose function is selected by PORTCCFG.3
(PC3) PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
PC4 or
I
Multiplexed pin whose function is selected by PORTCCFG.4
GPIFADR4
(PC4) PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Document #: 38-08039 Rev. *B
Page 18 of 50
CY7C64713/14
Table 5-1. FX1 Pin Definitions (continued)[8]
128 100
56
TQFP TQFP QFN
Name
PC5 or
GPIFADR5
Type
Description
Multiplexed pin whose function is selected by PORTCCFG.5
(PC5) PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
Default
77
78
79
62
63
64
I/O/Z
I
PC6 or
GPIFADR6
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.6
(PC6) PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
PC7 or
I
Multiplexed pin whose function is selected by PORTCCFG.7
GPIFADR7
(PC7) PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102
80
81
82
83
95
96
97
98
45 PD0 or
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
FD[8]
(PD0) EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
103
104
105
121
122
123
124
46 PD1 or
FD[9]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD1) EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
47 PD2 or
FD[10]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD2) EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
48 PD3 or
FD[11]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD3) EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
49 PD4 or
FD[12]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD4) EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
50 PD5 or
FD[13]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD5) EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
51 PD6 or
FD[14]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD6) EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
52 PD7 or
FD[15]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
(PD7) EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Port E
108
86
87
88
PE0 or
T0OUT
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.0 bit.
(PE0) PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0. T0OUT
outputs a high level for one CLKOUT clock cycle when Timer0 overflows.
If Timer0 is operated in Mode 3 (two separate timer/counters), T0OUT is
active when the low byte timer/counter overflows.
109
110
PE1 or
T1OUT
I
Multiplexed pin whose function is selected by the PORTECFG.1 bit.
(PE1) PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1 overflows.
If Timer1 is operated in Mode 3 (two separate timer/counters), T1OUT is
active when the low byte timer/counter overflows.
PE2 or
T2OUT
I
Multiplexed pin whose function is selected by the PORTECFG.2 bit.
(PE2) PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signalfrom 8051 Timer2. T2OUT isactive
(HIGH) for one clock cycle when Timer/Counter 2 overflows.
Document #: 38-08039 Rev. *B
Page 19 of 50
CY7C64713/14
Table 5-1. FX1 Pin Definitions (continued)[8]
128 100
56
TQFP TQFP QFN
Name
PE3 or
RXD0OUT
Type
Description
Multiplexed pin whose function is selected by the PORTECFG.3 bit.
(PE3) PE3 is a bidirectional I/O port pin.
Default
111
112
89
90
I/O/Z
I
RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is
selected and UART0 is in Mode 0, this pin provides the output data for
UART0 only when it is in sync mode. Otherwise it is a 1.
PE4 or
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.4 bit.
RXD1OUT
(PE4) PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT
is selected and UART1 is in Mode 0, this pin provides the output data for
UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
113
114
91
92
PE5 or
INT6
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.5 bit.
(PE5) PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The INT6 pin is edge-
sensitive, active HIGH.
PE6 or
T2EX
I
Multiplexed pin whose function is selected by the PORTECFG.6 bit.
(PE6) PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX reloads timer
2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON.
115
4
93
3
PE7 or
GPIFADR8
I/O/Z
Input
I
Multiplexed pin whose function is selected by the PORTECFG.7 bit.
(PE7) PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
1
2
RDY0 or
SLRD
N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity (FIFOPIN-
POLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0].
5
4
RDY1 or
SLWR
Input
N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity (FIFOPIN-
POLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0].
6
7
5
6
RDY2
RDY3
RDY4
RDY5
Input
Input
Input
Input
O/Z
N/A RDY2 is a GPIF input signal.
N/A RDY3 is a GPIF input signal.
N/A RDY4 is a GPIF input signal.
N/A RDY5 is a GPIF input signal.
8
7
9
8
69
54
29 CTL0 or
FLAGA
H
H
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
70
71
55
56
30 CTL1 or
FLAGB
O/Z
O/Z
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
31 CTL2 or
FLAGC
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
66
67
98
51
52
76
CTL3
CTL4
CTL5
O/Z
H
H
H
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
Output
Output
Document #: 38-08039 Rev. *B
Page 20 of 50
CY7C64713/14
Table 5-1. FX1 Pin Definitions (continued)[8]
128 100
56
TQFP TQFP QFN
Name
Type
Description
Default
32
26
13 IFCLK
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or out of the
slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is used (IFCONFIG.7 = 1)
the IFCLK pin can be configured to output 30/48 MHz by bits IFCONFIG.5
and IFCONFIG.6. IFCLK may be inverted, whether internally or externally
sourced, by setting the bit IFCONFIG.4 =1.
28
106
31
22
84
25
INT4
INT5#
T2
Input
Input
Input
N/A INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is edge-
sensitive, active HIGH.
N/A INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is edge-
sensitive, active LOW.
N/A T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides the
input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not use this
pin.
30
29
53
52
51
50
24
23
43
42
41
40
T1
Input
N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the input
to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use this bit.
T0
Input
N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the input
to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use this bit.
RXD1
TXD1
RXD0
TXD0
Input
N/A RXD1is an active-HIGH input signal for 8051 UART1, which provides data
to the UART in all modes.
Output
Input
H
TXD1is an active-HIGH output pin from 8051 UART1, which provides the
output clock in sync mode, and the output data in async mode.
N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides data
to the UART in all modes.
Output
H
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which provides
the output clock in sync mode, and the output data in async mode.
42
41
40
38
33
CS#
WR#
RD#
OE#
Output
Output
Output
Output
H
H
H
H
CS# is the active-LOW chip select for external memory.
WR# is the active-LOW write strobe output for external memory.
RD# is the active-LOW read strobe output for external memory.
OE# is the active-LOW output enable for external memory.
32
31
27
79
14 Reserved Input
N/A Reserved. Connect to ground.
101
44 WAKEUP Input
N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the
oscillator and interrupts the 8051 to allow it to exit the suspend mode.
Holding WAKEUP asserted inhibits the EZ-USBFX1 chip from suspending.
This pin has programmable polarity (WAKEUP.4).
36
37
29
30
15 SCL
16 SDA
OD
OD
Z
Clock for the I2C interface. Connect to VCC with a 2.2K resistor, even if no
I2C peripheral is attached.
Z
Data for I2C interface. Connect to VCC with a 2.2K resistor, even if no I2C
peripheral is attached.
2
1
55 VCC
11 VCC
17 VCC
VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
26
20
33
38
49
53
66
78
85
43
48
64
27 VCC
VCC
68
81
32 VCC
43 VCC
VCC
100
107
Document #: 38-08039 Rev. *B
Page 21 of 50
CY7C64713/14
Table 5-1. FX1 Pin Definitions (continued)[8]
128 100
56
TQFP TQFP QFN
Name
Type
Description
Default
3
27
2
56 GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
21
39
48
50
65
75
94
99
12 GND
GND
49
58
26 GND
28 GND
GND
65
80
93
41 GND
GND
116
125
53 GND
14
15
16
13
14
15
NC
NC
NC
N/A
N/A
N/A
N/A No Connect. This pin must be left open.
N/A No Connect. This pin must be left open.
N/A No-connect. This pin must be left open.
Document #: 38-08039 Rev. *B
Page 22 of 50
CY7C64713/14
6.0
Register Summary
FX1 register bit definitions are described in the EZ-USB TRM
in greater detail.
Table 6-1. FX1 Register Summary
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform
Descriptor 0, 1, 2, 3 data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
E480 128 reserved
GENERAL CONFIGURATION
E600
E601
1
1
CPUCS
CPU Control & Status
0
0
PORTCSTB CLKSPD1 CLKSPD0 CLKINV
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
10000000 RW
IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
IFCLKSRC 3048MHZ
IFCLKOE
FLAGB1
FLAGD1
0
IFCLKPOL ASYNC
GSTATE
FLAGA2
FLAGC2
EP2
[9]
[9]
E602
E603
E604
1
1
1
PINFLAGSAB
Slave FIFO FLAGA and FLAGB3
FLAGB Pin Configuration
FLAGB2
FLAGD2
0
FLAGB0
FLAGD0
0
FLAGA3
FLAGC3
EP3
FLAGA1
FLAGC1
EP1
FLAGA0
FLAGC0
EP0
00000000 RW
00000000 RW
PINFLAGSCD
Slave FIFO FLAGC and FLAGD3
FLAGD Pin Configuration
[9]
FIFORESET
Restore FIFOS to default NAKALL
state
xxxxxxxx
W
E605
E606
E607
E608
1
1
1
1
BREAKPT
BPADDRH
BPADDRL
UART230
Breakpoint Control
0
0
0
0
BREAK
A11
A3
BPPULSE BPEN
0
00000000 rrrrbbbr
xxxxxxxx RW
xxxxxxxx RW
Breakpoint Address H
Breakpoint Address L
A15
A7
0
A14
A6
0
A13
A5
0
A12
A4
0
A10
A2
0
A9
A1
A8
A0
230 Kbaud internally
generated ref. clock
0
230UART1 230UART0 00000000 rrrrrrbb
[9]
E609
1
FIFOPINPOLAR
REVID
Slave FIFO Interface pins 0
polarity
0
PKTEND
SLOE
rv4
SLRD
rv3
SLWR
rv2
EF
FF
00000000 rrbbbbbb
E60A 1
E60B 1
Chip Revision
rv7
rv6
0
rv5
0
rv1
rv0
RevA
00000001
R
[9]
REVCTL
Chip Revision Control
0
0
0
0
0
dyn_out
enh_pkt
00000000 rrrrrrbb
UDMA
E60C 1
3
GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA)
0
0
0
0
0
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
reserved
ENDPOINT CONFIGURATION
E610
E611
1
1
EP1OUTCFG
Endpoint 1-OUT
Configuration
VALID
VALID
0
0
TYPE1
TYPE1
TYPE0
TYPE0
0
0
0
0
0
0
0
0
10100000 brbbrrrr
10100000 brbbrrrr
EP1INCFG
Endpoint 1-IN
Configuration
E612
E613
E614
E615
1
1
1
1
2
1
EP2CFG
EP4CFG
EP6CFG
EP8CFG
reserved
Endpoint 2 Configuration VALID
Endpoint 4 Configuration VALID
Endpoint 6 Configuration VALID
Endpoint 8 Configuration VALID
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
0
0
0
0
BUF1
0
BUF0
0
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
SIZE
0
BUF1
0
BUF0
0
[9]
[9]
[9]
[9]
E618
E619
EP2FIFOCFG
Endpoint 2 / slave FIFO
configuration
0
0
0
0
INFM1
INFM1
INFM1
INFM1
OEP1
OEP1
OEP1
OEP1
AUTOOUT AUTOIN
AUTOOUT AUTOIN
AUTOOUT AUTOIN
AUTOOUT AUTOIN
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
ZEROLENIN 0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
1
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
reserved
Endpoint 4 / slave FIFO
configuration
E61A 1
E61B 1
E61C 4
Endpoint 6 / slave FIFO
configuration
Endpoint 8 / slave FIFO
configuration
[9]
E620
E621
E622
E623
E624
E625
E626
E627
1
1
1
1
1
1
1
1
EP2AUTOINLENH Endpoint 2 AUTOIN
0
0
0
0
0
PL10
PL2
0
PL9
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
00000010 rrrrrbbb
00000000 RW
Packet Length H
[9]
EP2AUTOINLENL
Endpoint 2 AUTOIN
Packet Length L
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL1
PL9
PL1
PL9
PL1
PL9
PL1
[9]
EP4AUTOINLENH Endpoint 4 AUTOIN
00000010 rrrrrrbb
00000000 RW
Packet Length H
[9]
EP4AUTOINLENL
Endpoint 4 AUTOIN
Packet Length L
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL2
PL10
PL2
0
[9]
EP6AUTOINLENH Endpoint 6 AUTOIN
00000010 rrrrrbbb
00000000 RW
Packet Length H
[9]
EP6AUTOINLENL
Endpoint 6 AUTOIN
Packet Length L
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
[9]
EP8AUTOINLENH Endpoint 8 AUTOIN
00000010 rrrrrrbb
00000000 RW
Packet Length H
[9]
EP8AUTOINLENL
Endpoint 8 AUTOIN
Packet Length L
PL7
PL6
PL5
PL4
PL3
PL2
E628
E629
1
1
ECCCFG
ECCRESET
ECC1B0
ECC1B1
ECC1B2
ECC2B0
ECC2B1
ECC Configuration
ECC Reset
0
0
0
0
0
0
0
ECCM
x
00000000 rrrrrrrb
x
x
x
x
x
x
x
00000000
11111111
11111111
11111111
11111111
11111111
W
R
R
R
R
R
E62A 1
E62B 1
E62C 1
E62D 1
E62E 1
Note:
ECC1 Byte 0 Address
ECC1 Byte 1 Address
ECC1 Byte 2 Address
ECC2 Byte 0 Address
ECC2 Byte 1 Address
LINE15
LINE7
COL5
LINE15
LINE7
LINE14
LINE6
COL4
LINE14
LINE6
LINE13
LINE5
COL3
LINE13
LINE5
LINE12
LINE4
COL2
LINE12
LINE4
LINE11
LINE3
COL1
LINE11
LINE3
LINE10
LINE2
COL0
LINE10
LINE2
LINE9
LINE1
LINE17
LINE9
LINE1
LINE8
LINE0
LINE16
LINE8
LINE0
9. Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08039 Rev. *B
Page 23 of 50
CY7C64713/14
Table 6-1. FX1 Register Summary (continued)
Hex Size Name
E62F 1 ECC2B2
Description
b7
b6
b5
b4
b3
b2
b1
0
b0
0
Default
Access
R
ECC2 Byte 2 Address
COL5
COL4
COL3
COL2
COL1
COL0
11111111
[9]
[9]
E630
E630
1
1
EP2FIFOPFH
Endpoint 2 / slave FIFO DECIS
ProgrammableFlagHISO
Mode
PKTSTAT
PKTSTAT
IN: PKTS[2] IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC9
PFC9
PFC8
10001000 bbbbbrbb
EP2FIFOPFH
Endpoint 2 / slave FIFO DECIS
Programmable Flag H
Non-ISO Mode
OUT:PFC12 OUT:PFC11 OUT:PFC10 0
IN:PKTS[2] 10001000 bbbbbrbb
OUT:PFC8
[9]
[9]
E631
1
EP2FIFOPFL
Endpoint 2 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5
Programmable Flag L OUT:PFC7 OUT:PFC6
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
E632
E632
1
1
EP4FIFOPFH
Endpoint 4 / slave FIFO DECIS
ProgrammableFlagHISO
Mode
PKTSTAT
PKTSTAT
0
0
IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC10 OUT:PFC9
0
0
PFC8
PFC8
10001000 bbrbbrrb
10001000 bbrbbrrb
[9]
EP4FIFOPFH
Endpoint 4 / slave FIFO DECIS
Programmable Flag H
Non-ISO Mode
OUT:PFC10 OUT:PFC9
0
[9]
[9]
E633
1
EP4FIFOPFL
Endpoint 4 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5
Programmable Flag L OUT:PFC7 OUT:PFC6
PFC4
PFC3
PFC2
PFC1
PFC0
PFC8
00000000 RW
E634
E634
1
1
EP6FIFOPFH
Endpoint 6 / slave FIFO DECIS
ProgrammableFlagHISO
Mode
PKTSTAT
PKTSTAT
INPKTS[2] IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC9
PFC9
00001000 bbbbbrbb
[9]
EP6FIFOPFH
Endpoint 6 / slave FIFO DECIS
Programmable Flag H
Non-ISO Mode
OUT:PFC12 OUT:PFC11 OUT:PFC10 0
IN:PKTS[2] 00001000 bbbbbrbb
OUT:PFC8
[9]
[9]
E635
1
EP6FIFOPFL
Endpoint 6 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5
Programmable Flag L OUT:PFC7 OUT:PFC6
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
E636
E636
1
1
EP8FIFOPFH
Endpoint 8 / slave FIFO DECIS
ProgrammableFlagHISO
Mode
PKTSTAT
PKTSTAT
0
0
IN: PKTS[1] IN: PKTS[0] 0
OUT:PFC10 OUT:PFC9
0
0
PFC8
PFC8
00001000 bbrbbrrb
00001000 bbrbbrrb
[9]
EP8FIFOPFH
Endpoint 8 / slave FIFO DECIS
Programmable Flag H
Non-ISO Mode
OUT:PFC10 OUT:PFC9
0
[9]
[9]
E637
E637
1
1
EP8FIFOPFL
ISO Mode
Endpoint 8 / slave FIFO PFC7
Programmable Flag L
PFC6
PFC5
PFC4
PFC4
PFC3
PFC3
PFC2
PFC2
PFC1
PFC1
PFC0
PFC0
00000000 RW
00000000 RW
EP8FIFOPFL
Endpoint 8 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5
Programmable Flag L OUT:PFC7 OUT:PFC6
Non-ISO Mode
8
1
1
1
1
4
1
7
reserved
E640
E641
E642
E643
E644
E648
E649
reserved
reserved
reserved
reserved
reserved
[9]
INPKTEND
Force IN Packet End
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx
xxxxxxxx
W
W
[9]
OUTPKTEND
INTERRUPTS
Force OUT Packet End Skip
[9]
E650
E651
E652
E653
E654
E655
E656
E657
E658
1
1
1
1
1
1
1
1
1
EP2FIFOIE
Endpoint 2 slave FIFO
Flag Interrupt Enable
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EDGEPF
PF
PF
PF
PF
PF
PF
PF
PF
EP2
EF
EF
EF
EF
EF
EF
EF
EF
EP1
FF
FF
FF
FF
FF
FF
FF
FF
EP0
00000000 RW
[9,10]
EP2FIFOIRQ
Endpoint 2 slave FIFO
Flag Interrupt Request
0
0
0
00000111 rrrrrbbb
00000000 RW
[9]
EP4FIFOIE
Endpoint 4 slave FIFO
Flag Interrupt Enable
0
0
EDGEPF
[9,10]
[9,10]
[9,10]
EP4FIFOIRQ
Endpoint 4 slave FIFO
Flag Interrupt Request
0
0
0
00000111 rrrrrbbb
00000000 RW
[9]
EP6FIFOIE
Endpoint 6 slave FIFO
Flag Interrupt Enable
0
0
EDGEPF
EP6FIFOIRQ
Endpoint 6 slave FIFO
Flag Interrupt Request
0
0
0
00000110 rrrrrbbb
00000000 RW
[9]
EP8FIFOIE
Endpoint 8 slave FIFO
Flag Interrupt Enable
0
0
EDGEPF
EP8FIFOIRQ
IBNIE
Endpoint 8 slave FIFO
Flag Interrupt Request
0
0
0
00000110 rrrrrbbb
00000000 RW
IN-BULK-NAK Interrupt
Enable
EP8
EP6
EP4
Note:
10. SFRs not part of the standard 8051 architecture.
The register can only be reset, it cannot be set.
Document #: 38-08039 Rev. *B
Page 24 of 50
CY7C64713/14
Table 6-1. FX1 Register Summary (continued)
Hex Size Name
Description
b7
0
b6
0
b5
b4
b3
b2
b1
b0
Default
Access
[10]
E659
1
IBNIRQ
IN-BULK-NAK interrupt
Request
EP8
EP6
EP4
EP2
EP1
EP0
00xxxxxx rrbbbbbb
E65A 1
E65B 1
NAKIE
Endpoint Ping-NAK / IBN EP8
Interrupt Enable
EP6
EP6
EP4
EP4
EP2
EP2
EP1
EP1
EP0
EP0
0
0
IBN
IBN
00000000 RW
[10]
[10]
NAKIRQ
Endpoint Ping-NAK / IBN EP8
Interrupt Request
xxxxxx0x bbbbbbrb
E65C 1
E65D 1
E65E 1
USBIE
USBIRQ
EPIE
USB Int Enables
0
EP0ACK
EP0ACK
EP6
0
URES
URES
EP2
SUSP
SUTOK
SUTOK
EP1IN
SOF
SUDAV
SUDAV
EP0IN
00000000 RW
USB Interrupt Requests
0
0
SUSP
SOF
0xxxxxxx rbbbbbbb
00000000 RW
Endpoint Interrupt
Enables
EP8
EP4
EP1OUT
EP0OUT
[10]
E65F 1
EPIRQ
Endpoint Interrupt
Requests
EP8
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
0
RW
[9]
E660
E661
E662
1
1
1
GPIFIE
GPIF Interrupt Enable
GPIF Interrupt Request
0
0
0
0
0
0
0
0
0
0
GPIFWF
GPIFWF
0
GPIFDONE 00000000 RW
GPIFDONE 000000xx RW
[9]
GPIFIRQ
0
0
0
0
USBERRIE
USB Error Interrupt
Enables
ISOEP8
ISOEP6
ISOEP4
ISOEP2
ERRLIMIT
ERRLIMIT
LIMIT0
00000000 RW
E663
E664
1
1
USBERRIRQ[10]
ERRCNTLIM
USB Error Interrupt
Requests
ISOEP8
EC3
ISOEP6
EC2
ISOEP4
EC1
ISOEP2
EC0
0
0
0
0000000x bbbbrrrb
xxxx0100 rrrrbbbb
USB Error counter and
limit
LIMIT3
LIMIT2
LIMIT1
E665
E666
1
1
CLRERRCNT
INT2IVEC
Clear Error Counter EC3:0x
x
x
x
x
x
x
x
xxxxxxxx
W
R
Interrupt 2 (USB)
Autovector
0
1
0
I2V4
I2V3
I2V2
I2V1
I2V0
0
0
00000000
E667
1
INT4IVEC
Interrupt 4 (slave FIFO &
GPIF) Autovector
0
0
I4V3
0
I4V2
0
I4V1
I4V0
0
0
0
10000000
R
E668
E669
1
7
INTSETUP
Interrupt 2&4 setup
AV2EN
INT4SRC
AV4EN
00000000 RW
reserved
INPUT / OUTPUT
PORTACFG
E670
E671
E672
1
1
1
I/O PORTA Alternate
Configuration
FLAGD
GPIFA7
GPIFA8
0
SLCS
GPIFA6
T2EX
0
0
0
0
0
INT1
GPIFA1
T1OUT
0
INT0
00000000 RW
00000000 RW
00000000 RW
00000000 rrrrrrrb
PORTCCFG
PORTECFG
I/O PORTC Alternate
Configuration
GPIFA5
INT6
0
GPIFA4
GPIFA3
GPIFA2
GPIFA0
T0OUT
EXTCLK
I/O PORTE Alternate
Configuration
RXD1OUT RXD0OUT T2OUT
E673
E677
E678
4
1
1
XTALINSRC
reserved
I2CS
XTALIN Clock Source
0
0
0
I²C Bus
Control & Status
START
STOP
d6
LASTRD
ID1
d4
0
ID0
d3
0
BERR
d2
ACK
d1
DONE
d0
000xx000 bbbrrrrr
xxxxxxxx RW
00000000 RW
xxxxxxxx RW
xxxxxxxx RW
E679
1
I2DAT
I²C Bus
Data
d7
0
d5
0
E67A 1
E67B 1
E67C 1
I2CTL
I²C Bus
Control
0
0
STOPIE
D1
400KHZ
D0
XAUTODAT1
XAUTODAT2
UDMA CRC
Autoptr1 MOVX access, D7
when APTREN=1
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
Autoptr2 MOVX access, D7
when APTREN=1
D1
D0
[9]
E67D 1
E67E 1
E67F 1
UDMACRCH
UDMA CRC MSB
UDMA CRC LSB
UDMA CRC Qualifier
CRC15
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
CRC10
CRC2
CRC9
CRC1
CRC8
CRC0
01001010 RW
10111010 RW
[9]
UDMACRCL
CRC7
UDMACRC-
QUALIFIER
QENABLE
QSTATE
QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
USBCS
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
USB Control & Status
Put chip into suspend
0
x
0
0
0
DISCON
NOSYNSOF RENUM
SIGRSUME x0000000 rrrrbbbb
SUSPEND
WAKEUPCS
TOGCTL
x
x
x
x
x
x
x
xxxxxxxx
W
Wakeup Control & Status WU2
WU
S
WU2POL
WUPOL
0
DPEN
EP2
FC10
FC2
WU2EN
EP1
FC9
FC1
WUEN
EP0
FC8
FC0
xx000101 bbbbrbbb
x0000000 rrrbbbbb
Toggle Control
Q
R
IO
EP3
0
USBFRAMEH
USBFRAMEL
reserved
USB Frame count H
USB Frame count L
0
0
0
0
00000xxx
xxxxxxxx
R
R
FC7
FC6
FC5
FC4
FC3
FNADDR
USB Function address
0
FA6
FA5
FA4
FA3
FA2
FA1
FA0
0xxxxxxx
R
reserved
ENDPOINTS
[9]
E68A 1
E68B 1
E68C 1
E68D 1
EP0BCH
Endpoint 0 Byte Count H (BC15)
Endpoint 0 Byte Count L (BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx RW
xxxxxxxx RW
[9]
EP0BCL
reserved
EP1OUTBC
Endpoint 1 OUT Byte
Count
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
xxxxxxxx RW
E68E 1
E68F 1
reserved
EP1INBC
Endpoint 1 IN Byte Count 0
Endpoint 2 Byte Count H
Endpoint 2 Byte Count L BC7/SKIP
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
xxxxxxxx RW
xxxxxxxx RW
xxxxxxxx RW
[9]
E690
E691
E692
E694
E695
E696
1
1
2
1
1
2
EP2BCH
0
[9]
EP2BCL
BC6
BC5
BC4
BC3
reserved
[9]
EP4BCH
Endpoint 4 Byte Count H
0
0
0
0
0
0
BC9
BC1
BC8
BC0
xxxxxxxx RW
xxxxxxxx RW
[9]
EP4BCL
Endpoint 4 Byte Count L BC7/SKIP
BC6
BC5
BC4
BC3
BC2
reserved
Document #: 38-08039 Rev. *B
Page 25 of 50
CY7C64713/14
Table 6-1. FX1 Register Summary (continued)
Hex Size Name
Description
b7
0
b6
0
b5
0
b4
0
b3
0
b2
b1
b0
Default
Access
[9]
E698
E699
1
1
EP6BCH
Endpoint 6 Byte Count H
BC10
BC2
BC9
BC1
BC8
BC0
xxxxxxxx RW
xxxxxxxx RW
[9]
EP6BCL
reserved
Endpoint 6 Byte Count L BC7/SKIP
BC6
BC5
BC4
BC3
E69A 2
E69C 1
E69D 1
E69E 2
E6A0 1
[9]
EP8BCH
Endpoint 8 Byte Count H
0
0
0
0
0
0
BC9
BC1
BC8
BC0
xxxxxxxx RW
xxxxxxxx RW
[9]
EP8BCL
reserved
EP0CS
Endpoint 8 Byte Count L BC7/SKIP
BC6
BC5
BC4
BC3
BC2
Endpoint 0 Control and HSNAK
Status
0
0
0
0
0
BUSY
BUSY
BUSY
0
STALL
STALL
STALL
STALL
STALL
STALL
STALL
FF
10000000 bbbbbbrb
00000000 bbbbbbrb
00000000 bbbbbbrb
00101000 rrrrrrrb
00101000 rrrrrrrb
00000100 rrrrrrrb
00000100 rrrrrrrb
E6A1 1
E6A2 1
E6A3 1
E6A4 1
E6A5 1
E6A6 1
E6A7 1
E6A8 1
E6A9 1
E6AA 1
E6AB 1
E6AC 1
E6AD 1
E6AE 1
E6AF 1
E6B0 1
E6B1 1
E6B2 1
E6B3 1
E6B4 1
E6B5 1
EP1OUTCS
EP1INCS
Endpoint 1 OUT Control
and Status
0
0
0
0
0
0
Endpoint 1 IN Control and 0
Status
0
0
0
0
0
EP2CS
Endpoint 2 Control and
Status
0
NPAK2
NPAK1
NPAK0
NPAK0
NPAK0
NPAK0
0
FULL
FULL
FULL
FULL
0
EMPTY
EMPTY
EMPTY
EMPTY
PF
EP4CS
Endpoint 4 Control and
Status
0
0
NPAK1
0
EP6CS
Endpoint 6 Control and
Status
0
NPAK2
NPAK1
0
EP8CS
Endpoint 8 Control and
Status
0
0
NPAK1
0
EP2FIFOFLGS
EP4FIFOFLGS
EP6FIFOFLGS
EP8FIFOFLGS
EP2FIFOBCH
EP2FIFOBCL
EP4FIFOBCH
EP4FIFOBCL
EP6FIFOBCH
EP6FIFOBCL
EP8FIFOBCH
EP8FIFOBCL
SUDPTRH
Endpoint 2 slave FIFO
Flags
0
0
0
EF
00000010
00000010
00000110
00000110
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
R
R
R
R
R
R
R
R
R
R
R
R
Endpoint 4 slave FIFO
Flags
0
0
0
0
0
PF
EF
FF
Endpoint 6 slave FIFO
Flags
0
0
0
0
0
PF
EF
FF
Endpoint 8 slave FIFO
Flags
0
0
0
0
0
PF
EF
FF
Endpoint 2 slave FIFO
total byte count H
0
0
0
BC12
BC4
0
BC11
BC3
0
BC10
BC2
BC10
BC2
BC10
BC2
BC10
BC2
A10
A2
BC9
BC1
BC9
BC1
BC9
BC1
BC9
BC1
A9
BC8
BC0
BC8
BC0
BC8
BC0
BC8
BC0
A8
Endpoint 2 slave FIFO
total byte count L
BC7
0
BC6
0
BC5
0
Endpoint 4 slave FIFO
total byte count H
Endpoint 4 slave FIFO
total byte count L
BC7
0
BC6
0
BC5
0
BC4
0
BC3
BC11
BC3
0
Endpoint 6 slave FIFO
total byte count H
Endpoint 6 slave FIFO
total byte count L
BC7
0
BC6
0
BC5
0
BC4
0
Endpoint 8 slave FIFO
total byte count H
Endpoint 8 slave FIFO
total byte count L
BC7
BC6
A14
A6
0
BC5
A13
A5
0
BC4
A12
A4
BC3
A11
A3
Setup Data Pointer high A15
address byte
xxxxxxxx RW
SUDPTRL
Setup Data Pointer low ad- A7
dress byte
A1
0
xxxxxxx0 bbbbbbbr
SUDPTRCTL
Setup Data Pointer Auto
Mode
0
0
0
0
0
SDPAUTO 00000001 RW
2
reserved
E6B8 8
SETUPDAT
8 bytes of setup data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
SETUPDAT[0] =
bmRequestType
SETUPDAT[1] =
bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] =
wLength
GPIF
E6C0 1
E6C1 1
GPIFWFSELECT
GPIFIDLECS
Waveform Selector
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0
FIFORD1
0
FIFORD0
IDLEDRV
11100100 RW
10000000 RW
GPIF Done, GPIF IDLE DONE
drive mode
0
0
0
0
0
E6C2 1
E6C3 1
E6C4 1
E6C5 1
GPIFIDLECTL
GPIFCTLCFG
Inactive Bus, CTL states
CTL Drive Type
0
0
CTL5
CTL5
0
CTL4
CTL4
0
CTL3
CTL3
0
CTL2
CTL2
0
CTL1
CTL1
0
CTL0
11111111 RW
00000000 RW
00000000 RW
00000000 RW
TRICTL
0
0
CTL0
[9]
GPIFADRH
GPIF Address H
0
GPIFA8
GPIFA0
[9]
GPIFADRL
GPIF Address L
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
FLOWSTATE
FLOWSTATE
E6C6 1
Flowstate Enable and
Selector
FSE
0
0
0
0
FS2
FS1
FS0
00000000 brrrrbbb
E6C7 1
E6C8 1
FLOWLOGIC
Flowstate Logic
LFUNC1
CTL0E3
LFUNC0
CTL0E2
TERMA2
TERMA1
TERMA0
CTL3
TERMB2
CTL2
TERMB1
CTL1
TERMB0
CTL0
00000000 RW
00000000 RW
FLOWEQ0CTL
CTL-Pin States in
Flowstate
(when Logic = 0)
CTL0E1/
CTL5
CTL0E0/
CTL4
E6C9 1
E6CA 1
FLOWEQ1CTL
CTL-Pin States in Flow- CTL0E3
state (when Logic = 1)
CTL0E2
CTL0E1/
CTL5
CTL0E0/
CTL4
CTL3
CTL2
CTL1
CTL0
00000000 RW
00000000 RW
FLOWHOLDOFF
Holdoff Configuration
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE HOCTL2
0
HOCTL1
HOCTL0
Document #: 38-08039 Rev. *B
Page 26 of 50
CY7C64713/14
Table 6-1. FX1 Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
0
b2
b1
b0
Default
Access
E6CB 1
FLOWSTB
Flowstate Strobe
Configuration
SLAVE
RDYASYNC CTLTOGL
SUSTAIN
MSTB2
MSTB1
MSTB0
00100000 RW
E6CC 1
FLOWSTBEDGE
Flowstate Rising/Falling
Edge Configuration
0
0
0
0
0
0
FALLING
RISING
00000001 rrrrrrbb
E6CD 1
E6CE 1
FLOWSTBPERIOD Master-Strobe Half-Period D7
[9]
D6
D5
D4
D3
D2
D1
D0
00000010 RW
00000000 RW
GPIFTCB3
GPIFTCB2
GPIFTCB1
GPIFTCB0
GPIF Transaction Count TC31
Byte 3
TC30
TC29
TC28
TC27
TC26
TC25
TC24
[9]
[9]
[9]
E6CF 1
E6D0 1
E6D1 1
2
GPIF Transaction Count TC23
Byte 2
TC22
TC14
TC6
TC21
TC13
TC5
TC20
TC12
TC4
TC19
TC11
TC3
TC18
TC10
TC2
TC17
TC9
TC1
TC16
TC8
TC0
00000000 RW
00000000 RW
00000001 RW
00000000 RW
GPIF Transaction Count TC15
Byte 1
GPIF Transaction Count TC7
Byte 0
reserved
reserved
reserved
[9]
E6D2 1
E6D3 1
EP2GPIFFLGSEL
Endpoint 2 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP2GPIFPFSTOP Endpoint 2 GPIF stop
FIFO2FLAG 00000000 RW
transaction on prog. flag
[9]
E6D4 1
3
EP2GPIFTRIG
reserved
Endpoint 2 GPIF Trigger
x
x
xxxxxxxx
W
reserved
reserved
[9]
E6DA 1
E6DB 1
EP4GPIFFLGSEL
Endpoint 4 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP4GPIFPFSTOP Endpoint 4 GPIF stop
FIFO4FLAG 00000000 RW
transaction on GPIF Flag
[9]
E6DC 1
3
EP4GPIFTRIG
reserved
Endpoint 4 GPIF Trigger
x
x
xxxxxxxx
W
reserved
reserved
[9]
E6E2 1
E6E3 1
EP6GPIFFLGSEL
Endpoint 6 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP6GPIFPFSTOP Endpoint 6 GPIF stop
FIFO6FLAG 00000000 RW
transaction on prog. flag
[9]
E6E4 1
3
EP6GPIFTRIG
reserved
Endpoint 6 GPIF Trigger
x
x
xxxxxxxx
W
reserved
reserved
[9]
E6EA 1
E6EB 1
EP8GPIFFLGSEL
Endpoint 8 GPIF Flag
select
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000 RW
EP8GPIFPFSTOP Endpoint 8 GPIF stop
FIFO8FLAG 00000000 RW
transaction on prog. flag
[9]
E6EC 1
3
EP8GPIFTRIG
reserved
Endpoint 8 GPIF Trigger
x
x
xxxxxxxx
W
E6F0 1
XGPIFSGLDATH
GPIF Data H
D15
D14
D6
D13
D12
D4
D4
0
D11
D3
D3
0
D10
D2
D2
0
D9
D1
D1
0
D8
D0
D0
0
xxxxxxxx RW
xxxxxxxx RW
(16-bit mode only)
E6F1 1
E6F2 1
E6F3 1
XGPIFSGLDATLX
Read/WriteGPIF Data L & D7
trigger transaction
D5
XGPIFSGLDATL-
NOX
Read GPIF Data L, no
transaction trigger
D7
D6
D5
xxxxxxxx
R
GPIFREADYCFG
InternalRDY, Sync/Async, INTRDY
RDY pin states
SAS
TCXRDY5
00000000 bbbrrrrr
E6F4 1
E6F5 1
E6F6 2
GPIFREADYSTAT
GPIFABORT
GPIF Ready Status
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx
xxxxxxxx
R
Abort GPIF Waveforms
W
reserved
ENDPOINT BUFFERS
E740 64 EP0BUF
E780 64 EP10UTBUF
E7C0 64 EP1INBUF
2048 reserved
EP0-IN/-OUT buffer
EP1-OUT buffer
EP1-IN buffer
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
xxxxxxxx RW
xxxxxxxx RW
xxxxxxxx RW
RW
F000 1023 EP2FIFOBUF
64/1023-byte EP 2 / slave D7
FIFO buffer (IN or OUT)
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx RW
F400 64 EP4FIFOBUF
64 byte EP 4 / slave FIFO D7
buffer (IN or OUT)
xxxxxxxx RW
F600 64 reserved
F800 1023 EP6FIFOBUF
64/1023-byte EP 6 / slave D7
FIFO buffer (IN or OUT)
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx RW
xxxxxxxx RW
FC00 64 EP8FIFOBUF
FE00 64 reserved
64 byte EP 8 / slave FIFO D7
buffer (IN or OUT)
xxxx
I²C Configuration Byte
0
DISCON
D6
0
0
0
0
0
400KHZ
D0
xxxxxxxx n/a
[[11]]
Special Function Registers (SFRs)
[10]
80
1
IOA
Port A (bit addressable) D7
D5
D4
D3
D2
D1
xxxxxxxx RW
Document #: 38-08039 Rev. *B
Page 27 of 50
CY7C64713/14
Table 6-1. FX1 Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
D3
A3
A11
A3
A11
0
b2
D2
A2
A10
A2
A10
0
b1
D1
A1
A9
A1
A9
0
b0
Default
Access
81
82
83
84
85
86
87
88
1
1
1
1
1
1
1
1
SP
Stack Pointer
D7
D6
A6
A14
A6
A14
0
D5
A5
A13
A5
A13
0
D4
A4
A12
A4
A12
0
D0
00000111 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00110000 RW
00000000 RW
DPL0
DPH0
Data Pointer 0 L
Data Pointer 0 H
Data Pointer 1 L
Data Pointer 1 H
Data Pointer 0/1 select
Power Control
A7
A0
A15
A7
A8
[10]
DPL1
DPH1
A0
[10]
A15
0
A8
[10]
DPS
SEL
IDLE
IT0
PCON
TCON
SMOD0
TF1
x
1
1
x
x
x
Timer/Counter Control
(bit addressable)
TR1
TF0
TR0
IE1
IT1
IE0
89
1
TMOD
Timer/Counter Mode
Control
GATE
CT
M1
M0
GATE
CT
M1
M0
00000000 RW
8A
8B
8C
8D
8E
8F
90
91
92
1
1
1
1
1
1
1
1
1
TL0
Timer 0 reload L
Timer 1 reload L
Timer 0 reload H
Timer 1 reload H
Clock Control
D7
D7
D15
D15
x
D6
D6
D14
D14
x
D5
D4
D3
D2
D1
D0
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000001 RW
TL1
D5
D4
D3
D2
D1
D0
TH0
D13
D13
T2M
D12
D12
T1M
D11
D11
T0M
D10
D10
MD2
D9
D8
TH1
D9
D8
[10]
CKCON
MD1
MD0
reserved
[10]
IOB
Port B (bit addressable) D7
External Interrupt Flag(s) IE5
D6
D5
D4
D3
1
D2
0
D1
0
D0
0
xxxxxxxx RW
00001000 RW
00000000 RW
[10]
EXIF
IE4
A14
I²CINT
A13
USBNT
A12
[10]
MPAGE
Upper Addr Byte of MOVX A15
using @R0 / @R1
A11
A10
A9
A8
93
98
5
1
reserved
SCON0
Serial Port 0 Control
(bit addressable)
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000 RW
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A8
1
1
1
1
1
1
1
1
1
1
5
1
SBUF0
Serial Port 0 Data Buffer D7
Autopointer 1 Address H A15
Autopointer 1 Address L A7
D6
D5
D4
D3
D2
D1
A9
A1
D0
A8
A0
00000000 RW
00000000 RW
00000000 RW
[10]
AUTOPTRH1
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
[10]
AUTOPTRL1
reserved
[10]
AUTOPTRH2
Autopointer 2 Address H A15
Autopointer 2 Address L A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000 RW
00000000 RW
[10]
AUTOPTRL2
reserved
[10]
IOC
Port C (bit addressable) D7
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
xxxxxxxx RW
[10]
INT2CLR
Interrupt 2 clear
Interrupt 4 clear
x
x
xxxxxxxx
xxxxxxxx
W
W
[10]
INT4CLR
x
x
x
x
x
x
x
reserved
IE
Interrupt Enable
(bit addressable)
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000 RW
A9
AA
1
1
reserved
[10]
EP2468STAT
Endpoint 2,4,6,8 status
flags
EP8F
EP8E
EP6F
EP6E
EP4F
EP4E
EP2F
EP2E
01011010
00100010
01100110
R
R
R
AB
AC
1
1
EP24FIFOFLGS
[10]
Endpoint 2,4 slave FIFO
status flags
0
0
EP4PF
EP8PF
EP4EF
EP8EF
EP4FF
EP8FF
0
0
EP2PF
EP6PF
EP2EF
EP6EF
EP2FF
EP6FF
EP68FIFOFLGS
[10]
Endpoint 6,8 slave FIFO
status flags
AD
AF
B0
B1
2
1
1
1
reserved
[10]
AUTOPTRSETUP
Autopointer 1&2 setup
0
0
0
0
0
APTR2INC APTR1INC APTREN
00000110 RW
xxxxxxxx RW
xxxxxxxx RW
[10]
IOD
Port D (bit addressable) D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
[10]
IOE
Port E
(NOT bit addressable)
D7
[10]
B2
B3
B4
B5
B6
B7
B8
1
1
1
1
1
1
1
OEA
Port A Output Enable
Port B Output Enable
Port C Output Enable
Port D Output Enable
Port E Output Enable
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
00000000 RW
00000000 RW
00000000 RW
00000000 RW
00000000 RW
[10]
OEB
[10]
OEC
[10]
OED
[10]
OEE
reserved
IP
Interrupt Priority (bit ad-
dressable)
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000 RW
B9
BA
1
1
reserved
[10]
EP01STAT
Endpoint 0&1 Status
0
0
0
0
0
0
0
0
0
EP1INBSY EP1OUTBS EP0BSY
Y
00000000 R
[10] [9]
BB
1
GPIFTRIG
Endpoint 2,4,6,8 GPIF
slave FIFO Trigger
DONE
RW
EP1
EP0
10000xxx brrrrbbb
BC
BD
1
1
reserved
[10]
GPIFSGLDATH
GPIF Data H (16-bit mode D15
only)
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx RW
xxxxxxxx RW
[10]
BE
BF
1
1
GPIFSGLDATLX
GPIFSGLDAT
GPIF Data L w/ Trigger D7
GPIF Data L w/ No TriggerD7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
R
[10]
LNOX
[10]
C0
1
SCON1
Serial Port 1 Control (bit SM0_1
addressable)
SM1_1
D6
SM2_1
D5
REN_1
D4
TB8_1
D3
RB8_1
D2
TI_1
D1
RI_1
D0
00000000 RW
00000000 RW
[10]
C1
C2
1
6
SBUF1
Serial Port 1 Data Buffer D7
reserved
Notes:
11. If no EEPROM is detected by the SIE then the default is 00000000.
Document #: 38-08039 Rev. *B
Page 28 of 50
CY7C64713/14
Table 6-1. FX1 Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
C8
1
T2CON
Timer/Counter 2 Control TF2
(bit addressable)
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000 RW
C9
CA
1
1
reserved
RCAP2L
Capture for Timer 2, auto- D7
reload, up-counter
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
00000000 RW
00000000 RW
CB
1
RCAP2H
Capture for Timer 2, auto- D7
reload, up-counter
CC
CD
CE
D0
1
1
2
1
TL2
Timer 2 reload L
Timer 2 reload H
D7
D6
D5
D4
D3
D2
D1
D9
D0
D8
00000000 RW
00000000 RW
TH2
D15
D14
D13
D12
D11
D10
reserved
PSW
Program Status Word (bit CY
addressable)
AC
F0
RS1
RS0
OV
F1
P
00000000 RW
D1
D8
D9
E0
7
1
7
1
reserved
[10]
EICON
reserved
ACC
External Interrupt Control SMOD1
1
ERESI
D5
RESI
D4
INT6
D3
0
0
0
01000000 RW
00000000 RW
Accumulator (bit address- D7
able)
D6
D2
D1
D0
E1
E8
7
1
reserved
[10]
EIE
External Interrupt En-
able(s)
1
1
1
EX6
EX5
EX4
EI²C
EUSB
11100000 RW
E9
F0
F1
F8
7
1
7
1
reserved
B
B (bit addressable)
D7
1
D6
1
D5
1
D4
D3
D2
D1
D0
00000000 RW
11100000 RW
reserved
[10]
EIP
External Interrupt Priority
Control
PX6
PX5
PX4
PI²C
PUSB
F9
7
reserved
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Document #: 38-08039 Rev. *B
Page 29 of 50
CY7C64713/14
Max Output Current, per I/O port................................ 10 mA
7.0
Absolute Maximum Ratings
Max Output Current, all five I/O ports
(128- and 100-pin packages) ..................................... 50 mA
Storage Temperature ..................................–65°C to +150°C
Ambient Temperature with Power Supplied......0°C to +70°C
Supply Voltage to Ground Potential............... –0.5V to +4.0V
DC Input Voltage to Any Input Pin .......................... 5.25V[12]
8.0
Operating Conditions
TA (Ambient Temperature Under Bias)............. 0°C to +70°C
Supply Voltage ...........................................+3.15V to +3.45V
Ground Voltage ................................................................. 0V
FOSC (Oscillator or Crystal Frequency) ... 24 MHz ± 100 ppm
.................................................................. Parallel Resonant
DC Voltage Applied to Outputs
in High-Z State ..................................... –0.5V to VCC + 0.5V
Power Dissipation .................................................... 235 mW
Static Discharge Voltage.......................................... > 2000V
9.0
DC Characteristics
Table 9-1. DC Characteristics
Parameter Description
VCC Supply Voltage
VCC Ramp Up 0 to 3.3V
Conditions
Min.
3.15
200
2
Typ.
Max.
Unit
V
3.3
3.45
µs
V
VIH
VIL
Input HIGH Voltage
5.25
0.8
Input LOW Voltage
–0.5
2
V
VIH_X
VIL_X
II
Crystal input HIGH Voltage
Crystal input LOW Voltage
Input Leakage Current
Output Voltage HIGH
Output LOW Voltage
Output Current HIGH
Output Current LOW
Input Pin Capacitance
5.25
0.8
V
–0.05
V
0< VIN < VCC
±10
µA
V
VOH
VOL
IOH
IOL
IOUT = 4 mA
2.4
IOUT = –4 mA
0.4
4
V
mA
mA
pF
pF
µA
µA
mA
mA
mA
ms
µs
4
CIN
Except D+/D–
D+/D–
3.29
12.96
300
100
.5
10
15
ISUSP
Suspend Current
CY7C64714
Connected
380[13]
150[13]
1.2
Disconnected
Connected
Suspend Current
CY7C64713
Disconnected
8051 running, connected to USB
VCC min = 3.0V
.3
1.0
ICC
Supply Current
35
65
TRESET
Reset Time after Valid Power
Pin Reset after powered on
5.0
200
9.1
USB Transceiver
USB 2.0-compliant in full-speed mode.
Note:
12. It is recommended to not power I/O when chip power is off.
13. Measured at Max VCC, 25ºC.
Document #: 38-08039 Rev. *B
Page 30 of 50
CY7C64713/14
10.0
10.1
AC Electrical Characteristics
USB Transceiver
USB 2.0-compliant in full-speed mode.
10.2
Program Memory Read
tCL
CLKOUT[14]
tAV
tAV
A[15..0]
tSTBH
tSTBL
PSEN#
D[7..0]
[15]
tACC1
tDH
data in
tSOEL
OE#
CS#
tSCSL
Figure 10-1. Program Memory Read Timing Diagram
Table 10-1. Program Memory Read Parameters
Parameter Description
tCL 1/CLKOUT Frequency
Min.
Typ.
20.83
41.66
83.2
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
48 MHz
24 MHz
12 MHz
tAV
Delay from Clock to Valid Address
Clock to PSEN Low
Clock to PSEN High
Clock to OE Low
0
0
0
10.7
8
tSTBL
tSTBH
tSOEL
tSCSL
tDSU
tDH
8
11.1
13
Clock to CS Low
Data Setup to Clock
Data Hold Time
9.6
0
Notes:
14. CLKOUT is shown with positive polarity.
15. ACC1 is computed from the above parameters as follows:
t
tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.
Document #: 38-08039 Rev. *B
Page 31 of 50
CY7C64713/14
10.3
Data Memory Read
tCL
Stretch = 0
CLKOUT[14]
tAV
tAV
A[15..0]
tSTBH
tSTBL
RD#
tSCSL
CS#
OE#
tSOEL
tDSU
[16
tDH
tACC1
D[7..0]
data in
Stretch = 1
tCL
CLKOUT[14]
tAV
A[15..0]
RD#
CS#
tDSU
tDH
[16]
tACC1
D[7..0]
data in
Figure 10-2. Data Memory Read Timing Diagram
Table 10-2. Data Memory Read Parameters
Parameter Description
tCL 1/CLKOUT Frequency
Min.
Typ.
20.83
41.66
83.2
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
48 MHz
24 MHz
12 MHz
tAV
Delay from Clock to Valid Address
Clock to RD LOW
10.7
11
tSTBL
tSTBH
tSCSL
tSOEL
tDSU
Clock to RD HIGH
11
Clock to CS LOW
13
Clock to OE LOW
11.1
Data Setup to Clock
Data Hold Time
9.6
0
tDH
Note:
16.
tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
Document #: 38-08039 Rev. *B
Page 32 of 50
CY7C64713/14
10.4
Data Memory Write
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
CS#
tSCSL
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
A[15..0]
tAV
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Figure 10-3. Data Memory Write Timing Diagram
Table 10-3. Data Memory Write Parameters
Parameter Description
Min.
Max.
10.7
11.2
11.2
13.0
13.1
13.1
Unit
ns
Notes
tAV
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
0
0
0
tSTBL
tSTBH
tSCSL
tON1
ns
ns
ns
0
0
ns
tOFF1
Clock to Data Hold Time
ns
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10.5
GPIF Synchronous Signals
tIFCLK
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
DATA(input)
valid
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N
N+1
tXGD
Figure 10-4. GPIF Synchronous Signals Timing Diagram[17]
Table 10-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[18, 19]
Parameter
tIFCLK
Description
Min.
20.83
8.9
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
RDYX to Clock Setup Time
Clock to RDYX
GPIF Data to Clock Setup Time
GPIF Data Hold Time
9.2
0
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
7.5
11
6.7
Table 10-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[19]
Parameter
tIFCLK
Description
Min.
20.83
2.9
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
200
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
RDYX to Clock Setup Time
Clock to RDYX
3.7
GPIF Data to Clock Setup Time
GPIF Data Hold Time
3.2
4.5
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
11.5
15
10.7
Notes:
17. Dashed lines denote signals with programmable polarity.
18. GPIF asynchronous RDYx signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
19. IFCLK must not exceed 48 MHz.
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10.6
Slave FIFO Synchronous Read
tIFCLK
IFCLK
SLRD
tRDH
tSRD
tXFLG
FLAGS
DATA
N+1
tXFD
N
tOEon
tOEoff
SLOE
Figure 10-5. Slave FIFO Synchronous Read Timing Diagram[17]
Table 10-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[19]
Parameter
tIFCLK
Description
Min.
20.83
18.7
0
Max.
Unit
ns
IFCLK Period
tSRD
tRDH
tOEon
tOEoff
tXFLG
tXFD
SLRD to Clock Setup Time
ns
Clock to SLRD Hold Time
ns
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
10.5
10.5
9.5
ns
ns
ns
TBD
11
ns
Table 10-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[19]
Parameter
tIFCLK
Description
Min.
20.83
12.7
3.7
Max.
Unit
ns
IFCLK Period
200
tSRD
tRDH
tOEon
tOEoff
tXFLG
tXFD
SLRD to Clock Setup Time
ns
Clock to SLRD Hold Time
ns
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
10.5
10.5
13.5
15
ns
ns
ns
TBD
ns
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10.7
Slave FIFO Asynchronous Read
tRDpwh
SLRD
tRDpwl
tXFLG
tXFD
FLAGS
DATA
SLOE
N
N+1
tOEon
tOEoff
Figure 10-6. Slave FIFO Asynchronous Read Timing Diagram[17]
Table 10-8. Slave FIFO Asynchronous Read Parameters[20]
Parameter Description
tRDpwl SLRD Pulse Width LOW
Min.
50
Max.
Unit
ns
tRDpwh
tXFLG
tXFD
SLRD Pulse Width HIGH
50
ns
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
70
15
ns
ns
tOEon
tOEoff
10.5
10.5
ns
ns
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10.8
Slave FIFO Synchronous Write
tIFCLK
IFCLK
SLWR
tWRH
tSWR
DATA
Z
N
Z
tSFD tFDH
FLAGS
tXFLG
Figure 10-7. Slave FIFO Synchronous Write Timing Diagram[17]
Table 10-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK [19]
Parameter
tIFCLK
Description
Min.
20.83
18.1
0
Max.
Unit
ns
IFCLK Period
tSWR
tWRH
tSFD
SLWR to Clock Setup Time
ns
Clock to SLWR Hold Time
ns
FIFO Data to Clock Setup Time
Clock to FIFO Data Hold Time
Clock to FLAGS Output Propagation Time
9.2
ns
tFDH
tXFLG
0
ns
9.5
ns
Table 10-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [19]
Parameter
tIFCLK
Description
Min.
20.83
12.1
3.6
Max.
Unit
ns
IFCLK Period
200
tSWR
tWRH
tSFD
tFDH
SLWR to Clock Setup Time
ns
Clock to SLWR Hold Time
ns
FIFO Data to Clock Setup Time
Clock to FIFO Data Hold Time
Clock to FLAGS Output Propagation Time
3.2
ns
4.5
ns
tXFLG
13.5
ns
Note:
20. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
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10.9
Slave FIFO Asynchronous Write
tWRpwh
SLWR/SLCS#
tWRpwl
tFDH
tSFD
DATA
tXFD
FLAGS
Figure 10-8. Slave FIFO Asynchronous Write Timing Diagram[17]
Table 10-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [20]
Parameter
tWRpwl
tWRpwh
tSFD
Description
Min.
50
Max.
Unit
ns
SLWR Pulse LOW
SLWR Pulse HIGH
70
ns
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
10
ns
tFDH
10
ns
tXFD
SLWR to FLAGS Output Propagation Delay
70
ns
10.10 Slave FIFO Synchronous Packet End Strobe
IFCLK
tPEH
PKTEND
FLAGS
tSPE
tXFLG
Figure 10-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram[17]
Table 10-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK [19]
Parameter
tIFCLK
Description
Min.
20.83
14.6
0
Max.
Unit
ns
IFCLK Period
tSPE
tPEH
tXFLG
PKTEND to Clock Setup Time
ns
Clock to PKTEND Hold Time
ns
Clock to FLAGS Output Propagation Delay
9.5
ns
Table 10-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK [19]
Parameter
tIFCLK
Description
Min.
20.83
8.6
Max.
Unit
ns
IFCLK Period
200
tSPE
tPEH
tXFLG
PKTEND to Clock Setup Time
ns
Clock to PKTEND Hold Time
2.5
ns
Clock to FLAGS Output Propagation Delay
13.5
ns
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is that the set-
up time tSPE and the hold time tPEH for PKTEND must be met.
Although typically there are no specific timing requirements for
asserting PKTEND in relation to SLWR, there exists a specific
Document #: 38-08039 Rev. *B
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corner case condition that needs attention. While using the
PKTEND to commit a one byte/word packet, an additional
timing requirement needs to be met when the FIFO is
configured to operate in auto mode and it is desired to send
two packets back to back:
scenario. X is the value the AUTOINLEN register is set to
when the IN endpoint is configured to be in auto mode.
Figure 10-10 shows a scenario where two packets are being
committed. The first packet gets comitted automatically when
the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
there is atleast one IFCLK cycle timing between asserting
PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
• A full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by
• Ashortonebyte/wordpacketcommittedmanuallyusingthe
PKTEND pin.
In this particular scenario, the developer must make sure to
assert PKTEND at least one clock cycle after the rising edge
that caused the last byte/word to be clocked into the previous
auto committed packet. Figure 10-10 below shows this
t
IFCLK
IFCLK
t
t
SFA
FAH
FIFOADR
>= t
WRH
>= t
SWR
SLWR
DATA
t
t
t
FDH
t
t
t
FDH
t
t
t
SFD
t
SFD
FDH
t
SFD
t
SFD
FDH
SFD
SFD
FDH
FDH
X-4
X-2
X-1
1
X-3
X
Atleast one IFCLK cycle
t
SPE
t
PEH
PKTEND
Figure 10-10. Slave FIFO Synchronous Write Sequence and Timing Diagram
10.11 Slave FIFO Asynchronous Packet End Strobe
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Figure 10-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[17]
Table 10-14. Slave FIFO Asynchronous Packet End Strobe Parameters[20]
Parameter Description
Min.
50
Max.
Unit
ns
tPEpwl PKTEND Pulse Width LOW
tPWpwh
tXFLG
PKTEND Pulse Width HIGH
50
ns
PKTEND to FLAGS Output Propagation Delay
115
ns
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10.12 Slave FIFO Output Enable
SLOE
tOEoff
tOEon
DATA
Figure 10-12. Slave FIFO Output Enable Timing Diagram[17]
Table 10-15. Slave FIFO Output Enable Parameters
Parameter
tOEon
tOEoff
Description
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
Min.
Max.
Unit
ns
10.5
10.5
ns
10.13 Slave FIFO Address to Flags/Data
FIFOADR [1.0]
FLAGS
tXFLG
tXFD
DATA
N
N+1
Figure 10-13. Slave FIFO Address to Flags/Data Timing Diagram[17]
Table 10-16. Slave FIFO Address to Flags/Data Parameters
Parameter
tXFLG
tXFD
Description
Min.
Max.
10.7
14.3
Unit
ns
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
ns
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10.14 Slave FIFO Synchronous Address
IFCLK
SLCS/FIFOADR [1:0]
tSFA
tFAH
Figure 10-14. Slave FIFO Synchronous Address Timing Diagram
Table 10-17. Slave FIFO Synchronous Address Parameters [19]
Parameter Description
tIFCLK Interface Clock Period
tSFA
tFAH
Min.
20.83
25
Max.
200
Unit
ns
FIFOADR[1:0] to Clock Setup Time
Clock to FIFOADR[1:0] Hold Time
ns
10
ns
10.15 Slave FIFO Asynchronous Address
SLCS/FIFOADR [1:0]
tFAH
tSFA
RD/WR/PKTEND
Figure 10-15. Slave FIFO Asynchronous Address Timing Diagram[17]
Table 10-18. Slave FIFO Asynchronous Address Parameters[20]
Parameter
Description
Min.
10
Max.
Unit
ns
tSFA
tFAH
FIFOADR[1:0] to RD/WR/PKTEND Setup Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
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10.16 Sequence Diagram
10.16.1 Single and Burst Synchronous Read Example
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
T=0
tSRD
tRDH
>= tSRD
>= tRDH
SLRD
SLCS
t=3
t=2
T=3
T=2
tXFLG
FLAGS
DATA
SLOE
tXFD
N+1
tXFD
tXFD
tXFD
N+4
Data Driven: N
tOEon
N+2
N+3
N+1
tOEon
tOEoff
tOEoff
t=4
T=4
T=1
t=1
Figure 10-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
IFCLK
N
IFCLK
N
IFCLK
N+1
IFCLK
N+1
IFCLK
N+1
IFCLK
N+2
IFCLK
N+3
IFCLK
N+4
IFCLK
N+4
IFCLK
N+4
FIFO POINTER
SLOE
SLRD
SLOE
SLRD
SLOE
Not Driven
SLRD
SLRD
N+4
SLOE
FIFO DATA BUS Not Driven
Driven: N
N+1
N+1
N+2
N+3
N+4
Not Driven
Figure 10-17. Slave FIFO Synchronous Sequence of Events Diagram
Figure 10-16 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
with SLRD, or before SLRD is asserted (i.e. the SLCS and
SLRD signals must both be asserted to start a valid read
condition).
• TheFIFOpointerisupdatedontherisingedgeoftheIFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge
of IFCLK) the new data value is present. N is the first data
value read from the FIFO. In order to have data on the FIFO
data bus, SLOE MUST also be asserted.
• At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note: tSFA has a minimum of 25 nsec. This means when
IFCLK is running at 48 MHz, the FIFO address setup time
is more than one IFCLK cycle.
• At = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
valueintheFIFO. Note: thedataispre-fetchedandisdriven
on the bus when SLOE is asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T=0 through 5. Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the data bus. During the first read cycle, on the rising edge
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incre-
mented and the next data value is placed on the data bus.
• At t = 2, SLRD is asserted. SLRD must meet the setup time
of tSRD (time from asserting the SLRD signal to the rising
edge of the IFCLK) and maintain a minimum hold time of
t
RDH (time from the IFCLK edge to the de-assertion of the
SLRDsignal).IftheSLCSsignalisused,itmustbeasserted
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10.16.2 Single and Burst Synchronous Write
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
>= tWRH
t=0
tSWR
tWRH
>= tSWR
T=0
SLWR
SLCS
T=2
T=5
tXFLG
tFDH
t=2
t=3
tXFLG
FLAGS
DATA
tSFD
tFDH
tFDH
tSFD
N+2
tSFD
N+1
tFDH
tSFD
N+3
N
T=4
T=3
t=1
T=1
tSPE
tPEH
PKTEND
Figure 10-18. Slave FIFO Synchronous Write Sequence and Timing Diagram[17]
The Figure 10-18 shows the timing relationship of the SLAVE
FIFO signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
of IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 10-18, once the four bytes are written to the
FIFO, SLWR is de-asserted. The short 4-byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met
for asserting PKTEND signal with regards to asserting the
SLWR signal. PKTEND can be asserted with the last data
value or thereafter. The only consideration is the setup time
tSPE and the hold time tPEH must be met. In the scenario of
Figure 10-18, the number of data values committed includes
the last value written to the FIFO. In this example, both the
data value and the PKTEND signal are clocked on the same
rising edge of IFCLK. PKTEND can be asserted in subsequent
clock cycles. The FIFOADDR lines should be held constant
during the PKTEND assertion.
• At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications)
Note:tSFAhasaminimumof25ns. This meanswhenIFCLK
is running at 48 MHz, the FIFO address setup time is more
than one IFCLK cycle.
• At t = 1, the external master/peripheral must outputs the
data value onto the data bus with a minimum set up time of
t
SFD before the rising edge of IFCLK.
• At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SLWR signal to the
rising edge of IFCLK) and maintain a minimum hold time of
tWRH (time from the IFCLK edge to the de-assertion of the
SLWR signal). If SLCS signal is used, it must be asserted
with SLWR or before SLWR is asserted. (i.e. the SLCS and
SLWR signals must both be asserted to start a valid write
condition).
Although there are no specific timing requirement for asserting
PKTEND, there is a specific corner case condition that needs
attention while using the PKTEND to commit a one byte/word
packet. Additional timing requirements exists when the FIFO
is configured to operate in auto mode and it is desired to send
two packets: a full packet (full defined as the number of bytes
in the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte/word
packet committed manually using the PKTEND pin. In this
case, the external master must make sure to assert the
PKTEND pin atleast one clock cycle after the rising edge that
caused the last byte/word to be clocked into the previous auto
committed packet ( the packet with the number of bytes equal
to what is set in the AUTOINLEN register). Refer to section 10-
10 for further details on this timing.
• While the SLWR is asserted, data is written to the FIFO and
on the rising edge of the IFCLK, the FIFO pointer is incre-
mented. The FIFO flag will also be updated after a delay of
t
XFLG from the rising edge of the clock.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T=0 through 5.
Note: For the burst mode, SLWR and SLCS are left asserted
for the entire duration of writing all the required data values. In
this burst write mode, once the SLWR is asserted, the data on
the FIFO data bus is written to the FIFO on every rising edge
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10.16.3 Sequence Diagram of a Single and Burst Asynchronous Read
tFAH
tSFA
tSFA
tFAH
FIFOADR
t=0
tRDpwl tRDpwh
tRDpwl
tRDpwl
tRDpwl tRDpwh
tRDpwh
tRDpwh
T=0
SLRD
SLCS
t=3
t=2
T=2
T=3
T=5
T=4
T=6
tXFLG
tXFLG
FLAGS
DATA
SLOE
tXFD
tXFD
tXFD
tXFD
N+3
Data (X)
Driven
N
N+1
N+2
N
tOEon
tOEoff
tOEoff
tOEon
t=4
T=1
T=7
t=1
Figure 10-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
SLOE
SLRD
SLRD
SLOE
SLOE
SLRD
N+1
SLRD
N+1
SLRD
N+2
SLRD
SLOE
FIFO POINTER
N
N
N
N
N+1
N
N+1
N+2
N+3
N+2
N+3
FIFO DATA BUS Not Driven
Driven: X
Not Driven
N
N+1
N+1
N+2
Not Driven
Figure 10-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
Figure 10-19 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
• The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propa-
gation delay of tXFD from the activating edge of SLRD. In
Figure 10-19, data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read
cycle(i.e.SLRDisasserted),SLOEMUSTbeinanasserted
state. SLRD and SLOE can also be tied together.
• At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
• At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven onto the bus is previous data,
it data that was in the FIFO from a prior read cycle.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
• At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of tRDpwl and minimum de-active
pulse width of tRDpwh. If SLCS is used then, SLCS must be
in asserted with SLRD or before SLRD is asserted. (i.e. the
SLCS and SLRD signals must both be asserted to start a
valid read condition.)
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10.16.4 Sequence Diagram of a Single and Burst Asynchronous Write
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
T=0
tWRpwl tWRpwh
tWRpwl
tWRpwl
tWRpwl
tWRpwh
tWRpwh
tWRpwh
SLWR
SLCS
t =1
t=3
T=1
T=4
T=3
T=7
T=6
T=9
tXFLG
tXFLG
FLAGS
DATA
tSFD tFDH
N
tSFD tFDH
N+1
tSFD tFDH
N+2
tSFD
tFDH
N+3
t=2
T=8
T=2
T=5
tPEpwl
tPEpwh
PKTEND
Figure 10-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram[17]
Figure 10-21 diagrams the timing relationship of the SLAVE FIFO write in an asynchronous mode. The diagram shows a single
write followed by a burst write of 3 bytes and committing the 4-byte-short packet using PKTEND.
·At t = 0 the FIFO address is applied, insuring that it meets the setup time of tSFA. If SLCS is used, it must also be asserted (SLCS
may be tied low in some applications).
·At t = 1 SLWR is asserted. SLWR must meet the minimum active pulse of tWRpwl and minimum de-active pulse width of tWRpwh
.
If the SLCS is used, it must be in asserted with SLWR or before SLWR is asserted.
·At t = 2, data must be present on the bus tSFD before the de-asserting edge of SLWR.
·At t = 3, deasserting SLWR will cause the data to be written from the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after tXFLG from the de-asserting edge of SLWR.
The same sequence of events are shown for a burst write and is indicated by the timing marks of T = 0 through 5. Note: In the
burst write mode, once SLWR is deasserted, the data is written to the FIFO and then the FIFO pointer is incremented to the next
byte in the FIFO. The FIFO pointer is post incremented.
In Figure 10-21 once the four bytes are written to the FIFO and SLWR is deasserted, the short 4-byte packet can be committed
to the host using the PKTEND. The external device should be designed to not assert SLWR and the PKTEND signal at the same
time. It should be designed to assert the PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The
FIFOADDR lines are to be held constant during the PKTEND assertion.
11.0
Ordering Information
Table 11-1. Ordering Information
8051
Address
/Data Busses
Ordering Code
Package Type
RAM Size
# Prog I/Os
Ideal for battery powered applications
CY7C64714-128AXC
CY7C64714-100AXC
CY7C64714-56LFXC
128 TQFP – Lead-Free
100 TQFP – Lead-Free
56 QFN – Lead-Free
16K
16K
16K
40
40
24
16/8 bit
–
–
Ideal for non-battery powered applications
CY7C64713-128AXC
CY7C64713-100AXC
CY7C64713-56LFXC
CY3674
128 TQFP - Lead-Free
16K
16K
16K
40
40
24
16/8 bit
100 TQFP - Lead-Free
56 QFN - Lead-Free
-
-
EZ-USB FX1 Development Kit
Document #: 38-08039 Rev. *B
Page 45 of 50
CY7C64713/14
12.0
Package Diagrams
The FX1 is available in three packages:
• 56-pin QFN
• 100-pin TQFP
• 128-pin TQFP
Package Diagrams
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.08[0.003]
C
1.00[0.039] MAX.
7.90[0.311]
A
8.10[0.319]
0.05[0.002] MAX.
0.80[0.031] MAX.
0.18[0.007]
0.28[0.011]
7.70[0.303]
7.80[0.307]
0.20[0.008] REF.
PIN1 ID
N
N
0.20[0.008] R.
1
1
2
2
0.45[0.018]
0.80[0.031]
DIA.
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0.30[0.012]
0.50[0.020]
0.24[0.009]
(4X)
0.60[0.024]
0°-12°
0.50[0.020]
6.45[0.254]
6.55[0.258]
C
SEATING
PLANE
51-85144-*D
Figure 12-1. 56-Lead QFN 8 x 8 mm LF56A
Document #: 38-08039 Rev. *B
Page 46 of 50
CY7C64713/14
Package Diagrams (continued)
51-85050-*A
Figure 12-2. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
Document #: 38-08039 Rev. *B
Page 47 of 50
CY7C64713/14
Package Diagrams (continued)
51-85101-*B
Figure 12-3. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
For further information on this package design please refer to
the application note Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology. This application note can
be downloaded from AMKOR’s website from the following
URL
http://www.amkor.com/products/notes_papers/MLF_AppNote
_0902.pdf. The application note provides detailed information
on board mounting guidelines, soldering flow, rework process,
etc.
13.0
Quad Flat Package No Leads (QFN)
Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the FX1 through the device’s metal
paddle on the bottom side of the package. Heat from here, is
conducted to the PCB at the thermal pad. It is then conducted
from the thermal pad to the PCB inner ground plane by a 5 x 5
array of via. A via is a plated through hole in the PCB with a
finished diameter of 13 mil. The QFN’s metal die paddle must
be soldered to the PCB’s thermal pad. Solder mask is placed
on the board top side over each via to resist solder flow into
the via. The mask on the top side also minimizes outgassing
during the solder reflow process.
Figure 13-1 below displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean” type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow.
Document #: 38-08039 Rev. *B
Page 48 of 50
CY7C64713/14
Figure 13-2 is a plot of the solder mask pattern and Figure 13-3 displays an X-Ray image of the assembly (darker areas indicate
solder).
0.017” dia
Solder Mask
Cu Fill
Cu Fill
0.013” dia
PCB Material
PCB Material
Via hole for thermally connecting the
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
QFN to the circuit board ground plane.
Figure 13-1. Cross-section of the Area Underneath the QFN Package
Figure 13-2. Plot of the Solder Mask (White Area)
Figure 13-3. X-ray Image of the Assembly
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. EZ-USB FX1, EZ-USB FX2LP, EZ-USB FX2, andReNumerationare trademarks, andEZ-USB is a registered
trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their
respective holders.
Document #: 38-08039 Rev. *B
Page 49 of 50
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
CY7C64713/14
Document History Page
Document Title: CY7C64713/4 EZ-USB FX1™ USB Microcontroller Full-Speed USB Peripheral Controller
Document Number: 38-08039
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
132091
230709
02/10/04
KKU
KKU
New Data Sheet
*A
SEE ECN
Changed Lead free Marketing part numbers in Table 11-1 according to spec
change in 28-00054.
*B
307474
SEE ECN
BHA
Changed default PID in Table 4-2.
Updated register table.
Removed word compatible where associated with I2C.
Changed Set-up to Setup.
Added Power Dissipation.
Changed Vcc from ± 10% to ± 5%
Added values for VIH_X, VIL_X
Added values for ICC
Added values for ISUSP
Removed IUNCONFIGURED from table 9-1
Changed PKTEND to FLAGS output propagation delay (asynchronous
interface) in Table 10-14 from a maximum value of 70 ns to 115 ns.
Removed 56 SSOP and added 56 QFN package
Provided additional timing restrictions and requirement regarding the use of
PKTEND pintocommitashortonebyte/wordpacketsubsequent tocommitting
a packet automatically (when in auto mode).
Added part number CY7C64714 ideal for battery powered applications.
Changed Supply Voltage in section 8 to read +3.15V to +3.45V
Added Min Vcc Ramp Up time (0 to 3.3v)
Removed Preliminary
Document #: 38-08039 Rev. *B
Page 50 of 50
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
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