CY3692 [CYPRESS]
200-MHz Field Programmable Zero Delay Buffer; 200 - MHz的现场可编程零延迟缓冲器
| 型号： | CY3692 |
| 厂家： | 
CYPRESS |
| 描述： | 200-MHz Field Programmable Zero Delay Buffer |
| 文件： | 总10页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY23FP12
200-MHz Field Programmable Zero Delay Buffer
Features
Functional Description
• Fully field-programmable
— Input and output dividers
— Inverting/noninverting outputs
The CY23FP12 is a high-performance fully field-program-
mable 200 MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using
high-performance ASICs and microprocessors.
— Phase-locked loop (PLL) or fanout buffer configu-
ration
The CY23FP12 is fully programmable via volume or prototype
programmers enabling the user to define an appli-
cation-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in
Table 2, and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
allows for the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon.
The CY23FP12 also features a proprietary auto-power-down
circuit that shuts down the device in case of a REF failure,
resulting in less than 50 µA of current draw.
• 10-MHz to 200-MHz operating range
• Split 2.5V or 3.3V outputs
• Two LVCMOS reference inputs
• Twelve low-skew outputs
— 35ps typ. output-to-output skew (same freq)
• 110 ps typ. cycle-cycle jitter (same freq)
• Three-stateable outputs
• < 50-µA shutdown current
• Spread Aware
• 28-pin SSOP
The CY23FP12 provides twelve outputs grouped in two banks
with separate power supply pins which can be connected
independently to either a 2.5V or a 3.3V rail.
• 3.3V operation
• Industrial temperature available
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source
when REFSEL is asserted/deasserted.
Pin Configuration
Block Diagram
SSOP
VDDA
VDDC
Top View
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
Lock Detect
1
28
27
26
25
24
23
22
21
20
REF2
REF1
REFSEL
2
FBK
CLKA0
CLKA1
3
CLKB0
4
CLKB1
5
VSSA
VSSB
CLKB2
REFSEL
REF1
6
CLKA2
CLKA3
VDDA
CLKA5
VSSA
VDDB
7
÷M
÷N
100 to
400MHz
PLL
CLKB3
÷1
÷2
÷3
÷4
÷X
REF2
8
VDDB
FBK
9
VSSA
VSSB
10
11
12
13
14
CLKB4
CLKB5
19
18
CLKA4
CLKA5
VDDA
VSSC
S1
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
VDDB
VDDC
S2
17
16
15
Test Logic
Function
Selection
VSSC
CLKB5
VSSB
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07246 Rev. *E
Revised December 13, 2004
CY23FP12
.
Pin Description
Pin
1
2
3
4
5
6
7
Name
I/O
Type
LVTTL/LVCMOS
LVTTL/LVCMOS
LVTTL
LVTTL
POWER
LVTTL
Description
REF2
REF1
CLKB0
CLKB1
VSSB
CLKB2
CLKB3
VDDB
I
I
O
O
PWR
O
O
PWR
PWR
O
Input reference frequency, 5V-tolerant input.
Input reference frequency, 5V-tolerant input.
Clock output, Bank B.
Clock output, Bank B.
Ground for Bank B.
Clock output, Bank B.
Clock output, Bank B.
2.5V or 3.3V supply, Bank B.
Ground for Bank B.
Clock output, Bank B.
Clock output, Bank B.
2.5V or 3.3V supply, Bank B.
3.3V core supply.
LVTTL
8
9
POWER
POWER
LVTTL
VSSB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
CLKB4
CLKB5
VDDB
O
LVTTL
PWR
PWR
I
POWER
POWER
LVTTL
VDDC
S2
S1
Select input.
Select input.
Ground for core.
I
LVTTL
VSSC
VDDA
CLKA5
CLKA4
VSSA
PWR
PWR
O
POWER
POWER
LVTTL
2.5V or 3.3V supply, Bank A.
Clock output, Bank A.
Clock output, Bank A.
Ground for Bank A.
2.5V or 3.3V supply Bank A.
Clock output, Bank A.
Clock output, Bank A.
Ground for Bank A.
O
LVTTL
PWR
PWR
O
O
PWR
O
O
I
I
POWER
POWER
LVTTL
LVTTL
POWER
LVTTL
LVTTL
LVTTL
LVTTL
VDDA
CLKA3
CLKA2
VSSA
CLKA1
CLKA0
FBK
Clock output, Bank A.
CLock output, Bank A.
PLL feedback input.
REFSEL
Reference select input. REFSEL = 0, REF1 is
selected. REFSEL = 1, REF2 is selected.
Document #: 38-07246 Rev. *E
Page 2 of 10
CY23FP12
CLKB5
CLKB4
/1,/2,/3,/4,
/x,/2x
/1,/2,/3,/4,
/x,/2x
CLKB3
CLKB2
Output
Function
Select
REF
FBK
/M
/N
CLKB1
CLKB0
/1,/2,/3,/4,
/x,/2x
PLL
CLKA5
CLKA4
/1,/2,/3,/4,
/x,/2x
Matrix
/1,/2,/3,/4,
/x,/2x
CLKA3
CLKA2
CLKA1
CLKA0
/1,/2,/3,/4,
/x,/2x
Figure 1. Basic PLL Block Diagram
Below is a list of independent functions that can be
programmed with a volume or prototype programmer on the
“default” silicon.
Table 1.
Configuration
Description
Default
DC Drive Bank A
Programs the drive strength of Bank A outputs. The user can select one out +16 mA
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
DC Drive Bank B
Programs the drive strength of Bank B outputs. The user can select one out +16 mA
of two possible drive strength settings that produce output DC currents in the
range of ±16 mA to ±20 mA.
Output Enable for Bank B clocks
Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled Enable
individually if not used, to minimize electromagnetic interference (EMI) and
switching noise.
Output Enable for Bank A clocks
Inv CLKA0
Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled Enable
individually if not used, to minimize EMI and switching noise.
Generates an inverted clock on the CLKA0 output. When this option is
Non-invert
Non-invert
Non-invert
Non-invert
Non-invert
programmed, CLKA0 and CLKA1 will become complimentary pairs.
Inv CLKA2
Generates an inverted clock on the CLKA2 output. When this option is
programmed, CLKA2 and CLKA3 will become complimentary pairs.
Inv CLKA4
Generates an inverted clock on the CLKA4 output. When this option is
programmed, CLKA4 and CLKA5 will become complimentary pairs.
Inv CLKB0
Generates an inverted clock on the CLKB0 output. When this option is
programmed, CLKB0 and CLKB1 will become complimentary pairs.
Inv CLKB2
Generates an inverted clock on the CLKB2 output. When this option is
programmed, CLKB2 and CLKB3 will become complimentary pairs.
Document #: 38-07246 Rev. *E
Page 3 of 10
CY23FP12
Table 1. (continued)
Configuration
Description
Default
Inv CLKB4
Generates an inverted clock on the CLKB4 output. When this option is
Non-invert
programmed, CLKB4 and CLKB5 will become complimentary pairs.
Pull-down Enable
Enables/Disables internal pulldowns on all outputs
Enable
Fbk Pull-down Enable
Enables/Disables internal pulldowns on the feedback path (applicable to both Enable
internal and external feedback topologies)
Fbk Sel
Selects between the internal and the external feedback topologies
External
Below is a list of independent functions, which can be
assigned to each of the four S1 and S2 combinations. When
a particular S1 and S2 combination is selected, the device will
assume the configuration (which is essentially a set of
functions given in Table 2, below) that has been preassigned
to that particular combination.
Table 2.
Function
Description
Default
Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair
Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair
Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair
Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair
Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair
Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair
Enable
Enable
Enable
Enable
Enable
Enable
Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising Enable
edges and shuts down the device in case of a reference “failure.” This failure is triggered
by a drift in reference frequency below a set limit. This auto power down circuit is
disabled internally when one or more of the outputs are configured to be driven directly
from the reference clock.
PLL Power-down
M[7:0]
Shuts down the PLL when the device is configured as a non-PLL fanout buffer.
PLL Enabled
Assigns an eight-bit value to reference divider –M. The divider can be any integer value 2
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
N[7:0]
X[6:0]
Assigns an eight-bit value to feedback divider –N. The divider can be any integer value 2
from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz.
Assigns a seven-bit value to output divider –X. The divider can be any integer value
from 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be
activated by the appropriate output mux setting.
1
Divider Source
CLKA54 Source
CLKA32 Source
CLKA10 Source
CLKB54 Source
CLKB32 Source
CLKB10 Source
Selects between the PLL output and the reference clock as the source clock for the
PLL
output dividers.
Independently selects one out of the eight possible output dividers that will connect to Divide by 2
the CLKA5 and CLKA4 pair. Please refer to Table 3 for a list of divider values.
Independently selects one out of the eight possible output dividers that will connect to Divide by 2
the CLKA3 and CLKA2 pair. Please refer to Table 3 for a list of divider values.
Independently selects one out of the eight possible output dividers that will connect to Divide by 2
the CLKA1 and CLKA0 pair. Please refer to Table 3 for a list of divider values.
Independently selects one out of the eight possible output dividers that will connect to Divide by 2
the CLKB5 and CLKB4 pair. Please refer to Table 3 for a list of divider values.
Independently selects one out of the eight possible output dividers that will connect to Divide by 2
the CLKB3 and CLKB2 pair. Please refer to Table 3 for a list of divider values.
Independently selects one out of the eight possible output dividers that will connect to Divide by 2
the CLKB1 and CLKB0 pair. Please refer to Table 3 for a list of divider values.
Document #: 38-07246 Rev. *E
Page 4 of 10
CY23FP12
Table 3 is a list of output dividers that are independently
CY3672 FTG Development Kit
selected to connect to each output pair.
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY23FP12 and
program samples and small prototype quantities. The kit
comes with the latest version of CyberClocks and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyberClocks can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
In the default (non-programmable) state of the device, S1 and
S2 pins will function, as indicated in Table 4.
Table 3.
CLKA/B Source
0 [000]
Output Connects To
REF
1 [001]
Divide by 1
2 [010]
Divide by 2
3 [011]
4 [100]
5 [101]
6 [110]
Divide by 3
Divide by 4
Divide by X
CY23FP12 Frequency Calculation
The CY23FP12 is an extremely flexible clock buffer with up to
twelve individual outputs, generated from an integrated PLL.
Divide by 2X[1]
TEST mode [LOCK signal][2]
There are four variables used to determine the final output
frequency. These are the input Reference Frequency M, the N
dividers, and the post divider X.
7 [111]
Table 4.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs pair has many output options available to it.
There are six post divider options: /1, /2, /3, /4, /X, and /2X.
The post divider options can be applied to the calculated PLL
frequency or to the REF directly. The feedback either is
connected to CLKA0 internally or connected to any output
externally.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
Output
S2
0
0
1
1
S1
0
1
0
1
CLKA[5:0]
Three-state
Driven
Driven
Driven
CLKB[5:0]
Three-state
Three-state
Driven
Source
PLL
PLL
Reference
PLL
Driven
Field Programming the CY23FP12
The CY23FP12 is programmed at the package level, i.e. in a
programmer socket. The CY23FP12 is flash-technology
based, so the parts can be reprogrammed up to 100 times.
This allows for fast and easy design changes and product
updates, and eliminates any issues with old and out-of-date
inventory.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
So the output can be calculated as following:
F
REF / M = FFBK / N.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large production quantities.
FPLL = (FREF * N * post divider)/M.
FOUT = FPLL / post divider.
In addition to above divider options, the another option
bypasses the PLL and passes the REF directly to the output.
CyberClocks Software
FOUT = FREF
.
CyberClocks is an easy-to-use software application that
allows the user to custom-configure the CY23FP12. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyberClocks
outputs an industry standard JEDEC file used for
programming the CY23FP12.
CyberClocks can be downloaded free of charge from the
Cypress website at www.cypress.com.
Note:
1. Outputs will be rising edge aligned only to those outputs using this same device setting.
2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is
set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If
CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
Document #: 38-07246 Rev. *E
Page 5 of 10
CY23FP12
Absolute Maximum Conditions
Parameter
VDD
VIN
VIN
LUI
Description
Supply Voltage
Input Voltage REF
Input Voltage Except REF
Latch-up Immunity
Condition
Non-functional
Relative to VCC
Relative to VCC
Functional
Min.
–0.5
–0.5
–0.5
Max.
7
7
Unit
VDC
VDC
VDC
mA
VDD + 0.5
300
TS
TA
TA
TJ
ØJc
ØJa
ESDh
MSL
GATES
UL–94
FIT
Temperature, Storage
Non-functional
–65
0
–40
+125
+70
+85
125
°C
°C
°C
°C
°C/W
°C/W
V
class
each
class
ppm
ms
Temperature, Operating Ambient
Temperature, Operating Ambient
Junction Temperature
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Moisture Sensitivity Level
Total Functional Gate Count
Flammability Rating
Commercial Temperature
Industrial Temperature
Industrial Temperature
Functional
34
86
Functional
2000
MSL – 1
21375
V–0
Assembled Die
@ 1/8 in.
Manufacturing test
Failure in Time
10
TPU
Power-up time for all VDDs to reach
minimum specified voltage (power
ramps must be monotonic)
0.05
500
DC Electrical Specifications for CY23FP12SC/I Commercial/Industrial Temperature Devices
Parameter
VDDC
Description
Core Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
Typ.
Max.
3.465
3.465
2.625
Unit
V
V
V
V
V
µA
µA
V
VDDA, VDDB Bank A, Bank B
Supply Voltage
VIL
VIH
IIL
IIH
VOL
Input LOW Voltage[3]
0.3 × VDD
Input HIGH Voltage[3]
0.7 × VDD
Input LOW Current[3] VIN = 0V
Input HIGH Current[3] VIN = VDD
50.0
50.0
0.5
Output LOW Voltage[4] VDDA/VDDB = 3.3V, IOL = 16 mA (standard drive)
V
DDA/VDDB = 3.3V, IOL = 20 mA (high drive)
V
DDA/VDDB = 2.5V, IOL = 16 mA (high drive)
VOH
Output HIGH
Voltage[4]
VDDA/VDDB = 3.3V, IOH = –16 mA (standard drive)
DDA/VDDB = 3.3V, IOH = –20 mA (high drive)
VDDA/VDDB = 2.5V, IOH = –16 mA (high drive)
VDD – 0.5
V
V
IDDS
IDD
Power-down Supply REF = 0 MHz
12
50
µA
Current
Supply Current
VDDA = VDDB = 2.5V, Unloaded outputs @ 166 MHz
40
65
65.0
100
mA
V
DDA = VDDB = 2.5V, Loaded outputs @ 166 MHz,
CL = 15 pF
VDDA = VDDB = 3.3V, Unloaded outputs @ 166 MHz
50
80
V
DDA = VDDB = 3.3V, Loaded outputs @ 166 MHz,
100
120
CL = 15 pF
Notes:
3. Applies to both Ref Clock and FBK.
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document #: 38-07246 Rev. *E
Page 6 of 10
CY23FP12
Switching Characteristics [5]
Parameter
Description
Reference Frequency[6]
Reference Edge Rate
Reference Duty Cycle
Output Frequency[7]
Test Conditions
Min.
10
1
25
10
10
10
10
45.0
40.0
Typ.
Max.
200
Unit
MHz
V/ns
%
75
200
166.7
100
83.3
55.0
60.0
1.6
t1
CL = 15 pF, Commercial Temperature
CL = 15 pF, Industrial Temperature
CL = 30 pF, Commercial Temperature
CL = 30 pF, Industrial Temperature
VDDA/B = 3.3V, measured at VDD/2
MHz
Duty Cycle[5]
Rise Time[5]
50.0
50.0
%
VDDA/B = 2.5V
t3
VDDA/B = 3.3V, 0.8V to 2.0V,
ns
CL = 30 pF (standard drive and high drive)
V
DDA/B = 3.3V, 0.8V to 2.0V,
0.8
2.0
1.0
1.6
0.8
1.6
0.8
650
CL = 15 pF (standard drive and high drive)
V
DDA/B = 2.5V, 0.6V to 1.8V,
CL = 30 pF (high drive only)
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 15 pF (high drive only)
t4
Fall Time[5]
VDDA/B = 3.3V, 0.8V to 2.0V,
ns
ps
CL = 30 pF (standard drive and high drive)
VDDA/B = 3.3V, 0.8V to 2.0V,
CL = 15 pF (standard drive and high drive)
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 30 pF (high drive only)
VDDA/B = 2.5V, 0.6V to 1.8V,
CL = 15 pF (high drive only)
TTB
Total Timing Budget,[8,9]
Bank A and B same
frequency
Outputs @200 MHz, tracking skew not
included
Total Timing Budget, Bank
850
A and B different frequency
t5
Output to Output Skew[5]
Bank to Bank Skew
Bank to Bank Skew
Bank to Bank Skew
All outputs equally loaded
Same frequency
Different frequency
35[10]
200
200
400
400
250
ps
ps
Different voltage, same frequency
t6
Input to Output Skew (static Measured at VDD/2, REF to FBK
0
phase offset)[5]
t7
tJ
Device to Device Skew[5] Measured at VDD/2
0
500
200
ps
ps
Cycle to Cycle Jitter[5]
(Peak)
Bank A and B same frequency
110[11]
Cycle to Cycle Jitter[5]
(Peak)
Bank A and B different frequency
400
Notes:
5. All parameters are specified with loaded outputs.
6. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the reference frequency can be as low as DC level.
7. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the output frequency can be as low as DC level.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew,
cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
10. Same frequency, 15pF load, high drive.
11. Same frequency, 15pF load, low drive.
Document #: 38-07246 Rev. *E
Page 7 of 10
CY23FP12
Switching Characteristics [5]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
ttsk
Tracking Skew
Input reference clock @ < 50-KHz modulation
200
ps
with ±3.75% spread
tLOCK
TLD
PLL Lock Time[5]
Inserted Loop Delay
Stable power supply, valid clock at REF
1.0
7
ms
ns
Max loop delay for PLL Lock (stable
frequency)
Max loop delay to meet Tracking Skew Spec
4
ns
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
3.3V
0V
2.0V
2.0V
0.8V
OUTPUT
0.8V
t
3
t
4
Output-Output Skew
1.4V
OUTPUT
1.4V
OUTPUT
t
5
Input-Output Propagation Delay
V
DD/2
INPUT
FBK
VDD/2
t6
Device-Device Skew
VDD/2
FBK, Device 1
V
DD/2
FBK, Device 2
t7
Document #: 38-07246 Rev. *E
Page 8 of 10
CY23FP12
Test Circuits
Test Circuit # 1
V
DD
CLK
C
0.1
0.1
µ
µ
F
F
OUT
OUTPUTS
LOAD
V
DD
GND
GND
Test Circuit for all parameters
Ordering Information
Ordering Code
CY23FP12OC
CY23FP12OCT
CY23FP12OI
CY23FP12OIT
CY3672
Package Type
Operating Range
28-pin SSOP
Commercial, 0°C to 70°C
Commercial,0°C to 70°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
28-pin SSOP – Tape and Reel
28-pin SSOP
28-pin SSOP – Tape and Reel
Development Kit
CY3692
CY23FP12S Socket (Label CY3672 ADP006)
Lead-free
CY23FP12OXC
CY23FP12OXCT
CY23FP12OXI
CY23FP12OXIT
28-pin SSOP
28-pin SSOP – Tape and Reel
28-pin SSOP
Commercial, 0°C to 70°C
Commercial,0°C to 70°C
Industrial, –40°C to 85°C
Industrial, –40°C to 85°C
28-pin SSOP – Tape and Reel
Package Drawing and Dimension
28-lead (5.3 mm) Shrunk Small Outline Package O28
51-85079-*C
Total Timing Budget, TTB, Spread Aware, and CyberClocks are trademarks of Cypress Semiconductor Corporation. All product
and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07246 Rev. *E
Page 9 of 10
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY23FP12
Document History Page
Document Title: CY23FP12 200-MHz Field Programmable Zero Delay Buffer
Document Number: 38-07246
Orig. of
REV.
**
*A
ECN NO.
115158
121880
124523
Issue Date
07/03/02
12/14/02
03/19/03
Change
HWT
RBI
Description of Change
New data sheet
Power-up requirements added to Absolute Maximum Ratings information
*B
RGL
Final data sheet
Changed title to “200-MHz Field Programmable Zero Delay Buffer”
*C
*D
*E
126938
129364
299718
06/16/03
09/10/03
See ECN
RGL
RGL
RGL
Interchanged REF2 in the Pin Configuration diagram
Replaced all divide by 2 default value to divide by 2 in Table 2
Fixed the formula in the Frequency Calculation section
Changed the CyClocksRT trademark to CyberClocks
Added Note 2 in the TEST mode in Table 3
Added TLD specifications in the Switching Characteristics table
Added lead-free devices
Added typical values
Document #: 38-07246 Rev. *E
Page 10 of 10
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