CY3681 [CYPRESS]
EZ-USB FX2⑩ USB Microcontroller High-speed USB Peripheral Controller; EZ- USB FX2⑩ USB微控制器,高速USB外设控制器型号: | CY3681 |
厂家: | CYPRESS |
描述: | EZ-USB FX2⑩ USB Microcontroller High-speed USB Peripheral Controller |
文件: | 总52页 (文件大小:534K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C68013
CY7C68013
EZ-USB FX2™ USB Microcontroller
High-speed USB Peripheral Controller
Cypress Semiconductor Corporation
Document #: 38-08012 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised December 19, 2002
CY7C68013
TABLE OF CONTENTS
1.0 EZ-USB FX2™ FEATURES .............................................................................................................6
2.0 APPLICATIONS ...............................................................................................................................7
3.0 FUNCTIONAL OVERVIEW ..............................................................................................................7
3.1 USB Signaling Speed .................................................................................................................7
3.2 8051 Microprocessor ..................................................................................................................7
2
3.3 I C-compatible Bus .....................................................................................................................8
3.4 Buses ..........................................................................................................................................8
3.5 USB Boot Methods .....................................................................................................................9
3.6 ReNumeration™ .........................................................................................................................9
3.7 Bus Powered Applications ..........................................................................................................9
3.8 Interrupt System ........................................................................................................................10
3.9 Reset and Wakeup ...................................................................................................................11
3.10 Program/Data RAM .................................................................................................................11
3.11 Register Addresses .................................................................................................................14
3.12 Endpoint RAM .........................................................................................................................14
3.13 External FIFO interface ...........................................................................................................16
3.14 GPIF ........................................................................................................................................16
3.15 USB Uploads and Downloads .................................................................................................17
3.16 Autopointer Access .................................................................................................................17
2
3.17 I C-compatible Controller ........................................................................................................17
4.0 PIN ASSIGNMENTS ......................................................................................................................18
4.1 CY7C68013 Pin Descriptions ...................................................................................................24
5.0 REGISTER SUMMARY ..................................................................................................................31
6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................37
7.0 OPERATING CONDITIONS ...........................................................................................................37
8.0 DC CHARACTERISTICS ...............................................................................................................37
8.1 USB Transceiver .......................................................................................................................37
9.0 AC ELECTRICAL CHARACTERISTICS .......................................................................................38
9.1 USB Transceiver .......................................................................................................................38
9.2 Program Memory Read .............................................................................................................38
9.3 Data Memory Read ...................................................................................................................39
9.4 Data Memory Write ...................................................................................................................40
9.5 GPIF Synchronous Signals .......................................................................................................41
9.6 Slave FIFO Synchronous Read ................................................................................................42
9.7 Slave FIFO Asynchronous Read ..............................................................................................43
9.8 Slave FIFO Synchronous Write ................................................................................................43
9.9 Slave FIFO Asynchronous Write ...............................................................................................44
9.10 Slave FIFO Synchronous Packet End Strobe .........................................................................44
9.11 Slave FIFO Asynchronous Packet End Strobe .......................................................................45
9.12 Slave FIFO Output Enable ......................................................................................................45
9.13 Slave FIFO Address to Flags/Data .........................................................................................45
9.14 Slave FIFO Synchronous Address ..........................................................................................46
9.15 Slave FIFO Asynchronous Address ........................................................................................46
Document #: 38-08012 Rev. *C
Page 2 of 52
CY7C68013
10.0 ORDERING INFORMATION ........................................................................................................46
11.0 PACKAGE DIAGRAMS ...............................................................................................................47
12.0 PCB LAYOUT RECOMMENDATIONS ........................................................................................50
13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES ................................50
Document #: 38-08012 Rev. *C
Page 3 of 52
CY7C68013
LIST OF FIGURES
Figure 1-1. Block Diagram....................................................................................................................... 6
Figure 3-1. Internal Code Memory, EA = 0............................................................................................ 12
Figure 3-2. External Code Memory, EA = 1........................................................................................... 13
Figure 3-3. Endpoint Configuration........................................................................................................ 15
Figure 4-1. Signals................................................................................................................................. 19
Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment ....................................................................... 20
Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment ....................................................................... 21
Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment......................................................................... 22
Figure 4-5. CY7C68013 56-pin QFN Pin Assignment ........................................................................... 23
Figure 9-1. Program Memory Read Timing Diagram............................................................................. 38
Figure 9-2. Data Memory Read Timing Diagram................................................................................... 39
Figure 9-3. Data Memory Write Timing Diagram................................................................................... 40
Figure 9-4. GPIF Synchronous Signals Timing Diagram....................................................................... 41
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram ................................................................ 42
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram .............................................................. 43
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram ................................................................ 43
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram...............................................................44
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram...........................................44
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram ....................................... 45
Figure 9-11. Slave FIFO Output Enable Timing Diagram...................................................................... 45
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram ......................................................... 45
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram.......................................................... 46
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram........................................................ 46
Figure 11-1. 56-lead Shrunk Small Outline Package O56..................................................................... 47
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 × 8 mm) LF56............................................. 47
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101......................................... 48
Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128 ...................................... 49
Figure 13-1. Cross-section of the Area Underneath the QFN Package ................................................ 50
Figure 13-2. Plot of the Solder Mask (White Area)................................................................................ 50
Figure 13-3. X-ray image of the assembly............................................................................................. 51
Document #: 38-08012 Rev. *C
Page 4 of 52
CY7C68013
LIST OF TABLES
Table 3-1. Special Function Registers ....................................................................................................9
Table 3-2. Default ID Values for FX2 ......................................................................................................9
Table 3-3. INT2 USB Interrupts ............................................................................................................10
Table 3-4. Individual FIFO/GPIF Interrupt Sources ..............................................................................11
Table 3-5. Default Full-Speed Alternate Settings .................................................................................15
Table 3-6. Default High-Speed Alternate Settings ................................................................................16
Table 3-7. Strap Boot EEPROM Address Lines to These Values ........................................................18
Table 4-1. FX2 Pin Descriptions ...........................................................................................................24
Table 5-1. FX2 Register Summary .......................................................................................................31
Table 8-1. DC Characteristics ...............................................................................................................37
Table 9-1. Program Memory Read Parameters ....................................................................................38
Table 9-2. Data Memory Read Parameters ..........................................................................................39
Table 9-3. Data Memory Write Parameters ..........................................................................................40
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK .............................41
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK ............................41
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK .......................42
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK .....................42
Table 9-8. Slave FIFO Asynchronous Read Parameters .....................................................................43
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK .......................43
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK ....................44
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ...................44
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK 44
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK 45
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters ..............................................45
Table 9-15. Slave FIFO Output Enable Parameters .............................................................................45
Table 9-16. Slave FIFO Address to Flags/Data Parameters ................................................................46
Table 9-17. Slave FIFO Synchronous Address Parameters .................................................................46
Table 9-18. Slave FIFO Asynchronous Address Parameters ...............................................................46
Table 10-1. Ordering Information ..........................................................................................................46
Document #: 38-08012 Rev. *C
Page 5 of 52
CY7C68013
1.0
EZ-USB FX2 Features
Cypress’s EZ-USB FX2 is the world’s first USB 2.0 integrated microcontroller. By integrating the USB 2.0 transceiver, SIE,
enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, Cypress has created a very cost-
effective solution that provides superior time-to-market advantages. The ingenious architecture of FX2 results in data transfer
rates of 56 Mbytes per second, the maximum allowable USB 2.0 bandwidth, while still using a low-cost 8051 microcontroller in
a package as small as a 56 SSOP. Because it incorporates the USB 2.0 transceiver, the FX2 is more economical, providing a
smaller footprint solution than USB 2.0 SIE or external transceiver implementations. With EZ-USB FX2, the Cypress Smart SIE
handles most of the USB 1.1 and 2.0 protocol in hardware, freeing the embedded microcontroller for application-specific functions
and decreasing development time to ensure USB compatibility. The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8- or 16-bit data bus) provides an easy and glueless interface to popular interfaces such as ATA, UTOPIA, EPP,
PCMCIA, and most DSP/processors.
Four packages are defined for the family: 56 SSOP, 56 QFN, 100 TQFP, and 128 TQFP.
High-performance micro
using standard tools
24 MHz
Ext. XTAL
with lower-power options
FX2
I2C
Compatible
Master
/0.5
8051 Core
x20
/1.0
/2.0
VCC
12/24/48 MHz,
four clocks/cycle
PLL
Abundant I/O
including two USARTS
Additional I/Os (24)
1.5k
connected for
full speed
General
ADDR (9)
programmable I/F
to ASIC/DSP or bus
standards such as
D+
GPIF
USB
2.0
XCVR
CY
Smart
USB
8.5 kB
RAM
RDY (6)
CTL (6)
ATAPI, EPP, etc.
D–
1.1/2.0
Engine
Integrated
full- and high-speed
XCVR
Up to 96 MBytes/s
burst rate
4 kB
FIFO
8/16
Enhanced USB core
Simplifies 8051 core
“Soft Configuration”
Easy firmware changes
FIFO and endpoint memory
(master or slave operation)
Figure 1-1. Block Diagram
• Single-chip integrated USB 2.0 Transceiver, SIE, and Enhanced 8051 Microprocessor
• Software: 8051 runs from internal RAM, which is:
— Downloaded via USB, or
— Loaded from EEPROM
— External memory device (128-pin configuration only)
• Four programmable BULK/INTERRUPT/ISOCHRONOUS endpoints
— Buffering options: double, triple and quad
• 8- or 16-bit external data interface
• GPIF
— Allows direct connection to most parallel interfaces; 8- and 16-bit
— Programmable waveform descriptors and configuration registers to define waveforms
— Supports multiple Ready (RDY) inputs and Control (CTL) outputs
• Integrated, industry standard 8051 with enhanced features:
— Up to 48-MHz clock rate
— Four clocks per instruction cycle
— Two USARTS
Document #: 38-08012 Rev. *C
Page 6 of 52
CY7C68013
— Three counter/timers
— Expanded interrupt system
— Two data pointers
• Supports bus powered applications by using renumeration
• 3.3V operation
• Smart Serial Interface Engine
• Vectored USB interrupts
• Separate data buffers for the SETUP and DATA portions of a CONTROL transfer
• Integrated I2C-compatible controller, runs at 100 or 400 kHz
• 48-MHz, 24-MHz, or 12-MHz 8051 operation
• Four integrated FIFOs
— Brings glue and FIFOs inside for lower system cost
— Automatic conversion to and from 16-bit buses
— Master or slave operation
— FIFOs can use externally supplied clock or asynchronous strobes
— Easy interface to ASIC and DSP ICs
• Special autovectors for FIFO and GPIF interrupts
• Up to 40 general purpose I/Os
• Four package options—128-pin TQFP, 100-pin TQFP, 56-pin QFN and 56-pin SSOP.
2.0
Applications
• DSL modems
• ATA interface
• Memory card readers
• Legacy conversion devices
• Cameras
• Scanners
• Home PNA
• Wireless LAN
• MP3 players
• Networking.
The “Reference Designs” section of the cypress website provides additional tools for typical USB 2.0 applications. Each reference
design comes complete with firmware source and object code, schematics, and documentation. Please visit
http://www.cypress.com for more information.
3.0
3.1
Functional Overview
USB Signaling Speed
FX2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0, dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbps
• High speed, with a signaling bit rate of 480 Mbps
FX2 does not support the low-speed signaling mode of 1.5 Mbps.
3.2
8051 Microprocessor
The 8051 microprocessor embedded in the FX2 family has 256 bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
Document #: 38-08012 Rev. *C
Page 7 of 52
CY7C68013
3.2.1
8051 Clock Frequency
FX2 has an on-chip oscillator circuit that uses an external 24-MHz (±100 ppm) crystal with the following characteristics:
• Parallel resonant
• Fundamental mode
• 500-µW drive level
• 20–33 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24-MHz oscillator up to 480 MHz, as required by the transceiver/PHY, and internal counters divide
it down for use as the 8051 clock. The default 8051 clock frequency is 12 MHz. The clock frequency of the 8051 can be changed
by the 8051 through the CPUCS register, dynamically.
The CLKOUT pin, which can be tri-stated and inverted using internal control bits, outputs the 50% duty cycle 8051 clock, at the
selected 8051 clock frequency—48, 24, or 12 MHz.
3.2.2
USARTS
FX2 contains two standard 8051 USARTs, addressed via Special Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port pins.
UART0 and UART1 can operate using an internal clock at 230 KBaud with no more than 1% baud rate error. 230-KBaud operation
is achieved by an internally derived clock source that generates overflow pulses at the appropriate time. The internal clock adjusts
for the 8051 clock rate (48, 24, 12 MHz) such that it always presents the correct frequency for 230-KBaud operation.
Note. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0 and/or UART1,
respectively.
3.2.3
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast access to critical FX2 functions. These SFR additions are shown in
Table 3-1. Bold type indicates non-standard, enhanced 8051 registers.
The two SFR rows that end with “0” and “8” contain bit-addressable registers. The four I/O ports A–D use the SFR addresses
used in the standard 8051 for ports 0–3, which are not implemented in FX2.
Because of the faster and more efficient SFR addressing, the FX2 I/O ports are not addressable in external RAM space (using
the MOVX instruction).
3.3
I2C-compatible Bus
FX2 supports the I2C-compatible bus as a master only at 100/400 kbps. SCL and SDA pins have open-drain outputs and
hysteresis inputs. These signals must be pulled up to 3.3V, even if no I2C-compatible device is connected.
3.4
Buses
All packages: 8- or 16-bit “FIFO” bidirectional data bus, multiplexed on I/O ports B and D. 128-pin package: adds 16-bit output-
only 8051 address bus, 8-bit bidirectional data bus.
Document #: 38-08012 Rev. *C
Page 8 of 52
CY7C68013
Table 3-1. Special Function Registers
x
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
8x
IOA
9x
IOB
Ax
Bx
Cx
Dx
Ex
Fx
IOC
IOD
SCON1
SBUF1
PSW
ACC
B
SP
EXIF
INT2CLR
INT4CLR
IOE
DPL0
DPH0
DPL1
DPH1
DPS
MPAGE
OEA
OEB
OEC
OED
OEE
PCON
TCON
TMOD
TL0
SCON0
SBUF0
IE
IP
T2CON
EICON
EIE
EIP
AUTOPTRH1
AUTOPTRL1
reserved
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
EP01STAT
GPIFTRIG
RCAP2L
RCAP2H
TL2
TL1
TH0
TH1
AUTOPTRH2
AUTOPTRL2
reserved
GPIFSGLDATH
GPIFSGLDATLX
TH2
CKCON
AUTOPTRSETUP GPIFSGLDATLNOX
3.5
USB Boot Methods
During the power-up sequence, internal logic checks the I2C-compatible port for the connection of an EEPROM whose first byte
is either 0xC0 or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM in place of the internally stored values (0xC0),
or it boot-loads the EEPROM contents into internal RAM (0xC2). If no EEPROM is detected, FX2 enumerates using internally
stored descriptors. The default ID values for FX2 are VID/PID/DID (0x04B4, 0x8613, 0xxxyy).
Table 3-2. Default ID Values for FX2
Default VID/PID/DID
Vendor ID
Prod ID
0x04B4
0x8613
0xXXYY
Cypress Semiconductor
EZ-USB FX2
Device release
Depends on revision (0x04 for Rev E)
Note. The I2C-compatible bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this
detection method does not work properly.
3.6
ReNumeration™
Because the FX2’s configuration is soft, one chip can take on the identities of multiple distinct USB devices.
When first plugged into USB, the FX2 enumerates automatically and downloads firmware and USB descriptor tables over the
USB cable. Next, the FX2 enumerates again, this time as a device defined by the downloaded information. This patented two-
step process, called ReNumeration™, happens instantly when the device is plugged in, with no hint that the initial download step
has occurred.
Two control bits in the USBCS (USB Control and Status) register control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit to indicate whether the firmware or the Default USB Device will
handle device requests over endpoint zero: if RENUM = 0, the Default USB Device will handle device requests; if RENUM = 1,
the firmware will.
3.7
Bus Powered Applications
Bus powered applications require the FX2 to enumerate in a unconfigured mode with less then 100 mA. To do this, the FX2 must
enumerate in the full speed mode and then, when configured, renumerate in high speed mode. For an example of the benefits
and limitations of this renumeration process see the application note titled “Bus Powered Enumeration with FX2”.
Document #: 38-08012 Rev. *C
Page 9 of 52
CY7C68013
3.8
Interrupt System
3.8.1
INT2 Interrupt Request and Enable Registers
FX2 implements an autovector feature for INT2 and INT4. There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See FX2 TRM for more details.
3.8.2
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. To save the code and processing time that normally would be required
to identify the individual USB interrupt source, the FX2 provides a second level of interrupt vectoring, called Autovectoring. When
a USB interrupt is asserted, the FX2 pushes the program counter onto its stack then jumps to address 0x0043, where it expects
to find a “jump” instruction to the USB Interrupt service routine.
The FX2 jump instruction is encoded as follows.
Table 3-3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority
1
INT2VEC Value Source
Notes
00
04
08
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
SUDAV
SETUP Data Available
2
SOF
Start of Frame (or microframe)
Setup Token Received
3
SUTOK
4
SUSPEND
USB RESET
HISPEED
EP0ACK
USB Suspend request
5
Bus reset
6
Entered high speed operation
FX2 ACK’d the CONTROL Handshake
reserved
7
8
9
EP0-IN
EP0-OUT
EP1-IN
EP1-OUT
EP2
EP0-IN ready to be loaded with data
EP0-OUT has USB data
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EP1-IN ready to be loaded with data
EP1-OUT has USB data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN: buffer available. OUT: buffer has data
IN-Bulk-NAK (any IN endpoint)
reserved
EP4
EP6
EP8
IBN
EP0PING
EP1PING
EP2PING
EP4PING
EP6PING
EP8PING
ERRLIMIT
EP0 OUT was Pinged and it NAK’d
EP1 OUT was Pinged and it NAK’d
EP2 OUT was Pinged and it NAK’d
EP4 OUT was Pinged and it NAK’d
EP6 OUT was Pinged and it NAK’d
EP8 OUT was Pinged and it NAK’d
Bus errors exceeded the programmed limit
reserved
reserved
reserved
EP2ISOERR
EP4ISOERR
EP6ISOERR
EP8ISOERR
ISO EP2 OUT PID sequence error
ISO EP4 OUT PID sequence error
ISO EP6 OUT PID sequence error
ISO EP8 OUT PID sequence error
Document #: 38-08012 Rev. *C
Page 10 of 52
CY7C68013
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP register), the FX2 substitutes its INT2VEC byte. Therefore, if the high
byte (“page”) of a jump-table address is preloaded at location 0x0044, the automatically-inserted INT2VEC byte at 0x0045 will
direct the jump to the correct address out of the 27 addresses within the page.
3.8.3
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14
individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 3-4 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources
Table 3-4. Individual FIFO/GPIF Interrupt Sources
Priority
INT4VEC Value
Source
EP2PF
EP4PF
EP6PF
EP8PF
EP2EF
EP4EF
EP6EF
EP8EF
EP2FF
EP4FF
Notes
Endpoint 2 Programmable Flag
1
2
80
84
88
8C
90
94
98
9C
A0
A4
A8
AC
B0
B4
Endpoint 4 Programmable Flag
Endpoint 6 Programmable Flag
Endpoint 8 Programmable Flag
Endpoint 2 Empty Flag
Endpoint 4 Empty Flag
Endpoint 6 Empty Flag
Endpoint 8 Empty Flag
Endpoint 2 Full Flag
3
4
5
6
7
8
9
10
11
12
13
14
Endpoint 4 Full Flag
EP6FF
Endpoint 6 Full Flag
EP8FF
GPIFDONE
GPIFWF
Endpoint 8 Full Flag
GPIF Operation Complete
GPIF Waveform
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP register), the FX2 substitutes its INT4VEC byte. Therefore, if the high
byte (“page”) of a jump-table address is preloaded at location 0x0054, the automatically-inserted INT4VEC byte at 0x0055 will
direct the jump to the correct address out of the 14 addresses within the page. When the ISR occurs, the FX2 pushes the program
counter onto its stack then jumps to address 0x0053, where it expects to find a “jump” instruction to the ISR Interrupt service
routine.
3.9
Reset and Wakeup
Reset Pin
3.9.1
An input pin (RESET#) resets the chip. This pin has hysteresis and is active LOW. The internal PLL stabilizes approximately 200
µs after VCC has reached 3.3V. Typically, an external RC network (R = 100k, C = 0.1 µF) is used to provide the RESET# signal.
3.9.2
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator restarts and after the PLL stabilizes, and the 8051 receives a wakeup
interrupt. This applies whether or not FX2 is connected to the USB.
The FX2 exits the power down (USB suspend) state using one of the following methods:
• USB bus signals resume
• External logic asserts the WAKEUP pin
• External logic asserts the PA3/WU2 pin.
The second wakeup pin, WU2, can also be configured as a general purpose I/O pin. This allows a simple external R-C network
to be used as a periodic wakeup source.
3.10
Program/Data RAM
3.10.1 Size
The FX2 has eight kbytes of internal program/data RAM, where PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control registers appear in this space.
Document #: 38-08012 Rev. *C
Page 11 of 52
CY7C68013
Two memory maps are shown in the following diagrams:
Figure 3-1 Internal Code Memory, EA = 0
Figure 3-2 External Code Memory, EA = 1.
3.10.2 Internal Code Memory, EA = 0
This mode implements the internal eight-kbyte block of RAM (starting at 0) as combined code and data memory. When external
RAM or ROM is added, the external read and write strobes are suppressed for memory spaces that exist inside the chip. This
allows the user to connect a 64-kbyte memory without requiring address decodes to keep clear of internal memory spaces.
Only the internal eight kbytes and scratch pad 0.5 kbytes RAM spaces have the following access:
• USB download
• USB upload
• Setup data pointer
• I2C-compatible interface boot load.
Inside FX2
Outside FX2
FFFF
7.5 kbytes
(OK to populate
US B regs and
4k EP buffers
(RD#,WR#)
data memory
here—RD#/WR#
strobes are not
active)
E200
E1FF
0.5 kbytes RAM
Data (RD#,WR#)*
E000
56 kbytes
External
Code
Memory
(PSEN#)
48 kbytes
External
Data
Memory
(RD#,WR#)
1FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
Eight kbytes RAM
Code and Data
(PSEN#,RD#,WR#)*
0000
Data
Code
*SUDPTR, USB upload/download, I2C-compatible interface boot access
Figure 3-1. Internal Code Memory, EA = 0
Document #: 38-08012 Rev. *C
Page 12 of 52
CY7C68013
3.10.3 External Code Memory, EA = 1
The bottom eight kbytes of program memory is external, and therefore the bottom eight kbytes of internal RAM is accessible only
as data memory.
Inside FX2
Outside FX2
FFFF
7.5 kbytes
(OK to populate
USB regs and
4k EP buffers
(RD#,WR#)
data memory
here—RD#/WR#
strobes are not
active)
E200
E1FF
0.5 kbytes RAM
Data (RD#,WR#)*
E000
48 kbytes
External
Data
Memory
(RD#,WR#)
64 kbytes
External
Code
Memory
(PSEN#)
1FFF
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
Eight kbytes
RAM
Data
(RD#,WR#)*
0000
Data
Code
*SUDPTR, USB upload/download, I2C-compatible interface boot access
Figure 3-2. External Code Memory, EA = 1
Document #: 38-08012 Rev. *C
Page 13 of 52
CY7C68013
3.11
Register Addresses
FFFF
4 kbytes EP2-EP8 buffers
(8 × 512)
F000
EFFF
2 kbytes RESERVED
E800
E7FF
64 bytes EP1IN
64 bytes EP1OUT
E7C0
E7BF
E780
E77F
64 bytes EP0 IN/OUT
64 bytes RESERVED
256 bytes Registers
384 bytes RESERVED
128 bytes GPIF Waveforms
E740
E73F
E700
E6FF
E600
E5FF
E480
E47F
E400
E3FF
512 bytes RESERVED
E200
E1FF
512 bytes
8051 xdata RAM
E000
3.12
Endpoint RAM
3.12.1 Size
• 3 × 64 bytes
• 8 × 512 bytes
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
3.12.2 Organization
• EP0
• EP1IN, EP1OUT
• EP2,4,6,8
Bidirectional endpoint zero, 64-byte buffer
64-byte buffers, bulk or interrupt
Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and 6 can be either double, triple, or quad
buffered. For high-speed endpoint configuration options, see Figure 3-3.
3.12.3 Setup Data Buffer
A separate eight-byte buffer at 0xE6B8-0xE6BF holds the SETUP data from a CONTROL transfer.
Document #: 38-08012 Rev. *C
Page 14 of 52
CY7C68013
3.12.4 Endpoint Configurations (High-speed Mode)
EP0 IN&OUT
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP1 IN
EP1 OUT
512
512
512
512
512
512
512
EP2
EP4
1024
1024
1024
1024
1024
1024
EP2
EP2
EP2
512
512
512
512
EP2
512
EP2
EP6
EP8
512
512
512
512
512
512
EP6
EP8
1024
1024
1024
1024
1024
EP6
EP6
512
512
512
512
512
512
512
512
EP8
Figure 3-3. Endpoint Configuration
Endpoints 0 and 1 are the same for every configuration. Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can be either
BULK or INTERRUPT. To the left of the vertical line, the user may pick different configurations for EP2&4 and EP6&8, since none
of the 512-byte buffers are combined between these endpoint groups. An example endpoint configuration would be:
EP2—1024 double buffered; EP6—512 quad buffered.
To the right of the vertical line, buffers are shared between EP2–8, and therefore only entire columns may be chosen.
3.12.5 Default Full-Speed Alternate Settings
Table 3-5. Default Full-Speed Alternate Settings[1, 2]
Alternate Setting
0
64
0
1
2
3
ep0
64
64
64
ep1out
ep1in
ep2
64 bulk
64 bulk
64 int
64 int
64 int
64 int
0
0
64 bulk out (2×)
64 bulk out (2×)
64 bulk in (2×)
64 bulk in (2×)
64 int out (2×)
64 bulk out (2×)
64 int in (2×)
64 iso out (2×)
64 bulk out (2×)
64 iso in (2×)
ep4
0
ep6
0
ep8
0
64 bulk in (2×)
64 bulk in (2×)
Notes:
1. “0” means “not implemented.”
2. “2x” means “double buffered.”
Document #: 38-08012 Rev. *C
Page 15 of 52
CY7C68013
3.12.6 Default High-Speed Alternate Settings
Table 3-6. Default High-Speed Alternate Settings[1, 2]
Alternate Setting
0
1
2
3
ep0
64
64
64
64
ep1out
ep1in
ep2
0
0
0
0
0
0
512 bulk[3]
512 bulk[3]
64 int
64 int
64 int
64 int
512 bulk out (2×)
512 bulk out (2×)
512 bulk in (2×)
512 bulk in (2×)
512 int out (2×)
512 bulk out (2×)
512 int in (2×)
512 iso out (2×)
512 bulk out (2×)
512 iso in (2×)
512 bulk in (2×)
ep4
ep6
ep8
512 bulk in (2×)
Note:
3. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
3.13
External FIFO interface
3.13.1 Architecture
The FX2 slave FIFO architecture has eight 512-byte blocks in the endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#, SLRD, SLWR, SLOE, PKTEND, and flags).
In operation, some of the eight RAM blocks fill or empty from the SIE, while the others are connected to the I/O transfer logic.
The transfer logic takes two forms, the GPIF for internally generated control signals, or the slave FIFO interface for externally
controlled transfers.
3.13.2 Master/Slave Control Signals
The FX2 endpoint FIFOS are implemented as eight physically distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domains, the USB (SIE) domain and the 8051-I/O Unit domain. This switching is done virtually instan-
taneously, giving essentially zero transfer time between “USB FIFOS” and “Slave FIFOS.” Since they are physically the same
memory, no bytes are actually transferred between buffers.
At any given time, some RAM blocks are filling/emptying with USB data under SIE control, while other RAM blocks are available
to the 8051 and/or the I/O control unit. The RAM blocks operate as single-port in the USB domain, and dual-port in the 8051-I/O
domain. The blocks can be configured as single, double, triple, or quad buffered as previously shown.
The I/O control unit implements either an internal-master (M for master) or external-master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0] to select a FIFO. The RDY pins (two in the 56-pin package, six
in the 100-pin and 128-pin packages) can be used as flag inputs from an external FIFO or other logic if desired. The GPIF can
be run from either an internally derived clock or externally supplied clock (IFCLK), at a rate that transfers data up to 96
Megabytes/s (48 MHz).
In Slave (S) mode, the FX2 accepts either an internally derived clock or externally supplied clock (IFCLK, max. frequency 48
MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals from external logic. Each endpoint can individually be selected for byte
or word operation by an internal configuration bit, and a Slave FIFO Output Enable signal SLOE enables data of the selected
width. External logic must insure that the output enable signal is inactive when writing data to a slave FIFO. The slave interface
can also operate asynchronously, where the SLRD and SLWR signals act directly as strobes, rather than a clock qualifier as in
synchronous mode. The signals SLRD, SLWR, SLOE and PKTEND are gated by the signal SLCS#.
3.13.3 GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the internally supplied interface clock: 30 MHz and 48 MHz. Alternatively,
an externally supplied clock of 5 MHz – 48 MHz feeding the IFCLK pin can be used as the interface clock. IFCLK can be configured
to function as an output clock when the GPIF and FIFOs are internally clocked. An output enable bit in the IFCONFIG register
turns this clock output off, if desired. Another bit within the IFCONFIG register will invert the IFCLK signal whether internally or
externally sourced.
3.14
GPIF
The GPIF is a flexible 8- or 16-bit parallel interface driven by a user-programmable finite state machine. It allows the CY7C68013
to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, printer parallel port, and
Utopia.
Document #: 38-08012 Rev. *C
Page 16 of 52
CY7C68013
The GPIF has six programmable control outputs (CTL), nine address outputs (GPIFADRx), and six general-purpose ready inputs
(RDY). The data bus width can be 8 or 16 bits. Each GPIF vector defines the state of the control outputs, and determines what
state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to
the next data value, advance an address, etc. A sequence of the GPIF vectors make up a single waveform that will be executed
to perform the desired data move between the CY7C68013 and the external design.
3.14.1 Six Control OUT Signals
The 100- and 128-pin packages bring out all six Control Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to define
the CTL waveforms. The 56-pin package brings out three of these signals, CTL0–CTL2. CTLx waveform edges can be
programmed to make transitions as fast as once per clock (20.8 ns using a 48-MHz clock).
3.14.2 Six Ready IN Signals
The 100- and 128-pin packages bring out all six Ready inputs (RDY0–RDY5). The 8051 programs the GPIF unit to test the RDY
pins for GPIF branching. The 56-pin package brings out two of these signals, RDY0–1.
3.14.3 Nine GPIF Address OUT signals
Nine GPIF address lines are available in the 100- and 128-pin packages, GPIFADR[8..0]. The GPIF address lines allow indexing
through up to a 512-byte block of RAM. If more address lines are needed, I/O port pins can be used.
3.14.4 Long Transfer Mode
In master mode, the 8051 appropriately sets GPIF transaction count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 4,294,967,296 bytes. The GPIF automatically throttles data flow to prevent under
or overflow until the full number of requested transactions complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
3.15
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the internal 8-kbyte RAM and of the internal 512-byte scratch pad
RAM via a vendor-specific command. This capability is normally used when “soft” downloading user code and is available only
to and from internal RAM, whether the 8051 is held in reset or running. The available RAM spaces are 8 kbytes from
0x0000–0x1FFF (code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad RAM).
Note: A “loader” running in internal RAM can be used to transfer downloaded data to external memory.
3.16
Autopointer Access
FX2 provides two identical autopointers. They are similar to the internal 8051 data pointers, but with an additional feature: they
can optionally increment a pointer address after every memory access. This capability is available to and from both internal and
external RAM. The autopointers are available in external FX2 registers, under control of a mode bit (AUTOPTRSETUP.0). Using
the external FX2 autopointer access (at 0xE67B – 0xE67C) allows the autopointer to access all RAM, internal and external to
the part. Also, the autopointers can point to any FX2 register or endpoint buffer space. When autopointer access to external
memory is enabled, location 0xE67B and 0xE67C in XDATA and PDATA space cannot be used.
3.17
I2C-compatible Controller
FX2 has one I2C-compatible port that is driven by two internal controllers, one that automatically operates at boot time to load
VID/PID/DID and configuration information, and another that the 8051, once running, uses to control external I2C-compatible
devices. The I2C-compatible port operates in master mode only.
3.17.1 I2C-compatible Port Pins
The I2C-compatible pins SCL and SDA must have external 2.2-kΩ pull-up resistors. External EEPROM device address pins must
be configured properly. See Table 3-7 for configuring the device address pins.
Document #: 38-08012 Rev. *C
Page 17 of 52
CY7C68013
Table 3-7. Strap Boot EEPROM Address Lines to These Values
Bytes Example EEPROM
A2
N/A
0
A1
N/A
0
A0
N/A
0
16
24LC00[4]
24LC01
24LC02
24LC32
24LC64
128
256
4K
0
0
0
0
0
1
8K
0
0
1
3.17.2 I2C-compatible Interface Boot Load Access
At power-on reset the I2C-compatible interface boot loader will load the VID/PID/DID/a configuration byte and up to 8 kbytes of
program/data. The available RAM spaces are 8 kbytes from 0x0000–0x1FFF and 512 bytes from 0xE000–0xE1FF. The 8051 will
be in reset. I2C-compatible interface boot loads only occur after power-on reset.
3.17.3 I2C-compatible Interface General Purpose Access
The 8051 can control peripherals connected to the I2C-compatible bus using the I2CTL and I2DAT registers. FX2 provides I2C
compatible master control only, it is never an I2C-compatible slave.
4.0
Pin Assignments
Figure 4-1 identifies all signals for the four package types. The following pages illustrate the individual pin diagrams, plus a
combination diagram showing which of the full set of signals are available in the 128-, 100-, and 56-pin packages.
The 56-pin package is the lowest-cost version. The signals on the left edge of the 56-pin package in Figure 4-1 are common to
all versions in the FX2 family. Three modes are available in all package versions: Port, GPIF master, and Slave FIFO. These
modes define the signals on the right edge of the diagram. The 8051 selects the interface mode using the IFCONFIG[1:0] register
bits. Port mode is the power-on default configuration.
The 100-pin package adds functionality to the 56-pin package by adding these pins:
• PORTC or alternate GPIFADR[7...0] address signals
• PORTE or alternate GPIFADR8 address signals and 7 more 8051 signals
• 3 GPIF Control signals
• 4 GPIF Ready signals
• Nine 8051 signals (two USARTs, three timer inputs, INT4,and INT5#)
• BKPT, RD#, WR#
The 128-pin package is the full version, adding the 8051 address and data buses plus control signals. Note that two of the required
signals, RD# and WR#, are present in the 100-pin version. In the 100-pin and 128-pin versions, an 8051 control bit can be set to
pulse the RD# and WR# pins when the 8051 reads from/writes to PORTC.
Note:
4. This EEPROM does not have address pins.
Document #: 38-08012 Rev. *C
Page 18 of 52
CY7C68013
Port
GPIF Master
Slave FIFO
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
56
XTALIN
SLRD
SLWR
RDY0
RDY1
XTALOUT
RESET#
WAKEUP#
FLAGA
FLAGB
FLAGC
CTL0
CTL1
CTL2
SCL
SDA
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
INT0#/ PA0
INT1#/ PA1
SLOE
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
IFCLK
CLKOUT
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
DPLUS
DMINUS
PA5
PA6
PA7
PA7/FLAGD/SLCS#
PA7
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
100
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
TIMER2
TIMER1
TIMER0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
A15
A14
A13
A12
A11
A10
A9
128
A8
A7
A6
A5
A4
A3
EA
A2
A1
A0
Figure 4-1. Signals
Document #: 38-08012 Rev. *C
Page 19 of 52
CY7C68013
1
102
CLKOUT
VCC
GND
PD0/FD8
*WAKEUP
VCC
RESET#
2
101
3
100
4
99
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
5
98
CTL5
6
97
A3
A2
A1
A0
7
96
8
95
9
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
93
GND
92
PA7/*FLAGD/SLCS#
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
CY7C68013
128-pin TQFP
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
T2
IFCLK
RESERVED
BKPT
EA
SCL
SDA
CTL4
CTL3
GND
OE#
Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *C
Page 20 of 52
CY7C68013
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VCC
GND
PD0/FD8
*WAKEUP
VCC
RESET#
2
3
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
VCC
DPLUS
DMINUS
GND
VCC
GND
INT4
T0
T1
T2
IFCLK
RESERVED
BKPT
SCL
4
5
CTL5
GND
6
7
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PA2/*SLOE
PA1/INT1#
PA0/INT0#
CY7C68013
100-pin TQFP
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
SDA
Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *C
Page 21 of 52
CY7C68013
CY7C68013
56-pin SSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
2
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
3
4
5
6
7
GND
8
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
RESET#
9
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
VCC
DPLUS
DMINUS
GND
VCC
GND
IFCLK
RESERVED
SCL
SDA
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *C
Page 22 of 52
CY7C68013
RESET#
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
3
XTALOUT
XTALIN
AGND
4
5
6
CY7C68013
56-pin QFN
VCC
7
PA2/*SLOE
DPLUS
DMINUS
GND
8
PA1/INT1#
9
PA0/INT0#
10
11
12
13
14
VCC
VCC
CTL2/*FLAGC
CTL1/*FLAGB
GND
*IFCLK
29 CTL0/*FLAGA
RESERVED
Figure 4-5. CY7C68013 56-pin QFN Pin Assignment
* denotes programmable polarity
Document #: 38-08012 Rev. *C
Page 23 of 52
CY7C68013
4.1
CY7C68013 Pin Descriptions
[5]
Table 4-1. FX2 Pin Descriptions
128 100 56 56
TQFP TQFP SSOP QFN
Name
Type
Default
Description
10
13
9
10
13
3
6
AVCC
Power
N/A Analog VCC. This signal provides power to the analog section of
the chip.
12
AGND
Power
N/A Analog Ground. Connect to ground with as short a path as
possible.
19
18
18
17
16
15
9
8
DMINUS
DPLUS
A0
I/O/Z
I/O/Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
H
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
94
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O/Z
8051 Address Bus. This bus is driven at all times. When the
8051 is addressing internal RAM it reflects the internal address.
95
A1
96
A2
97
A3
117
118
119
120
126
127
128
21
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
22
23
24
25
59
8051 Data Bus. This bidirectional bus is high-impedance when
inactive, input for bus reads, and output for bus writes. The data
bus is used for external 8051 program and data memory. The data
bus is active only for external bus accesses, and is driven LOW in
suspend.
60
D1
I/O/Z
61
D2
I/O/Z
62
D3
I/O/Z
63
D4
I/O/Z
86
D5
I/O/Z
87
D6
I/O/Z
88
D7
I/O/Z
39
PSEN#
Output
Program Store Enable. Thisactive-LOWsignalindicatesan8051
code fetch from external memory. It is active for program memory
fetches from 0x2000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
34
28
77
BKPT
Output
Input
L
Breakpoint. This pin goes active (HIGH) when the 8051 address
bus matches the BPADDRH/L registers and breakpoints are
enabled in the BREAKPT register (BPEN = 1). If the BPPULSE bit
in the BREAKPT register is HIGH, this signal pulses HIGH for eight
12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the signal
remains HIGH until the 8051 clears the BREAK bit (by writing 1 to
it) in the BREAKPT register.
99
49
42 RESET#
N/A Active LOW Reset. Resets the entire chip. This pin is normally
tied to VCC through a 100K resistor, and to GND through a 0.1-µF
capacitor.
Note:
5. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power-up and
in standby.
Document #: 38-08012 Rev. *C
Page 24 of 52
CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128
100
56
56
TQFP TQFP SSOP QFN
Name
EA
Type
Default
Description
35
Input
N/A External Access. This pin determines where the 8051 fetches
code between addresses 0x0000 and 0x1FFF. If EA = 0 the 8051
fetches this code from its internal RAM. IF EA = 1 the 8051 fetches
this code from external memory.
12
11
12
5
4
XTALIN
Input
N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive XTALIN with an external 24 MHz square
wave derived from another clock source.
11
1
10
11
5
XTALOUT
Output
O/Z
N/A Crystal Output. Connect this signal to a 24-MHz parallel-
resonant, fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, leave this pin open.
100
54 CLKOUT
12 MHz 12-, 24- or 48-MHz clock, phase locked to the 24-MHz input clock.
The 8051 defaults to 12-MHz operation. The 8051 may tri-state
this output by setting CPUCS.1 = 1.
Port A
82
67
68
69
40
41
42
33 PA0 or
INT0#
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA0) PORTACFG.0
PA0 is a bidirectional IO port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which
is either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83
84
34 PA1 or
INT1#
I
Multiplexed pin whose function is selected by:
(PA1) PORTACFG.1
PA1 is a bidirectional IO port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which
is either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
35 PA2 or
SLOE
I
Multiplexed pin whose function is selected by two bits:
(PA2) IFCONFIG[1:0].
PA2 is a bidirectional IO port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
85
70
43
36 PA3 or
WU2
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA3) WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB Wakeup, enabled by WU2EN
bit (WAKEUP.1) and polarity set by WU2POL (WAKEUP.4). If the
8051 is in suspend and WU2EN = 1, a transition on this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Asserting this pin inhibits the chip from
suspending, if WU2EN=1.
89
90
91
71
72
73
44
45
46
37 PA4 or
FIFOADR0
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by:
(PA4) IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
38 PA5 or
FIFOADR1
I
Multiplexed pin whose function is selected by:
(PA5) IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
39 PA6 or
PKTEND
I
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
(PA6) bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input-only packet end with programmable polarity
(FIFOPOLAR.5) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Document #: 38-08012 Rev. *C
Page 25 of 52
CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128
100
56
56
TQFP TQFP SSOP QFN
Name
Type
Default
Description
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
92
74
47
40 PA7 or
I/O/Z
I
FLAGD or
SLCS#
(PA7) and PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
Port B
44
34
35
36
37
44
45
46
47
25
26
27
28
29
30
31
32
18 PB0 or
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the following bits:
FD[0]
(PB0) IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
45
46
47
54
55
56
57
19 PB1 or
FD[1]
I
Multiplexed pin whose function is selected by the following bits:
(PB1) IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
20 PB2 or
FD[2]
I
Multiplexed pin whose function is selected by the following bits:
(PB2) IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
21 PB3 or
TXD1 or
FD[3]
I
Multiplexed pin whose function is selected by the following bits:
(PB3) IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
22 PB4 or
FD[4]
I
Multiplexed pin whose function is selected by the following bits:
(PB4) IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
23 PB5 or
FD[5]
I
Multiplexed pin whose function is selected by the following bits:
(PB5) IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
24 PB6 or
FD[6]
I
Multiplexed pin whose function is selected by the following bits:
(PB6) IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
25 PB7 or
FD[7]
I
Multiplexed pin whose function is selected by the following bits:
(PB7) IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
PORT C
72
57
58
59
60
61
PC0 or
GPIFADR0
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.0
(PC0) PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73
74
75
76
PC1 or
GPIFADR1
I
Multiplexed pin whose function is selected by PORTCCFG.1
(PC1) PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
PC2 or
GPIFADR2
I
Multiplexed pin whose function is selected by PORTCCFG.2
(PC2) PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
PC3 or
GPIFADR3
I
Multiplexed pin whose function is selected by PORTCCFG.3
(PC3) PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
PC4 or
I
Multiplexed pin whose function is selected by PORTCCFG.4
GPIFADR4
(PC4) PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
Document #: 38-08012 Rev. *C
Page 26 of 52
CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128
100
56
56
TQFP TQFP SSOP QFN
Name
PC5 or
GPIFADR5
Type
Default
Description
Multiplexed pin whose function is selected by PORTCCFG.5
77
78
79
62
63
64
I/O/Z
I
(PC5) PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
PC6 or
GPIFADR6
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by PORTCCFG.6
(PC6) PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
PC7 or
I
Multiplexed pin whose function is selected by PORTCCFG.7
GPIFADR7
(PC7) PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102
80
81
82
83
95
96
97
98
52
53
54
55
56
1
45 PD0 or
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
FD[8]
(PD0) and EPxFIFCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
103
104
105
121
122
123
124
46 PD1 or
FD[9]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD1) and EPxFIFCFG.0 (wordwide) bits.
FD[9] is the bidirectional FIFO/GPIF data bus.
47 PD2 or
FD[10]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD2) and EPxFIFCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
48 PD3 or
FD[11]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD3) and EPxFIFCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
49 PD4 or
FD[12]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD4) and EPxFIFCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
50 PD5 or
FD[13]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD5) and EPxFIFCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
2
51 PD6 or
FD[14]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD6) and EPxFIFCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
3
52 PD7 or
FD[15]
I
Multiplexed pin whose function is selected by the IFCONFIG[1..0]
(PD7) and EPxFIFCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Port E
108
86
87
PE0 or
T0OUT
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.0
(PE0) bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active-HIGH signal from 8051 Timer-counter0.
T0OUT outputs a high level for one CLKOUT clock cycle when
Timer0 overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte timer/counter
overflows.
109
PE1 or
T1OUT
I
Multiplexed pin whose function is selected by the PORTECFG.1
(PE1) bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active-HIGH signal from 8051 Timer-counter1.
T1OUT outputs a high level for one CLKOUT clock cycle when
Timer1 overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
Document #: 38-08012 Rev. *C
Page 27 of 52
CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128
100
56
56
TQFP TQFP SSOP QFN
Name
PE2 or
Type
Default
Description
Multiplexed pin whose function is selected by the PORTECFG.2
110
88
I/O/Z
I
T2OUT
(PE2) bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active-HIGH output signal from 8051 Timer2.
T2OUT is active (HIGH) for one clock cycle when Timer/Counter
2 overflows.
111
89
PE3 or
RXD0OUT
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.3
(PE3) bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If
RXD0OUT is selected and UART0 is in Mode 0, this pin provides
the output data for UART0 only when it is in sync mode. Otherwise
it is a 1.
112
90
PE4 or
I
Multiplexed pin whose function is selected by the PORTECFG.4
RXD1OUT
(PE4) bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When
RXD1OUT is selected and UART1 is in Mode 0, this pin provides
the output data for UART1 only when it is in sync mode. In Modes
1, 2, and 3, this pin is HIGH.
113
114
91
92
PE5 or
INT6
I/O/Z
I/O/Z
I
Multiplexed pin whose function is selected by the PORTECFG.5
(PE5) bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT5 interrupt request input signal. The INT6 pin
is edge-sensitive, active HIGH.
PE6 or
T2EX
I
Multiplexed pin whose function is selected by the PORTECFG.6
(PE6) bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX
reloads timer 2 on its falling edge. T2EX is active only if the EXEN2
bit is set in T2CON.
115
4
93
3
PE7 or
GPIFADR8
I/O/Z
Input
I
Multiplexed pin whose function is selected by the PORTECFG.7
(PE7) bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
8
9
1
2
RDY0 or
SLRD
N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPOLAR.3) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
5
4
RDY1 or
SLWR
Input
N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity
(FIFOPOLAR.2) for the slave FIFOs connected to FDI[7..0] or
FDI[15..0].
6
7
8
9
5
6
7
8
RDY2
RDY3
RDY4
RDY5
Input
Input
Input
Input
N/A RDY2 is a GPIF input signal.
N/A RDY3 is a GPIF input signal.
N/A RDY4 is a GPIF input signal.
N/A RDY5 is a GPIF input signal.
Document #: 38-08012 Rev. *C
Page 28 of 52
CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128
100
56
56
TQFP TQFP SSOP QFN
Name
Type
Default
Description
69
54
36
29 CTL0 or
FLAGA
Output
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the
FIFOADR[1:0] pins.
70
71
55
56
37
38
30 CTL1 or
FLAGB
Output
Output
H
H
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
31 CTL2 or
FLAGC
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0]
pins.
66
67
98
32
51
52
76
26
CTL3
CTL4
Output
Output
Output
I/O/Z
H
H
H
Z
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
CTL5
20
13 IFCLK
Interface Clock, used for synchronously clocking data into or out
of the slave FIFOs. IFCLK also serves as a timing reference for all
slave FIFO control signals and GPIF. When internal clocking,
IFCONFIG.7 = 1, is used the IFCLK pin can be configured to
output 30/48 MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK
may be inverted, whether internally or externally sourced, by
setting the bit
IFCONFIG.4 =1.
28
106
31
22
84
25
INT4
INT5#
T2
Input
Input
Input
N/A INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin
is edge-sensitive, active HIGH.
N/A INT5# is the 8051 INT5 interrupt request input signal. The INT5
pin is edge-sensitive, active LOW.
N/A T2 is the active-HIGH T2 input signal to 8051 Timer2, which
provides the input to Timer2 when C/T2 = 1. When C/T2 = 0,
Timer2 does not use this pin.
30
29
24
23
T1
T0
Input
Input
N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which provides
the input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does
not use this bit.
N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which provides
the input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does
not use this bit.
53
52
43
42
RXD1
TXD1
Input
N/A RXD1is an active-HIGH input signal for 8051 UART1, which
provides data to the UART in all modes.
Output
H
TXD1is an active-HIGH output pin from 8051 UART1, which
provides the output clock in sync mode, and the output data in
async mode.
51
50
41
40
RXD0
TXD0
Input
N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which
provides data to the UART in all modes.
Output
H
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in
async mode.
42
41
CS#
Output
Output
H
H
CS# is the active-LOW chip select for external memory.
32
WR#
WR# is the active-LOW write strobe output for external memory.
Document #: 38-08012 Rev. *C
Page 29 of 52
CY7C68013
Table 4-1. FX2 Pin Descriptions (continued)[5]
128 100 56 56
TQFP TQFP SSOP QFN
Name
Type
Output
Output
Default
Description
40
38
31
RD#
H
H
RD# is the active-LOW read strobe output for external memory.
OE# is the active-LOW output enable for external memory.
OE#
33
27
79
21
51
14 Reserved
44 WAKEUP
Input
Input
N/A Reserved. Connect to ground.
101
N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts
up the oscillator and interrupts the 8051 to allow it to exit the
suspend mode. Holding WAKEUP asserted inhibits the EZ-USB
chip from suspending. This pin has programmable polarity
(WAKEUP.4).
36
37
29
30
22
23
15 SCL
16 SDA
OD
OD
Z
Clock for the I2C-compatible interface. Connect to VCC with a
2.2K resistor, even if no I2C-compatible peripheral is attached.
Z
Data for I2C-compatible interface. Connect to VCC with a 2.2K
resistor, even if no I2C-compatible peripheral is attached.
2
17
1
6
55 VCC
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
N/A VCC. Connect to 3.3V power source.
16
20
33
38
49
53
66
78
85
14
18
24
34
39
50
7
VCC
26
11 VCC
17 VCC
27 VCC
32 VCC
43 VCC
VCC
43
48
64
68
81
100
107
VCC
VCC
3
20
27
49
58
65
80
93
116
125
2
4
53 GND
56 GND
10 GND
12 GND
26 GND
28 GND
41 GND
GND
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
N/A Ground.
19
21
39
48
50
65
75
94
99
7
17
19
33
35
48
GND
GND
14
15
16
13
14
15
NC
NC
NC
N/A
N/A
N/A
N/A No-connect. This pin must be left open.
N/A No-connect. This pin must be left open.
N/A No-connect. This pin must be left open.
Document #: 38-08012 Rev. *C
Page 30 of 52
CY7C68013
5.0
Register Summary
FX2 register bit definitions are described in the FX2 TRM in greater detail.
Table 5-1. FX2 Register Summary
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
xxxxxxxx RW
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform Descriptor
0, 1, 2, 3 data
D7
D6
D5
D4
D3
D2
D1
D0
E480 384 reserved
GENERAL CONFIGURATION
E600
E601
1
1
CPUCS
CPU Control & Status
0
0
PORTCSTB CLKSPD1 CLKSPD0
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES 00000010 rrbbbbbr
IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
IFCLKSRC 3048MHZ
IFCLKOE
FLAGB1
FLAGD1
0
IFCLKPOL
FLAGB0
FLAGD0
0
ASYNC
FLAGA3
FLAGC3
EP3
IFCFG0
11000000
RW
RW
RW
W
[6]
[6]
E602
E603
E604
1
1
1
PINFLAGSAB
Slave FIFO FLAGA and
FLAGB Pin Configuration
FLAGB3
FLAGD3
NAKALL
FLAGB2
FLAGD2
0
FLAGA2
FLAGC2
EP2
FLAGA1
FLAGC1
EP1
FLAGA0 00000000
FLAGC0 01000000
PINFLAGSCD
Slave FIFO FLAGC and
FLAGD Pin Configuration
[6]
FIFORESET
Restore FIFOS to default
state
EP0
xxxxxxxx
E605
E606
E607
E608
1
1
1
1
BREAKPT
BPADDRH
BPADDRL
UART230
Breakpoint Control
0
A15
A7
0
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
BPPULSE
BPEN
A9
0
00000000 rrrrbbbr
Breakpoint Address H
Breakpoint Address L
A10
A2
0
A8
A0
xxxxxxxx
xxxxxxxx
RW
RW
A1
230 Kbaud internally
generated ref. clock
0
230UART1 230UART0 00000000 rrrrrrbb
[6]
E609
E60A
1
1
FIFOPINPOLAR Slave FIFO Interface pins
polarity
0
0
PKTEND
rv5
SLOE
rv4
SLRD
rv3
SLWR
rv2
EF
rv1
FF
00000000 rrbbbbbb
REVID
Chip Revision
rv7
rv6
rv0
Rev A, B -
00000000
Rev C, D -
00000010
Rev E -
R
00000100
[6]
E60B
E60C
1
REVCTL
Chip Revision Control
0
0
0
0
0
0
0
0
0
0
0
0
dyn_out
enh_pkt
00000000 rrrrrrbb
UDMA
1
3
GPIFHOLDTIME MSTB Hold Time (for UDMA)
reserved
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
ENDPOINT CONFIGURATION
E610
1
EP1OUTCFG
Endpoint 1-OUT Configura-
tion
VALID
0
TYPE1
TYPE0
0
0
0
0
10100000 brbbrrrr
E611
E612
E613
E614
E615
1
1
1
1
1
2
1
EP1INCFG
EP2CFG
Endpoint 1-IN Configuration
Endpoint 2 Configuration
Endpoint 4 Configuration
Endpoint 6 Configuration
Endpoint 8 Configuration
VALID
VALID
VALID
VALID
VALID
0
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
0
SIZE
0
0
0
0
0
0
0
BUF1
0
0
BUF0
0
10100000 brbbrrrr
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
DIR
DIR
DIR
DIR
EP4CFG
EP6CFG
SIZE
0
BUF1
0
BUF0
0
EP8CFG
reserved
[6]
[6]
[6]
[6]
E618
E619
E61A
E61B
EP2FIFOCFG
Endpoint 2 / slave FIFO con-
figuration
0
0
0
0
INFM1
INFM1
INFM1
INFM1
OEP1
OEP1
OEP1
OEP1
AUTOOUT
AUTOOUT
AUTOOUT
AUTOOUT
AUTOIN ZEROLENIN
AUTOIN ZEROLENIN
AUTOIN ZEROLENIN
AUTOIN ZEROLENIN
0
0
0
0
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
1
1
1
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
reserved
Endpoint 4 / slave FIFO con-
figuration
Endpoint 6 / slave FIFO con-
figuration
Endpoint 8 / slave FIFO con-
figuration
4
1
E620
E621
E622
E623
E624
E625
E626
E627
EP2AUTOINLENH Endpoint 2 AUTOIN Packet
0
PL7
0
0
PL6
0
0
PL5
0
0
PL4
0
0
PL3
0
PL10
PL2
0
PL9
PL1
PL9
PL1
PL9
PL1
PL9
PL1
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
[6]
Length H
1
1
1
1
1
1
1
EP2AUTOINLENL Endpoint 2 AUTOIN Packet
[6]
Length L
EP4AUTOINLENH Endpoint 4 AUTOIN Packet
[6]
Length H
EP4AUTOINLENL Endpoint 4 AUTOIN Packet
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
PL2
PL10
PL2
0
[6]
Length L
EP6AUTOINLENH Endpoint 6 AUTOIN Packet
[6]
Length H
EP6AUTOINLENL Endpoint 6 AUTOIN Packet
PL7
0
PL6
0
PL5
0
PL4
0
PL3
0
[6]
Length L
EP8AUTOINLENH Endpoint 8 AUTOIN Packet
[6]
Length H
EP8AUTOINLENL Endpoint 8 AUTOIN Packet
PL7
PL6
PL5
PL4
PL3
PL2
[6]
Length L
8
1
reserved
[6]
E630
H.S.
EP2FIFOPFH
Endpoint 2 / slave FIFO Pro-
grammable Flag H
DECIS
DECIS
PFC7
PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
0
0
PFC9
PFC9
PFC1
PFC8
10001000 bbbbbrbb
[6]
E630
F.S.
1
1
EP2FIFOPFH
Endpoint 2 / slave FIFO Pro-
grammable Flag H
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10
IN:PKTS[2] 10001000 bbbbbrbb
OUT:PFC8
[6]
E631
H.S.
EP2FIFOPFL
Endpoint 2 / slave FIFO Pro-
grammable Flag L
PFC6
PFC5
PFC4
PFC3
PFC2
PFC0
00000000
RW
Note:
6. Read and writes to these register may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”
Document #: 38-08012 Rev. *C
Page 31 of 52
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
00000000 RW
[6]
[6]
E631
F.S
1
1
1
1
1
1
1
1
1
1
1
1
1
EP2FIFOPFL
Endpoint 2 / slave FIFO Pro- IN:PKTS[1] IN:PKTS[0]
grammable Flag L
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
OUT:PFC7 OUT:PFC6
E632
H.S.
EP4FIFOPFH
Endpoint 4 / slave FIFO Pro-
grammable Flag H
DECIS
DECIS
PFC7
PKTSTAT
PKTSTAT
PFC6
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
0
0
0
PFC8
PFC8
PFC0
PFC0
PFC8
10001000 bbrbbrrb
10001000 bbrbbrrb
[6]
E632
F.S
EP4FIFOPFH
Endpoint 4 / slave FIFO Pro-
grammable Flag H
0
OUT:PFC10 OUT:PFC9
0
[6]
[6]
[6]
E633
H.S.
EP4FIFOPFL
EP4FIFOPFL
Endpoint 4 / slave FIFO Pro-
grammable Flag L
PFC5
PFC5
PFC4
PFC4
PFC3
PFC3
PFC2
PFC2
0
PFC1
PFC1
PFC9
PFC9
PFC1
PFC1
0
00000000
00000000
RW
RW
E633
F.S
Endpoint 4 / slave FIFO Pro- IN: PKTS[1] IN: PKTS[0]
grammable Flag L
OUT:PFC7 OUT:PFC6
E634
H.S.
EP6FIFOPFH
Endpoint 6 / slave FIFO Pro-
grammable Flag H
DECIS
DECIS
PFC7
PKTSTAT IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
00001000 bbbbbrbb
[6]
E634
F.S
EP6FIFOPFH
Endpoint 6 / slave FIFO Pro-
grammable Flag H
PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10
0
IN:PKTS[2] 00001000 bbbbbrbb
OUT:PFC8
[6]
[6]
[6]
E635
H.S.
EP6FIFOPFL
EP6FIFOPFL
Endpoint 6 / slave FIFO Pro-
grammable Flag L
PFC6
PFC5
PFC5
0
PFC4
PFC4
PFC3
PFC3
PFC2
PFC2
0
PFC0
PFC0
PFC8
PFC8
PFC0
PFC0
00000000
RW
E635
F.S
Endpoint 6 / slave FIFO Pro- IN:PKTS[1] IN:PKTS[0]
grammable Flag L
00000000
RW
OUT:PFC7 OUT:PFC6
E636
H.S.
EP8FIFOPFH
Endpoint 8 / slave FIFO Pro-
grammable Flag H
DECIS
DECIS
PFC7
PKTSTAT
PKTSTAT
PFC6
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
00001000 bbrbbrrb
00001000 bbrbbrrb
[6]
E636
F.S
EP8FIFOPFH
Endpoint 8 / slave FIFO Pro-
grammable Flag H
0
OUT:PFC10 OUT:PFC9
0
0
[6]
[6]
E637
H.S.
EP8FIFOPFL
EP8FIFOPFL
reserved
Endpoint 8 / slave FIFO Pro-
grammable Flag L
PFC5
PFC5
PFC4
PFC4
PFC3
PFC3
PFC2
PFC2
PFC1
PFC1
00000000
00000000
RW
RW
E637
F.S
Endpoint 8 / slave FIFO Pro- IN: PKTS[1] IN: PKTS[0]
grammable Flag L OUT:PFC7 OUT:PFC6
8
1
E640
E641
E642
E643
EP2ISOINPKTS EP2 (if ISO) IN Packets per
frame (1-3)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INPPF1
INPPF1
INPPF1
INPPF1
INPPF0
INPPF0
INPPF0
INPPF0
00000001 rrrrrrbb
00000001 rrrrrrbb
00000001 rrrrrrbb
00000001 rrrrrrbb
1
1
1
4
EP4ISOINPKTS EP4 (if ISO) IN Packets per
frame (1-3)
EP6ISOINPKTS EP6 (if ISO) IN Packets per
frame (1-3)
EP8ISOINPKTS EP8 (if ISO) IN Packets per
frame (1-3)
reserved
[6]
E648
E649
1
7
INPKTEND
Force IN Packet End
Skip
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx
xxxxxxxx
R/W
W
[6]
OUTPKTEND
Force OUT Packet End
INTERRUPTS
[6]
E650
E651
E652
E653
E654
E655
E656
E657
E658
E659
E65A
E65B
1
1
1
1
1
1
1
1
1
1
1
1
EP2FIFOIE
Endpoint 2 slave FIFO Flag
Interrupt Enable
0
0
0
0
0
0
0
0
EDGEPF
PF
PF
EF
EF
EF
EF
EF
EF
EF
EF
EP1
EP1
0
FF
FF
00000000
00000xxx
00000000
00000xxx
00000000
00000xxx
00000000
00000xxx
00000000
00xxxxxx
00000000
xxxxxxxx
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
[6]
EP2FIFOIRQ
Endpoint 2 slave FIFO Flag
Interrupt Request
0
EDGEPF
0
[6]
EP4FIFOIE
Endpoint 4 slave FIFO Flag
Interrupt Enable
0
0
0
0
PF
FF
[6]
[6]
[6]
EP4FIFOIRQ
Endpoint 4 slave FIFO Flag
Interrupt Request
0
0
0
0
PF
FF
[6]
EP6FIFOIE
Endpoint 6 slave FIFO Flag
Interrupt Enable
0
0
0
0
EDGEPF
0
PF
FF
EP6FIFOIRQ
Endpoint 6 slave FIFO Flag
Interrupt Request
0
0
0
0
PF
FF
[6]
EP8FIFOIE
Endpoint 8 slave FIFO Flag
Interrupt Enable
0
0
0
0
EDGEPF
0
PF
FF
EP8FIFOIRQ
IBNIE
Endpoint 8 slave FIFO Flag
Interrupt Request
0
0
0
0
PF
FF
IN-BULK-NAK Interrupt En-
able
0
0
EP8
EP8
EP4
EP4
EP6
EP6
EP2
EP2
EP4
EP2
EP2
EP0
EP0
EP0
EP0
IBN
IBN
IBNIRQ
NAKIE
IN-BULK-NAK interrupt Re-
quest
0
0
EP4
Endpoint Ping-NAK / IBN In-
terrupt Enable
EP8
EP8
EP6
EP6
EP1
NAKIRQ
Endpoint Ping-NAK / IBN In-
terrupt Request
EP1
0
E65C
E65D
E65E
E65F
E660
E661
E662
E663
1
1
1
1
1
1
1
1
USBIE
USBIRQ
EPIE
USB Int Enables
0
0
EP0ACK
EP0ACK
EP6
HSGRANT
HSGRANT
EP4
URES
URES
EP2
SUSP
SUTOK
SOF
SOF
SUDAV
SUDAV
EP0IN
EP0IN
00000000
0xxxxxxx
00000000
xxxxxxxx
RW
RW
RW
RW
RW
RW
RW
RW
USB Interrupt Requests
Endpoint Interrupt Enables
Endpoint Interrupt Requests
GPIF Interrupt Enable
GPIF Interrupt Request
SUSP
SUTOK
EP8
EP8
0
EP1OUT
EP1IN
EP0OUT
EP0OUT
GPIFWF
GPIFWF
0
EPIRQ
EP6
EP4
EP2
EP1OUT
EP1IN
[6]
GPIFIE
0
0
0
0
0
0
0
0
0
0
0
GPIFDONE 00000000
GPIFDONE 000000xx
ERRLIMIT 00000000
ERRLIMIT xxxx000x
[6]
GPIFIRQ
0
0
0
0
USBERRIE
USB Error Interrupt Enables ISOEP8
ISOEP6
ISOEP6
ISOEP4
ISOEP4
ISOEP2
ISOEP2
USBERRIRQ
USB Error Interrupt Re-
quests
ISOEP8
0
E664
E665
E666
E667
1
1
1
1
ERRCNTLIM
USB Error counter and limit
Clear Error Counter EC3:0
Interrupt 2 (USB) Autovector
EC3
EC2
x
EC1
x
EC0
x
LIMIT3
x
LIMIT2
x
LIMIT1
LIMIT0
xxxx0100 rrrrbbbb
CLRERRCNT
INT2IVEC
x
0
1
x
0
0
x
0
0
xxxxxxxx
00000000
10000000
W
R
I2V4
0
I2V3
I4V3
I2V2
I4V2
I2V1
I4V1
I2V0
I4V0
INT4IVEC
Interrupt 4 (slave FIFO &
GPIF) Autovector
R
E668
1
INTSETUP
Interrupt 2&4 Setup
0
0
0
0
AV2EN
0
INT4SRC
AV4EN
00000000
RW
Document #: 38-08012 Rev. *C
Page 32 of 52
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
E669
7
reserved
INPUT / OUTPUT
PORTACFG
E670
E671
E672
1
1
1
I/O PORTA Alternate Config- FLAGD
uration
SLCS
GPIFA6
T2EX
0
0
0
0
INT1
INT0
00000000
00000000
00000000
RW
RW
RW
PORTCCFG
PORTECFG
I/O PORTC Alternate Config- GPIFA7
uration
GPIFA5
INT6
GPIFA4
GPIFA3
GPIFA2
T2OUT
GPIFA1
T1OUT
GPIFA0
T0OUT
I/O PORTE Alternate Config- GPIFA8
uration
RXD1OUT RXD0OUT
E673
E678
5
1
reserved
I2CS
I²C-Compatible Bus
START
d7
STOP
d6
LASTRD
ID1
d4
0
ID0
d3
0
BERR
d2
ACK
d1
DONE
d0
000xx000 bbbrrrrr
Control & Status
E679
E67A
E67B
E67C
1
1
1
1
I2DAT
I²C-Compatible Bus
Data
d5
0
xxxxxxxx
00000000
xxxxxxxx
xxxxxxxx
RW
RW
RW
RW
I2CTL
I²C-Compatible Bus
Control
0
0
0
STOPIE
D1
400KHZ
D0
XAUTODAT1
XAUTODAT2
UDMA CRC
Autoptr1 MOVX access,
when APTREN=1
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
Autoptr2 MOVX access,
when APTREN=1
D7
D1
D0
[6]
E67D
E67E
E67F
1
1
1
UDMACRCH
UDMA CRC MSB
UDMA CRC LSB
UDMA CRC Qualifier
CRC15
CRC7
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
CRC10
CRC2
CRC9
CRC1
CRC8
CRC0
01001010
10111010
RW
RW
[6]
UDMACRCL
UDMACRC-
QUALIFIER
QENABLE
QSTATE
QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
USBCS
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
USB Control & Status
Put chip into suspend
Wakeup Control & Status
Toggle Control
HSM
x
0
x
0
0
DISCON NOSYNSOF
RENUM
x
SIGRSUME x0000000 rrrrbbbb
SUSPEND
WAKEUPCS
TOGCTL
x
x
WUPOL
IO
x
0
x
x
xxxxxxxx
W
WU2
Q
WU
S
WU2POL
DPEN
EP2
FC10
FC2
MF2
FA2
WU2EN
EP1
WUEN
EP0
FC8
FC0
MF0
FA0
xx000101 bbbbrbbb
xxxxxxxx rbbbbbbb
R
0
EP3
0
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
USB Frame count H
USB Frame count L
Microframe count, 0-7
USB Function address
0
0
0
FC9
00000xxx
xxxxxxxx
00000xxx
0xxxxxxx
R
R
R
R
FC7
0
FC6
0
FC5
0
FC4
0
FC3
0
FC1
MF1
FA1
0
FA6
FA5
FA4
FA3
reserved
ENDPOINTS
[6]
E68A
E68B
E68C
E68D
E68E
E68F
E690
E691
E692
E694
E695
E696
E698
E699
E69A
E69C
E69D
E69E
E6A0
1
1
1
1
1
1
1
1
2
1
1
2
1
1
2
1
1
2
1
EP0BCH
Endpoint 0 Byte Count H
Endpoint 0 Byte Count L
(BC15)
(BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx
xxxxxxxx
RW
RW
[6]
EP0BCL
reserved
EP1OUTBC
reserved
Endpoint 1 OUT Byte Count
0
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0xxxxxxx
RW
EP1INBC
Endpoint 1 IN Byte Count
Endpoint 2 Byte Count H
Endpoint 2 Byte Count L
0
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
0xxxxxxx
00000xxx
xxxxxxxx
RW
RW
RW
[6]
EP2BCH
[6]
EP2BCL
BC7/SKIP
BC6
BC5
BC4
BC3
reserved
[6]
EP4BCH
Endpoint 4 Byte Count H
Endpoint 4 Byte Count L
0
0
0
0
0
0
BC9
BC1
BC8
BC0
000000xx
xxxxxxxx
RW
RW
[6]
EP4BCL
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
reserved
[6]
EP6BCH
Endpoint 6 Byte Count H
Endpoint 6 Byte Count L
0
0
0
0
0
BC10
BC2
BC9
BC1
BC8
BC0
00000xxx
xxxxxxxx
RW
RW
[6]
EP6BCL
BC7/SKIP
BC6
BC5
BC4
BC3
reserved
[6]
EP8BCH
Endpoint 8 Byte Count H
Endpoint 8 Byte Count L
0
0
0
0
0
0
BC9
BC1
BC8
BC0
000000xx
xxxxxxxx
RW
RW
[6]
EP8BCL
BC7/SKIP
BC6
BC5
BC4
BC3
BC2
reserved
EP0CS
Endpoint 0 Control and Sta-
tus
HSNAK
0
0
0
0
0
BUSY
STALL
STALL
STALL
STALL
STALL
STALL
STALL
10000000 bbbbbbrb
00000000 bbbbbbrb
00000000 bbbbbbrb
00101000 rrrrrrrb
00101000 rrrrrrrb
00000100 rrrrrrrb
00000100 rrrrrrrb
E6A1
E6A2
E6A3
E6A4
E6A5
E6A6
1
1
1
1
1
1
EP1OUTCS
EP1INCS
EP2CS
Endpoint 1 OUT Control and
Status
0
0
0
0
0
0
0
0
0
0
0
BUSY
Endpoint 1 IN Control and
Status
0
NPAK2
0
0
0
0
0
BUSY
Endpoint 2 Control and Sta-
tus
NPAK1
NPAK1
NPAK1
NPAK1
NPAK0
NPAK0
NPAK0
NPAK0
FULL
FULL
FULL
FULL
EMPTY
EMPTY
EMPTY
EMPTY
0
0
0
0
EP4CS
Endpoint 4 Control and Sta-
tus
EP6CS
Endpoint 6 Control and Sta-
tus
NPAK2
0
EP8CS
Endpoint 8 Control and Sta-
tus
E6A7
E6A8
E6A9
E6AA
E6AB
1
1
1
1
1
EP2FIFOFLGS
EP4FIFOFLGS
EP6FIFOFLGS
EP8FIFOFLGS
EP2FIFOBCH
Endpoint 2 slave FIFO Flags
Endpoint 4 slave FIFO Flags
Endpoint 6 slave FIFO Flags
Endpoint 8 slave FIFO Flags
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PF
PF
EF
EF
FF
FF
00000010
00000010
00000110
00000110
00000000
R
R
R
R
R
0
0
0
0
PF
EF
FF
0
0
PF
EF
FF
Endpoint 2 slave FIFO total
byte count H
BC12
BC11
BC10
BC9
BC8
Document #: 38-08012 Rev. *C
Page 33 of 52
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
E6A
C
1
1
1
1
1
1
1
1
1
1
EP2FIFOBCL
EP4FIFOBCH
EP4FIFOBCL
EP6FIFOBCH
EP6FIFOBCL
EP8FIFOBCH
EP8FIFOBCL
SUDPTRH
Endpoint 2 slave FIFO total
byte count L
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000
00000000
00000000
00000000
00000000
00000000
00000000
xxxxxxxx
R
E6A
D
Endpoint 4 slave FIFO total
byte count H
0
BC7
0
0
BC6
0
0
BC5
0
0
BC4
0
0
BC3
BC11
BC3
0
BC10
BC2
BC10
BC2
BC10
BC2
A10
A2
BC9
BC1
BC9
BC1
BC9
BC1
A9
BC8
BC0
BC8
BC0
BC8
BC0
A8
R
E6AE
E6AF
E6B0
E6B1
E6B2
E6B3
E6B4
E6B5
Endpoint 4 slave FIFO total
byte count L
R
Endpoint 6 slave FIFO total
byte count H
R
Endpoint 6 slave FIFO total
byte count L
BC7
0
BC6
0
BC5
0
BC4
0
R
Endpoint 8 slave FIFO total
byte count H
R
Endpoint 8 slave FIFO total
byte count L
BC7
A15
A7
0
BC6
A14
A6
0
BC5
A13
A5
0
BC4
A12
A4
0
BC3
A11
A3
R
Setup Data Pointer high ad-
dress byte
RW
SUDPTRL
Setup Data Pointer low ad-
dress byte
A1
0
xxxxxxx0 bbbbbbbr
SUDPTRCTL
Setup Data Pointer Auto
Mode
0
0
0
SDPAUTO 00000001
RW
2
8
reserved
E6B8
SETUPDAT
8 bytes of SETUP data
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx
R
SETUPDAT[0] =
bmRequestType
SETUPDAT[1] = bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] = wLength
GPIF
E6C0
E6C1
1
1
GPIFWFSELECT Waveform Selector
SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0
FIFORD1
0
FIFORD0 11100100
IDLEDRV 10000000
RW
RW
GPIFIDLECS
GPIF Done, GPIF IDLEdrive
mode
DONE
0
0
0
0
0
E6C2
E6C3
E6C4
E6C5
1
1
1
1
GPIFIDLECTL
GPIFCTLCFG
Inactive Bus, CTL states
CTL Drive Type
GPIF Address H
GPIF Address L
0
0
CTL5
CTL5
0
CTL4
CTL4
0
CTL3
CTL3
0
CTL2
CTL2
0
CTL1
CTL1
0
CTL0
CTL0
11111111
00000000
00000000
00000000
RW
RW
RW
RW
TRICTL
0
0
0
[6]
GPIFADRH
GPIFA8
GPIFA0
[6]
GPIFADRL
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
FLOWSTATE
E6C6
1
FLOWSTATE
Flowstate Enable and Selec-
tor
FSE
0
0
0
0
FS2
FS1
FS0
00000000 brrrrbbb
E6C7
E6C8
1
1
FLOWLOGIC
Flowstate Logic
LFUNC1
CTL0E3
LFUNC0
CTL0E2
TERMA2
TERMA1
TERMA0
CTL3
TERMB2
CTL2
TERMB1
CTL1
TERMB0 00000000
RW
RW
FLOWEQ0CTL
CTL-Pin States in Flowstate
(when Logic = 0)
CTL0E1/
CTL5
CTL0E0/
CTL4
CTL0
00000000
E6C9
1
1
1
1
1
1
1
1
1
2
FLOWEQ1CTL
CTL-Pin States in Flowstate
(when Logic = 1)
CTL0E3
CTL0E2
CTL0E1/
CTL5
CTL0E0/
CTL4
CTL3
CTL2
HOCTL2
MSTB2
0
CTL1
HOCTL1
MSTB1
FALLING
D1
CTL0
00000000
RW
RW
RW
E6C
A
FLOWHOLDOFF Holdoff Configuration
HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD0 HOSTATE
HOCTL0 00010010
E6C
B
FLOWSTB
Flowstate Strobe Configura-
tion
SLAVE
0
RDYASYNC CTLTOGL
SUSTAIN
0
0
MSTB0
RISING
D0
00100000
E6C
C
FLOWSTBEDGE Flowstate Rising/Falling
Edge Configuration
0
0
0
00000001 rrrrrrbb
E6C
D
FLOWSTBPERI- Master-Strobe Half-Period
D7
D6
D5
D4
D3
D2
00000010
00000000
00000000
00000000
00000001
00000000
RW
RW
RW
RW
RW
RW
OD
[6]
E6C
E
GPIFTCB3
GPIFTCB2
GPIFTCB1
GPIFTCB0
GPIF Transaction Count
Byte 3
TC31
TC23
TC15
TC7
TC30
TC22
TC14
TC6
TC29
TC21
TC13
TC5
TC28
TC20
TC12
TC4
TC27
TC19
TC11
TC3
TC26
TC18
TC10
TC2
TC25
TC24
TC16
TC8
[6]
[6]
[6]
E6CF
E6D0
E6D1
GPIF Transaction Count
Byte 2
TC17
GPIF Transaction Count
Byte 1
TC9
GPIF Transaction Count
Byte 0
TC1
TC0
reserved
reserved
reserved
E6D2
E6D3
E6D4
1
1
EP2GPIFFLGSEL Endpoint 2 GPIF Flag select
[6]
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000
RW
RW
W
EP2GPIFPFSTOP Endpoint 2 GPIF stop trans-
FIFO2FLAG 00000000
action on prog. flag
[6]
1
3
EP2GPIFTRIG
reserved
Endpoint 2 GPIF Trigger
x
x
xxxxxxxx
reserved
reserved
E6D
A
1
1
1
3
EP4GPIFFLGSEL Endpoint 4 GPIF Flag select
[6]
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000
RW
RW
W
E6D
B
EP4GPIFPFSTOP Endpoint 4 GPIF stop trans-
FIFO4FLAG 00000000
xxxxxxxx
action on GPIF Flag
[6]
E6D
C
EP4GPIFTRIG
reserved
Endpoint 4 GPIF Trigger
x
x
Document #: 38-08012 Rev. *C
Page 34 of 52
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
reserved
reserved
Description
b7
b6
b5
b4
b3
b2
b1
b0
Default Access
E6E2
E6E3
E6E4
1
EP6GPIFFLGSEL Endpoint 6 GPIF Flag select
[6]
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000
RW
RW
W
1
EP6GPIFPFSTOP Endpoint 6 GPIF stop trans-
FIFO6FLAG 00000000
action on prog. flag
[6]
1
3
EP6GPIFTRIG
reserved
Endpoint 6 GPIF Trigger
x
x
xxxxxxxx
reserved
reserved
E6EA
E6EB
1
1
1
EP8GPIFFLGSEL Endpoint 8 GPIF Flag select
[6]
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
0
0
x
FS1
0
FS0
00000000
RW
RW
W
EP8GPIFPFSTOP Endpoint 8 GPIF stop trans-
FIFO8FLAG 00000000
action on prog. flag
[6]
E6E
C
EP8GPIFTRIG
reserved
Endpoint 8 GPIF Trigger
x
x
xxxxxxxx
3
1
E6F0
E6F1
E6F2
E6F3
XGPIFSGLDATH GPIF Data H (16-bit mode
only)
D15
D7
D14
D6
D13
D5
D12
D4
D4
0
D11
D3
D3
0
D10
D2
D2
0
D9
D1
D1
0
D8
D0
D0
0
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
RW
R
1
1
1
XGPIFSGLDATLX Read/Write GPIF Data L &
trigger transaction
XGPIFSGLDATL- Read GPIF Data L, no trans-
D7
D6
D5
NOX
action trigger
GPIFREADYCFG Internal RDY, Sync/Async,
RDY pin states
INTRDY
SAS
TCXRDY5
00000000 bbbrrrrr
E6F4
E6F5
E6F6
1
1
2
GPIFREADYSTAT GPIF Ready Status
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx
xxxxxxxx
R
GPIFABORT
reserved
Abort GPIF Waveforms
W
ENDPOINT BUFFERS
E740 64 EP0BUF
E780 64 EP10UTBUF
E7C0 64 EP1INBUF
2048 reserved
EP0-IN/-OUT buffer
EP1-OUT buffer
EP1-IN buffer
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
RW
RW
RW
RW
F000 1024 EP2FIFOBUF
512/1024-byte EP 2 / slave
FIFO buffer (IN or OUT)
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
F400 512 EP4FIFOBUF
512 byte EP 4 / slave FIFO
buffer (IN or OUT)
RW
F600 512 reserved
F800 1024 EP6FIFOBUF
512/1024-byte EP 6 / slave
FIFO buffer (IN or OUT)
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
RW
FC00 512 EP8FIFOBUF
FE00 512 reserved
512 byte EP 8 / slave FIFO
buffer (IN or OUT)
xxxx
I²C Compatible Configuration Byte
0
DISCON
0
0
0
0
0
400KHZ
xxxxxxxx
[8]
n/a
Special Function Registers (SFRs)
[7]
80
81
82
83
84
85
86
87
88
1
1
1
1
1
1
1
1
1
IOA
SP
Port A (bit addressable)
Stack Pointer
D7
D7
D6
D6
A6
A14
A6
A14
0
D5
D5
A5
A13
A5
A13
0
D4
D4
A4
A12
A4
A12
0
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
00000111
00000000
00000000
00000000
00000000
00000000
00110000
00000000
RW
RW
RW
RW
RW
RW
RW
RW
RW
DPL0
DPH0
Data Pointer 0 L
Data Pointer 0 H
Data Pointer 1 L
Data Pointer 1 H
Data Pointer 0/1 select
Power Control
A7
A3
A2
A1
A0
A15
A7
A11
A3
A10
A2
A9
A8
[7]
DPL1
DPH1
A1
A0
[7]
A15
0
A11
0
A10
0
A9
A8
[7]
DPS
0
SEL
IDLE
IT0
PCON
TCON
SMOD0
TF1
x
1
1
GF1
IE1
GF0
IT1
STOP
IE0
Timer/Counter Control (bit
addressable)
TR1
TF0
TR0
89
8A
8B
8C
8D
8E
8F
90
91
92
1
1
1
1
1
1
1
1
1
1
TMOD
TL0
Timer/Counter Mode Control
Timer 0 reload L
GATE
D7
CT
D6
D6
D14
D14
x
M1
D5
M0
D4
GATE
D3
CT
D2
M1
D1
M0
D0
00000000
00000000
00000000
00000000
00000000
00000001
RW
RW
RW
RW
RW
RW
TL1
Timer 1 reload L
D7
D5
D4
D3
D2
D1
D0
TH0
Timer 0 reload H
Timer 1 reload H
Clock Control
D15
D15
x
D13
D13
T2M
D12
D12
T1M
D11
D11
T0M
D10
D10
MD2
D9
D8
TH1
D9
D8
[7]
CKCON
MD1
MD0
reserved
[7]
IOB
Port B (bit addressable)
External Interrupt Flag(s)
D7
IE5
A15
D6
IE4
A14
D5
I²CINT
A13
D4
USBNT
A12
D3
1
D2
0
D1
0
D0
0
xxxxxxxx
00001000
00000000
RW
RW
RW
[7]
EXIF
[7]
MPAGE
Upper Addr Byte of MOVX
using @R0 / @R1
A11
A10
A9
A8
93
98
5
1
reserved
SCON0
Serial Port 0 Control (bit ad-
dressable)
SM0_0
D7
SM1_0
D6
SM2_0
D5
REN_0
D4
TB8_0
D3
RB8_0
D2
TI_0
RI_0
00000000
RW
RW
R = all bits read-only
00000000
99
1
SBUF0
Serial Port 0 Data Buffer
D1
D0
Notes:
W = all bits write-only
r = read-only bit
7. SFRs not part of the standard 8051 architecture.
8. If no EEPROM is detected by the SIE then the default is 00000000.
w = write-only bit
b = both read/write bit
Document #: 38-08012 Rev. *C
Page 35 of 52
CY7C68013
Table 5-1. FX2 Register Summary (continued)
Hex Size Name
Description
b7
A15
A7
b6
A14
A6
b5
A13
A5
b4
A12
A4
b3
A11
A3
b2
A10
A2
b1
A9
A1
b0
A8
A0
Default Access
[7]
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A8
1
1
1
1
1
1
1
1
1
5
1
AUTOPTRH1
Autopointer 1 Address H
Autopointer 1 Address L
00000000
00000000
RW
RW
[7]
AUTOPTRL1
reserved
[7]
AUTOPTRH2
Autopointer 2 Address H
Autopointer 2 Address L
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000
00000000
RW
RW
[7]
AUTOPTRL2
reserved
[7]
IOC
Port C (bit addressable)
Interrupt 2 clear
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
xxxxxxxx
xxxxxxxx
xxxxxxxx
RW
W
[7]
INT2CLR
[7]
INT4CLR
Interrupt 4 clear
x
x
x
x
x
x
x
x
W
reserved
IE
Interrupt Enable (bit addres-
sable)
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000
RW
A9
AA
AB
1
1
1
reserved
[7]
EP2468STAT
Endpoint 2,4,6,8 status flags
EP8F
0
EP8E
EP6F
EP6E
EP4F
0
EP4E
EP2F
EP2E
01011010
00100010
R
R
[7]
EP24FIFOFLGS Endpoint 2,4 slave FIFO sta-
tus flags
EP4PF
EP4EF
EP4FF
EP2PF
EP2EF
EP2FF
[7]
AC
1
EP68FIFOFLGS Endpoint 6,8 slave FIFO sta-
0
EP8PF
EP8EF
EP8FF
0
EP6PF
EP6EF
EP6FF
01100110
R
tus flags
AD
AF
2
1
reserved
AUTOPTRSET-
Autopointer 1&2 Setup
0
0
0
0
0
APTR2INC APTR1INC
APTREN 00000110
RW
[7]
UP
[7]
B0
B1
B2
B3
B4
B5
B6
B7
B8
1
1
1
1
1
1
1
1
1
IOD
Port D (bit addressable)
Port E (NOT bit addressable)
Port A Output Enable
Port B Output Enable
Port C Output Enable
Port D Output Enable
Port E Output Enable
D7
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
xxxxxxxx
xxxxxxxx
00000000
00000000
00000000
00000000
00000000
RW
RW
RW
RW
RW
RW
RW
[7]
IOE
[7]
OEA
[7]
OEB
[7]
OEC
[7]
OED
[7]
OEE
reserved
IP
Interrupt Priority (bit addres-
sable)
1
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000
RW
B9
BA
BB
1
1
1
reserved
[7]
EP01STAT
Endpoint 0&1 Status
0
0
0
0
0
0
0
0
0
EP1INBSY EP1OUTBSY EP0BSY 00000000
R
[7] [6]
GPIFTRIG
Endpoint 2,4,6,8 GPIF slave
FIFO Trigger
DONE
RW
EP1
EP0
10000xxx brrrrbbb
BC
BD
1
1
reserved
[7]
GPIFSGLDATH
GPIF Data H (16-bit mode
only)
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx
RW
[7]
BE
BF
1
1
GPIFSGLDATLX GPIF Data L w/ Trigger
GPIFSGLDATL- GPIF Data L w/ No Trigger
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
xxxxxxxx
xxxxxxxx
RW
R
[7]
NOX
[7]
C0
1
SCON1
Serial Port 1 Control (bit ad-
dressable)
SM0_1
D7
SM1_1
D6
SM2_1
D5
REN_1
D4
TB8_1
D3
RB8_1
D2
TI_1
D1
RI_1
D0
00000000
00000000
RW
RW
[7]
C1
C2
C8
1
6
1
SBUF1
reserved
T2CON
Serial Port 1 Data Buffer
Timer/Counter 2 Control (bit
addressable)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000
RW
C9
CA
1
1
reserved
RCAP2L
Capture for Timer 2, auto-re-
load, up-counter
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
00000000
00000000
RW
RW
CB
1
RCAP2H
Capture for Timer 2, auto-re-
load, up-counter
CC
CD
CE
D0
1
1
2
1
TL2
Timer 2 reload L
Timer 2 reload H
D7
D6
D5
D4
D3
D2
D1
D9
D0
D8
00000000
00000000
RW
RW
TH2
D15
D14
D13
D12
D11
D10
reserved
PSW
Program Status Word (bit ad-
dressable)
CY
AC
F0
RS1
RS0
OV
F1
P
00000000
RW
D1
D8
D9
E0
7
1
7
1
reserved
[7]
EICON
External Interrupt Control
SMOD1
D7
1
ERESI
D5
RESI
D4
INT6
D3
0
0
0
01000000
00000000
RW
RW
reserved
ACC
Accumulator (bit address-
able)
D6
D2
D1
D0
E1
E8
E9
F0
F1
F8
7
1
7
1
7
1
reserved
[7]
EIE
External Interrupt Enable(s)
B (bit addressable)
1
D7
1
1
D6
1
1
D5
1
EX6
D4
EX5
D3
EX4
D2
EI²C
D1
EUSB
D0
11100000
00000000
11100000
RW
RW
RW
reserved
B
reserved
[7]
EIP
External Interrupt Priority
Control
PX6
PX5
PX4
PI²C
PUSB
F9
7
reserved
Document #: 38-08012 Rev. *C
Page 36 of 52
CY7C68013
6.0
Absolute Maximum Ratings
Storage Temperature .................................................................................................................................... –65°C to +150°C
Ambient Temperature with Power Supplied........................................................................................................ 0°C to +70°C
Supply Voltage to Ground Potential..................................................................................................................–0.5V to +4.0V
DC Input Voltage to Any Input Pin ................................................................................................................................. 5.25V
DC Voltage Applied to Outputs in High Z State....................................................................................... –0.5V to VCC + 0.5V
Power Dissipation ...................................................................................................................................................... 936 mW
Static Discharge Voltage............................................................................................................................................ > 2000V
Max Output Current, per I/O port .................................................................................................................................. 10 mA
Max Output Current, all five I/O ports (128- and 100-pin packages) ............................................................................ 50 mA
7.0
Operating Conditions
TA (Ambient Temperature Under Bias) ............................................................................................................... 0°C to +70°C
Supply Voltage..................................................................................................................................................+3.0V to +3.6V
Ground Voltage.................................................................................................................................................................... 0V
FOSC (Oscillator or Crystal Frequency)...................................................................................................... 24 MHz ± 100 ppm
Parallel Resonant
8.0
DC Characteristics
Table 8-1. DC Characteristics
Parameter
VCC
VIH
Description
Conditions
Min.
3.0
2
Typ.
Max.
3.6
Unit
V
Supply Voltage
3.3
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Voltage HIGH
Output LOW Voltage
Output Current HIGH
Output Current LOW
Input Pin Capacitance
5.25
0.8
V
VIL
–0.5
V
II
0< VIN < VCC
±10
µA
V
VOH
VOL
IOH
IOUT = 4 mA
2.4
IOUT = –4 mA
0.4
4
V
mA
mA
pF
pF
µA
µA
mA
mA
ms
IOL
4
CIN
Except D+/D–
10
D+/D–
15
ISUSP
Suspend Current
Connected
250
30
400
180
260
150
Disconnected
ICC
Supply Current
8051 running, connected to USB HS
8051 running, connected to USB FS
Vcc min = 3.0V
200
90
TRESET
Reset Time after valid power
1.91
8.1
USB Transceiver
USB 2.0-certified in full- and high-speed modes.
Note:
9. Connected to the USB includes 1.5k ohm internal pull-up. Disconnected has the 1.5k ohm internal pull-up excluded.
Document #: 38-08012 Rev. *C
Page 37 of 52
CY7C68013
9.0
9.1
AC Electrical Characteristics
USB Transceiver
USB 2.0-certified in full- and high-speed modes.
9.2
Program Memory Read
tCL
CLKOUT[10]
tAV
tAV
A[15..0]
tSTBH
tSTBL
PSEN#
D[7..0]
[11]
tACC1
tDH
data in
tSOEL
OE#
CS#
tSCSL
Figure 9-1. Program Memory Read Timing Diagram
Table 9-1. Program Memory Read Parameters
Parameter Description
tCL 1/CLKOUT Frequency
Min.
Typ.
20.83
41.66
83.2
Max.
Unit
Notes
48 MHz
24 MHz
12 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAV
Delay from Clock to Valid Address
Clock to PSEN Low
Clock to PSEN High
Clock to OE Low
0
0
0
10.7
8
tSTBL
tSTBH
tSOEL
tSCSL
tDSU
tDH
8
11.1
13
Clock to CS Low
Data Set-up to Clock
Data Hold Time
9.6
0
Notes:
10. CLKOUT is shown with positive polarity.
11. tACC1 is computed from the above parameters as follows:
tACC1(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.
Document #: 38-08012 Rev. *C
Page 38 of 52
CY7C68013
9.3
Data Memory Read
tCL
Stretch = 0
CLKOUT[10]
tAV
tAV
A[15..0]
tSTBH
tSTBL
RD#
tSCSL
CS#
OE#
tSOEL
tDSU
[12]
tACC1
tDH
D[7..0]
data in
Stretch = 1
tCL
CLKOUT[10]
tAV
A[15..0]
RD#
CS#
tDSU
[12]
tACC1
tDH
D[7..0]
data in
Figure 9-2. Data Memory Read Timing Diagram
Table 9-2. Data Memory Read Parameters
Parameter Description
tCL 1/CLKOUT Frequency
Min.
Typ.
20.83
41.66
83.2
Max.
Unit
Notes
48 MHz
24 MHz
12 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAV
Delay from Clock to Valid Address
Clock to RD LOW
10.7
11
tSTBL
tSTBH
tSCSL
tSOEL
tDSU
Clock to RD HIGH
11
Clock to CS LOW
13
Clock to OE LOW
11.1
Data Set-up to Clock
Data Hold Time
9.6
0
tDH
Note:
12. tACC2 and tACC3 are computed from the above parameters as follows:
tACC2(24 MHz) = 3*tCL – tAV –tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV –tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
Document #: 38-08012 Rev. *C
Page 39 of 52
CY7C68013
9.4
Data Memory Write
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
CS#
tSCSL
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
A[15..0]
tAV
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Figure 9-3. Data Memory Write Timing Diagram
Table 9-3. Data Memory Write Parameters
Parameter Description
Min.
Max.
10.7
11.2
11.2
13.0
13.1
13.1
Unit
ns
Notes
tAV
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
0
0
0
tSTBL
tSTBH
tSCSL
tON1
ns
ns
ns
0
0
ns
tOFF1
Clock to Data Hold Time
ns
Document #: 38-08012 Rev. *C
Page 40 of 52
CY7C68013
9.5
GPIF Synchronous Signals
tIFCLK
IFCLK
tSGA
GPIFADR[8:0]
RDYX
tSRY
tRYH
DATA(input)
valid
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N
N+1
tXGD
Figure 9-4. GPIF Synchronous Signals Timing Diagram[13]
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[14, 15]
Parameter
tIFCLK
Description
Min.
20.83
8.9
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
RDYX to Clock Set-up Time
Clock to RDYX
GPIF Data to Clock Set-up Time
GPIF Data Hold Time
9.2
0
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
7.5
11
6.7
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[15]
Parameter
tIFCLK
Description
Min.
20.83
2.9
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IFCLK Period
200
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
RDYX to Clock Set-up Time
Clock to RDYX
3.7
GPIF Data to Clock Set-up Time
GPIF Data Hold Time
3.2
4.5
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTLX Output Propagation Delay
11.5
15
10.7
Notes:
13. Dashed lines denote signals with programmable polarity
14. GPIF asynchronous RDYx signals have a minimum set-up time of 50 ns when using internal 48-MHz IFCLK.
15. IFCLK must not exceed 48 MHz.
Document #: 38-08012 Rev. *C
Page 41 of 52
CY7C68013
9.6
Slave FIFO Synchronous Read
tIFCLK
IFCLK
SLRD
tRDH
tSRD
tXFLG
FLAGS
DATA
N
N+1
tXFD
tOEon
tOEoff
SLOE
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram[13]
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[15]
Parameter
tIFCLK
Description
Min.
20.83
18.7
0
Max.
Unit
ns
IFCLK Period
tSRD
tRDH
tOEon
tOEoff
tXFLG
tXFD
SLRD to Clock Set-up Time
ns
Clock to SLRD Hold Time
ns
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
10.5
10.5
9.5
ns
ns
ns
11
ns
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[15]
Parameter
tIFCLK
Description
Min.
20.83
12.7
3.7
Max.
Unit
ns
IFCLK Period
200
tSRD
tRDH
tOEon
tOEoff
tXFLG
tXFD
SLRD to Clock Set-up Time
ns
Clock to SLRD Hold Time
ns
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
Clock to FLAGS Output Propagation Delay
Clock to FIFO Data Output Propagation Delay
10.5
10.5
13.5
15
ns
ns
ns
ns
Document #: 38-08012 Rev. *C
Page 42 of 52
CY7C68013
9.7
Slave FIFO Asynchronous Read
tRDpwh
SLRD
tRDpwl
tXFLG
tXFD
FLAGS
DATA
SLOE
N+1
N
tOEon
tOEoff
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram[13]
Table 9-8. Slave FIFO Asynchronous Read Parameters[16]
Parameter Description
tRDpwl SLRD Pulse Width LOW
Min.
50
Max.
Unit
ns
tRDpwh
tXFLG
tXFD
SLRD Pulse Width HIGH
50
ns
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
70
15
ns
ns
tOEon
tOEoff
10.5
10.5
ns
ns
9.8
Slave FIFO Synchronous Write
tIFCLK
IFCLK
SLWR
tWRH
tSWR
DATA
Z
N
tSFD tFDH
Z
FLAGS
tXFLG
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram[13]
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK [15]
Parameter
tIFCLK
Description
Min.
20.83
18.1
0
Max.
Unit
ns
IFCLK Period
tSWR
tWRH
tSFD
tFDH
SLWR to Clock Set-up Time
ns
Clock to SLWR Hold Time
ns
FIFO Data to Clock Set-up Time
Clock to FIFO Data Hold Time
Clock to FLAGS Output Propagation Time
9.2
ns
0
ns
tXFLG
9.5
ns
Note:
16. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Document #: 38-08012 Rev. *C
Page 43 of 52
CY7C68013
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [15]
Parameter
tIFCLK
Description
Min.
20.83
12.1
3.6
Max.
Unit
ns
IFCLK Period
200
tSWR
tWRH
tSFD
SLWR to Clock Set-up Time
ns
Clock to SLWR Hold Time
ns
FIFO Data to Clock Set-up Time
Clock to FIFO Data Hold Time
Clock to FLAGS Output Propagation Time
3.2
ns
tFDH
tXFLG
4.5
ns
13.5
ns
9.9
Slave FIFO Asynchronous Write
tWRpwh
SLWR/SLCS#
tWRpwl
tFDH
tSFD
DATA
tXFD
FLAGS
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram[13]
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [16]
Parameter
tWRpwl
tWRpwh
tSFD
Description
Min.
50
Max.
Unit
ns
SLWR Pulse LOW
SLWR Pulse HIGH
70
ns
SLWR to FIFO DATA Set-up Time
FIFO DATA to SLWR Hold Time
10
ns
tFDH
10
ns
tXFD
SLWR to FLAGS Output Propagation Delay
70
ns
9.10
Slave FIFO Synchronous Packet End Strobe
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram[13]
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK [15]
Parameter
tIFCLK
Description
Min.
20.83
14.6
0
Max.
Unit
ns
IFCLK Period
tSPE
tPEH
tXFLG
PKTEND to Clock Set-up Time
ns
Clock to PKTEND Hold Time
ns
Clock to FLAGS Output Propagation Delay
9.5
ns
Document #: 38-08012 Rev. *C
Page 44 of 52
CY7C68013
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK [15]
Parameter
tIFCLK
Description
Min.
20.83
8.6
Max.
Unit
ns
IFCLK Period
200
tSPE
tPEH
tXFLG
PKTEND to Clock Set-up Time
ns
Clock to PKTEND Hold Time
2.5
ns
Clock to FLAGS Output Propagation Delay
13.5
ns
9.11
Slave FIFO Asynchronous Packet End Strobe
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[13]
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters[16]
Parameter
tPEpwl
tPWpwh
tXFLG
Description
PKTEND Pulse Width LOW
Min.
50
Max.
Unit
ns
PKTEND Pulse Width HIGH
50
ns
PKTEND to FLAGS Output Propagation Delay
70
ns
9.12
Slave FIFO Output Enable
SLOE
tOEoff
tOEon
DATA
Figure 9-11. Slave FIFO Output Enable Timing Diagram[13]
Table 9-15. Slave FIFO Output Enable Parameters
Parameter
tOEon
Description
SLOE Assert to FIFO DATA Output
SLOE Deassert to FIFO DATA Hold
Min.
Max.
10.5
10.5
Unit
ns
tOEoff
ns
9.13
Slave FIFO Address to Flags/Data
FIFOADR [1.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram[13]
Document #: 38-08012 Rev. *C
Page 45 of 52
CY7C68013
Table 9-16. Slave FIFO Address to Flags/Data Parameters
Parameter
tXFLG
Description
Min.
Max.
10.7
14.3
Unit
ns
FIFOADR[1:0] to FLAGS Output Propagation Delay
FIFOADR[1:0] to FIFODATA Output Propagation Delay
tXFD
ns
9.14
Slave FIFO Synchronous Address
IFCLK
SLCS/FIFOADR [1:0]
tSFA
tFAH
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram
Table 9-17. Slave FIFO Synchronous Address Parameters [15]
Parameter Description
tIFCLK Interface Clock Period
tSFA
tFAH
Min.
20.83
25
Max.
Unit
ns
200
FIFOADR[1:0] to Clock Set-up Time
Clock to FIFOADR[1:0] Hold Time
ns
10
ns
9.15
Slave FIFO Asynchronous Address
SLCS/FIFOADR [1:0]
tFAH
tSFA
RD/WR/PKTEND
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram[13]
Table 9-18. Slave FIFO Asynchronous Address Parameters[16]
Parameter
tSFA
tFAH
Description
Min.
10
Max.
Unit
ns
FIFOADR[1:0] to RD/WR/PKTEND Set-up Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
10
ns
10.0
Ordering Information
Table 10-1. Ordering Information
8051
Address
/Data Busses
Ordering Code
Package Type
RAM Size
# Prog I/Os
CY7C68013-128AC
CY7C68013-100AC
CY7C68013-56PVC
CY7C68013-56LFC
CY3681
128 TQFP
8K
8K
8K
8K
40
16/8 bit
100 TQFP
56 SSOP
56 QFN
40
24
24
–
–
–
EZ-USB FX2 Xcelerator Development Kit
Document #: 38-08012 Rev. *C
Page 46 of 52
CY7C68013
11.0
Package Diagrams
The FX2 is available in four packages:
• 56-pin SSOP
• 56-pin QFN
• 100-pin TQFP
• 128-pin TQFP.
51-85062-*C
Figure 11-1. 56-lead Shrunk Small Outline Package O56
51-85144-*B
Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 X 8 mm) LF56
Document #: 38-08012 Rev. *C
Page 47 of 52
CY7C68013
51-85050-*A
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
Document #: 38-08012 Rev. *C
Page 48 of 52
CY7C68013
51-85101-*B
Figure 11-4. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128
Document #: 38-08012 Rev. *C
Page 49 of 52
CY7C68013
12.0
PCB Layout Recommendations[17]
The following recommendations should be followed to ensure reliable high-performance operation.
• At least a four-layer impedance controlled boards are required to maintain signal quality.
• Specify impedance targets (ask your board vendor what they can achieve).
• To control impedance, maintain trace widths and trace spacing.
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal ground must be done near the USB connector.
• Bypass/flyback caps on VBus, near connector, are recommended.
• DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other in length, with preferred length of 20-30 mm.
• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces.
• It is preferred is to have no vias placed on the DPLUS or DMINUS trace routing.
• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.
13.0
Quad Flat Package No Leads (QFN) Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred
from the FX2 through the device’s metal paddle on the bottom side of the package. Heat from here, is conducted to the PCB at
the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of via. A via is a plated
through hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal
pad. Solder mask is placed on the board top side over each via to resist solder flow into the via. The mask on the top side also
minimizes outgassing during the solder reflow process.
For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s
MicroLeadFrame (MLF) Technology.” This application note can be downloaded from AMKOR’s website from the following URL
http://www.amkor.com/products/notes_papers/MLF_AppNote_0902.pdf. The application note provides detailed information on
board mounting guidelines, soldering flow, rework process, etc.
Figure 13-1 below display a cross-sectional area underneath the package. The cross section is of only one via. The solder paste
template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5
mil. It is recommended that “No Clean”, type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during
reflow.
0.017” dia
Solder Mask
Cu Fill
Cu Fill
0.013” dia
PCB Material
PCB Material
Via hole for thermally connecting the
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane
QFN to the circuit board ground plane.
Figure 13-1. Cross-section of the Area Underneath the QFN Package
Figure 13-2 is a plot of the solder mask pattern and Figure 13-3 displays an X-Ray image of the assembly (darker areas indicate
solder.)
Figure 13-2. Plot of the Solder Mask (White Area)
Note:
17. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High
Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
Document #: 38-08012 Rev. *C
Page 50 of 52
CY7C68013
Figure 13-3. X-ray image of the assembly
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. EZ-USB FX2 and ReNumeration are trademarks, and EZ-USB is a registered trademark, of Cypress
Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-08012 Rev. *C
Page 51 of 52
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C68013
Document History Page
Document Title: CY7C68013 EZ-USB FX2™ USB Microcontroller High-speed USB Peripheral Controller
Document Number: 38-08012
Issue
Date
Orig. of
REV.
**
ECN NO.
111753
Change Description of Change
11/15/01
02/20/02
DSG
KKU
Change from Spec number: 38-00929 to 38-08012
*A
111802
Update functional changes between revision D part and revision E part.
Changed timing data from simulation data to revision E characterization data.
*B
115480
06/26/02
01/06/03
KKU
KKU
Added new 56-pin Quad Flatpack No Lead package and pinout.
Revised pin description table to reflect new package.
Corrected Figure 9-8 by moving tsfd parameter location.
Corrected labels on Dplus and Dminus in Table 4-1.
Removed Preliminary from spec title.
*C
120776
Added bus powered references and PCB layout recommendations and QFN
package design notes.
Updated QFN package drawing 51-85144 to current revision.
Document #: 38-08012 Rev. *C
Page 52 of 52
相关型号:
©2020 ICPDF网 联系我们和版权申明