CY3682_技术文档

CY7C68001

EZ-USB SX2™ High-Speed USB Interface Device

1.0

EZ-USB SX2™ Features

2.0

Applications

• USB 2.0-certified compliant

• DSL modems

—On the USB-IF Integrators List: Test ID Number

40000713

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

• Operates at high (480 Mbps) or full (12 Mbps) speed

• Supports Control Endpoint 0:

—Used for handling USB device requests

• Scanners

• Supports four configurable endpoints that share a 4-

KB FIFO space

• Home PNA

• Wireless LAN

• MP3 players

• Networking

—Endpoints 2, 4, 6, 8 for application-specific control

and data

• Standard 8- or 16-bit external master interface

• Printers

—Glueless interface to most standard microproces-

sors DSPs, ASICs, and FPGAs

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB applications. Each

reference design comes complete with firmware source code

and object code, schematics, and documentation. Please see

the Cypress web site at www.cypress.com.

—Synchronous or Asynchronous interface

• Integrated phase-locked loop (PLL)

• 3.3V operation, 5V tolerant I/Os

• 56-pin SSOP and QFN package

• Complies with most device class specifications

2.1

Block Diagram

SCL

SDA

I2C Bus

Controller

(Master Only)

IFCLK*

Read*, Write*, OE*, PKTEND*, CS#

Interrupt#, Ready

24 MHz

XTAL

PLL

SX2 Internal Logic

Flags (3/4)

Address (3)

Control

VCC

FIFO

Data

Bus

1.5K

8/16-Bit Data

CY Smart USB

FS/HS Engine

4 KB

FIFO

DPLUS

DMINUS

Data

USB 2.0 XCVR

Figure 2-1. Block Diagram

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-08013 Rev. *E

Revised July 13, 2004

FOR

CY7C68001

2.2

Introduction

3.3

Boot Methods

The EZ-USB SX2™ USB interface device is designed to work

with any external master, such as standard microprocessors,

DSPs, ASICs, and FPGAs to enable USB 2.0 support for any

peripheral design. SX2 has a built-in USB transceiver and

Serial Interface Engine (SIE), along with a command decoder

for sending and receiving USB data. The controller has four

endpoints that share a 4-KB FIFO space for maximum flexi-

bility and throughput, as well as Control Endpoint 0. SX2 has

three address pins and a selectable 8- or 16- bit data bus for

command and data input or output.

During the power-up sequence, internal logic of the SX2

2

[1,2]

checks for the presence of an I C EEPROM.

If it finds an

EEPROM, it will boot off the EEPROM. When the presence of

an EEPROM is detected, the SX2 checks the value of first

byte. If the first byte is found to be a 0xC4, the SX2 loads the

next two bytes into the IFCONFIG and POLAR registers,

respectively. If the fourth byte is also 0xC4, the SX2

enumerates using the descriptor in the EEPROM, then signals

to the external master when enumeration is complete via an

ENUMOK interrupt (Section 3.4). If no EEPROM is detected,

the SX2 relies on the external master for the descriptors. Once

this descriptor information is receive from the external master,

the SX2 will connect to the USB bus and enumerate.

2.3

System Diagram

3.3.1

EEPROM Organization

The valid sequence of bytes in the EEPROM are displayed

below

W indows/USB Capable Host

Table 3-1. Descriptor Length Set to 0x06:

Default Enumeration

Byte Index

Description

USB

Cable

0

1

0xC4

IFCONFIG

POLAR

0xC4

USB Connection

2

3

4

Descriptor Length (LSB):0x06

Descriptor Length (MSB): 0x00

VID (LSB)

Cypress

SX2

EEPROM

5

RAM/ROM

6

Device CPU

Application

7

VID (MSB)

8

PID (LSB)

9

PID (MSB)

10

11

DID (LSB)

Figure 2-2. Example USB System Diagram

DID (MSB)

3.0

3.1

Functional Overview

USB Signaling Speed

Table 3-2. Descriptor Length Not Set to 0x06

Byte Index

Description

SX2 operates at two of the three rates defined in the Universal

Serial Bus Specification Revision 2.0, dated April 27, 2000:

0

1

2

3

4

5

6

7

8

0xC4

IFCONFIG

POLAR

0xC4

• Full-speed, with a signaling bit rate of 12 Mbits/s

• High-speed, with a signaling bit rate of 480 Mbits/s.

SX2 does not support the low-speed signaling rate of 1.5

Mbits/s.

Descriptor Length (LSB)

Descriptor Length (MSB

Descriptor[0]

3.2

Buses

Descriptor[1]

SX2 features:

Descriptor[2]

• A selectable 8- or 16-bit bidirectional data bus

• An address bus for selecting the FIFO or Command Inter-

face.

Notes:

1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0

to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and double-

byte EEPROMs (24LC64, etc.) should be strapped to address 001.

2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull-up values are 2.2K – 10K

Ohms.

Document #: 38-08013 Rev. *E

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• 0xC4: This initial byte tells the SX2 that this is a valid EE-

PROM with configuration information.

3.4

Interrupt System

3.4.1

Architecture

• IFCONFIG: The IFCONFIG byte contains the settings for

the IFCONFIG register. The IFCONFIG register bits are de-

fined in Section 7.1. If the external master requires an in-

terface configurationdifferentfrom thedefault,thatinterface

can be specified by this byte.

The SX2 provides an output signal that indicates to the

external master that the SX2 has an interrupt condition, or that

the data from a register read request is available. The SX2 has

six interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK,

BUSACTIVITY, and READY. Each interrupt can be enabled or

disabled by setting or clearing the corresponding bit in the

INTENABLE register.

• POLAR: The Polar byte contains the polarity of the FIFO

flag pin signals. The POLAR register bits are defined in

Section 7.3. If the external master requires signal polarity

different from the default, the polarity can be specified by

this byte.

When an interrupt occurs, the INT# pin will be asserted, and

the corresponding bit will be set in the Interrupt Status Byte.

The external master reads the Interrupt Status Byte by

strobing SLRD/SLOE. This presents the Interrupt Status Byte

on the lower portion of the data bus (FD[7:0]). Reading the

Interrupt Status Byte automatically clears the interrupt. Only

one interrupt request will occur at a time; the SX2 buffers

multiple pending interrupts.

• Descriptor: The Descriptor byte determines if the SX2

loads the descriptor from the EEPROM. If this byte = 0xC4,

the SX2 will load the descriptor starting with the next byte.

If this byte does not equal 0xC4, the SX2 will wait for de-

scriptor information from the external master.

• Descriptor Length: The Descriptor length is within the next

two bytesand indicate the length of the descriptorcontained

within the EEPROM. The length is loaded least significant

byte (LSB) first, then most significant byte (MSB).

If the external master has initiated a register read request, the

SX2 will buffer interrupts until the external master has read the

data. This insures that after a read sequence has begun, the

next interrupt that is received from the SX2 will indicate that

the corresponding data is available. Following is a description

of this INTENABLE register.

• Byte 7 Starts Descriptor Information: The descriptor can

be a maximum of 500 bytes.

3.3.2

Default Enumeration

3.4.2

INTENABLE Register Bit Definition

An optional default descriptor can be used to simplify enumer-

ation. Only the Vendor ID (VID), Product ID (PID), and Device

ID (DID) need to be loaded by the SX2 for it to enumerate with

this default set-up. This information is either loaded from an

EEPROM in the case when the presence of an EEPROM

(Table 3-1) is detected, or the external master may simply load

a VID, PID, and DID when no EEPROM is present. In this

default enumeration, the SX2 uses the in-built default

descriptor (refer to Section 12.0).

Bit 7: SETUP

If this interrupt is enabled, and the SX2 receives a set-up

packet from the USB host, the SX2 asserts the INT# pin and

sets bit 7 in the Interrupt Status Byte. This interrupt only occurs

if the set-up request is not one that the SX2 automatically

handles. For complete details on how to handle the SETUP

interrupt, refer to Section 5.0 of this data sheet.

Bit 6: EP0BUF

If the descriptor length loaded from the EEPROM is 6, SX2 will

load a VID, PID, and DID from the EEPROM and enumerate.

The VID, PID, and DID are loaded LSB, then MSB. For

example, if the VID, PID, and DID are 0x0547, 0x1002, and

0x0001, respectively, then the bytes should be stored as:

If this interrupt is enabled, and the Endpoint 0 buffer becomes

available to the external master for read or write operations,

the SX2 asserts the INT# pin and sets bit 6 in the Interrupt

Status Byte. This interrupt is used for handling the data phase

of a set-up request. For complete details on how to handle the

EP0BUF interrupt, refer to Section 5.0 of this data sheet.

• 0x47, 0x05, 0x02, 0x10, 0x01, 0x00.

Bit 5: FLAGS

If there is no EEPROM, SX2 will wait for the external master

to provide the descriptor information. To use the default

descriptor, the external master must write to the appropriate

register (0x30) with descriptor length equal to 6 followed by the

VID, PID, and DID. Refer to Section 4.2 for further information

on how the external master may load the values.

If this interrupt is enabled, and any OUT endpoint FIFO’s state

changes from empty to not-empty, the SX2 asserts the INT#

pin and sets bit 5 in the Interrupt Status Byte. This is an

alternate way to monitor the status of OUT endpoint FIFOs

instead of using the FLAGA-FLAGD pins, and can be used to

indicate when an OUT packet has been received from the

host.

The default descriptor enumerates four endpoints as listed in

the following page:

Bit 2: ENUMOK

• Endpoint 2: Bulk out, 512 bytes in high-speed mode, 64

bytes in full-speed mode

If this interrupt is enabled and the SX2 receives

a

SET_CONFIGURATION request from the USB host, the SX2

asserts the INT# pin and sets bit 2 in the Interrupt Status Byte.

This event signals the completion of the SX2 enumeration

process.

• Endpoint 4: Bulk out, 512 bytes in high-speed mode, 64

bytes in full-speed mode

• Endpoint 6:Bulk in, 512 bytes in high-speed mode, 64 bytes

in full-speed mode

Bit 1: BUSACTIVITY

• Endpoint 8:Bulk in, 512 bytes in high-speed mode, 64 bytes

in full-speed mode.

If this interrupt is enabled, and the SX2 detects either an

absence or resumption of activity on the USB bus, the SX2

asserts the INT# pin and sets bit 1 in the Interrupt Status Byte.

This usually indicates that the USB host is either suspending

The entire default descriptor is listed in Section 12.0 of this

data sheet.

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or resuming or that a self-powered device has been plugged

in or unplugged. If the SX2 is bus-powered, the external

master must put the SX2 into a low-power mode after

detecting a USB suspend condition to be USB-compliant.

RESET# signal. The Clock must be in a stable state for at least

200 us before the RESET is released.

3.5.2

USB Reset

Bit 0: READY

When the SX2 detects a USB Reset condition on the USB bus,

SX2 handles it like any other enumeration sequence. This

means that SX2 will enumerate again and assert the

ENUMOK interrupt to let the external master know that it has

enumerated. The external master will then be responsible for

configuring the SX2 for the application. The external master

should also check whether SX2 enumerated at High or Full

speed in order to adjust the EPxPKTLENH/L register values

accordingly. The last initialization task is for the external

master to flush all of the SX2 FIFOs.

If this interrupt is enabled, bit 0 in the Interrupt Status Byte is

set when the SX2 has powered up and performed a self-test.

The external master should always wait for this interrupt

before trying to read or write to the SX2, unless an external

EEPROM with a valid descriptor is present. If an external

EEPROM with a valid descriptor is present, the ENUMOK

interrupt will occur instead of the READY interrupt after power

up. A READY interrupt will also occur if the SX2 is awakened

from a low-power mode via the WAKEUP pin. This READY

interrupt indicates that the SX2 is ready for commands or data.

3.5.3

Wakeup

Although it is true that all interrupts will be buffered once a

command read request has been initiated, in very rare condi-

tions, there might be a situation when there is a pending

interrupt already, when a read request is initiated by the

external master. In this case it is the interrupt status byte that

will be output when the external master asserts the SLRD. So,

a condition exists where the Interrupt Status Data Byte can be

mistaken for the result of a command register read request. In

order to get around this possible race condition, the first thing

that the external master must do on getting an interrupt from

the SX2 is check the status of the READY pin. If the READY

is low at the time the INT# was asserted, the data that will be

output when the external master strobes the SLRD is the

interrupt status byte (not the actual data requested). If the

READY pin is high at the time when the interrupt is asserted,

the data output on strobing the SLRD is the actual data byte

requested by the external master. So it is important that the

state of the READY pin be checked at the time the INT# is

asserted to ascertain the cause of the interrupt.

The SX2 exits its low-power state when one of the following

events occur:

• USB bus signals a resume. The SX2 will assert a BUSAC-

TIVITY interrupt.

• The external master asserts the WAKEUP pin. TheSX2 will

assert a READY interrupt

[3]

.

3.6

3.6.1

Endpoint RAM

Size

• Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).

• FIFO Endpoints: 4096 Bytes: 8 × 512 bytes (Endpoint 2, 4,

6, 8).

3.6.2

Organization

• EP0–Bidirectional Endpoint 0, 64-byte buffer.

• EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or iso-

chronous. EP2 and EP6 can be either double-, triple-, or

quad-buffered. EP4 and EP8 can only be double-buffered.

For high-speed endpoint configuration options, see

Figure 3-1.

3.5

Resets and Wakeup

3.5.1

Reset

An input pin (RESET#) resets the chip. The internal PLL stabi-

lizes after V has reached 3.3V. Typically, an external RC

CC

network (R = 100 K Ohms, C = 0.1 uf) is used to provide the

Note:

3. if the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic will perform RESUME

signalling after a WAKEUP interrupt.

Document #: 38-08013 Rev. *E

Page 4 of 42

FOR

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3.6.3

Endpoint Configurations (High-speed Mode)

EP0 IN&O UT

64

G roup C

G roup A

512

1024

512

EP2

EP4

512

1024

EP2

G roup B

512

EP6

EP8

1024

EP6

EP8

512

EP6

512

EP8

Figure 3-1. Endpoint Configuration

Endpoint 0 is the same for every configuration as it serves as

the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to

Figure 3-1. Endpoints 2, 4, 6, and 8 may be configured by

choosing either:

3.7.1

Architecture

The SX2 slave FIFO architecture has eight 512-byte blocks in

the endpoint RAM that directly serve as FIFO memories and

are controlled by FIFO control signals (IFCLK, CS#, SLRD,

SLWR, SLOE, PKTEND, and FIFOADR[2:0]).

• One configuration from Group A and one from Group B

• One configuration from Group C.

The SX2 command interface is used to set up the SX2, read

status, load descriptors, and access Endpoint 0. The

command interface has its own READY signal for gating

writes, and an INT# signal to indicate that the SX2 has data to

be read, or that an interrupt event has occurred. The command

interface uses the same control signals (IFCLK, CS#, SLRD,

SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface,

except for PKTEND.

Some example endpoint configurations are as follows.

• EP2: 1024 bytes double-buffered, EP6: 512 bytes quad-

buffered.

• EP2: 512 bytes double-buffered, EP4: 512 bytes double-

buffered, EP6: 512 bytes double-buffered, EP8: 512 bytes

double buffered.

• EP2: 1024 bytes quad-buffered.

3.7.2

Control Signals

3.6.4

Default Endpoint Memory Configuration

3.7.2.1 FIFOADDR Lines

At power-on-reset, the endpoint memories are configured as

follows:

The SX2 has three address pins that are used to select either

the FIFOs or the command interface. The addresses corre-

spond to the following table.

• EP2: Bulk OUT, 512 bytes/packet, 2x buffered.

• EP4: Bulk OUT, 512 bytes/packet, 2x buffered.

• EP6: Bulk IN, 512 bytes/packet, 2x buffered.

• EP8: Bulk IN, 512 bytes/packet, 2x buffered.

Table 3-3. FIFO Address Lines Setting

Address/Selection FIFOADR2 FIFOADR1 FIFOADR0

FIFO2

FIFO4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3.7

External Interface

FIFO6

The SX2 presents two interfaces to the external master.

FIFO8

1. A FIFO interface through which EP2, 4, 6, and 8 data flows.

COMMAND

RESERVED

2. A command interface, which is used to set up the SX2, read

status, load descriptors, and access Endpoint 0.

Document #: 38-08013 Rev. *E

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The SX2 accepts either an internally derived clock (30 or 48

MHz) or externally supplied clock (IFCLK, 5-50 MHz), and

SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals

from an external master. The interface can be selected for 8-

or 16- bit operation by an internal configuration bit, and an

Output Enable signal SLOE enables the data bus driver of the

selected width. The external master must ensure that the

output enable signal is inactive when writing data to the SX2.

The interface can operate either asynchronously where the

SLRD and SLWR signals act directly as strobes, or synchro-

nously where the SLRD and SLWR act as clock qualifiers. The

optional CS# signal will tristate the data bus and ignore SLRD,

SLWR, PKTEND.

• Asynchronous–SLRD, SLWR, and PKTEND pins are

strobes.

• Synchronous–SLRD, SLWR, and PKTEND pins are en-

ables for the IFCLK clock pin.

An external master accesses the FIFOs through the data bus,

FD [15:0]. This bus can be either 8- or 16-bits wide; the width

is selected via the WORDWIDE bit in the EPxPKTLENH/L

registers. The data bus is bidirectional, with its output drivers

controlled by the SLOE pin. The FIFOADR[2:0] pins select

which of the four FIFOs is connected to the FD [15:0] bus, or

if the command interface is selected.

3.7.5

FIFO Flag Pins Configuration

The external master reads from OUT endpoints and writes to

IN endpoints, and reads from or writes to the command

interface.

The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD.

These FLAGx pins report the status of the FIFO selected by

the FIFOADR[2:0] pins. At reset, these pins are configured to

report the status of the following:

3.7.2.2 Read: SLOE and SLRD

In synchronous mode, the FIFO pointer is incremented on

each rising edge of IFCLK while SLRD is asserted. In

asynchronous mode, the FIFO pointer is incremented on each

asserted-to-deasserted transition of SLRD.

• FLAGA reports the status of the programmable flag.

• FLAGB reports the status of the full flag.

• FLAGC reports the status of the empty flag.

• FLAGD defaults to the CS# function.

SLOE is a data bus driver enable. When SLOE is asserted, the

data bus is driven by the SX2.

The FIFO flags can either be indexed or fixed. Fixed flags

report the status of a particular FIFO regardless of the value

on the FIFOADR [2:0] pins. Indexed flags report the status of

3.7.2.3 Write: SLWR

[4]

In synchronous mode, data on the FD bus is written to the

FIFO (and the FIFO pointer is incremented) on each rising

edge of IFCLK while SLWR is asserted. In asynchronous

mode, data on the FD bus is written to the FIFO (and the FIFO

pointer is incremented) on each asserted-to-deasserted

transition of SLWR.

the FIFO selected by the FIFOADR [2:0]pins.

3.7.6

Default FIFO Programmable Flag Set-up

By default, FLAGA is the Programmable Flag (PF) for the

endpoint being pointed to by the FIFOADR[2:0] pins. For EP2

and EP4, the default endpoint configuration is BULK, OUT,

512, 2x, and the PF pin asserts when the entire FIFO has

greater than/equal to 512 bytes. For EP6 and EP8, the default

endpoint configuration is BULK, IN, 512, 2x, and the PF pin

asserts when the entire FIFO has less than/equal to 512 bytes.

In other words, EP6/8 report a half-empty state, and EP2/4

report a half-full state. The polarity of the programmable flag

is set to active low and cannot be altered.

3.7.2.4 PKTEND

PKTEND commits the current buffer to USB. To send a short

IN packet (one which has not been filled to max packet size

determined by the value of PL[X:0] in EPxPKTLENH/L), the

external master strobes the PKTEND pin.

All these interface signals have a default polarity of low. In

order to change the polarity of PKTEND pin, the master may

write to the POLAR register anytime. In order to switch the

polarity of the SLWR/SLRD/SLOE, the master must set the

appropriate bits 2, 3 and 4 respectively in the FIFOPINPOLAR

register located at XDATA space 0xE609. Please note that the

SX2 powers up with the polarities set to low. Section 7.3

provides further information on how to access this register

located at XDATA space.

3.7.7

Each FIFO’s programmable-level flag (PF) asserts when the

FIFO reaches user-defined fullness threshold. That

FIFO Programmable Flag (PF) Set-up

a

threshold is configured as follows:

1. For OUT packets: The threshold is stored in PFC12:0. The

PF is asserted when the number of bytes in the entire FIFO

is less than/equal to (DECIS = 0) or greater than/equal to

(DECIS = 1) the threshold.

3.7.3

IFCLK

The IFCLK pin can be configured to be either an input (default)

or an output interface clock. Bits IFCONFIG[7:4] define the

behavior of the interface clock. To use the SX2’s internally-

derived 30- or 48-MHz clock, set IFCONFIG.7 to 1 and set

IFCONFIG.6 to 0 (30 MHz) or to 1 (48 MHz). To use an exter-

nally supplied clock, set IFCONFIG.7=0 and drive the IFCLK

pin (5 MHz – 50 MHz). The input or output IFCLK signal can

be inverted by setting IFCONFIG.4=1.

2. For IN packets, with PKTSTAT = 1: The threshold is stored

in PFC9:0. The PF is asserted when the number of bytes

written into the current packet in the FIFO is less than/equal

to (DECIS = 0) or greater than/equal to (DECIS = 1) the

threshold.

3. For IN packets, with PKTSTAT = 0: The threshold is stored

in two parts: PKTS2:0 holds the number of committed pack-

ets, and PFC9:0 holds the number of bytes in the current

packet. The PF is asserted when the FIFO is at or less full

than (DECIS = 0), or at or more full than (DECIS = 1), the

threshold.

3.7.4

FIFO Access

An external master can access the slave FIFOs either

asynchronously or synchronously:

Document #: 38-08013 Rev. *E

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3.7.8

Command Protocol

• The next six bits represent the register address (000001

binary = 0x01 hex).

An address of [1 0 0] on FIFOADR [2:0] will select the

command interface. The command interface is used to write

to and read from the SX2 registers and the Endpoint 0 buffer,

as well as the descriptor RAM. Command read and write trans-

actions occur over FD[7:0] only. Each byte written to the SX2

is either an address or a data byte, as determined by bit7. If

bit7 = 1, then the byte is considered an address byte. If bit7 =

0, then the byte is considered a data byte. If bit7 = 1, then bit6

determines whether the address byte is a read request or a

write request. If bit6 = 1, then the byte is considered a read

request. If bit6 = 0 then the byte is considered a write request.

Bits [5:0] hold the register address of the request. The format

of the command address byte is shown in Table 3-4.

Once the byte has been received the SX2 pulls the READY

pin low to inform the external master not to send any more

information. When the SX2 is ready to receive the next byte,

the SX2 pulls the READY pin high again. This next byte, the

upper nibble of the data byte, is written to the SX2 as follows.

Table 3-8. Command Data Write Byte One

Address/ Don’t

Don’t

Care

Don’t

Care

Data#

Care

D7

D6

D5

D4

0

X

1

0

1

• The first bit signifies that this is a data transfer.

• The next three are don’t care bits.

Table 3-4. Command Address Byte

• The next four bits hold the upper nibble of the transferred

byte.

Address/

Data#

Read/

Write#

A5

A4

A3

A2

A1

A0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Once the byte has been received the SX2 pulls the READY

pin low to inform the external master not to send any more

information. When the SX2 is ready to receive the next byte,

the SX2 pulls the READY pin high again. This next byte, the

lower nibble of the data byte is written to the SX2.

Each Write request is followed by two or more data bytes. If

another address byte is received before both data bytes are

received, the SX2 ignores the first address and any incomplete

data transfers. The format for the data bytes is shown in

Table 3-5 and Table 3-6. Some registers take a series of bytes.

Each byte is transferred using the same protocol.

Table 3-9. Command Data Write Byte Two

Address/

Data#

Don’t

Care

Don’t

Care

Don’t

Care

D3

D2

D1

D0

Table 3-5. Command Data Byte One

0

X

0

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

At this point the entire byte <10110000> has been transferred

to register 0x01 and the write sequence is complete.

0

X

D7

D6

D5

D4

Table 3-6. Command Data Byte Two

3.7.8.2 Read Request Example

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The Read cycle is simpler than the write cycle. The Read cycle

consists of a read request from the external master to the SX2.

For example, to read the contents of register 0x01, a

command address byte is written to the SX2 as follows.

0

X

D3

D2

D1

D0

The first command data byte contains the upper nibble of data,

and the second command byte contains the lower nibble of

data.

Table 3-10. Command Address Read Byte

Address/ Read/

3.7.8.1 Write Request Example

Data#

Write#

A5

A4

A3

A2

A1

A0

Prior to writing to a register, two conditions must be met:

FIFOADR[2:0] must hold [1 0 0], and the Ready line must be

HIGH. The external master should not initiate a command if

the READY pin is not in a HIgh state.

1

0

1

When the data is ready to be read, the SX2 asserts the INT#

pin to tell the external master that the data it requested is

waiting on FD[7:0].

[5]

Example: to write the byte <10110000> into the IFCONFIG

register (0x01), first send a command address byte as follows.

Table 3-7. Command Address Write Byte

Address/ Read/

Data#

Write#

A5

A4

A3

A2

A1

A0

1

0

1

• The first bit signifies an address transfer.

• The second bit signifies that this is a write command.

Note:

4. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).

5. An important note: Once the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources

described in Section 3.4 is asserted, the SX2 will buffer that interrupt until the read request completes.

Document #: 38-08013 Rev. *E

Page 7 of 42

FOR

CY7C68001

4.0

Enumeration

5.0

Endpoint 0

The SX2 has two modes of enumeration. The first mode is

automatic through EEPROM boot load, as described in

Section 3.3. The second method is a manual load of the

descriptor or VID, PID, and DID as described below.

The SX2 will automatically respond to USB chapter 9 requests

without any external master intervention. If the SX2 receives

a request to which it cannot respond automatically, the SX2

will notify the external master. The external master then has

the choice of responding to the request or stalling.

After the SX2 receives a set-up packet to which it cannot

respond automatically, the SX2 will assert a SETUP interrupt.

After the external master reads the Interrupt Status Byte to

determine that the interrupt source was the SETUP interrupt,

it can initiate a read request to the SETUP register, 0x32.

When the SX2 sees a read request for the SETUP register, it

will present the first byte of set-up data to the external master.

Each additional read request will present the next byte of set-

up data, until all eight bytes have been read.

4.1

Standard Enumeration

The SX2 has 500 bytes of descriptor RAM into which the

external master may write its descriptor. The descriptor RAM

is accessed through register 0x30. To load a descriptor, the

external master does the following:

• Initiate a Write Request to register 0x30.

• Write two bytes (four command data transfers) that define

the length of the entire descriptor about to be transferred.

The LSB is written first, followed by the MSB.

[6]

The external master can stall this request at this or any other

time. To stall a request, the external master initiates a write

request for the SETUP register, 0x32, and writes any non-zero

value to the register.

[6]

• Write the descriptor, one byte at a time until complete.

Note: the register address is only written once.

After the entire descriptor has been transferred, the SX2 will

float the pull-up resistor connected to D+, and parse through

the descriptor to locate the individual descriptors. After the

SX2 has parsed the entire descriptor, the SX2 will connect the

pull-up resistor and enumerate automatically. When enumer-

ation is complete, the SX2 will notify the external master with

an ENUMOK interrupt.

If this set-up request has a data phase, the SX2 will then

interrupt the external master with an EP0BUF interrupt when

the buffer becomes available. The SX2 determines the

direction of the set-up request and interrupts when either:

• IN: the Endpoint 0 buffer becomes available to write to, or

• OUT: the Endpoint 0 buffer receives a packet from the USB

host.

The format and order of the descriptor should be as follows

(see Section 12.0 for an example):

For an IN set-up transaction, the external master can write up

to 64 bytes at a time for the data phase. The steps to write a

packet are as follows:

• Device.

• Device qualifier.

1. Wait for an EP0BUF interrupt, indicating that the buffer is

available.

• High-speed configuration, high-speed interface, high-

speed endpoints.

2. Initiate a write request for register 0x31.

3. Write one data byte.

• Full-speed configuration, full-speed interface, full-speed

endpoints.

• String.

4. Repeat steps 2 and 3 until either all the data or 64 bytes

have been written, whichever is less.

4.2

Default Enumeration

5. Write the number of bytes in this packet to the byte count

register, 0x33.

The external master may simply load a VID, PID, and DID and

use the default descriptor built into the SX2. To use the default

descriptor, the descriptor length described above must equal

6. After the external master has written the length, the VID,

PID, and DID must be written LSB, then MSB. For example, if

the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001

respectively, then the external master does the following:

To send more than 64 bytes, the process is repeated. The SX2

internally stores the length of the data phase that was

specified in the wLength field (bytes 6,7) of the set-up packet.

To send less than the requested amount of data, the external

master writes a packet that is less than 64 bytes, or if a multiple

of 64, the external master follows the data with a zero-length

packet. When the SX2 sees a short or zero-length packet, it

will complete the set-up transfer by automatically completing

the handshake phase. The SX2 will not allow more data than

the wLength field specified in the set-up packet. Note: the

PKTEND pin does not apply to Endpoint 0. The only way to

send a short or zero length packet is by writing to the byte

count register with the appropriate value.

• Initiates a Write Request to register 0x30.

• Writes two bytes (four command data transfers) that define

the length of the entire descriptor about to be transferred.

In this case, the length is always six.

• Writes the VID, PID, and DID bytes:0xB4, 0x04, 0x02, 0x10,

0x01, 0x00 (in nibble format per the command protocol).

The default descriptor is listed in Section 12.0. The default

descriptor can be used as a starting point for a custom

descriptor.

Note:

6. These and all other data bytes must conform to the command protocol.

Document #: 38-08013 Rev. *E

Page 8 of 42

FOR

CY7C68001

For an OUT set-up transaction, the external master can read

each packet received from the USB host during the data

phase. The steps to read a packet are as follows:

Bit 6: S, Set Data Toggle to DATA1

After selecting the desired endpoint by writing the endpoint

select bits (IO and EP3:0), set S=1 to set the data toggle to

DATA1. The endpoint selection bits should not be changed

while this bit is written.

1. Wait for an EP0BUF interrupt, indicating that a packet was

received from the USB host into the buffer.

Bit 5: R, Set Data Toggle to DATA0

2. Initiate a read request for the byte count register, 0x33.

This indicates the amount of data received from the host.

Set R=1 to set the data toggle to DATA0. The endpoint

selection bits should not be changed while this bit is written.

3. Initiate a read request for register 0x31.

4. Read one byte.

Bit 4: IO, Select IN or OUT Endpoint

Set this bit to select an endpoint direction prior to setting its R

or S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN

endpoint.

5. Repeat steps 3 and 4 until the number of bytes specified

in the byte count register has been read.

To receive more than 64 bytes, the process is repeated. The

SX2 internally stores the length of the data phase that was

specified in the wLength field of the set-up packet (bytes 6,7).

When the SX2 sees that the specified number of bytes have

been received, it will complete the set-up transfer by automat-

ically completing the handshake phase. If the external master

does not wish to receive the entire transfer, it can stall the

transfer.

Bit 3-0: EP3:0, Select Endpoint

Set these bits to select an endpoint prior to setting its R or S

bit. Valid values are 0, 1, 2, , 6, and 8.

A two-step process is employed to clear an endpoint data

toggle bit to 0. First, write to the TOGCTL register with an

endpoint address (EP3:EP0) plus a direction bit (IO). Keeping

the endpoint and direction bits the same, write a “1” to the R

(reset) bit. For example, to clear the data toggle for EP6

configured as an “IN” endpoint, write the following values

sequentially to TOGCTL:

If the SX2 receives another set-up packet before the current

transfer has completed, it will interrupt the external master with

another SETUP interrupt. If the SX2 receives a set-up packet

with no data phase, the external master can accept the packet

and complete the handshake phase by writing zero to the byte

count register.

00010110b

00110110b

The SX2 automatically responds to all USB standard requests

covered in chapter 9 of the USB 2.0 specification except the

Set/Clear Feature Endpoint requests. When the host issues a

Set Feature or a Clear feature request, the SX2 will trigger a

SETUP interrupt to the external master. The USB spec

requires that the device respond to the Set endpoint feature

request by doing the following:

Following is the sequence of events that the master should

perform to set this register to 0x16:

(1) Send Low Byte of the Register (0x83)

• Command address write of address 0x3A

• Command data write of upper nibble of the Low Byte of

Register Address (0x08)

• Set the STALL condition on that endpoint.

• Command data write of lower nibble of the Low Byte of

Register Address (0x03)

The USB spec requires that the device respond to the Clear

endpoint feature request by doing the following:

(2) Send High Byte of the Register (0xE6)

• Reset the Data Toggle for that endpoint

• Clear the STALL condition of that endpoint.

• Command address write of address 0x3B

• Command data write of upper nibble of the High Byte of

Register Address (0x0E)

The register that is used to reset the data toggle TOGCTL

(located at XDATA location 0xE683) is not an index register

that can be addressed by the command protocol presented in

Section 3.7.8. The following section provides further infor-

mation on this register bits and how to reset the data toggle

accordingly using a different set of command protocol

sequence.

• Command data write of lower nibble of the High Byte of

Register Address (0x06)

(3) Send the actual value to write to the register Register (in

this case 0x16)

• Command address write of address0x3C

• Command data write of upper nibble of the High Byte of

Register Address (0x01)

5.1

Resetting Data Toggle

• Command data write of lower nibble of the High Byte of

Following is the bit definition of the TOGCTL register:

Register Address (0x06)

TOGCTL

0xE683

0

Bit #

7

Q

R

0

6

S

W

0

5

R

W

1

4

I/O

R/W

1

3

2

1

The same command sequence needs to be followed to set

TOGCTL register to 0x36. The same command protocol

sequence can be used to reset the data toggle for the other

endpoints. In order to read the status of this register, the

external master must do the following sequence of events:

Bit Name

Read/Write

Default

EP3

R/W

0

EP2

R/W

0

EP1

R/W

1

EP0

R/W

0

Bit 7: Q, Data Toggle Value

(1) Send Low Byte of the Register (0x83)

Q=0 indicates DATA0 and Q=1 indicates DATA1, for the

endpoint selected by the I/O and EP3:0 bits. Write the endpoint

select bits (IO and EP3:0), before reading this value.

• Command address write of 0x3A

Document #: 38-08013 Rev. *E

Page 9 of 42

FOR

CY7C68001

• Command data write of upper nibble of the Low Byte of

Register Address (0x08)

• Command data write of lower nibble of the Low Byte of

Register Address (0x03)

(2) Send High Byte of the Register (0xE6)

• Command address write of address 0x3B

• Command data write of upper nibble of the High Byte of

Register Address (0x0E)

• Command data write of lower nibble of the High Byte of

Register Address (0x06)

(3) Get the actual value from the TOGCTL register (0x16)

• Command address READ of 0x3C

6.0

6.1

Pin Assignments

56-pin SSOP

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1

FD13

FD14

FD15

GND

NC

VCC

GND

*SLRD

*SLWR

AVCC

XTALOUT

XTALIN

AGND

VCC

DPLUS

DMINUS

GND

FD12

FD11

FD10

FD9

FD8

2

3

4

5

6

*WAKEUP

VCC

RESET#

GND

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

*FLAGD/CS#

*PKTEND

FIFOADR1

FIFOADR0

FIFOADR2

*SLOE

INT#

READY

VCC

*FLAGC

*FLAGB

*FLAGA

GND

VCC

GND

*IFCLK

RESERVED

SCL

SDA

VCC

FD0

FD1

FD2

FD3

CY7C68001

56-pin SSOP

VCC

GND

FD7

FD6

FD5

FD4

[7]

Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment

Note:

7. A * denotes programmable polarity.

Document #: 38-08013 Rev. *E

Page 10 of 42

FOR

CY7C68001

6.2

56-pin QFN

*SLRD

*SLW R

AVCC

1

42 RESET#

2

3

4

5

6

7

8

9

41 GND

40 *FLAGD/CS#

39 *PKTEND

38 FIFOADR1

37 FIFOADR0

36 FIFOADR2

35 *SLOE

XTALOUT

XTALIN

AGND

VCC

CY7C68001

56-pin QFN

DPLUS

DMINUS

34 INT#

GND 10

VCC 11

33 READY

32 VCC

GND 12

31 *FLAGC

30 *FLAGB

29 *FLAGA

*IFCLK 13

RESERVED 14

[7]

Figure 6-2. CY7C68001 56-pin QFN Assignment

Document #: 38-08013 Rev. *E

Page 11 of 42

FOR

CY7C68001

6.3

CY7C68001 Pin Definitions

Table 6-1. SX2 Pin Definitions

QFN SSOP

10

13

16

15

49

Name

AVCC

Type

Power

I/O/Z

Default

Description

3

N/A Analog V . This signal provides power to the analog section of the chip.

CC

6

AGND

N/A Analog Ground. Connect to ground with as short a path as possible.

9

DMINUS

DPLUS

RESET#

Z

USB D– Signal. Connect to the USB D– signal.

USB D+ Signal. Connect to the USB D+ signal.

8

I/O/Z

42

Input

N/A Active LOW Reset. Resets the entire chip. This pin is normally tied to V

through a 100K resistor, and to GND through a 0.1-µF capacitor.

CC

5

4

12

11

XTALIN

Input

N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental

mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with

an external 24-MHz square wave derived from another clock source.

XTALOUT Output

N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental

mode crystal and 20-pF capacitor to GND. If an external clock is used to drive

XTALIN, leave this pin open.

54

33

5

NC

Output

O

No Connect. This pin must be left unconnected.

40

READY

L

READY is an output-only ready that gates external command reads and writes.

Active High.

34

35

41

42

INT#

Output

Input

H

I

INT# is an output-only external interrupt signal. Active Low.

SLOE

SLOE is an input-only output enable with programmable polarity (POLAR.4) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

36

37

38

39

40

43 FIFOADR2

44 FIFOADR0

45 FIFOADR1

Input

I

FIFOADR2 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

FIFOADR0 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

FIFOADR1 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

46

47

PKTEND

PKTEND is an input-only packet end with programmable polarity (POLAR.5) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

FLAGD/C

S#

CS#:I

FLAGD:O

FLAGD is a programmable slave-FIFO output status flag signal. CS# is a master

chip select (default).

18

19

20

21

22

23

24

25

45

46

47

48

49

50

51

52

25

26

27

28

29

30

31

32

52

53

54

55

56

1

FD[0]

FD[1]

FD[2]

FD[3]

FD[4]

FD[5]

FD[6]

FD[7]

FD[8]

FD[9]

FD[10]

FD[11]

FD[12]

FD[13]

FD[14]

FD[15]

I/O/Z

I

FD[0] is the bidirectional FIFO/Command data bus.

FD[1] is the bidirectional FIFO/Command data bus.

FD[2] is the bidirectional FIFO/Command data bus.

FD[3] is the bidirectional FIFO/Command data bus.

FD[4] is the bidirectional FIFO/Command data bus.

FD[5] is the bidirectional FIFO/Command data bus.

FD[6] is the bidirectional FIFO/Command data bus.

FD[7] is the bidirectional FIFO/Command data bus.

FD[8] is the bidirectional FIFO data bus.

FD[9] is the bidirectional FIFO data bus.

FD[10] is the bidirectional FIFO data bus.

FD[11] is the bidirectional FIFO data bus.

FD[12] is the bidirectional FIFO data bus.

FD[13] is the bidirectional FIFO data bus.

2

FD[14] is the bidirectional FIFO data bus.

3

FD[15] is the bidirectional FIFO data bus.

Document #: 38-08013 Rev. *E

Page 12 of 42

FOR

CY7C68001

Table 6-1. SX2 Pin Definitions (continued)

QFN SSOP

Name

Type

Default

Description

1

8

SLRD

SLWR

FLAGA

FLAGB

FLAGC

IFCLK

Input

N/A SLRD is the input-only read strobe with programmable polarity (POLAR.3) for the

slave FIFOs connected to FD[7:0] or FD[15:0].

2

9

N/A SLWR is the input-only write strobe with programmable polarity (POLAR.2) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

29

30

31

13

36

37

38

20

Output

I/O/Z

H

Z

FLAGA is a programmable slave-FIFO output status flag signal.

Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.

FLAGB is a programmable slave-FIFO output status flag signal.

Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.

FLAGC is a programmable slave-FIFO output status flag signal.

Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.

Interface Clock, used for synchronously clocking data into or out of the slave

FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals.

When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be

configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6.

IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity.

14

44

21

51

Reserved

WAKEUP

Input

N/A Reserved. Must be connected to ground.

N/A USB Wakeup. If the SX2 is in suspend, asserting this pin starts up the oscillator

and interrupts the SX2 to allow it to exit the suspend mode. During normal

operation, holding WAKEUP asserted inhibits the SX2 chip from suspending. This

pin has programmable polarity (POLAR.7).

2

15

16

22

23

SCL

SDA

OD

Z

I C Clock. Connect to V with a 2.2K-10 K Ohms resistor, even if no I C

CC

EEPROM is attached.

2

Z

I C Data. Connect to V with a 2.2K-10 K Ohms resistor, even if no I C EEPROM

CC

is attached.

55

7

6

V

Power

Ground

N/A

V

. Connect to 3.3V power source.

CC

14

18

24

34

39

50

4

11

17

27

32

43

53

56

10

12

26

28

41

GND

N/A Connect to ground.

7

17

19

33

35

48

Document #: 38-08013 Rev. *E

Page 13 of 42

FOR

CY7C68001

7.0

Register Summary

Table 7-1. SX2 Register Summary

Hex SizeName

Description

D7

D6

D5

D4

D3

D2

D1

D0

Default

Access

General Configuration

01

02

1

IFCONFIG

FLAGSAB

Interface Configuration

FIFO FLAGA and FLAGB Assign-

ments

FIFO FLAGC and FLAGD Assign-

ments

IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL

ASYNC STANDBY FLAGD/CS# DISCON 11001001 bbbbbbbb

FLAGB3 FLAGB2 FLAGB1

FLAGD3 FLAGD2 FLAGD1

FLAGB0

FLAGD0

FLAGA3

FLAGC3

FLAGA2

FLAGC2

FLAGA1

FLAGC1

FLAGA0 00000000 bbbbbbbb

FLAGC0 00000000 bbbbbbbb

03

1

FLAGSCD

04

05

1

POLAR

REVID

Endpoint Configuration

FIFO polarities

WUPOL

Major

0

PKTEND

Major

SLOE

Major

SLRD

minor

SLWR

minor

EF

minor

FF

minor

00000000 bbbrrrbb

xxxxxxxx rrrrrrrr

Chip Revision

Major

[8]

06

07

08

09

0A

1

EP2CFG

EP4CFG

EP6CFG

EP8CFG

Endpoint 2 Configuration

VALID

INFM1

dir

OEP1

TYPE1

ZEROLEN

TYPE0

WORD-

WIDE

SIZE

STALL

PL10

BUF1

0

BUF1

0

BUF0

0

BUF0

0

10100010 bbbbbbbb

10100000 bbbbrbrr

11100010 bbbbbbbb

11100000 bbbbrbrr

00110010 bbbbbbbb

Endpoint 4 Configuration

Endpoint 6 Configuration

Endpoint 8 Configuration

0

SIZE

0

EP2PKTLENH Endpoint 2 Packet Length H

0

PL9

PL8

0B

0C

1

EP2PKTLENL Endpoint 2 Packet Length L (IN only)

EP4PKTLENH Endpoint 4 Packet Length H

PL7

INFM1

PL6

OEP1

PL5

ZEROLEN

PL4

WORD-

WIDE

PL3

0

PL2

0

PL1

PL9

PL0

PL8

00000000 bbbbbbbb

00110010 bbbbbbbb

0D

0E

1

EP4PKTLENL Endpoint 4 Packet Length L (IN only)

EP6PKTLENH Endpoint 6 Packet Length H

PL7

INFM1

PL6

OEP1

PL5

ZEROLEN

PL4

WORD-

WIDE

PL3

0

PL2

PL10

PL1

PL9

PL0

PL8

00000000 bbbbbbbb

00110010 bbbbbbbb

0F

10

1

EP6PKTLENL Endpoint 6 Packet Length L (IN only)

EP8PKTLENH Endpoint 8 Packet Length H

PL7

INFM1

PL6

OEP1

PL5

ZEROLEN

PL4

WORD-

WIDE

PL3

0

PL2

0

PL1

PL9

PL0

PL8

00000000 bbbbbbbb

00110010 bbbbbbbb

11

12

1

EP8PKTLENL Endpoint 8 Packet Length L (IN only)

PL7

PL6

PL5

PL4

PL3

PL2

0

PL1

PFC9

PL0

PFC8

00000000 bbbbbbbb

10001000 bbbbbbbb

EP2PFH

EP2 Programmable Flag H

DECIS PKTSTAT IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

13

14

1

EP2PFL

EP4PFH

EP2 Programmable Flag L

EP4 Programmable Flag H

PFC7

DECIS PKTSTAT

PFC6

PFC5

0

PFC4

PFC3

PFC2

0

PFC1

0

PFC0

PFC8

00000000 bbbbbbbb

10001000 bbbbbbbb

IN: PKTS[1] IN: PKTS[0]

OUT:PFC10 OUT:PFC9

15

16

1

EP4PFL

EP6PFH

EP4 Programmable Flag L

EP6 Programmable Flag H

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

0

PFC1

PFC9

PFC0

PFC8

00000000 bbbbbbbb

00001000 bbbbbbbb

DECIS PKTSTAT IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

17

18

1

EP6PFL

EP8PFH

EP6 Programmable Flag L

EP8 Programmable Flag H

PFC7

DECIS PKTSTAT

PFC6

PFC5

0

PFC4

PFC3

PFC2

0

PFC1

0

PFC0

PFC8

00000000 bbbbbbbb

00001000 bbbbbbbb

IN: PKTS[1] IN: PKTS[0]

OUT:PFC10 OUT:PFC9

19

1A

1B

1C

1D

1

EP8PFL

EP8 Programmable Flag L

PFC7

PFC6

PFC5

PFC4

PFC3

PFC2

PFC1

PFC0

00000000 bbbbbbbb

EP2ISOINPKTS EP2 (if ISO) IN Packets per frame(1-3)

EP4ISOINPKTS EP4 (if ISO) IN Packets per frame(1-3)

EP6ISOINPKTS EP6 (if ISO) IN Packets per frame(1-3)

EP8ISOINPKTS EP8 (if ISO) IN Packets per frame(1-3)

FLAGS

0

INPPF1

INPPF0 00000001 bbbbbbbb

1E

1F

1

EP24FLAGS

EP68FLAGS

INPKTEND/FLUSH

Endpoints 2,4 FIFO Flags

0

EP4PF

EP8PF

EP4EF

EP8EF

EP4FF

EP8FF

0

EP2PF

EP6PF

EP2EF

EP6EF

EP2FF

EP6FF

00100010

01100110

rrrrrrrr

Endpoints 6,8 FIFO Flags

[9]

20

1

INPK-

TEND/FLUSH

Force Packet End / Flush FIFOs

FIFO8

FIFO6

FIFO4

FIFO2

EP3

EP2

EP1

EP0

00000000 wwwwww-

ww

USB Configuration

2A

2B

2C

2D

1

USBFRAMEH USB Frame count H

USBFRAMEL USB Frame count L

MICROFRAME Microframe count, 0-7

0

FC7

0

FC6

0

FC5

0

FC4

0

FC3

0

FC10

FC2

MF2

FA2

FC9

FC1

MF1

FA1

FC8

FC0

MF0

FA0

xxxxxxxx

00000000

rrrrrrrr

FNADDR

USB Function address

HSGRANT

FA6

FA5

FA4

FA3

Interrupts

INTENABLE

Descriptor

2E

1

Interrupt Enable

SETUP

d7

EP0BUF

d6

FLAGS

d5

1

ENUMOK BUSACTIVITY READY 11111111 bbbbbbbb

30 500 DESC

Descriptor RAM

d4

d3

d2

d1

d0

xxxxxxxx wwwwww-

ww

Endpoint 0

31 64 EP0BUF

32 8/1 SETUP

Endpoint 0 Buffer

Endpoint 0 Set-up Data / Stall

Endpoint 0 Byte Count

d7

d6

d5

d4

d3

d2

d1

d0

xxxxxxxx bbbbbbbb

33

1

EP0BC

Un-Indexed Register control

Un-Indexed Register Low Byte pointer

3A

3B

1

a7

a6

a5

a4

a3

a2

a1

a0

Un-Indexed Register High Byte point-

er

3C

1

Un-Indexed Register Data

d7

d6

d5

d4

d3

d2

d1

d0

Address Un-Indexed Registers in XDATA Space

0xE609 FIFOPINPOLAR FIFO Interface Pins Polarity

0

Q

0

S

PKTEND

R

SLOE

IO

SLRD

EP3

SLWR

EP2

EF

EP1

FF

EP0

00000000 rrbbbbbb

xxxxxxxx rbbbbbbb

0xE683 TOGCTL

Data Toggle Control

Notes:

8. Please note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your applications need the ability to

change endpoint configurations after the device has already enumerated with a specific configuration, please expect some delay in being able to access the

FIFOs after changing the configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 us measured from the time the READY signal

is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic

change of endpoint configuration registers.

9. Please note that the SX2 was not designed to support dynamic modification of the INPKTEND/FLUSH register. If your applications need the ability to change

endpoint configurations or access the INPKTEND register after the device has already enumerated with a specific configuration, please expect some delay in

being able to access the FIFOs after changing this register. After writing to INPKTEND/FLUSH, you must wait for at least 85 us measured from the time the

READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed

for this dynamic change of endpoint configuration registers

Document #: 38-08013 Rev. *E

Page 14 of 42

FOR

CY7C68001

7.1

IFCONFIG Register 0x01

IFCONFIG

Bit #

0x01

0

7

IFCLKSRC

R/W

6

3048MHZ

R/W

5

IFCLKOE

R/W

4

IFCLKPOL

R/W

3

ASYNC

R/W

1

2

STANDBY

R/W

1

Bit Name

Read/Write

Default

FLAGD/CS#

DISCON

R/W

1

R/W

0

1

0

7.1.1

Bit 7: IFCLKSRC

When ASYNC = 1 (default), the FIFOs operate asynchro-

nously. No clock signal input to IFCLK is required, and the

FIFO control signals function directly as read and write

strobes.

This bit selects the clock source for the FIFOs. If IFCLKSRC

= 0, the external clock on the IFCLK pin is selected. If

IFCLKSRC = 1 (default), an internal 30 or 48 MHz clock is

used.

7.1.6

Bit 2: STANDBY

7.1.2

Bit 6: 3048MHZ

This bit instructs the SX2 to enter a low-power mode. When

STANDBY=1, the SX2 will enter a low-power mode by turning

off its oscillator. The external master should write this bit after

it receives a bus activity interrupt (indicating that the host has

signaled a USB suspend condition). If SX2 is disconnected

from the USB bus, the external master can write this bit at any

time to save power. Once suspended, the SX2 is awakened

either by resumption of USB bus activity or by assertion of its

WAKEUP pin.

This bit selects the internal FIFO clock frequency. If 3048MHZ

= 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1

(default), the internal clock frequency is 48 MHz.

7.1.3

Bit 5: IFCLKOE

This bit selects if the IFCLK pin is driven. If IFCLKOE = 0

(default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK

pin is driven.

7.1.7

Bit 1: FLAGD/CS#

7.1.4

Bit 4: IFCLKPOL

This bit controls the function of the FLAGD/CS# pin. When

FLAGD/CS# = 0 (default), the pin operates as a slave chip

select. If FLAGD/CS# = 1, the pin operates as FLAGD.

This bit controls the polarity of the IFCLK signal.

• When IFCLKPOL=0, the clock has the polarity shown in all

the timing diagrams in this data sheet (rising edge is the

activating edge).

7.1.8

Bit 0: DISCON

This bit controls whether the internal pull-up resistor

connected to D+ is pulled high or floating. When DISCON = 1

(default), the pull-up resistor is floating simulating a USB

unplug. When DISCON=0, the pull-up resistor is pulled high

signaling a USB connection.

• When IFCLKPOL=1, the clock is inverted (in some cases

may help with satisfying data set-up times).

7.1.5

Bit 3: ASYNC

This bit controls whether the FIFO interface is synchronous or

asynchronous. When ASYNC = 0, the FIFOs operate synchro-

nously. In synchronous mode, a clock is supplied either inter-

nally or externally on the IFCLK pin, and the FIFO control

signals function as read and write enable signals for the clock

signal.

7.2

FLAGSAB/FLAGSCD Registers 0x02/0x03

The SX2 has four FIFO flags output pins: FLAGA, FLAGB,

FLAGC, FLAGD.

FLAGSAB

0x02

Bit #

7

FLAGB3

R/W

0

6

FLAGB2

R/W

0

5

FLAGB1

R/W

4

FLAGB0

R/W

0

3

FLAGA3

R/W

2

FLAGA2

R/W

0

1

FLAGA1

R/W

0

FLAGA0

R/W

0

Bit Name

Read/Write

Default

0

FLAGSCD

Bit #

0x03

7

FLAGD3

R/W

6

FLAGD2

R/W

5

FLAGD1

R/W

4

FLAGD0

R/W

3

FLAGC3

R/W

2

FLAGC2

R/W

1

FLAGC1

R/W

0

FLAGC0

R/W

Bit Name

Read/Write

Default

0

Document #: 38-08013 Rev. *E

Page 15 of 42

FOR

CY7C68001

These flags can be programmed to represent various FIFO

flags using four select bits for each FIFO. The 4-bit coding for

7.3.1

Bit 7: WUPOL

This flag sets the polarity of the WAKEUP pin. If WUPOL = 0

(default), the polarity is active LOW. If WUPOL=1, the polarity

is active HIGH.

all four flags is the same, as shown in the following table

.

Table 7-2. FIFO Flag 4-bit Coding

FLAGx3 FLAGx2 FLAGx1 FLAGx0 Pin Function

7.3.2

Bit 5: PKTEND

0

FLAGA = PF,

FLAGB = FF,

FLAGC = EF,

FLAGD = CS#

(actual FIFO is

selected by

FIFOADR[2:0]

pins)

This flag selects the polarity of the PKTEND pin. If PKTEND =

0 (default), the polarity is active LOW. If PKTEND = 1, the

polarity is active HIGH.

7.3.3

Bit 4: SLOE

This flag selects the polarity of the SLOE pin. If SLOE = 0

(default), the polarity is active LOW. If SLOE = 1, the polarity

is active HIGH. This bit can only be changed by using the

EEPROM configuration load.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

EP2 PF

EP4 PF

EP6 PF

EP8 PF

EP2 EF

EP4 EF

EP6 EF

EP8 EF

EP2 FF

EP4 FF

EP6 FF

EP8 FF

7.3.4

Bit 3: SLRD

This flag selects the polarity of the SLRD pin. If SLRD = 0

(default), the polarity is active LOW. If SLRD = 1, the polarity

is active HIGH. This bit can only be changed by using the

EEPROM configuration load.

7.3.5

SLWR Bit 2

This flag selects the polarity of the SLWR pin. If SLWR = 0

(default), the polarity is active LOW. If SLWR = 1, the polarity

is active HIGH. This bit can only be changed by using the

EEPROM configuration load.

7.3.6

EF Bit 1

This flag selects the polarity of the EF pin (FLAGA/B/C/D). If

EF = 0 (default), the EF pin is pulled low when the FIFO is

empty. If EF = 1, the EF pin is pulled HIGH when the FIFO is

empty.

For the default (0000) selection, the four FIFO flags are fixed-

function as shown in the first table entry; the input pins

FIFOADR[2:0] select to which of the four FIFOs the flags

correspond. These pins are decoded as shown in Table 3-3.

7.3.7

FF Bit 0

This flag selects the polarity of the FF pin (FLAGA/B/C/D). If

FF = 0 (default), the FF pin is pulled low when the FIFO is full.

If FF = 1, the FF pin is pulled HIGH when the FIFO is full.

The other (non-zero) values of FLAGx[3:0] allow the designer

to independently configure the four flag outputs FLAGA-

FLAGD to correspond to any flag-Programmable, Full, or

Empty-from any of the four endpoint FIFOs. This allows each

flag to be assigned to any of the four FIFOs, including those

not currently selected by the FIFOADR [2:0] pins. For

example, the external master could be filling the EP2IN FIFO

with data while also checking the empty flag for the EP4OUT

FIFO.

Note that bits 2(SLWR), 3(SLRD) and 4 (SLOE) are READ

only bits and cannot be set by the external master or the

EEPROM. On power-up, these bits are set to active low

polarity. In order to change the polarity after the device is

powered-up, the external master must access the previously

undocumented (un-indexed) SX2 register located at XDATA

space at 0xE609. This register has exact same bit definition

as the POLAR register except that bits 2, 3 and 4 defined as

SLWR, SLRD and SLOE respectively are Read/Write bits.

Following is the sequence of events that the master should

perform for setting this register to 0x1C (setting bits 4,3,and 2):

7.3

POLAR Register 0x04

This register controls the polarities of FIFO pin signals and the

WAKEUP pin.

1) Send Low Byte of the Register (0x09)

• Command address write of address 0x3A

POLAR

Bit #

0x04

0

7

6

0

5

4

3

2

1

• Command data write of upper nibble of the Low Byte of

Register Address (0x00)

Bit

Name

WUPOL

PKTEND SLOE SLRD SLWR

EF

FF

• Command data write of lower nibble of the Low Byte of

Register Address (0x09)

Read/W

rite

R/W

0

R/W

0

R/W

0

R

0

R

0

R

0

R/W R/W

Default

0

Document #: 38-08013 Rev. *E

Page 16 of 42

FOR

CY7C68001

.

(2) Send High Byte of the Register (0xE6)

• Command address write of address 0x3B

EPxCFG

Bit #

0x07, 0x09

7

6

5

4

3

2

1

0

• Command data write of upper nibble of the High Byte of

Register Address (0x0E)

Bit

Name

VALID

DIR TYPE1 TYPE0 SIZE STALL BUF1 BUF0

• Command data write of lower nibble of the High Byte of

Register Address (0x06)

Read/W R/W

R/W

0

R/W

1

R/W

0

R

0

R/W

0

R

1

R

0

rite

Default

1

(3) Send the actual value to write to the register Register (in

this case 0x1C)

7.5.1

Bit 7: VALID

• Command address write of address 0x3C

The external master sets VALID = 1 to activate an endpoint,

and VALID = 0 to deactivate it. All SX2 endpoints default to

valid. An endpoint whose VALID bit is 0 does not respond to

any USB traffic.

• Command data write of upper nibble of the High Byte of

Register Address (0x01)

• Command data write of lower nibble of the High Byte of

Register Address (0x0C)

7.5.2

Bit 6: DIR

In order to avoid altering any other bits of the FIFOPINPOLAR

register (0xE609) inadvertently, the external master must do a

read (from POLAR register), modify the value to set/clear

appropriate bits and write the modified value to FIFOPIN-

POLAR register. The external master may read from the

POLAR register using the command read protocol as stated in

Section 3.7.8. Modify the value with the appropriate bit set to

change the polarity as needed and write this modified value to

the FIFOPINPOLAR register.

0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for

EP6/8 are DIR = 1, IN.

7.5.3

Bit [5,4]: TYPE1, TYPE0

These bits define the endpoint type, as shown in Table 7-3.

The TYPE bits apply to all of the endpoint configuration

registers. All SX2 endpoints except EP0 default to BULK.

Table 7-3. Endpoint Type

TYPE1

TYPE0

Endpoint Type

Invalid

7.4

REVID Register 0x05

0

1

0

1

0

1

These register bits define the silicon revision.

Isochronous

Bulk (Default)

Interrupt

REVID

0x05

0

Bit #

7

6

5

4

3

2

1

Bit

Name

Major Major Major Major Minor Minor Minor Minor

7.5.4

Bit 3: SIZE

Read/

Write

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

R/W

X

0 = 512 bytes (default), 1 = 1024 bytes.

Default

Endpoints 4 and 8 can only be 512 bytes and is a read only

bit. The size of endpoints 2 and 6 is selectable.

The upper nibble is the major revision. The lower nibble is the

minor revision. For example: if REVID = 0x11, then the silicon

revision is 1.1.

7.5.5

Bit 2: STALL

Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the

external master sets this bit, any requests to the endpoint

return a STALL handshake rather than ACK or NAK. The Get

Status-Endpoint Request returns the STALL state for the

endpoint indicated in byte 4 of the request. Note that bit 7 of

the endpoint number EP (byte 4) specifies direction.

7.5

EPxCFG Register 0x06–0x09

These registers configure the large, data-handling SX2

endpoints, EP2, 4, 6, and 8. Figure 3-1 shows the configu-

ration choices for these endpoints. Shaded blocks group

endpoint buffers for double-, triple-, or quad-buffering. The

endpoint direction is set independently—any shaded block

can have any direction.

7.5.6

Bit [1,0]: BUF1, BUF0

For EP2 and EP6 the depth of endpoint buffering is selected

via BUF1:0, as shown in Table 7-4. For EP4 and EP8 the

buffer is internally set to double buffered and are read only bits.

EPxCFG

Bit #

0x06, 0x08

1 0

7

6

5

4

3

2

Table 7-4. Endpoint Buffering

Bit

Name

VALID

DIR TYPE1 TYPE0 SIZE STALL BUF1 BUF0

BUF1

BUF0

Buffering

Read/

Write

R/W

1

R/W

0

R/W

1

R/W

0

R/W

0

R/W

0

R/W

1

R/W

0

1

0

1

0

1

Quad

[10]

Invalid

Default

Double

Triple

Notes:

10. Setting the endpoint buffering to invalid causes improper buffer allocation

Document #: 38-08013 Rev. *E

Page 17 of 42

FOR

CY7C68001

7.6.4

Bit 4: WORDWIDE EPxPKTLENH.4

7.6

EPxPKTLENH/L Registers 0x0A–0x11

This bit controls whether the data interface is 8 or 16 bits wide.

If WORDWIDE = 0, the data interface is eight bits wide, and

FD[15:8] have no function. If WORDWIDE = 1 (default), the

data interface is 16 bits wide.

The external master can use these registers to set smaller

packet sizes than the physical buffer size (refer to the previ-

ously described EPxCFG registers). The default packet size is

512 bytes for all endpoints. Note that EP2 and EP6 can have

maximum sizes of 1024 bytes, and EP4 and EP8 can have

maximum sizes of 512 bytes, to be consistent with the

endpoint structure.

7.6.5

Bit [2..0]: PL[X:0] Packet Length Bits

The default packet size is 512 bytes for all endpoints.

In addition, the EPxPKTLENH register has four other endpoint

configuration bits.

7.7

EPxPFH/L Registers 0x12–0x19

The Programmable Flag registers control when the PF goes

active for each of the four endpoint FIFOs: EP2, EP4, EP6,

and EP8. The EPxPFH/L fields are interpreted differently for

the high speed operation and full speed operation and for OUT

and IN endpoints.

EPxPKTLENL

0x0B, 0x0D,

0x0F, 0x11

Bit #

7

PL7

R/W

0

6

5

4

3

2

1

PL1

R/W

0

Bit Name

Read/Write

Default

PL6

R/W

0

PL5

R/W

0

PL4

R/W

0

PL3

R/W

0

PL2

R/W

0

PL0

R/W

0

Following is the register bit definition for high speed operation

and for full speed operation (when endpoint is configured as

an isochronous endpoint).

EP2PKTLENH,

EP6PKTLENH

0x0A, 0x0E

Full Speed ISO and High Speed Mode: EP2PFL,

EP4PFL, EP6PFL, EP8PFL

0x13, 0x15,

0x17, 0x19

Bit #

7

6

5

4

3

0

2

1

0

Bit #

7

6

5

4

3

2

1

0

Bit Name

INFM1 OEP1 ZERO WORD

LEN WIDE

PL10

PL9

PL8

Bit Name

PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0

Read/Write

Default

R/W

0

R/W

0

R/W

1

R/W

1

R/W

0

R/W

0

R/W

1

R/W

0

Read/Write R/W

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

EP4PKTLENH,

EP8PKTLENH

0x0C, 0x10

Full Speed ISO and High Speed Mode:

EP4PFH, EP8PFH

0x14, 0x18

Bit #

7

6

5

4

3

0

2

0

1

0

Bit #

7

6

5

0

4

3

2

0

1

0

Bit Name

INFM1 OEP1 ZERO WORD

LEN WIDE

PL9

PL8

Bit Name

DECIS PKTSTAT

IN:

PKTS[1] PKTS[0]

OUT: OUT:

PFC10 PFC9

IN:

PFC8

Read/Write

Default

R/W

0

R/W

0

R/W

1

R/W

1

R/W

0

R/W

0

R/W

1

R/W

0

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

1

R/W R/W R/W

7.6.1

Bit 7: INFM1 EPxPKTLENH.7

0

When the external master sets INFM = 1 in an endpoint config-

uration register, the FIFO flags for that endpoint become valid

one sample earlier than when the full condition occurs. These

bits take effect only when the FIFOs are operating synchro-

nously according to an internally or externally supplied clock.

Having the FIFO flag indications one sample early simplifies

some synchronous interfaces. This applies only to IN

endpoints. Default is INFM1 = 0.

Full Speed ISO and High Speed Mode:

EP2PFH, EP6PFH

0x12, 0x16

Bit #

7

6

5

4

3

2

1

0

Bit Name

DECIS PKTSTAT

IN:

0

PFC9 PFC8

PKTS[2] PKTS[1] PKTS[0]

OUT:

PFC12 PFC11 PFC10

Read/Write

Default

R/W

1

R/W

0

R/W

0

R/W

0

R/W R/W R/W R/W

1

0

7.6.2

Bit 6: OEP1 EPxPKTLENH.6

When the external master sets an OEP = 1 in an endpoint

configuration register, the FIFO flags for that endpoint become

valid one sample earlier than when the empty condition

occurs. These bits take effect only when the FIFOs are

operating synchronously according to an internally or exter-

nally supplied clock. Having the FIFO flag indications one

sample early simplifies some synchronous interfaces. This

applies only to OUT endpoints. Default is OEP1 = 0.

Following is the bit definition for the same register when the

device is operating at full speed and the endpoint is not

configured as isochronous endpoint.

Full Speed Non-ISO Mode: EP2PFL,

EP4PFL, EP6PFL, EP8PFL

0x13, 0x15,

0x17, 0x19

Bit #

7

6

5

4

3

2

1

0

Bit Name

IN:

PFC5 PFC4 PFC3 PFC2 PFC1 PFC0

PKTS[1] PKTS[0]

OUT:

PFC7 PFC6

OUT:

7.6.3

Bit 5: ZEROLEN EPxPKTLENH.5

When ZEROLEN = 1 (default), a zero length packet will be

sent when the PKTEND pin is asserted and there are no bytes

in the current packet. If ZEROLEN = 0, then a zero length

packet will not be sent under these conditions.

Read/Write

Default

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Document #: 38-08013 Rev. *E

Page 18 of 42

FOR

CY7C68001

Table 7-5. PKTS Bits (continued)

Full Speed Non-ISO Mode:

EP2PFH, EP6PFH

0x12, 0x16

1 0

PKTS2

PKTS1

PKTS0

Number of Packets

Bit #

7

6

5

4

3

2

0

1

0

4

Bit Name

DECIS PKTSTAT OUT: OUT: OUT:

PFC12 PFC11 PFC10

PFC9

IN:

PKTS[2]

OUT:

When PKTSTAT = 1, the PF considers when there are PFC

bytes in the FIFO, no matter how many packets are in the

FIFO. The PKTS[2:0] bits are ignored.

PFC8

Read/Write R/W

Default

R/W

0

R/W

0

R/W

0

R/W R/W R/W

R/W

0

1

0

7.7.3.2 OUT Endpoints

The PF considers when there are PFC bytes in the FIFO

regardless of the PKTSTAT bit setting.

Full Speed Non-ISO Mode:

EP4PFH, EP8PFH

0x14, 0x18

Bit #

7

6

5

0

4

3

2

0

1

0

7.8

EPxISOINPKTS Registers 0x1A–0x1D

Bit Name

DECIS

PKT-

STAT

OUT: OUT:

PFC10 PFC9

0

PFC8

EP2ISOINOKTS, EP4ISOINPKTS,

EP6ISOINPKTS, EP8ISOINPKTS

0x1A, 0x1B,

0x1C, 0x1D

Read/Write R/W

R/W

0

R/W

0

R/W

0

R/W R/W R/W R/W

Default

0

1

0

Bit #

7

0

6

0

5

0

4

0

3

0

2

1

0

Bit Name

INPPF2 INPPF1 INPPF0

7.7.1

DECIS: EPxPFH.7

Read/Write R/W R/W R/W R/W R/W

Default

R/W

0

R/W

0

R/W

1

If DECIS = 0, then PF goes high when the byte count i is equal

to or less than what is defined in the PF registers. If DECIS =

1 (default), then PF goes high when the byte count equal to or

greater than what is set in the PF register. For OUT endpoints,

the byte count is the total number of bytes in the FIFO that are

available to the external master. For IN endpoints, the byte

count is determined by the PKSTAT bit.

0

For ISOCHRONOUS IN endpoints only, these registers

determine the number of packets per frame (only one per

frame for full-speed mode) or microframe (up to three per

microframe for high-speed mode), according to the following

table.

Table 7-6. EPxISOINPKTS

7.7.2

PKSTAT: EPxPFH.6

For IN endpoints, the PF can apply to either the entire FIFO,

comprising multiple packets, or only to the current packet

being filled. If PKTSTAT = 0 (default), the PF refers to the entire

IN endpoint FIFO. If PKTSTAT = 1, the PF refers to the number

of bytes in the current packet.

INPPF1

INPPF0

Packets

0

1

0

1

0

1

Invalid

1 (default)

2

3

EPnPFH:L

PKTSTAT

PF applies to

format

7.9

EPxxFLAGS Registers 0x1E–0x1F

0

Number of committed

packets + current packet

bytes

PKTS[] and PFC[]

The EPxxFLAGS provide an alternate way of checking the

status of the endpoint FIFO flags. If enabled, the SX2 can

interrupt the external master when a flag is asserted, and the

external master can read these two registers to determine the

state of the FIFO flags. If the INFM1 and/or OEP1 bits are set,

then the EPxEF and EPxFF bits are actually empty +1 and full

–1.

1

Current packet bytes only

PFC[ ]

7.7.3

IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3]

These three bits have a different meaning, depending on

whether this is an IN or OUT endpoint.

EP24FLAGS

Bit #

0x1E

0

7.7.3.1 IN Endpoints

7

0

6

5

4

3

0

2

1

If IN endpoint, the meaning of this EPxPFH[5:3] bits depend

on the PKTSTAT bit setting. When PKTSTAT = 0 (default), the

PF considers when there are PKTS packets plus PFC bytes in

the FIFO. PKTS[2:0] determines how many packets are

considered, according to the following table.

Bit Name

Read/Write

Default

EP4PF EP4EF EP4FF

EP2PF EP4EF EP4FF

R/W

0

R/W

0

R/W

1

R/W R/W R/W

R/W

1

R/W

0

EP68FLAGS

Bit #

0x1F

0

Table 7-5. PKTS Bits

7

0

6

5

4

3

0

2

1

PKTS2

PKTS1

PKTS0

Number of Packets

Bit Name

Read/Write

Default

EP8PF EP8EF EP8FF

EP6PF EP6EF EP6FF

R/W

0

R/W

0

R/W

1

R/W R/W R/W

R/W

1

R/W

0

1

0

1

0

1

0

1

2

3

0

7.9.1

EPxPF Bit 6, Bit 2

This bit is the current state of endpoint x’s programmable flag.

Document #: 38-08013 Rev. *E

Page 19 of 42

FOR

CY7C68001

7.9.2

EPxEF Bit 5, Bit 1

7.12

MICROFRAME Registers 0x2C

This bit is the current state of endpoint x’s empty flag. EPxEF

= 1 if the endpoint is empty.

MICROFRAME

Bit #

0x2C

7

0

6

0

5

0

4

0

3

0

2

MF2

R

1

MF1

R

0

MF0

R

Bit Name

Read/Write

Default

7.9.3

EPxFF Bit 4, Bit 0

R

X

R

X

R

X

R

X

R

X

This bit is the current state of endpoint x’s full flag. EPxFF = 1

if the endpoint is full.

X

x

MICROFRAME contains a count 0–7 that indicates which of

the 125 microsecond microframes last occurred.

7.10

INPKTEND/FLUSH Register 0x20

This register allows the external master to duplicate the

function of the PKTEND pin. The register also allows the

external master to selectively flush endpoint FIFO buffers.

This register is active only when SX2 is operating in high-

speed mode (480 Mbits/sec).

7.13

FNADDR Register 0x2D

INPKTEND/FLUSH

0x20

0

During the USB enumeration process, the host sends a device

a unique 7-bit address that the SX2 copies into this register.

There is normally no reason for the external master to know

its USB device address because the SX2 automatically

responds only to its assigned address.

Bit #

7

6

5

4

3

2

EP2

W

1

EP1

W

Bit Name

Read/Write

Default

FIFO8 FIFO6 FIFO4 FIFO2 EP3

EP0

W

0

W

0

W

0

W

0

W

0

FNADDR

Bit #

0x2D

0

Bit [4..7]: FIFOx

7

6

5

4

FA4

R

3

FA3

R

2

FA2

R

1

FA1

R

These bits allows the external master to selectively flush any

or all of the endpoint FIFOs. By writing the desired endpoint

FIFO bit, SX2 logic flushes the selected FIFO. For example

setting bit 7 flushes endpoint 8 FIFO.

Bit Name

Read/Write

Default

HSGRANT FA6 FA5

FA0

R

0

R

0

R

0

Bit [3..0]: EPx

Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high

speed. Set to 0 if the SX2 enumerated at full speed.

These bits are is used only for IN transfers. By writing the

desired endpoint number (2,4,6 or 8), SX2 logic automatically

commits an IN buffer to the USB host. For example, for

committing a packet through endpoint 6, set the lower nibble

to 6: set bits 1 and 2 high.

Bit[6..0]: Address set by the host.

7.14

INTENABLE Register 0x2E

This register is used to enable/disable the various interrupt

sources, and by default all interrupts are enabled.

7.11

USBFRAMEH/L Registers 0x2A, 0x2B

Every millisecond, the USB host sends an SOF token

indicating “Start Of Frame,” along with an 11-bit incrementing

frame count. The SX2 copies the frame count into these

registers at every SOF.

INTENABLE

Bit #

0x2E

0

7

6

5

4

1

3

1

2

1

Bit Name

SETUP EP0 FLAGS

BUF

ENUM

OK ACTIVITY

BUS

READY

USBFRAMEH

Bit #

0x2A

Read/Write

Default

R/W

1

R/W R/W R/W R/W R/W

R/W

1

R/W

1

7

0

6

0

5

0

4

0

3

0

2

1

0

FC8

R

1

Bit Name

Read/Write

Default

FC10 FC9

7.14.1 SETUP Bit 7

R

X

R

X

R

X

R

X

R

X

R

X

R

X

Setting this bit to a 1 enables an interrupt when a set-up packet

is received from the USB host.

x

USBFRAMEL

Bit #

0x2B

0

7.14.2 EP0BUF Bit 6

7

FC7

R

6

FC6

R

5

FC5

R

4

FC4

R

3

FC3

R

2

FC2

R

1

FC1

R

Setting this bit to a 1 enables an interrupt when the Endpoint

0 buffer becomes available.

Bit Name

Read/Write

Default

FC0

R

7.14.3 FLAGS Bit 5

X

Setting this bit to a 1 enables an interrupt when an OUT

endpoint FIFO’s state transitions from empty to not-empty.

One use of the frame count is to respond to the USB

SYNC_FRAME Request. If the SX2 detects a missing or

garbled SOF, the SX2 generates an internal SOF and incre-

ments USBFRAMEL–USBRAMEH.

7.14.4 ENUMOK Bit 2

Setting this bit to a 1 enables an interrupt when SX2 enumer-

ation is complete.

7.14.5 BUSACTIVITY Bit 1

Setting this bit to a 1 enables an interrupt when the SX2

detects an absence or presence of bus activity.

Document #: 38-08013 Rev. *E

Page 20 of 42

FOR

CY7C68001

7.14.6 READY Bit 0

to complete Endpoint 0 data transfers. For complete details,

refer to Section 5.0.

Setting this bit to a 1 enables an interrupt when the SX2 has

powered on and performed an internal self-test.

7.17

SETUP Register 0x32

7.15

DESC Register 0x30

This register address is used to access the 8-byte set-up

packet received from the USB host. If the external master

writes to this register, it can stall Endpoint 0. For complete

details, refer to Section 5.0.

This register address is used to write the 500-byte descriptor

RAM. The external master writes two bytes (four command

data transfers) to this address corresponding to the length of

the descriptor or VID/PID/DID data to be written. The external

master then consecutively writes that number of bytes into the

descriptor RAM in nibble format. For complete details, refer to

Section 4.0.

7.18

EP0BC Register 0x33

This register address is used to access the byte count of

Endpoint 0. For Endpoint 0 OUT transfers, the external master

can read this register to get the number of bytes transferred

from the USB host. For Endpoint 0 IN transfers, the external

master writes the number of bytes in the Endpoint 0 buffer to

transfer the bytes to the USB host. For complete details, refer

to Section 5.0.

7.16

EP0BUF Register 0x31

This register address is used to access the 64-byte Endpoint

0 buffer. The external master can read or write to this register

Document #: 38-08013 Rev. *E

Page 21 of 42

FOR

CY7C68001

8.0

Absolute Maximum Ratings

Storage Temperature ...........................................................................................................................................–65°C to +150°C

Ambient Temperature with Power Supplied................................................................................................................0°C to +70°C

Supply Voltage to Ground Potential.........................................................................................................................–0.5V to +4.0V

DC Input Voltage to Any Pin ................................................................................................................................................. 5.25V

DC Voltage Applied to

Outputs in High-Z State ................................................................................................................................. –0.5V to V + 0.5V

CC

Power Dissipation ............................................................................................................................................................. 936 mW

Static Discharge Voltage................................................................................................................................................... > 2000V

9.0

Operating Conditions

T (Ambient Temperature Under Bias) .......................................................................................................................0°C to +70°C

A

Supply Voltage.........................................................................................................................................................+3.0V to +3.6V

Ground Voltage........................................................................................................................................................................... 0V

F

(Oscillator or Crystal Frequency) .............................................................................................................................. 24 MHz

± 100-ppm Parallel Resonant

OSC

10.0

DC Electrical Characteristics

Table 10-1. DC Characteristics

Parameter Description

[11]

Conditions

Min.

3.0

2

Typ.

Max.

3.6

Unit

V

Supply Voltage

3.3

CC

IH

V

Input High Voltage

Input Low Voltage

Input Leakage Current

Output Voltage High

Output Voltage Low

Output Current High

Output Current Low

Input Pin Capacitance

5.25

0.8

V

–0.5

V

IL

I

0< V < V

CC

±10

µA

V

I

IN

V

I

= 4 mA

2.4

OH

OL

OUT

= –4 mA

0.4

4

V

I

mA

pF

µA

mA

mS

OH

OL

4

C

Except D+/D-

D+/D-

10

IN

15

I

Suspend Current

Supply Current

includes 1.5k integrated pull-up

excluding 1.5k integrated pull-up

Connected to USB at high speed

Connected to USB at full speed

Vcc min = 3.0V

250

30

400

180

260

150

SUSP

CC

I

200

90

T

RESET Time after valid power

1.91

RESET

Note:

11. Specific conditions for I_CCmeasurements: HS typical 3.3V, 25°C, 48 MHz; FS typical 3.3V, 25°C, 48 MHz.

Document #: 38-08013 Rev. *E

Page 22 of 42

FOR

CY7C68001

11.0

11.1

AC Electrical Characteristics

USB Transceiver

USB 2.0-certified compliant in full and high speed.

11.2 Command Interface

11.2.1 Command Synchronous Read

t_IFCLK

IFCLK

SLRD

t_RDH

t_SRD

t_INT

INT#

DATA

N

t_OEon

t_OEoff

SLOE

[12]

Figure 11-1. Command Synchronous Read Timing Diagram

Table 11-1. Command Synchronous Read Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

18.7

0

Max.

Unit

ns

t

IFCLK period

IFCLK

SLRD to Clock Set-up Time

ns

SRD

RDH

OEon

OEoff

INT

Clock to SLRD Hold Time

ns

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to INT# Output Propagation Delay

10.5

9.5

ns

[13]

Table 11-2. Command Synchronous Read with Externally Sourced IFCLK

Parameter Description

Min.

20

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

SLRD to Clock Set-up Time

12.7

3.7

ns

SRD

RDH

OEon

OEoff

INT

Clock to SLRD Hold Time

ns

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to INT# Output Propagation Delay

10.5

13.5

ns

Notes:

12. Dashed lines denote signals with programmable polarity.

13. Externally sourced IFCLK must not exceed 50 MHz.

Document #: 38-08013 Rev. *E

Page 23 of 42

FOR

CY7C68001

11.2.2 Command Synchronous Write

t_IFCLK

IFCLK

SLWR

t_SWR

t_WRH

t_SFD

t_FDH

N

DATA

t_NRDY

READY

[12]

Figure 11-2. Command Synchronous Write Timing Diagram

Table 11-3. Command Synchronous Write Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

18.1

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

SLWR to Clock Set-up Time

ns

SWR

WRH

SFD

Clock to SLWR Hold Time

ns

Command Data to Clock Set-up Time

Clock to Command Data Hold Time

Clock to READY Output Propagation Time

9.2

0

ns

FDH

9.5

ns

NRDY

[13]

Table 11-4. Command Synchronous Write Parameters with Externally Sourced IFCLK

Parameter

Description

Min.

20

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

SLWR to Clock Set-up Time

12.1

3.6

3.2

4.5

ns

SWR

WRH

SFD

Clock to SLWR Hold Time

ns

Command Data to Clock Set-up Time

Clock to Command Data Hold Time

Clock to READY Output Propagation Time

ns

FDH

13.5

ns

NRDY

Document #: 38-08013 Rev. *E

Page 24 of 42

FOR

CY7C68001

11.2.3 Command Asynchronous Read

t_RDpwh

SLRD

t_RDpwl

t_XINT

t_IRD

INT#

DATA

N

t_OEon

t_OEoff

SLOE

[12]

Figure 11-3. Command Asynchronous Read Timing Diagram

Table 11-5. Command Read Parameters

Parameter

Description

SLRD Pulse Width LOW

Min.

50

0

Max.

Unit

ns

t

RDpwl

SLRD Pulse Width HIGH

INTERRUPT to SLRD

ns

RDpwh

IRD

ns

SLRD to INTERRUPT

70

ns

XINT

OEon

OEoff

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

10.5

ns

11.2.4 Command Asynchronous Write

t_WRpwh

t_WRpwl

SLWR

t_FDH

t_SFD

DATA

t_RDYWR

t_RDY

READY

t_NRDY

[12]

Figure 11-4. Command Asynchronous Write Timing Diagram

Table 11-6. Command Write Parameters

Parameter

Description

Min.

50

70

10

0

Max.

Unit

ns

t

SLWR Pulse LOW

SLWR Pulse HIGH

WRpwl

ns

WRpwh

SFD

SLWR to Command DATA Set-up Time

Command DATA to SLWR Hold Time

READY to SLWR Time

ns

FDH

ns

RDYWR

RDY

SLWR to READY

70

ns

Document #: 38-08013 Rev. *E

Page 25 of 42

FOR

CY7C68001

11.3

FIFO Interface

11.3.1 Slave FIFO Synchronous Read

t_IFCLK

IFCLK

SLRD

t_RDH

t_SRD

t_XFLG

FLAGS

DATA

N+1

t_XFD

N

t_OEon

t_OEoff

SLOE

[12]

Figure 11-5. Slave FIFO Synchronous Read Timing Diagram

[13]

Table 11-7. Slave FIFO Synchronous Read with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

18.7

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

SLRD to Clock Set-up Time

ns

SRD

Clock to SLRD Hold Time

ns

RDH

OEon

OEoff

XFLG

XFD

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to FLAGS Output Propagation Delay

Clock to FIFO Data Output Propagation Delay

10.5

9.5

ns

11

ns

[13]

Table 11-8. Slave FIFO Synchronous Read with Externally Sourced IFCLK

Parameter Description

Min.

20

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

SLRD to Clock Set-up Time

12.7

3.7

ns

SRD

RDH

OEon

OEoff

XFLG

XFD

Clock to SLRD Hold Time

ns

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to FLAGS Output Propagation Delay

Clock to FIFO Data Output Propagation Delay

10.5

13.5

15

ns

Document #: 38-08013 Rev. *E

Page 26 of 42

FOR

CY7C68001

11.3.2 Slave FIFO Synchronous Write

t_IFCLK

IFCLK

SLWR

t_WRH

t_SWR

DATA

N

t_SFDt_FDH

FLAGS

t_XFLG

[12]

Figure 11-6. Slave FIFO Synchronous Write Timing Diagram

[13]

Table 11-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

20.83

18.1

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

SLWR to Clock Set-up Time

ns

SWR

WRH

SFD

Clock to SLWR Hold Time

ns

FIFO Data to Clock Set-up Time

Clock to FIFO Data Hold Time

Clock to FLAGS Output Propagation Time

9.2

0

ns

FDH

9.5

ns

XFLG

[13]

Table 11-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK

Parameter

Description

Min.

20

Max.

Unit

ns

t

IFCLK Period

IFCLK

SLWR to Clock Set-up Time

12.1

3.6

3.2

4.5

ns

SWR

WRH

SFD

Clock to SLWR Hold Time

ns

FIFO Data to Clock Set-up Time

Clock to FIFO Data Hold Time

Clock to FLAGS Output Propagation Time

ns

FDH

13.5

ns

XFLG

Document #: 38-08013 Rev. *E

Page 27 of 42

FOR

CY7C68001

11.3.3 Slave FIFO Synchronous Packet End Strobe

IFCLK

t_PEH

PKTEND

FLAGS

t_SPE

t_XFLG

[12]

Figure 11-7. Slave FIFO Synchronous Packet End Strobe Timing Diagram

[13]

Table 11-11. Slave FIFO Synchronous Packet End Strobe Parameters, Internally Sourced IFCLK

Parameter

Description

Min.

20.83

14.6

0

Max.

Unit

ns

t

IFCLK Period

IFCLK

PKTEND to Clock Set-up Time

ns

SPE

Clock to PKTEND Hold Time

ns

PEH

XFLG

Clock to FLAGS Output Propagation Delay

9.5

ns

[13]

Table 11-12. Slave FIFO Synchronous Packet End Strobe Parameters, Externally Sourced IFCLK

Parameter

Description

Min.

20

Max.

Unit

ns

t

IFCLK Period

200

IFCLK

PKTEND to Clock Set-up Time

8.6

2.5

ns

SPE

Clock to PKTEND Hold Time

ns

PEH

XFLG

Clock to FLAGS Output Propagation Delay

13.5

ns

11.3.4 Slave FIFO Synchronous Address

IFCLK

SLCS#/FIFOADR[2:0]

t_SFA

t_FAH

Figure 11-8. Slave FIFO Synchronous Address Timing Diagram

[13]

Table 11-13. Slave FIFO Synchronous Address Parameters

Parameter Description

Interface Clock Period

Min.

20

Max.

Unit

ns

t

200

IFCLK

FIFOADR[2:0] to Clock Set-up Time

Clock to FIFOADR[2:0] Hold Time

25

ns

SFA

FAH

10

ns

Document #: 38-08013 Rev. *E

Page 28 of 42

FOR

CY7C68001

11.3.5 Slave FIFO Asynchronous Read

t_RDpwh

SLRD

t_RDpwl

t_XFLG

t_XFD

FLAGS

DATA

SLOE

N+1

N

t_OEon

t_OEoff

[12]

Figure 11-9. Slave FIFO Asynchronous Read Timing Diagram

[14]

Table 11-14. Slave FIFO Asynchronous Read Parameters

Parameter Description

SLRD Pulse Width Low

Min.

50

Max.

Unit

ns

t

RDpwl

SLRD Pulse Width HIGH

50

ns

RDpwh

XFLG

XFD

SLRD to FLAGS Output Propagation Delay

SLRD to FIFO Data Output Propagation Delay

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

70

15

ns

10.5

ns

OEon

OEoff

ns

11.3.6 Slave FIFO Asynchronous Write

t_WRpwh

SLWR/SLCS#

t_WRpwl

t_SFD

t_FDH

DATA

t_XFD

FLAGS

[12]

Figure 11-10. Slave FIFO Asynchronous Write Timing Diagram

[14]

Table 11-15. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK

Parameter

Description

Min.

50

Max.

Unit

ns

t

SLWR Pulse LOW

SLWR Pulse HIGH

WRpwl

70

ns

WRpwh

SFD

SLWR to FIFO DATA Set-up Time

FIFO DATA to SLWR Hold Time

10

ns

10

ns

FDH

SLWR to FLAGS Output Propagation Delay

70

ns

XFD

Note:

14. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz.

Document #: 38-08013 Rev. *E

Page 29 of 42

FOR

CY7C68001

11.3.7 Slave FIFO Asynchronous Packet End Strobe

t_PEpwh

PKTEND

t_PEpwl

FLAGS

t_XFLG

Figure 11-11. Slave FIFO Asynchronous Packet End Strobe Timing Diagram

[14]

Table 11-16. Slave FIFO Asynchronous Packet End Strobe Parameters

Parameter Description

PKTEND Pulse Width LOW

Min.

50

Max.

Unit

ns

t

PEpwl

PKTEND Pulse Width HIGH

50

ns

PWpwh

XFLG

PKTEND to FLAGS Output Propagation Delay

110

ns

11.3.8 Slave FIFO Asynchronous Address

SLCS/FIFOADR[2:0]

t_FAH

t_SFA

SLRD/SLWR/PKTEND

[12]

Figure 11-12. Slave FIFO Asynchronous Address Timing Diagram

[14]

Table 11-17. Slave FIFO Asynchronous Address Parameters

Parameter

Description

Min.

10

Max.

Unit

ns

t

FIFOADR[2:0] to RD/WR/PKTEND Set-up Time

SLRD/PKTEND to FIFOADR[2:0] Hold Time

SLWR to FIFOADR[2:0] Hold Time

SFA

FAH

20

ns

70

ns

11.4

Slave FIFO Address to Flags/Data

Following timing is applicable to synchronous and asynchronous interfaces.

FIFOADR [2.0]

t_XFLG

FLAGS

t_XFD

DATA

N

N+1

[11]

Figure 11-13. Slave FIFO Address to Flags/Data Timing Diagram

Table 11-18. Slave FIFO Address to Flags/Data Parameters

Parameter

Description

Min.

Max.

10.7

14.3

Unit

ns

t

FIFOADR[2:0] to FLAGS Output Propagation Delay

FIFOADR[2:0] to FIFODATA Output Propagation Delay

XFLG

XFD

ns

Document #: 38-08013 Rev. *E

Page 30 of 42

FOR

CY7C68001

11.5

Slave FIFO Output Enable

Following timings are applicable to synchronous and asynchronous interfaces.

SLOE

t_OEoff

t_OEon

DATA

[11]

Figure 11-14. Slave FIFO Output Enable Timing Diagram

Table 11-19. Slave FIFO Output Enable Parameters

Parameter

Description

SLOE assert to FIFO DATA Output

SLOE deassert to FIFO DATA Hold

Min.

Max.

10.5

Unit

ns

t

OEon

OEoff

ns

11.6

Sequence Diagram

11.6.1 Single and Burst Synchronous Read Example

t

IFCLK

t

SFA

t

FAH

FIFOADR

t=0

T=0

t

>= t

SRD

>= t

RDH

SRD

RDH

SLRD

SLCS

t=3

t=2

T=3

T=2

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

N+4

Data Driven: N

OEon

N+2

N+3

N+1

t

OEon

t

OEoff

t

OEoff

t=4

T=4

T=1

t=1

Figure 11-15. Slave FIFO Synchronous Read Sequence and Timing Diagram

IFCLK

N

IFCLK

N

IFCLK

N+1

IFCLK

N+1

IFCLK

N+1

IFCLK

N+2

IFCLK

N+3

IFCLK

N+4

IFCLK

N+4

IFCLK

N+4

FIFO POINTER

SLOE

SLRD

SLOE

SLRD

N+4

SLOE

FIFO DATA BUS Not Driven

Driven: N

N+1

Not Driven

N+1

N+2

N+3

N+4

Not Driven

Figure 11-16. Slave FIFO Synchronous Sequence of Events Diagram

Document #: 38-08013 Rev. *E

Page 31 of 42

FOR

CY7C68001

Figure 11-15 shows the timing relationship of the SLAVE FIFO

signals during a synchronous FIFO read using IFCLK as the

synchronizing clock. The diagram illustrates a single read

followed by a burst read.

SLRD signals must both be asserted to start a valid read

condition).

• The FIFO pointeris updated ontherising edge of the IFCLK,

while SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

• At t = 0 the FIFO address is stable and the signal SLCS is

asserted (SLCS may be tied low in some applications).

propagation delay of t

(measured from the rising edge

XFD

Note: t

has a minimum of 25 nsec. This means when

of IFCLK) the new data value is present. N is the first data

value read from the FIFO. In order to have data on the FIFO

data bus, SLOE MUST also be asserted.

SFA

IFCLK is running at 48 MHz, the FIFO address setup time

is more than one IFCLK cycle.

• At = 1, SLOE is asserted. SLOE is an output enable only,

whose sole function is to drive the data bus. The data that

is driven on the bus is the data that the internal FIFO pointer

is currently pointing to. In this example it is the first data

value in the FIFO. Note:the data is pre-fetched and is driven

on the bus when SLOE is asserted.

The same sequence of events are shown for a burst read and

are marked with the time indicators of T = 0 through 5. Note:

For the burst mode, the SLRD and SLOE are left asserted

during the entire duration of the read. In the burst read mode,

when SLOE is asserted, data indexed by the FIFO pointer is

on the data bus. During the first read cycle, on the rising edge

of the clock the FIFO pointer is updated and increments to

point to address N+1. For each subsequent rising edge of

IFCLK, while the SLRD is asserted, the FIFO pointer is incre-

mented and the next data value is placed on the data bus.

• At t = 2, SLRD is asserted. SLRD must meet the setup time

of t

(time from asserting the SLRD signal to the rising

SRD

edge of the IFCLK) and maintain a minimum hold time of

(time from the IFCLK edge to the deassertion of the

t

RDH

SLRDsignal). If theSLCS signalis used, itmustbe asserted

with SLRD, or before SLRD is asserted (i.e. the SLCS and

11.6.2 Single and Burst Synchronous Write

t

IFCLK

t

SFA

t

SFA

t

FAH

FIFOADR

>= t

t=0

WRH

t

>= t

SWR

T=0

WRH

SWR

SLWR

SLCS

T=2

T=5

t=2

t=3

t

XFLG

t

XFLG

FLAGS

DATA

t

FDH

t

SFD

FDH

SFD

FDH

SFD

FDH

N+1

N+3

N

N+2

T=4

T=3

t=1

T=1

t

SPE

t

PEH

PKTEND

[12]

Figure 11-17. Slave FIFO Synchronous Write Sequence and Timing Diagram

Figure 11-17 shows the timing relationship of the SLAVE FIFO

signals during a synchronous write using IFCLK as the

synchronizing clock. The diagram illustrates a single write

followed by burst write of 3 bytes and committing all 4 bytes as

a short packet using the PKTEND pin.

• At t = 1, the external master/peripheral must outputs the

data value onto the data bus with a minimum set up time of

t

before the rising edge of IFCLK.

SFD

• At t = 2, SLWR is asserted. The SLWR must meet the setup

time of t (time from asserting the SLWR signal to the

SWR

• At t = 0 the FIFO address is stable and the signal SLCS is

asserted. (SLCS may be tied low in some applications)

rising edge of IFCLK) and maintain a minimum hold time of

(time from the IFCLK edge to the de-assertion of the

SLWR signal). If SLCS signal is used, it must be asserted

with SLWR or before SLWR is asserted. (i.e. the SLCS and

SLWR signals must both be asserted to start a valid write

condition).

t

WRH

Note:t

has aminimum of 25 ns. This means when IFCLK

SFA

is running at 48 MHz, the FIFO address setup time is more

than one IFCLK cycle.

Document #: 38-08013 Rev. *E

Page 32 of 42

FOR

CY7C68001

• While the SLWR is asserted, data is written to the FIFO and

on the rising edge of the IFCLK, the FIFO pointer is incre-

mented. The FIFO flag will also be updated after a delay of

There is no specific timing requirement that needs to be met

for asserting PKTEND signal with regards to asserting the

SLWR signal. PKTEND can be asserted with the last data

value or thereafter. The only consideration is the setup time

t

from the rising edge of the clock.

XFLG

t

and the hold time t

must be met. In the scenario of

SPE

PEH

The same sequence of events are also shown for a burst write

and are marked with the time indicators of T=0 through 5.

Note: For the burst mode, SLWR and SLCS are left asserted

for the entire duration of writing all the required data values. In

this burst write mode, once the SLWR is asserted, the data on

the FIFO data bus is written to the FIFO on every rising edge

of IFCLK. The FIFO pointer is updated on each rising edge of

IFCLK. In Figure 11-17, once the four bytes are written to the

FIFO, SLWR is de-asserted. The short 4-byte packet can be

committed to the host by asserting the PKTEND signal.

Figure 11-17, the number of data values committed includes

the last value written to the FIFO. In this example, both the

data value and the PKTEND signal are clocked on the same

rising edge of IFCLK. PKTEND can be asserted in subsequent

clock cycles. The FIFOADDR lines should be held constant

during the PKTEND assertion.

11.6.3 Sequence Diagram of a Single and Burst Asynchro-

nous Read

t

FAH

SFA

FAH

FIFOADR

t=0

t

RDpwh

t

RDpwl

t

RDpwh

t

T=0

RDpwl

RDpwh

SLRD

SLCS

t=3

t=2

T=2

T=3

T=5

T=4

T=6

t

XFLG

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

t

XFD

Data (X)

Driven

N+3

N

N+1

N+2

N

t

OEon

t

OEoff

OEon

t=4

T=1

T=7

t=1

Figure 11-18. Slave FIFO Asynchronous Read Sequence and Timing Diagram

SLOE

SLRD

SLOE

SLRD

N+1

SLRD

N+1

SLRD

N+2

SLRD

N+2

SLOE

FIFO POINTER

N

N+1

N

N+1

N+3

N+2

N+3

FIFO DATA BUS Not Driven

Driven: X

Not Driven

N

N+1

N+2

Not Driven

Figure 11-19. Slave FIFO Asynchronous Read Sequence of Events Diagram

Figure 11-18 diagrams the timing relationship of the SLAVE

FIFO signals during an asynchronous FIFO read. It shows a

single read followed by a burst read.

SLCS and SLRD signals must both be asserted to start a

valid read condition.)

• The data that will be driven, after asserting SLRD, is the

updated data from the FIFO. This data is valid after a propa-

• At t = 0 the FIFO address is stable and the SLCS signal is

asserted.

gation delay of t

from the activating edge of SLRD. In

XFD

Figure 11-18, data N is the first valid data read from the

FIFO. For data to appear on the data bus during the read

cycle(i.e. SLRDis asserted),SLOE MUSTbeinanasserted

state. SLRD and SLOE can also be tied together.

• At t = 1, SLOE is asserted. This results in the data bus being

driven. The data that is driven on to the bus is previous data,

it data that was in the FIFO from a prior read cycle.

• At t = 2, SLRD is asserted. The SLRD must meet the

The same sequence of events is also shown for a burst read

marked with T = 0 through 5. Note: In burst read mode, during

SLOE is assertion, the data bus is in a driven state and outputs

the previous data. Once SLRD is asserted, the data from the

minimum active pulse of t

and minimum de-active

RDpwl

pulse width of t

. If SLCS is used then, SLCS must be

RDpwh

in asserted with SLRD or before SLRD is asserted. (i.e. the

Document #: 38-08013 Rev. *E

Page 33 of 42

FOR

CY7C68001

FIFO is driven on the data bus (SLOE must also be asserted)

and then the FIFO pointer is incremented.

11.6.4 Sequence Diagram of a Single and Burst Asynchronous Write

t

FAH

t

SFA

FAH

FIFOADR

t=0

T=0

t

WRpwl

t

WRpwh

WRpwl

WRpwh

WRpwl

SLWR

SLCS

t=3

t =1

T=1

T=4

T=3

T=7

T=6

T=9

t

XFLG

t

XFLG

FLAGS

DATA

t

FDH

t

SFD

t

SFD

SFD FDH

FDH

N

N+1

N+2

N+3

t=2

T=8

T=2

T=5

t

PEpwl

PEpwh

PKTEND

[12]

Figure 11-20. Slave FIFO Asynchronous Write Sequence and Timing Diagram

Figure 11-20 diagrams the timing relationship of the SLAVE

FIFO write in an asynchronous mode. The diagram shows a

single write followed by a burst write of 3 bytes and committing

the 4-byte-short packet using PKTEND.

pointer. The FIFO flag is also updated after t

asserting edge of SLWR.

from the de-

XFLG

The same sequence of events are shown for a burst write and

is indicated by the timing marks of T = 0 through 5. Note: In

the burst write mode, once SLWR is de-asserted, the data is

written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post incre-

mented.

·At t = 0 the FIFO address is applied, insuring that it meets the

setup time of t

. If SLCS is used, it must also be asserted

SFA

(SLCS may be tied low in some applications).

·..At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of t

and minimum de-active pulse width of

In Figure 11-20 once the four bytes are written to the FIFO and

SLWR is deasserted, the short 4-byte packet can be

committed to the host using the PKTEND. The external device

should be designed to not assert SLWR and the PKTEND

signal at the same time. It should be designed to assert the

PKTEND after SLWR is deasserted and met the minimum de-

asserted pulse width. The FIFOADDR lines are to be held

constant during the PKTEND assertion.

WRpwl

t

. If the SLCS is used, it must be in asserted with SLWR

WRpwh

or before SLWR is asserted.

·At t = 2, data must be present on the bus t

asserting edge of SLWR.

before the de-

SFD

·At t = 3, de-asserting SLWR will cause the data to be written

from the data bus to the FIFO and then increments the FIFO

Document #: 38-08013 Rev. *E

Page 34 of 42

FOR

CY7C68001

12.0

Default Descriptor

//Device Descriptor

18,

1,

//Descriptor length

//Descriptor type

00,02,

00,

64,

//Specification Version (BCD)

//Device class

//Device sub-class

//Device sub-sub-class

//Maximum packet size

LSB(VID),MSB(VID),//Vendor ID

LSB(PID),MSB(PID),//Product ID

LSB(DID),MSB(DID),//Device ID

1,

2,

0,

1,

//Manufacturer string index

//Product string index

//Serial number string index

//Number of configurations

//DeviceQualDscr

10,

6,

//Descriptor length

//Descriptor type

0x00,0x02,

//Specification Version (BCD)

//Device class

00,

64,

1,

//Device sub-class

//Device sub-sub-class

//Maximum packet size

//Number of configurations

//Reserved

0,

//HighSpeedConfigDscr

9,

//Descriptor length

2,

//Descriptor type

46,

0,

1,

0,

//Total Length (LSB)

//Total Length (MSB)

//Number of interfaces

//Configuration number

//Configuration string

0xA0,

50,

//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)

//Power requirement (div 2 ma)

//Interface Descriptor

9,

//Descriptor length

4,

//Descriptor type

0,

//Zero-based index of this interface

//Alternate setting

4,

//Number of end points

//Interface class

//Interface sub class

//Interface sub sub class

//Interface descriptor string index

0xFF,

0x00,

0,

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x02,

2,

//Endpoint number, and direction

//Endpoint type

0x00,

0x02,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

Document #: 38-08013 Rev. *E

Page 35 of 42

FOR

CY7C68001

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x04,

2,

//Endpoint number, and direction

//Endpoint type

0x00,

0x02,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x86,

2,

//Endpoint number, and direction

//Endpoint type

0x00,

0x02,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x88,

2,

//Endpoint number, and direction

//Endpoint type

0x00,

0x02,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

//FullSpeedConfigDscr

9,

//Descriptor length

2,

//Descriptor type

46,

0,

1,

0,

//Total Length (LSB)

//Total Length (MSB)

//Number of interfaces

//Configuration number

//Configuration string

0xA0,

50,

//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)

//Power requirement (div 2 ma)

//Interface Descriptor

9,

//Descriptor length

4,

//Descriptor type

0,

//Zero-based index of this interface

//Alternate setting

4,

//Number of end points

//Interface class

//Interface sub class

//Interface sub sub class

//Interface descriptor string index

0xFF,

0x00,

0,

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x02,

2,

//Endpoint number, and direction

//Endpoint type

0x40,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

Document #: 38-08013 Rev. *E

Page 36 of 42

FOR

CY7C68001

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x04,

2,

//Endpoint number, and direction

//Endpoint type

0x40,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x86,

2,

//Endpoint number, and direction

//Endpoint type

0x40,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

//Endpoint Descriptor

7,

//Descriptor length

5,

//Descriptor type

0x88,

2,

//Endpoint number, and direction

//Endpoint type

0x40,

0x00,

//Maximum packet size (LSB)

//Max packet size (MSB)

//Polling interval

//StringDscr

//StringDscr0

4,

3,

//String descriptor length

//String Descriptor

//US LANGID Code

0x09,0x04,

//StringDscr1

16,

3,

//String descriptor length

//String Descriptor

'C',00,

'y',00,

'p',00,

'r',00,

'e',00,

's',00,

//StringDscr2

20,

3,

//String descriptor length

//String Descriptor

'C',00,

'Y',00,

'7',00,

'C',00,

'6',00,

'8',00,

'0',00,

'1',00,

Document #: 38-08013 Rev. *E

Page 37 of 42

FOR

CY7C68001

13.0

General PCB Layout Guidelines^[15]

The following recommendations should be followed to ensure reliable high-performance operation.

• At least a four-layer impedance controlled boards are re-

quired to maintain signal quality.

thermal bond to the circuit board. A Copper (Cu) fill is to be

designed into the PCB as a thermal pad under the package.

Heat is transferred from the SX2 through the device’s metal

paddle on the bottom side of the package. Heat from here, is

conducted to the PCB at the thermal pad. It is then conducted

from the thermal pad to the PCB inner ground plane by a 5 x

5 array of via. A via is a plated through hole in the PCB with a

finished diameter of 13 mil. The QFN’s metal die paddle must

be soldered to the PCB’s thermal pad. Solder mask is placed

on the board top side over each via to resist solder flow into

the via. The mask on the top side also minimizes outgassing

during the solder reflow process.

• Specify impedance targets (ask your board vendor what

they can achieve).

• To control impedance, maintain trace widths and trace spac-

ing.

• Minimize stubs to minimize reflected signals.

• Connections between the USB connector shell and signal

ground must be done near the USB connector.

• Bypass/flyback caps on VBus, near connector, are recom-

mended.

• DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of 20–30

mm.

For further information on this package design please refer to

the application note “Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology.” This application note

can be downloaded from AMKOR’s web site from the following

URL

http://www.amkor.com/products/notes_papers/MLF_AppNote

_0902.pdf. The application note provides detailed information

on board mounting guidelines, soldering flow, rework process,

etc.

• Maintain a solid ground plane under the DPLUS and DMI-

NUS traces. Do not allow the plane to be split under these

traces.

• It is preferred to have no vias placed on the DPLUS or DMI-

NUS trace routing.

• Isolate the DPLUS and DMINUS traces from all other signal

traces by no less than 10 mm.

Figure 14-1 below display a cross-sectional area underneath

the package. The cross section is of only one via. The solder

paste template needs to be designed to allow at least 50%

solder coverage. The thickness of the solder paste template

should be 5 mil. It is recommended that “No Clean” type 3

solder paste is used for mounting the part. Nitrogen purge is

recommended during reflow.

14.0

Quad Flat Package No Leads (QFN)

Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

QFN to the circuit board ground plane.

circuit board: Top Solder, PCB Dielectric, and the Ground Plane.

Figure 14-1. Cross section of the Area Underneath the QFN Package

Figure 14-2a is a plot of the solder mask pattern and Figure 14-2b displays an X-Ray image of the assembly (darker areas indicate

solder.

Figure 14-2(b) X-ray Image of the Assembly

Figure 14-2. (a) Plot of the Solder Mask (White Area)

Note:

15. Source for recommendations: High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.

Document #: 38-08013 Rev. *E

Page 38 of 42

FOR

CY7C68001

15.0

Ordering Information

Table 15-1. Ordering Information

Ordering Code

CY7C68001-56PVC

CY7C68001-56LFC

CY7C68001-56PVXC

CY7C68001-56LFXC

CY3682

Package Type

56 SSOP

56 QFN

56 SSOP, Lead-free

56 QFN, Lead-free

EZ-USB SX2 Development Kit

16.0

16.1

Package Diagrams

56-pin SSOP Package

56-pin Shrunk Small Outline Package 056

51-85062-*C

Figure 16-1. 56-lead Shrunk Small Outline Package

Note:

16. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz.

Document #: 38-08013 Rev. *E

Page 39 of 42

CY7C68001

16.2

56-pin QFN Package

56-Lead QFN 8 x 8 MM LF56A

TOP VIEW

BOTTOM VIEW

SIDE VIEW

0.08[0.003]

C

1.00[0.039] MAX.

0.80[0.031] MAX.

7.90[0.311]

8.10[0.319]

A

0.05[0.002] MAX.

0.18[0.007]

0.28[0.011]

7.70[0.303]

7.80[0.307]

0.20[0.008] REF.

PIN1 ID

N

0.20[0.008] R.

1

2

1

2

0.45[0.018]

0.80[0.031]

DIA.

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

0.30[0.012]

0.50[0.020]

0.24[0.009]

0.60[0.024]

(4X)

0°-12°

0.50[0.020]

6.45[0.254]

6.55[0.258]

C

SEATING

PLANE

Dimensions in millimeters

51-85144-*D

Figure 16-2. LF56A 56-pin QFN Package

2

Purchase of I C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips

2

I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification

as defined by Philips. EZ-USB SX2 is a trademark of Cypress Semiconductor. All product and company names mentioned in this

document are the trademarks of their respective holders.

Document #: 38-08013 Rev. *E

Page 40 of 42

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

FOR

CY7C68001

17.0

Document Revision History

Description Title: CY7C68001 EZ-USB SX2™ High-Speed USB Interface Device

Document Number: 38-08013

Origin of

REV. ECN No. Issue Date Change

Description of Change

**

111807

123155

06/07/02

02/07/03

BHA

New Data Sheet

*A

Minor clean-up and clarification

Removed references to IRQ Register and replaced them with references to

Interrupt Status Byte

Modified pin-out description for XTALIN and XTALOUT

Added CS# timing to Figure 11-10, Figure 11-8, and Figure 11-12

Changed Command Protocol example to IFCONFIG (0x01)

Edited PCB Layout Recommendations

Added AR#10691

Added USB high-speed logo

*B

126324

07/02/03

MON

Default state of registers specified in section where the register bits are defined

Reorganized timing diagram presentation: First all timing related to synchronous

interface, followed by timing related to asynchronous interface, followed by timing

diagrams common to both interfaces

Provided further information in section 3.3 regarding boot methods

Provided timing diagram that encapsulates ALL relevant signals for a synchronous

and asynchronous slave read and write interface

Added section on (QFN) Package Design Notes

FIFOADR[2:0] Hold Time (t

for Asynchronous FIFO Interface has been updated

FAH)

as follows: SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns; SLWR to

FIFOADR[2:0] Hold Time:70 ns (recommended)

Added information on the polarity of the programmable flag

Fixed the Command Synchronous Write Timing Diagram

Fixed the Command Asynchronous Write Timing Diagram

Added information on the delay required when endpoint configuration registers are

changed after SX2 has already enumerated

*C

129463

10/07/03

MON

Added Test ID for the USB Compliance Test

Added information on the fact that the SX2 does not automatically respond to

Set/Clear Feature Endpoint (Stall) request, external master intervention required

Added information on accessing undocumented register which are not indexed (for

resetting data toggle)

Added information on requirement of clock stability before releasing reset

Added information on configuration of PF register for full speed

Updated confirmed timing on FIFOADR[2:0] Hold Time (t

)for Asynchronous

FAH

FIFO Interface has been updated

Corrected the default bit settings of EPxxFLAGS register

Added information on how to change SLWR/SLRD/SLOE polarities

Added further information on buffering interrupt on initiation of a command read

request

Change the default state of the FNADDR to 0x00

Added further labels on the sequence diagram for synchronous and asynchronous

read and write in single and burst mode

Added information on the maximum delay allowed between each descriptor byte

write once a command write request to register 0x30 has been initiated by the

external master

Document #: 38-08013 Rev. *E

Page 41 of 42

FOR

CY7C68001

Description Title: CY7C68001 EZ-USB SX2™ High-Speed USB Interface Device

Document Number: 38-08013

*D

130447

12/17/03

KKU

Replaced package diagram in Figure 16-2 spec number 51-85144 with clear image

Fixed last history entry for rev *C

Change reference in section 2.7.2.4 from XXXXXXX to 7.3

Removed the word “compatible” in section 3.3

Change the text in section 5.0, last paragraph from 0xE6FB to 0xE683

Changed label “Reset” to “Default” in sections 5.1 and 7.2 through 7.14

Reformatted Figure 6-2

Added entries 3A, 3B, 3C, 0xE609, and 0xE683 to Figure 7-1

Change access on hex values 07 and 09 from bbbbbbbb to bbbbrbrr

Removed t

from Figure 11-1 and Figure 11-3 and tables 11-1,2, and 5

XFD

Corrected timing diagrams, figures 11-1,11-2, 11-6

Changed Figure 11-15 through Figure 11-20 for clarity, text which followed had

reference to t3 which should be t2, added reference of t3 for deasserting SLWR and

reworded section 11.6

Updated I typical and maximum values

CC

*E

243316

See ECN

KKU

Reformated data sheet to latest format

Added Lead-free parts numbers

Updated default value for address 0x07 and 0x09

Added Footnote 3.

Removed requirement of less then 360 nsec period between nibble writes in

command

Changed PKTEND to FLAGS output propagation delay in table 11-16 from a max

value of 70 ns to 110 ns

Document #: 38-08013 Rev. *E

Page 42 of 42


型号：	CY3682
厂家：	CYPRESS
描述：	EZ-USB SX2⑩ High-Speed USB Interface Device EZ -USB SX2 ？高速USB接口设备
文件：	总42页 (文件大小：980K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY3682 [CYPRESS]

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