CY3683_技术文档

CY7C68000

TX2™ USB 2.0 UTMI Transceiver

• Synchronous field and EOP detection on receive

packets

1.0

EZ-USBTX2™ Features

The Cypress EZ-USB TX2™ is a Universal Serial Bus (USB)

specification revision 2.0 transceiver, serial/deserializer, to a

parallel interface of either 16 bits at 30 MHz or eight bits at 60

MHz. The TX2 provides a high-speed physical layer interface

that operates at the maximum allowable USB 2.0 bandwidth.

This allows the system designer to keep the complex high-

speed analog USB components external to the digital ASIC

which decreases development time and associated risk. A

standard interface is provided that is USB 2.0-certified and is

compliant with Transceiver Macrocell Interface (UTMI) speci-

fication version 1.05 dated 3/29/01.

• Synchronous field and EOP generation on transmit

packets

• Data and clock recovery from the USB serial stream

• Bit stuffing/unstuffing; bit stuff error detection

• Staging register to manage data rate variation due to

bit stuffing/unstuffing

• 16-bit 30-MHz, and 8-bit 60-MHz parallel interface

• Ability to switch between FS and HS terminations and

signaling

• Supports detection of USB reset, suspend, and resume

Two packages are defined for the family: 56-pin SSOP and 56-

pin QFN.

• Supports HS identification and detection as defined by

the USB 2.0 Specification

The function block diagram is shown in Figure 1-1. The

features of the EX-USB TX2 are:

• Supports transmission of resume signaling

• 3.3 V operation

• UTMI-compliant/USB-2.0-certified for device operation

• Two package options—56-pin QFN, and 56-pin SSOP

• Operates in both USB 2.0 high speed (HS), 480

Mbits/second, and full speed (FS), 12 Mbits/second

• All required terminations, including 1.5K-ohm pull up

on DPLUS, are internal to the chip

• Serial-to-parallel and parallel-to-serial conversions

• Supports USB 2.0 test modes

• 8-bit unidirectional, 8-bit bidirectional, or 16-bit

bidirectional external data interface

CY7C68000

20X

PLL

XTALIN/

OUT

UTMI CLK

OSC

UTMI CLK

PLL_480

Full-Speed Rx

High-Speed Rx

UTMI Rx Ctl

Digital

Rx

UTMI Rx Data 8/16

Fast

Digital

Rx

Traffic

Sync

Elasticity

Buffer

USB

BIDI Option

Also

USB

2.0

Fast

Digital

Tx

XCVR

High-Speed Tx

Full-Speed Tx

UTMI TRx Data 8/16

UTMI Tx Ctl

Digital

Tx

Figure 1-1. Block Diagram

Cypress Semiconductor Corporation

Document #: 38-08016 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 2, 2006

CY7C68000

signal. On the CLK edge the state of these lines reflect the

state of the USB data lines. Upon the clock edge the 0-bit of

the LineState pins is the state of the DPLUS line and the one

bit of LineState is the DMINUS line. When synchronized, the

set up and hold timing of the LineState is identical to the

parallel data bus.

2.0

Applications

• DSL modems

• ATA interface

• Memory card readers

• Legacy conversion devices

• Cameras

3.6

Full-speed vs. High-speed Select

• Scanners

The FS vs. HS is done through the use of both XcvrSelect and

the TermSelect input signals. The TermSelect signal enables

the 1.5 K ohm pull up on to the DPLUS pin. When TermSelect

is driven LOW, a SE0 is asserted on the USB providing the HS

termination and generating the HS Idle state on the bus. The

XcvrSelect signal is the control which selects either the FS

transceivers or the HS transceivers. To select the HS trans-

ceivers, set this pin to ‘0’. To select the FS transceivers, set

this pin to ‘1’.

• Home PNA

• Wireless LAN

• MP3 players

• Networking

3.0

3.1

Functional Overview

USB Signaling Speed

TX2 operates at two of the rates defined in the USB Specifi-

cation 2.0, dated April 27, 2000:

3.7

Operational Modes

The operational modes are controlled by the OpMode signals.

The OpMode signals are capable of inhibiting normal

operation of the transceiver and evoking special test modes.

These modes take effect immediately and take precedence

over any pending data operations. The transmission data rate

when in OpMode depends on the state of the XcvrSelect

input.

• Full speed, with a signaling bit rate of 12 Mbps

• High speed, with a signaling bit rate of 480 Mbps

TX2 does not support the low-speed (LS) signaling rate of 1.5

Mbps.

3.2

Transceiver Clock Frequency

OpMode[1:0]

Mode

Description

Normal operation

Non-driving

TX2 has an on-chip oscillator circuit that uses an external 24-

MHz (±100-ppm) crystal with the following characteristics:

00

01

10

0

1

2

• Parallel resonant

Disable Bit Stuffing and

NRZI encoding

• Fundamental mode

• 500-μW drive level

• 27–33 pF (5% tolerance) load capacitors

11

3

Reserved

An on-chip phase-locked loop (PLL) multiplies the 24-MHz

oscillator up to 30/60 MHz, as required by the transceiver

parallel data bus. The default UTMI interface clock (CLK)

frequency is determined by the DataBus16_8 pin.

Mode 0 allows the transceiver to operate with normal USB

data decoding and encoding.

Mode 1 allows the transceiver logic to support a soft

disconnect feature which three-states both the HS and FS

transmitters, and removes any termination from the USB,

making it appear to an upstream port that the device has been

disconnected from the bus.

3.3

Buses

The two packages allow for 8/16-bit bidirectional data bus for

data transfers to a controlling unit.

Mode 2 disables Bit Stuff and NRZI encoding logic so 1s

loaded from the data bus becomes Js on the DPLUS/DMINUS

lines and 0s become Ks.

3.4

Reset Pin

An input pin (Reset) resets the chip. This pin has hysteresis

and is active HIGH according to the UTMI specification. The

internal PLL stabilizes approximately 200 μs after V_CChas

reached 3.3V.

4.0

DPLUS/DMINUS Impedance Termination

The CY7C68000 does not require external resistors for USB

data line impedance termination or an external pull up resistor

on the DPLUS line. These resistors are incorporated into the

part. They are factory trimmed to meet the requirements of

USB 2.0. Incorporating these resistors also reduces the pin

count on the part.

3.5

Line State

The Line State output pins LineState[1:0] are driven by combi-

national logic and may be toggling between the J and the K

states. They are synchronized to the CLK signal for a valid

Document #: 38-08016 Rev. *H

Page 2 of 14

CY7C68000

5.0

Pin Assignments

The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin SSOP packages.

The packages offered use either an 8-bit (60-MHz) or 16-bit (30-MHz) bus interface.

56-pin QFN

GND

D5

TXReady

Suspend

Reset

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

Reserved

D6

3

AV_CC

4

D7

XTALOUT

XTALIN

AGND

5

D8

6

CY7C68000

56-pin QFN

D9

7

Reserved

D10

AV_CC

8

DPLUS

9

D11

DMINUS

AGND

10

11

12

13

14

V_CC

D12

XcvrSelect

TermSelect

OpMode0

GND

29 D13

Figure 5-1. CY7C68000 56-pin QFN Pin Assignment

Document #: 38-08016 Rev. *H

Page 3 of 14

CY7C68000

56-pin SSOP

56

55

1

2

CLK

D0

D1

DataBus16_8

54

53

3

4

Uni_Bidi

GND

Reserved

D2

52

51

5

6

TXValid

V

CC

V

CC

D3

50

49

7

8

ValidH

D4

GND

TXReady

48

47

9

Suspend

D5

10 Reset

Reserved

46

45

11 AVCC

D6

D7

12 XTALOUT

44

43

13 XTALIN

14 AGND

D8

D9

42

41

15 AVCC

Reserved

16 DPLUS

D10

D11

DMINUS

17

40

39

AGND

18

V

CC

XcvrSelect

19

D12

38

37

TermSelect

20

GND

36

35

21

22

OpMode0

OpMode1

D13

V

CC

34

33

23

24

GND

D14

D15

V

CC

32

31

LineState0

LineState1

Reserved

25

26

GND

RXError

30

29

27

28

RXValid

RXActive

Figure 5-2. CY7C68000 56-pin SSOP Pin Assignment

CY7C68000 Pin Descriptions

5.1

[1]

Table 5-1. Pin Descriptions

SSOP QFN

Name

AVCC

Type

Default

N/A

Z

Description

11

15

14

18

16

4

8

7

Power

I/O/Z

Analog V_CC. This signal provides power to the analog section of the chip.

Analog Ground. Connect to ground with as short a path as possible.

USB DPLUS Signal. Connect to the USB DPLUS signal.

AVCC

AGND

11 AGND

DPLUS

10 DMINUS

9

17

I/O/Z

Z

USB DMINUS Signal. Connect to the USB DMINUS signal.

Note:

1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure

signals at power-up and in standby.

Document #: 38-08016 Rev. *H

Page 4 of 14

CY7C68000

Table 5-1. Pin Descriptions (continued)^[1]

SSOP QFN

49 D0

Name

Type

I/O

Default

Description

56

55

53

51

50

48

46

45

44

43

41

40

38

36

34

33

1

Bidirectional Data Bus. This bidirectional bus is used as the entire data

bus in the 8-bit bidirectional mode or the least significant eight bits in the 16-

bit mode or under the 8-bit unidirectional mode these bits are used as inputs

for data, selected by the RxValid signal.

48 D1

46 D2

44 D3

43 D4

41 D5

39 D6

38 D7

37 D8

36 D9

34 D10

33 D11

31 D12

29 D13

27 D14

26 D15

50 CLK

I/O

Bidirectional Data Bus. This bidirectional bus is used as the upper eight

bits of the data bus when in the 16-bit mode, and not used when in the 8-bit

bidirectional mode. Under the 8-bit unidirectional mode these bits are used

as outputs for data, selected by the TxValid signal.

I/O

Output

Clock. This output is used for clocking the receive and transmit parallel data

on the D[15:0] bus.

10

19

3

Reset

Input

N/A

Active HIGH Reset. Resets the entire chip. This pin can be tied to V_CC

through a 0.1 μF capacitor and to GND through a 100 K resistor for a 10

msec RC time constant.

12 XcvrSelect

13 TermSelect

Transceiver Select. This signal selects between the Full Speed (FS) and

the High Speed (HS) transceivers:

0: HS transceiver enabled

1: FS transceiver enabled

20

9

Input

N/A

Termination Select. This signal selects between the between the Full

Speed (FS) and the High Speed (HS) terminations:

0: HS termination

1: FS termination

2

Suspend

Suspend. Places the CY7C68000 in a mode that draws minimal power from

supplies. Shuts down all blocks not necessary for Suspend/Resume opera-

tions. While suspended, TermSelect must always be in FS mode to ensure

that the 1.5 K ohm pull-up on DPLUS remains powered.

0: CY7C68000 circuitry drawing suspend current

1: CY7C68000 circuitry drawing normal current

26

19 LineState1

Output

Line State. These signals reflect the current state of the single-ended

receivers. They are combinatorial until a “usable” CLK is available then they

are synchronized to CLK. They directly reflect the current state of the

DPLUS (LineState0) and DMINUS (LineState1).

D– D+ Description

0 0 0: SE0

0 1 1: ‘J’ State

1 0 2: ‘K’ State

1 1 3: SE1

25

18 LineState0

Output

Line State. These signals reflect the current state of the single-ended

receivers. They are combinatorial until a ‘usable’ CLK is available then they

are synchronized to CLK. They directly reflect the current state of the

DPLUS (LineState0) and DMINUS (LineState1).

D– D+ Description

00–0: SE0

01–1: ‘J’ State

10–2: ‘K’ State

11–3: SE1.

Document #: 38-08016 Rev. *H

Page 5 of 14

CY7C68000

Table 5-1. Pin Descriptions (continued)^[1]

SSOP QFN

Name

Type

Default

Description

22

21

5

15 OpMode1

14 OpMode0

54 TXValid

Input

Operational Mode. These signals select among various operational

modes:

10 Description

00–0: Normal Operation

01–1: Non-driving

10–2: Disable Bit Stuffing and NRZI encoding

11–3: Reserved.

Input

Operational Mode. These signals select among various operational

modes:

10 Description

00–0: Normal Operation

01–1: Non-driving

10–2: Disable Bit Stuffing and NRZI encoding

11–3: Reserved.

Transmit Valid. Indicates that the data bus is valid. The assertion of Trans-

mit Valid initiates SYNC on the USB. The negation of Transmit Valid initiates

EOP on the USB. The start of SYNC must be initiated on the USB no less

than one or no more that two CLKs after the assertion of TXValid.

In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the

USB between 8- and 16-bit times after the assertion of TXValid is detected

by the Transmit State Machine.

In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less

than one or more than two CLKs after the assertion of TXValid is detected

by the Transmit State Machine.

8

1

TXReady

Output

Transmit Data Ready. If TXValid is asserted, the SIE must always have

data available for clocking in to the TX Holding Register on the rising edge

of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of

CLK, the CY7C68000 will load the data on the data bus into the TX Holding

Register on the next rising edge of CLK. At that time, the SIE should immedi-

ately present the data for the next transfer on the data bus.

28

29

21 RXValid

22 RXActive

Output

Receive Data Valid. Indicates that the DataOut bus has valid data. The

Receive Data Holding Register is full and ready to be unloaded. The SIE is

expected to latch the DataOut bus on the clock edge.

Receive Active. Indicates that the receive state machine has detected

SYNC and is active.

RXActive is negated after a bit stuff error or an EOP is detected.

30

7

23 RXError

56 ValidH

Output

I/O

Receive Error.

0 Indicates no error.

1 Indicates that a receive error has been detected.

ValidH. This signal indicates that the high-order eight bits of a 16-bit data

word presented on the Data bus are valid. When DataBus16_8 = 1 and

TXValid = 0, ValidH is an output, indicating that the high-order receive data

byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid = 1,

ValidH is an input and indicates that the high-order transmit data byte,

presented on the Data bus by the transceiver, is valid. When DataBus16_8

= 0, ValidH is undefined. The status of the receive low-order data byte is

determined by RXValid and are present on D0–D7.

2

51 DataBus16_8

Input

Data Bus 16_8. Selects between 8- and 16-bit data transfers.

1–16-bit data path operation enabled. CLK = 30 MHz.

0–8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are unde-

fined. When Uni_Bidi =1, D[0:7] are valid on RxValid and D[8:15] are valid

on TxValid. CLK = 60 MHz

Note: DataBus16_8 is static after Power-on Reset (POR) and is only sam-

pled at the end of Reset.

Document #: 38-08016 Rev. *H

Page 6 of 14

CY7C68000

Table 5-1. Pin Descriptions (continued)^[1]

SSOP QFN

Name

XTALIN

Type

Default

Description

13

6

Input

N/A

Crystal Input. Connect this signal to a 24-MHz parallel-resonant, funda-

mental mode crystal and 20-pF capacitor to GND.

It is also correct to drive XTALIN with an external 24-MHz square wave

derived from another clock source.

12

3

5

XTALOUT

Output

Input

N/A

Crystal Output. Connect this signal to a 24-MHz parallel-resonant, funda-

mental mode crystal and 30-pF (nominal) capacitor to GND. If an external

clock is used to drive XTALIN, leave this pin open.

52 Uni_Bidi

Driving this pin HIGH enables the unidirectional mode when the 8-bit

interface is selected. Uni_Bidi is static after power on reset (POR).

6

55 V_CC

17 V_CC

28 V_CC

32 V_CC

45 V_CC

Power

V_CC. Connect to 3.3V power source.

24

35

39

52

N/A

4

53 GND

16 GND

20 GND

30 GND

42 GND

Ground

N/A

Ground.

23

27

37

49

31

54

47

42

32

24 Reserved

47 Reserved

40 Reserved

35 Reserved

25 Reserved

INPUT

Connect pin to Ground.

Document #: 38-08016 Rev. *H

Page 7 of 14

CY7C68000

6.0

Absolute Maximum Ratings

7.0

Operating Conditions

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with Power Supplied......0°C to +70°C

Supply Voltage to Ground Potential............... –0.5V to +4.0V

DC Input Voltage to Any Input Pin .............................. 5.25 V

T_A(Ambient Temperature Under Bias)............. 0°C to +70°C

Supply Voltage................................................+3.0V to +3.6V

Ground Voltage.................................................................. 0V

F_OSC(Oscillator or Crystal Frequency).... 24 MHz ± 100 ppm

................................................................... Parallel Resonant

DC Voltage Applied to Outputs

in High-Z State .......................................–0.5V to V_CC+ 0.5V

Power Dissipation .....................................................630 mW

Static Discharge Voltage...........................................>2000V

Max Output Current, per IO pin..................................... 4 mA

Max Output Current, all 21–IO pins ............................84 mA

8.0

DC Characteristics

Table 8-1. DC Characteristics

Parameter

V_CC

V_IH

Description

Conditions

Min.

3.0

2

Typ.

Max.

3.6

Unit

V

Supply Voltage

3.3

Input High Voltage

Input Low Voltage

Input Leakage Current

Output Voltage High

Output Low Voltage

Output Current High

Output Current Low

Input Pin Capacitance

5.25

0.8

V

V_IL

–0.5

V

I_I

0< V_IN< V_CC

I_OUT= 4 mA

±10

μA

V

V_OH

V_OL

I_OH

2.4

I_OUT= –4 mA

0.4

4

V

mA

pF

μA

mA

ms

I_OL

4

C_IN

Except DPLUS/DMINUS/CLK

DPLUS/DMINUS/CLK

Output pins

Connected^[2]

Disconnected^[2]

10

15

30

293

55

175

90

C_LOAD

I_SUSP

Maximum Output Capacitance

Suspend Current

235

15

I_CC

Supply Current HS Mode

Supply Current FS Mode

Minimum Reset time

Normal operation OPMOD[1:0] = 00

I_CC

t_RESET

1.9

8.1

USB 2.0 Transceiver

USB 2.0 compliant in FS and HS modes.

Note:

2. Connected to the USB includes 1.5k-ohm internal pull-up. Disconnected has the 1.5k-ohm internal pull-up excluded.

Document #: 38-08016 Rev. *H

Page 8 of 14

CY7C68000

9.0

9.1

AC Electrical Characteristics

USB 2.0 Transceiver

USB 2.0 certified in FS and HS.

9.2

Timing Diagram

9.2.1

HS/FS Interface Timing–60 MHz

CLK

TCH_MIN

TDH_MIN

TCSU_MIN

Control_In

TDSU_MIN

DataIn

TCCO

TCDO

Control_Out

DataOut

Figure 9-1. 60-MHz Interface Timing Constraints

Table 9-1. 60-MHz Interface Timing Constraints Parameters

Parameter

T_{CSU_MIN}

Description

Min.

Typ.

Max.

Unit

ns

Notes

Minimum set-up time for TXValid

8

1

8

1

T_{CH_MIN}

T_{DSU_MIN}

T_{DH_MIN}

T_CCO

Minimum hold time for TXValid

ns

Minimum set-up time for Data (transmit direction)

Minimum hold time for Data (transmit direction)

ns

Clock to Control out time for TXReady, RXValid,

RXActive and RXError

8

ns

T_CDO

Clock to Data out time (Receive direction)

1

ns

Document #: 38-08016 Rev. *H

Page 9 of 14

CY7C68000

9.2.2

HS/FS Interface Timing–30 MHz

CLK

TCH_MIN

TDH_MIN

TCSU_MIN

Control_In

TDSU_MIN

TVSU_MIN

DataIn

Control_Out

DataOut

TCDO

TCCO

TCVO

TVH_MIN

Figure 9-2. 30-MHz Timing Interface Timing Constraints

Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters

Parameter

T_{CSU_MIN}

Description

Min.

20

1

Typ.

Max.

Unit

ns

Notes

Minimum set-up time for TXValid

T_{CH_MIN}

T_{DSU_MIN}

T_{DH_MIN}

T_CCO

Minimum hold time for TXValid

ns

Minimum set-up time for Data (Transmit direction)

Minimum hold time for Data (Transmit direction)

20

1

ns

Clock to Control Out time for TXReady, RXValid,

RXActive and RXError

1

20

ns

T_CDO

Clock to Data out time (Receive direction)

1

20

1

ns

T_{VSU_MIN}

T_{VH_MIN}

T_CVO

Minimum set-up time for ValidH (transmit Direction)

Minimum hold time for ValidH (Transmit direction)

Clock to ValidH out time (Receive direction)

1

20

Document #: 38-08016 Rev. *H

Page 10 of 14

CY7C68000

10.0

Ordering Information

Table 10-1. Ordering Information

Ordering Code

CY7C68000-56LFXC

CY7C68000-56LFXCT

CY7C68000-56PVC

CY7C68000-56PVCT

CY7C68000-56PVXC

CY7C68000-56PVXCT

CY3683

Package Type

56 QFN (Pb-Free)

56 QFN (Pb-Free) Tap/Reel

56 SSOP

56 SSOP Tape/Reel

56 SSOP (Pb-Free)

56 SSOP (Pb-Free) Tape/Reel

EZ-USB TX2 Development Board

11.0

Package Diagrams

The TX2 is available in two packages:

• 56-pin SSOP

• 56-pin QFN.

51-85062-*C

Figure 11-1. 56-lead Shrunk Small Outline Package O56

Document #: 38-08016 Rev. *H

Page 11 of 14

CY7C68000

56-Lead QFN 8 x 8 mm (Sawn Version) LS56B

DIMENSIONS IN MM[INCHES] MIN.

REFERENCE JEDEC MO-220

MAX.

TOP VIEW

BOTTOM VIEW

SIDE VIEW

0.08[0.003]

C

7.90[0.311]

1.00[0.039] MAX.

A

8.10[0.319]

0.20[0.008] REF.

PIN #1

0.18[0.007]

0.28[0.011]

CORNER

0.04[0.0015] MAX.

E-PAD

(PAD SIZE VARY

BY DEVICE TYPE)

0.30[0.012]

0.50[0.020]

C

0.50[0.020]

SEATING

PLANE

6.45[0.254]

6.55[0.258]

E-PAD maximum size

4.75 X 5.46 mm [187 x 215 mils] (width x length).

51-85187-*A

Figure 11-2. 56-lead Quad Flatpack No Lead Package (8 x 8 mm) (SAWN VERSION)

12.0

PCB Layout Recommendations^[3]

The following recommendations should be followed to ensure

reliable high-performance operation.

• Bypass/flybackcapacitorsonVBus, neartheconnector, are

recommended.

• At least a four-layer impedance controlled boards are

required to maintain signal quality.

• DPLUS and DMINUS trace lengths should be kept to within

2 mm of each other in length, with preferred length of 20–30

mm.

• Specify impedance targets (ask your board vendor what

they can achieve).

• Maintain a solid ground plane under the DPLUS and

DMINUS traces. Do not allow the plane to be split under

these traces.

• To control impedance, maintain trace widths and trace

spacing to within specifications.

• If possible, do not place any vias on the DPLUS or DMINUS

trace routing.

• Minimize stubs to minimize reflected signals.

• Connections between the USB connector shell and signal

ground must be done near the USB connector.

• Isolate the DPLUS and DMINUS traces from all other signal

traces by no less than 10 mm.

Note:

3. Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High-

Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

Document #: 38-08016 Rev. *H

Page 12 of 14

CY7C68000

mask on the top side also minimizes outgassing during the

solder reflow process.

13.0

Quad Flat Package No Leads (QFN)

Package Design Notes

For further information on this package design please refer to

the application note “Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology.” This application note

can be downloaded from AMKOR’s web site from the following

URL http://www.amkor.com/products/notes_papers/MLFApp

Note.pdf. The application note provides detailed information

on board mounting guidelines, soldering flow, rework process,

etc.

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good ther-

mal bond to the circuit board. A Copper (Cu) fill is to be de-

signed into the PCB as a thermal pad under the package. Heat

is transferred from the TX2 through the device’s metal paddle

on the bottom side of the package. Heat from here, is conduct-

ed to the PCB at the thermal pad. It is then conducted from the

thermal pad to the PCB inner ground plane by an array of via.

A via is a plated through hole in the PCB with a finished diam-

eter of 13 mil. The QFN’s metal die paddle must be soldered

to the PCB’s thermal pad. Solder mask is placed on the board

top side over each via to resist solder flow into the via. The

Figure 13-1 below displays a cross-sectional area underneath

the package. The cross section is of only one via. The solder

paste template needs to be designed to allow at least 50%

solder coverage. The thickness of the solder paste template

should be 5 mil. Cypress recommends that ’No Clean’, type 3

solder paste is used for mounting the part. Nitrogen purge is

recommended during reflow.

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

circuit board: Top Solder, PCB Dielectric, and

the Ground Plane

QFN to the circuit board ground plane.

Figure 13-1. Crosssection of the Area Underneath the QFN Package

Figure 13-2 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder).

Figure 13-2. Plot of the Solder Mask (White Area)

EZ-USB TX2 is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document

are the trademarks of their respective holders.

Document #: 38-08016 Rev. *H

Page 13 of 14

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY7C68000

Document History Page

Document Title: CY7C68000 TX2™ USB 2.0 UTMI Transceiver

Document Number: 38-08016

Orig. of

REV.

**

ECN NO. Issue Date Change

Description of Change

112019

113885

03/01/02

07/01/02

KKU

New data sheet

*A

Updated pinouts on BGA package, signal names.

Added timing diagrams.

*B

118521

11/18/02

KKU/

BHA

Added USB Logo.

Updated characterization data.

Changed from Preliminary to Final.

*C

*D

124507

126665

02/21/03

07/03/03

BHA

KKU

Changed ISB Suspend Current maximums.

Removed BGA package and added Rev C of QFN package drawing with PCB

layout Recommendations for the QFN package.

*E

*F

*G

*H

285634

301832

375694

448451

SEE ECN

KKU

TEH

Updated description on signals DataBus16_8, and D0-D15.

Updated data sheet format.

Removed Preliminary and changed block diagram on input to Digital Tx block;

was “UTMI Rx Data 8/16” changed to “UTMI Tx Data 8/16”

Added note to figure 11-2:

E-PAD maximum size 4.75 X 5.46 mm [187 x 215 mils] (width x length).

Updated Ordering information to include Pb-Free part numbers.

Document #: 38-08016 Rev. *H

Page 14 of 14


型号：	CY3683
厂家：	CYPRESS
描述：	TX2⑩ USB 2.0 UTMI Transceiver TX2 USB 2.0 UTMI收发器
文件：	总14页 (文件大小：334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY3683 [CYPRESS]

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