CDB4351 [CIRRUS]
192 kHz STEREO DAC WITH 2 Vrms LINE OUT; 192 kHz立体声DAC 2 Vrms的线路输出
| 型号： | CDB4351 |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 192 kHz STEREO DAC WITH 2 Vrms LINE OUT |
| 文件： | 总41页 (文件大小：1097K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4351
192 kHz Stereo DAC with 2 Vrms Line Out
Features
Description
The CS4351 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-em-
phasis, volume control, channel mixing, analog filtering,
and on-chip 2 Vrms line level driver. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature, high toler-
ance to clock jitter, and a minimal set of external
components.
z Multi-bit Delta-Sigma Modulator
z 24-Bit Conversion
z Up to 192 kHz Sample Rates
z 112 dB Dynamic Range
z -100 dB THD+N
z +3.3 V, +9 to 12 V, and VL Power Supplies
z 2 Vrms Output into 5 kΩ AC Load
z Digital Volume Control with Soft Ramp
– 119 dB Attenuation
These features are ideal for cost-sensitive, 2-channel
audio systems including DVD players, A/V receivers,
set-top boxes, digital TVs and VCRs, mini-component
systems, and mixing consoles.
– 1/2 dB Step Size
– Zero Crossing Click-Free Transitions
z ATAPI Mixing
z Low Clock Jitter Sensitivity
®
z Popguard Technology for Control of Clicks
and Pops
ORDERING INFORMATION
CS4351-CZ
-10 to 70 °C 20-pin TSSOP
CS4351-CZZ, Lead Free -10 to 70 °C 20-pin TSSOP
CDB4351
Evaluation Board
I
9 V to 12 V
1.8 V to 3.3V
3.3 V
Hardware or I2C/SPI
Control Data
Register/Hardware
Configuration
Reset
Amp
+
Filter
Interpolation
Filter with
Volume Control
Multibit
∆Σ Modulator
2 Vrms Line Level
Left Channel Output
DAC
DAC
PCM
Serial
Interface
Serial Audio Input
Interpolation
Filter with
Volume Control
2 Vrms Line Level
Right Channel
Output
Amp
+
Filter
Multibit
∆Σ Modulator
Auto Speed Mode
Detect
External
Mute
Control
Left and Right
Mute Controls
Internal Voltage
Reference
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Preliminary Product Information
Copyright © Cirrus Logic, Inc. 2004
Sep ‘04
DS566PP2
http://www.cirrus.com
(All Rights Reserved)
CS4351
Table 1. Revision History
Changes
Initial Release
Release
A1
Date
July 2003
2
A2
August 2003
Added I C/SPI switching characterics
A3
November 2003 removed “Confidential”, moved legal statement to last page
PP1
June 2004
Updated Legal.
Updated Analog Performance specifications (Typ is improved).
Consolidated speed mode performance for analog performance.
Updated Current Consumption specifications (Typ and Min/Max increased).
Updated PSRR (improved Typ performance for 60 Hz).
Reduced recommended VBIAS+ capacitor in Typical Connection Diagram (to
improve startup settling times).
Changed bit 0 (POPG) in register 07h to reserved (must always be 1).
PP2
Sep 2004
Update w/ lead-free device ordering info.
2
DS566PP2
CS4351
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................. 5
2. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 6
SPECIFIED OPERATING CONDITIONS................................................................................. 6
ABSOLUTE MAXIMUM RATINGS........................................................................................... 6
DAC ANALOG CHARACTERISTICS....................................................................................... 7
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .......................... 9
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................ 10
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE .......................................... 11
2
SWITCHING CHARACTERISTICS - CONTROL PORT - I C FORMAT................................ 12
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 13
DIGITAL CHARACTERISTICS............................................................................................... 14
POWER AND THERMAL CHARACTERISTICS .................................................................... 14
3. TYPICAL CONNECTION DIAGRAM ..................................................................................... 15
4. APPLICATIONS ..................................................................................................................... 16
4.1 Sample Rate Range/Operational Mode Detect ............................................................... 16
4.1.1 Auto-Detect Enabled ........................................................................................... 16
4.1.2 Auto-Detect Disabled .......................................................................................... 16
4.2 System Clocking .............................................................................................................. 17
4.3 Digital Interface Format ................................................................................................... 18
4.3.1 Stand-Alone Mode .............................................................................................. 18
4.3.2 Control Port Mode .............................................................................................. 18
4.4 De-Emphasis Control ...................................................................................................... 19
4.4.1 Stand-Alone Mode .............................................................................................. 19
4.4.2 Control Port Mode ............................................................................................... 19
4.5 Recommended Power-up Sequence ............................................................................... 20
4.5.1 Stand-Alone Mode .............................................................................................. 20
4.5.2 Control Port Mode ............................................................................................... 20
®
4.6 Popguard Transient Control .......................................................................................... 21
4.6.1 Power-up ............................................................................................................. 21
4.6.2 Power-down ........................................................................................................ 21
4.6.3 Discharge Time ................................................................................................... 21
4.7 Mute Control .................................................................................................................... 21
4.8 Grounding and Power Supply Arrangements .................................................................. 22
4.8.1 Capacitor Placement ........................................................................................... 22
4.9 Control Port Interface ...................................................................................................... 23
4.9.1 MAP Auto Increment ........................................................................................... 23
2
4.9.2 I C Mode ............................................................................................................. 23
2
4.9.2.1 I C Write ............................................................................................. 23
2
4.9.2.2 I C Read ............................................................................................. 23
4.9.3 SPI Mode ............................................................................................................ 24
4.9.3.1 SPI Write ............................................................................................. 24
4.10 Memory Address Pointer (MAP) ................................................................................ 26
5. REGISTER QUICK REFERENCE .......................................................................................... 26
6. REGISTER DESCRIPTION .................................................................................................... 27
7. PARAMETER DEFINITIONS .................................................................................................. 34
8. PACKAGE DIMENSIONS ..................................................................................................... 35
9. APPENDIX ............................................................................................................................ 36
DS566PP2
3
CS4351
LIST OF FIGURES
Figure 1. Serial Input Timing ....................................................................................................... 11
2
Figure 2. Control Port Timing - I C Format ................................................................................. 12
Figure 3. Control Port Timing - SPI Format (Write) ..................................................................... 13
Figure 4. Typical Connection Diagram ........................................................................................ 15
Figure 5. Left Justified up to 24-Bit Data ..................................................................................... 18
2
Figure 6. I S, up to 24-Bit Data ................................................................................................... 18
Figure 7. Right Justified Data ...................................................................................................... 18
Figure 8. De-Emphasis Curve ..................................................................................................... 19
Figure 9. Control Port Timing, I2C Mode ..................................................................................... 24
Figure 10. Control Port Timing, SPI mode .................................................................................... 25
Figure 11. De-Emphasis Curve ..................................................................................................... 28
Figure 12. ATAPI Block Diagram .................................................................................................. 29
Figure 13. Single Speed (fast) Stopband Rejection ...................................................................... 36
Figure 14. Single Speed (fast) Transition Band ............................................................................ 36
Figure 15. Single Speed (fast) Transition Band (detail) ................................................................ 36
Figure 16. Single Speed (fast) Passband Ripple .......................................................................... 36
Figure 17. Single Speed (slow) Stopband Rejection ..................................................................... 36
Figure 18. Single Speed (slow) Transition Band ........................................................................... 36
Figure 19. Single Speed (slow) Transition Band (detail) ............................................................... 37
Figure 20. Single Speed (slow) Passband Ripple ......................................................................... 37
Figure 21. Double Speed (fast) Stopband Rejection ..................................................................... 37
Figure 22. Double Speed (fast) Transition Band ........................................................................... 37
Figure 23. Double Speed (fast) Transition Band (detail) ............................................................... 37
Figure 24. Double Speed (fast) Passband Ripple ......................................................................... 37
Figure 25. Double Speed (slow) Stopband Rejection ................................................................... 38
Figure 26. Double Speed (slow) Transition Band .......................................................................... 38
Figure 27. Double Speed (slow) Transition Band (detail) .............................................................. 38
Figure 28. Double Speed (slow) Passband Ripple ........................................................................ 38
Figure 29. Quad Speed (fast) Stopband Rejection ....................................................................... 38
Figure 30. Quad Speed (fast) Transition Band .............................................................................. 38
Figure 31. Quad Speed (fast) Transition Band (detail) .................................................................. 39
Figure 32. Quad Speed (fast) Passband Ripple ............................................................................ 39
Figure 33. Quad Speed (slow) Stopband Rejection ...................................................................... 39
Figure 34. Quad Speed (slow) Transition Band ............................................................................ 39
Figure 35. Quad Speed (slow) Transition Band (detail) ................................................................ 39
Figure 36. Quad Speed (slow) Passband Ripple .......................................................................... 39
4
DS566PP2
CS4351
LIST OF TABLES
Table 1. Revision History ...............................................................................................................2
Table 2. CS4351 Auto-Detect .......................................................................................................16
Table 3. CS4351 Mode Select ......................................................................................................16
Table 4. Single-Speed Mode Standard Frequencies ....................................................................17
Table 5. Double-Speed Mode Standard Frequencies...................................................................17
Table 6. Quad-Speed Mode Standard Frequencies .....................................................................17
Table 7. Digital Interface Format - Stand-Alone Mode..................................................................18
Table 8. Digital Interface Formats.................................................................................................27
Table 9. ATAPI Decode ................................................................................................................29
Table 10. Example Digital Volume Settings..................................................................................31
DS566PP2
5
CS4351
1. PIN DESCRIPTION
20
19
18
1
SDIN
SCLK
LRCK
MCLK
VD
VL
2
AMUTEC
AOUTA
VA_H
GND
AOUTB
BMUTEC
VQ
3
4
17
16
15
14
13
12
5
6
GND
7
DIF1(SCL/CCLK)
DIF0(SDA/CDIN)
DEM(AD0/CS)
RST
8
9
VBIAS
VA
10
11
Pin Name
SDIN
#
1
2
3
Pin Description
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
Serial Clock (Input) - Serial clock for the serial audio interface.
SCLK
LRCK
Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
MCLK
VD
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Digital Power (Input) - Positive power supply for the digital section.
Ground (Input) - Ground reference.
4
5
GND
6
16
Reset (Input) - Powers down device and resets all internal resisters to their default settings when
enabled.
RST
10
VA
11 Low Voltage Analog Power (Input) - Positive power supply for the analog section.
Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.
VBIAS
VQ
12
13 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
17 High Voltage Analog Power (Input) - Positive power supply for the analog section.
VA_H
VL
Serial Audio Interface Power (Input) - Positive power for the serial audio interface
Mute Control (Output) - Control signal for optional mute circuit.
20
BMUTEC
AMUTEC
14
19
AOUTB
AOUTA
Analog Outputs (Output) - The full scale analog line output level is specified in the Analog Characteris-
tics table.
15
18
Control Port
Definitions
SCL/CCLK
SDA/CDIN
Serial Control Port Clock (Input) - Serial clock for the control port interface.
Serial Control Data (Input/Output) - Input/Output for I2C data. Input for SPI data.
7
8
Address Bit 0 / Chip Select (Input) - Chip address bit in I2C Mode. Control Port enable in SPI mode.
AD0/CS
9
Stand-Alone
Definitions
DIF0
DIF1
Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial
Clock, and Serial Audio Data.
8
7
DEM
9
De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for 44.1 kHz
sample rates
6
DS566PP2
CS4351
2. CHARACTERISTICS AND SPECIFICATIONS
(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Conditions.
Typical specifications are derived from performance measurements at T = 25 °C, VA_H = 12 V, VA = 3.3 V,
A
VD = 3.3 V.)
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
High Voltage Analog power
Symbol
Min
Typ
Max
Units
DC Power Supply
V
8.55
3.13
3.13
1.7
12
3.3
3.3
3.3
12.6
3.47
3.47
3.47
V
V
V
V
A_H
Low Voltage Analog power
Digital power
V
A
V
D
Interface power
V
L
Specified Temperature Range
TA
-10
-
70
°C
ABSOLUTE MAXIMUM RATINGS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
DC Power Supply
High Voltage Analog power
Low Voltage Analog power
Digital power
V
V
V
V
-0.3
-0.3
-0.3
-0.3
14
V
V
V
V
A_H
3.63
3.63
3.63
A
D
Interface power
L
Input Current, Any Pin Except Supplies
Digital Input Voltage
I
-
±10
mA
V
in
Digital Interface
V
-0.3
-55
-65
V + 0.4
IN-L
L
Ambient Operating Temperature (power applied)
Storage Temperature
T
125
150
°C
°C
A
T
stg
Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaran-
teed at these extremes.
DS566PP2
7
CS4351
DAC ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): input test sig-
nal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz)
Parameter
Symbol
Min
Typ
Max
Unit
All Speed Modes
Fs = 48, 96, and 192 kHz
Dynamic Range (Note 2) 24-bit unweighted
A-Weighted
99
102
-
-
109
112
95
-
-
-
-
dB
dB
dB
dB
16-bit unweighted
A-Weighted
98
Total Harmonic Distortion + Noise
24-bit
(Note 2) THD+N
-
-
-
-
-
-
-
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-100
-89
-49
-92
-75
-35
-90
-79
-39
-
-
-
dB
dB
dB
dB
dB
dB
16-bit
All Speed Modes
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation (1 kHz)
-
-
109
100
-
-
dB
dB
Notes: 1. One-half LSB of triangular PDF dither is added to data.
ANALOG CHARACTERISTICS (Continued)
Parameters
Analog Output - All Modes
Full Scale Output Voltage
Common Mode Voltage
Max DC Current draw from an AOUT pin
Max Current draw from VQ
Interchannel Gain Mismatch
Gain Drift
Symbol
Min
Typ
Max
Units
1.9
2.0
4
2.1
Vrms
Vdc
µA
µA
dB
V
-
-
-
Q
I
10
1
-
OUTmax
I
-
-
Qmax
-
0.1
100
50
-
-
-
-
ppm/°C
Ω
Output Impedance
Z
-
-
-
OUT
AC-Load Resistance
R
5
-
kΩ
pF
L
Load Capacitance
C
-
100
L
8
DS566PP2
CS4351
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (The
filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate
by multiplying the given characteristic by Fs.)
Fast Roll-Off
Parameter
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode - 48 kHz
Passband (Note 3)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.454
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
s
s
dB
dB
dB
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
De-emphasis Error (Note 5)
(Relative to 1 kHz)
-0.01
0.547
102
(Note 4)
-
-
-
-
-
-
-
-
-
9.4/Fs
-
-
-
-
-
±0.56/Fs
0
±0.23
±0.14
±0.09
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz
Passband (Note 3)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.430
.499
0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
-0.01
.583
80
-
-
(Note 4)
-
-
4.6/Fs
-
±0.03/Fs
0
-
-
s
s
-
Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz
Passband (Note 3)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.105
.490
0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
-0.01
.635
90
-
-
(Note 4)
-
-
4.7/Fs
-
±0.01/Fs
0
-
-
s
s
-
DS566PP2
9
CS4351
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (cont.)
Slow Roll-Off (Note 2)
Parameter
Single Speed Mode - 48 kHz
Min
Typ
Max
Unit
Passband (Note 3)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
0.417
0.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
s
s
dB
dB
dB
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
De-emphasis Error (Note 5)
(Relative to 1 kHz)
-0.01
.583
64
-
-
-
-
-
-
(Note 4)
-
-
-
6.5/Fs
-
-
-
-
-
±0.14/Fs
0
±0.23
±0.14
±0.09
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Double Speed Mode - 96 kHz
Passband (Note 3)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.296
.499
0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Total Group Delay (Fs = Output Sample Rate)
Intra-channel Phase Deviation
Inter-channel Phase Deviation
Quad Speed Mode - 192 kHz
Passband (Note 3)
-0.01
.792
70
-
-
(Note 4)
-
-
3.9/Fs
-
±0.01/Fs
0
-
-
s
s
-
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.104
.481
0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
Intra-channel Phase Deviation
Inter-channel Phase Deviation
-0.01
.868
75
(Note 4)
-
-
-
4.2/Fs
-
±0.01/Fs
0
-
-
s
s
-
Notes: 2. Slow Roll-off interpolation filter is only available in Control Port mode.
3. Response is clock dependent and will scale with Fs.
4. For Single Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
5. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-
Alone Mode.
6. Amplitude vs. Frequency plots of this data are available in “Appendix” on page 37.
10
DS566PP2
CS4351
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
Symbol
Min
1.024
45
Max
51.2
55
Units
MHz
%
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate (Manual selection)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
50
100
50
100
200
kHz
kHz
kHz
Input Sample Rate (Auto selection)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Fs
Fs
Fs
4
84
170
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle
40
20
20
60
-
%
ns
ns
-
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
t
sclkl
t
-
sclkh
sclkw
1
Single Speed Mode
Double Speed Mode
Quad Speed Mode
t
t
t
-
---------------------
(128)Fs
1
-
-
-
-
------------------
sclkw
sclkw
(64)Fs
2
-----------------
MCLK
20
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
t
-
-
-
-
ns
ns
ns
ns
slrd
t
20
20
20
slrs
t
sdlrs
t
sdh
LRCK
t
t
sclkh
slrs
t
slrd
t
sclkl
SCLK
t
t
sdh
sdlrs
SDATA
Figure 1. Serial Input Timing
DS566PP2
11
CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C = 20 pF)
L
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f
-
100
kHz
scl
RST Rising Edge to Start
t
500
4.7
4.0
4.7
4.0
4.7
0
-
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
irs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
t
-
buf
t
-
hdst
t
-
low
Clock High Time
t
-
high
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
t
-
sust
(Note 7)
t
-
hdd
t
250
-
-
1
sud
t , t
rc rc
Fall Time SCL and SDA
t , t
-
300
-
fc fc
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
t
4.7
300
susp
t
1000
ack
Notes: 7. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
R S T
t
irs
R e p e a te d
Stop
S ta rt
Stop
S ta rt
t
t
rd
fd
S D A
S C L
t
t
t
t
t
buf
t
high
hdst
fc
susp
hdst
lo w
t
t
t
t
t
t
sust
sud
ack
rc
hdd
2
Figure 2. Control Port Timing - I C Format
12
DS566PP2
CS4351
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VL, C = 20 pF)
L
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
f
-
6
MHz
sclk
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t
500
500
1.0
20
66
66
40
15
-
-
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
srs
(Note 8)
t
-
spi
t
-
csh
t
-
css
t
-
scl
sch
dsu
CCLK High Time
t
-
-
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
t
(Note 9)
(Note 10)
(Note 10)
t
-
dh
t
100
100
r2
t
-
f2
Notes: 8. t only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi
spi
9. Data must be held for sufficient time to bridge the transition time of CCLK.
10. For F < 1 MHz.
SCK
RST
t
t
srs
spi
CS
t
t
t
css
scl
sch
t
csh
CCLK
t
t
r2
f2
C DIN
t
t
dsu
dh
Figure 3. Control Port Timing - SPI Format (Write)
DS566PP2
13
CS4351
DIGITAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
V
V
V
2.0
1.7
0.65•V
-
-
-
-
-
-
V
V
V
High-Level Input Voltage
VL = 3.3 V
VL = 2.5 V
VL = 1.8 V
IH
IH
IH
L
V
V
V
-
-
-
-
-
-
0.8
0.7
0.35•V
V
V
V
Low-Level Input Voltage
VL = 3.3 V
VL = 2.5 V
VL = 1.8 V
IL
IL
IL
L
Input Leakage Current
I
-
-
-
-
-
-
±10
µA
pF
mA
V
in
Input Capacitance
8
2
-
-
-
-
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
V
VA_H
0
OH
V
V
OL
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
(Note 11)
normal operation, V
= 12 V
= 9 V
I
I
-
-
-
-
-
-
15
14
20
19
8
mA
mA
mA
mA
µA
A_H
A_H
A_H
V
A_H
V = 3.3 V
I
6
A
A
V = 3.3 V
I
21
26
400
-
D
D
Interface current (Note 12) V = 3.3 V
I
100
200
L
L
power-down state, all supplies (Note 13)
I
µA
pd
Power Dissipation (all supplies)
VA_H = 12 V
(Note 11)
normal operation
power-down (Note 13)
normal operation
-
-
-
-
270
1
216
1
354
mW
mW
mW
mW
-
285
-
VA_H = 9 V
power-down (Note 13)
Power Supply Rejection Ratio (Note 14)
(1 kHz) PSRR
(60 Hz)
-
-
60
60
-
-
dB
dB
Notes: 11. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are
based on highest FS and highest MCLK. Variance between speed modes is small.
12. I measured with no external loading on pin 8 (SDA).
L
13. Power down mode is defined as RES pin = Low with all clock and data lines held static.
14. Valid with the recommended capacitor values on VQ and V
diagram in Section 3.
as shown in the typical connection
BIAS
14
DS566PP2
CS4351
3. TYPICAL CONNECTION DIAGRAM
5.1Ω∗
+3.3 V
+3.3 V *
*Optional
+
+
10 µF
0.1 µF
0.1 µF
12
10 µF
*Remove this supply if
optional resistor is present.
The decoupling caps should
remain.
5
11
VA
3.3 µF
+
VD
VBIAS+
4
MCLK
3
2
1
17
Digital
Audio
Source
LRCK
VA_H
+9 V to +12 V
0.1 µF
+
SCLK
SDIN
10 µF
Optional Mute Circuit
19
18
AMUTEC
AOUTA
20
+1.8 V to VD
VL
576 k
412 k
Ω
Ω
560 Ω
0.1 µF
AOUTA
+
2.2 nF*
CS4351
3.3 µF
10 k
Ω
Optional Mute Circuit
14
BMUTEC
AOUTB
576 k
412 k
Ω
Ω
10
7
RST
560 Ω
15
µ C/
Mode
DIF1(SCL/CCLK)
DIF0(SDA/CDIN)
DEM(AD0/CS)
AOUTA
+
2.2 nF*
8
9
3.3 µF
Configuration
10k
Ω
*Shown value is
for fc=130kHz
13
VQ
3.3 µF
+
GND
6
GND
15
Figure 4. Typical Connection Diagram
DS566PP2
15
CS4351
4. APPLICATIONS
4.1 Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode will
depend on whether the Auto-Detect Defeat bit is enabled/disabled.
4.1.1 Auto-Detect Enabled
The Auto-Detect feature is enabled by default. In this state, the CS4351 will auto-detect the correct
mode when the input sample rate (F ), defined by the LRCK frequency, falls within one of the rang-
s
es illustrated in Table 2. Sample rates outside the specified range for each mode are not supported.
Input Sample Rate (F )
MODE
S
4 kHz - 50 kHz
84 kHz - 100 kHz
170 kHz - 200 kHz
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Table 2. CS4351 Auto-Detect
4.1.2 Auto-Detect Disabled
The Auto-Detect feature can be defeated only by the format bits in the control port register 02h. In
this state, the CS4351 will not auto-detect the correct mode based on the input sample rate (F ). The
s
operational mode must then be set manually according to one of the ranges illustrated in Table 3.
Please refer to section 6.2.3 for implementation details. Sample rates outside the specified range
for each mode are not supported. In stand-alone mode it is not possible to disable auto-detect of
sample rates.
FM1
FM0
Input Sample Rate (F )
MODE
S
0
0
1
1
0
1
0
1
Auto speed mode detect
4 kHz - 50 kHz
50 kHz - 100 kHz
100 kHz - 200 kHz
Auto
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Table 3. CS4351 Mode Select
16
DS566PP2
CS4351
4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)
clocks. The left/right clock, defined also as the input sample rate (F ), must be synchronously derived from
s
the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-
dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.
Refer to section 4.3 for the required SCLK timing associated with the selected Digital Interface Format,
and SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE, page 11 for the maximum allowed
clock frequencies.
Sample Rate
(kHz)
MCLK (MHz)
256x
384x
512x
768x
1024x
32.7680
45.1584
49.1520
1152x
36.8640
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
Table 4. Single-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
128x
192x
256x
384x
512x
64
88.2
96
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
24.5760
33.8688
36.8640
32.7680
45.1584
49.1520
Table 5. Double-Speed Mode Standard Frequencies
Sample Rate
(kHz)
MCLK (MHz)
64x
96x
128x
192x
256x
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Table 6. Quad-Speed Mode Standard Frequencies
= Denotes clock modes which are NOT auto detected
DS566PP2
17
CS4351
4.3 Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated
in Table 7, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.
4.3.1 Stand-Alone Mode
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required rela-
tionship between the LRCK, SCLK and SDIN, see Figures 5-7. For all formats, SDIN is valid on
the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2,
and 48 cycles per LRCK period in format 3.
DIF0 DIF1
DESCRIPTION
I S, up to 24-bit Data
Left Justified, up to 24-bit Data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
FORMAT
FIGURE
2
0
0
1
1
0
1
0
1
0
1
2
3
6
5
7
7
Table 7. Digital Interface Format - Stand-Alone Mode
4.3.2
Control Port Mode
The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see
section 6.2.1) . For an illustration of the required relationship between LRCK, SCLK and SDIN,
see Figures 5-7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have
at least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and
36 cycles in format 5.
Left Channel
Right Channel
LRCK
SCLK
LSB
LSB
MSB
-1 -2 -3 -4
MSB
SDIN
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
Figure 5. Left Justified up to 24-Bit Data
Left Channel
Right Channel
+5 +4 +3 +2 +1
Right Channel
LRCK
SCLK
LSB
LSB
+5 +4 +3 +2 +1
MSB
-1 -2 -3 -4
MSB
SDIN
-1 -2 -3 -4 -5
2
Figure 6. I S, up to 24-Bit Data
LRCK
SCLK
Left Channel
MSB
LSB
MSB
+1 +2 +3 +4 +5
-7 -6 -5 -4 -3 -2 -1
MSB
LSB
SDIN
+1 +2 +3 +4
+5
-7 -6 -5 -4 -3 -2 -1
Figure 7. Right Justified Data
18
DS566PP2
CS4351
4.4 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 8 shows the de-emphasis curve for F equal to
s
44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sam-
ple rate, Fs.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 8. De-Emphasis Curve
Notes: De-emphasis is only available in Single-Speed Mode.
4.4.1 Stand-Alone Mode
When pulled to VL the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND
the DEM pin turns off the de-emphasis filter.
4.4.2 Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section
6.2.2 for the desired de-emphasis control.
DS566PP2
19
CS4351
4.5 Recommended Power-up Sequence
4.5.1 Stand-Alone Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and
left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2. In this state,
the control port is reset to its default settings, VQ will remain low, and VBIAS will be connected
to VA.
2. Bring RST high. The device will remain in a low power state with VQ low and will initiate the
Stand-Alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode
(1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2 Control Port Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to
the appropriate frequencies, as discussed in section 4.2. In this state, the control port is reset to its
default settings, VQ will remain low, and VBIAS will be connected to VA.
2. Bring RST high. The device will remain in a low power state with VQ low.
3. Perform a control port write to the CP_EN bit prior to the completion of approximately 512
LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK
cycles in Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN
bit set to 1.
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs
when the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description
of power-up timing.
20
DS566PP2
CS4351
®
4.6 Popguard Transient Control
The CS4351 uses a novel technique to minimize the effects of output transients during power-up and pow-
er-down. This technology, when used with external DC-blocking capacitors in series with the audio out-
puts, minimizes the audio transients commonly produced by single-ended single-supply converters. It is
activated inside the DAC when the RST pin is toggled and requires no other external control, aside from
choosing the appropriate DC-blocking capacitors.
4.6.1 Power-up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to
GND. Following a delay of approximately 1000 sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000 LRCK cycles later, the outputs reach V and audio
Q
output begins. This gradual voltage ramping allows time for the external DC-blocking capacitors
to charge to the quiescent voltage, minimizing audible power-up transients.
4.6.2 Power-down
To prevent audible transients at power-down, the device must first enter its power-down state.
When this occurs, audio output ceases and the internal output buffers are disconnected from AOU-
TA and AOUTB. In their place, a soft-start current sink is substituted which allows the DC-block-
ing capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be
turned off and the system is ready for the next power-on.
4.6.3 Discharge Time
To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully dis-
charge before turning on the power or exiting the power-down state. If full discharge does not oc-
cur, a transient will occur when the audio outputs are initially clamped to GND. The time that the
device must remain in the power-down state is related to the value of the DC-blocking capacitance
and the output load. For example, with a 3.3 µF capacitor, the minimum power-down time will be
approximately 0.4 seconds.
4.7 Mute Control
The Mute Control pins go active during power-up initialization, reset, muting (see section 6.4.3), or if the
MCLK to LRCK ratio is incorrect. These pins are intended to be used as control for external mute circuits
to prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system de-
signer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute cir-
cuit. Please see “Typical Connection Diagram” on page 15 for a suggested mute circuit for single supply
systems. This FET circuit must be placed in series after the RC filter, otherwise noise may occur during
muting conditions. Further ESD protection will need to be taken into consideration for the FET used. If
dual supplies are available, the BJT mute circuit from Figure 12 in the CS4398 datasheet (active Low) may
be used.
DS566PP2
21
CS4351
4.8 Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4351 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 4 shows the recommended power
arrangements, with VA_H, VA, VD, and VL connected to clean supplies. If the ground planes are split
between digital ground and analog ground, the GND pins of the CS4351 should be connected to the analog
ground plane.
All signals, especially clocks, should be kept away from the VBIAS and VQ pins in order to avoid unwant-
ed coupling into the DAC.
4.8.1 Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceram-
ic capacitor being the closest. To further minimize impedance, these capacitors should be located
on the same layer as the DAC. If desired, all supply pins may be connected to the same supply, but
a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4351 evaluation board demonstrates the optimum layout and power supply arrangements.
22
DS566PP2
CS4351
4.9 Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interference
problems, the control port pins should remain static if no operation is required.
2
The control port operates in one of two modes: I C or SPI.
4.9.1 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit
2
(also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I C writes
or reads and SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written,
allowing block reads or writes of successive registers.
2
4.9.2 I C Mode
2
In the I C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by
the serial control port clock, SCL (see Figure 9 for the clock to data relationship). There is no CS
pin. Pin AD0 enables the user to alter the chip address (100110[AD0][R/W]) and should be tied to
VL or GND as required, before powering up the device. If the device ever detects a high to low
transition on the AD0/CS pin after power-up, SPI mode will be selected.
2
4.9.2.1 I C Write
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in section 7.
2
1) Initiate a START condition to the I C bus followed by the address byte. The upper 6 bits
must be 100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be
0. The eighth bit of the address byte is the R/W bit.
2) Wait for an acknowledge (ACK) from the part, then write to the memory address pointer,
MAP. This byte points to the register to be written.
3) Wait for an acknowledge (ACK) from the part, then write the desired data to the register
pointed to by the MAP.
4) If the INCR bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired
registers are written, then initiate a STOP condition to the bus.
2
5) If the INCR bit is set to 0 and further I C writes to other registers are desired, it is necessary
to initiate a repeated START condition and follow the procedure detailed from step 1. If no fur-
ther writes to other registers are desired, initiate a STOP condition to the bus.
2
4.9.2.2 I C Read
To read from the device, follow the procedure below while adhering to the control port Switch-
ing Specifications.
DS566PP2
23
CS4351
2
1) Initiate a START condition to the I C bus followed by the address byte. The upper 6 bits
must be 100110. The seventh bit must match the setting of the AD0 pin, and the eighth must be
1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of the
register pointed to by the MAP. The MAP register will contain the address of the last register
2
written to the MAP, or the default address (see section 4.10.2) if an I C read is the first opera-
tion performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue an
ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired reg-
isters are read, then initiate a STOP condition to the bus.
2
5) If the INCR bit is set to 0 and further I C reads from other registers are desired, it is necessary
to initiate a repeated START condition and follow the procedure detailed from steps 1 and 2
2
2
from the I C Write instructions followed by step 1 of the I C Read section. If no further reads
from other registers are desired, initiate a STOP condition to the bus.
NOTE
DATA
1-8
DATA
1-8
100110
R/W
ACK
ACK
ACK
SDA
SCL
AD0
Start
Stop
NOTE: If operation is a write, this byte contains the Memory Address Pointer, MAP. If
operation is a read, this byte contains the data of the register pointed to by the MAP.
2
Figure 9. Control Port Timing, I C Mode
4.9.3 SPI Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock,
CCLK (see Figure 10 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip
select signal and is used to control SPI writes to the control port. When the device detects a high to
low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs
and data is clocked in on the rising edge of CCLK.
4.9.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in Section 7.
1) Bring CS low.
2) The address byte on the CDIN pin must then be 10011000.
3) Write to the memory address pointer, MAP. This byte points to the register to be written.
24
DS566PP2
CS4351
4) Write the desired data to the register pointed to by the MAP.
5) If the INCR bit (see section 4.9.1) is set to 1, repeat the previous step until all the desired
registers are written, then bring CS high.
6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary
to bring CS high, and follow the procedure detailed from step 1. If no further writes to other
registers are desired, bring CS high.
CS
CCLK
CHIP
ADDRESS
MAP
DATA
1001100
LSB
CDIN
MSB
R/W
byte 1
byte n
MAP = Memory Address Pointer
Figure 10. Control Port Timing, SPI mode
DS566PP2
25
CS4351
4.10 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
4.10.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
4.10.2 MAP (MEMORY ADDRESS POINTER)
Default = ‘0000’
26
DS566PP2
CS4351
5. REGISTER QUICK REFERENCE
Addr
Function
7
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
1h Chip ID
PART4
1
Reserved
0
default
2h Mode Control
default
DIF2
0
DIF0
0
DEM1
0
DEM0
0
FM1
0
FM0
0
DIF1
0
3h Volume, Mixing,
and Inversion
Control
VOLB=A INVERTA INVERTB Reserved
ATAPI3
ATAPI2
ATAPI1
ATAPI0
0
0
0
0
1
0
0
1
default
4h Mute Control
AMUTE
Reserved MUTEC
A=B
MUTE_A
MUTE_B Reserved Reserved Reserved
1
0
0
0
0
0
0
0
default
5h Channel A Volume
Control
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
default
6h Channel B Volume
Control
VOL7
VOL6
VOL5
VOL4
VOL3
VOL2
VOL1
VOL0
0
0
0
0
0
0
0
0
default
7h Ramp and Filter
Control
SZC1
SZC0
RMP_UP RMP_DN
Reserved FILT_SEL Reserved Reserved
1
PDN
1
0
CPEN
0
1
1
0
0
0
1
default
8h Misc. Control
default
FREEZE Reserved
Reserved Reserved Reserved Reserved
0
0
0
0
0
0
DS566PP2
27
CS4351
6. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
6.1
Chip ID - Register 01h
7
6
5
PART2
1
4
PART1
1
3
PART0
1
2
REV2
-
1
REV1
-
0
REV0
-
PART4
1
PART3
1
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11111b and the remaining
Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
6.2
Mode Control 1 - Register 02h
7
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
Reserved
0
6.2.1 DIGITAL INTERFACE FORMAT (DIF2:0) BITS 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 5-7.
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5
6
7
7
7
7
Left Justified, up to 24-bit data
I S, up to 24-bit data
0 (Default)
2
1
2
3
4
5
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
Table 8. Digital Interface Formats
28
DS566PP2
CS4351
6.2.2 DE-EMPHASIS CONTROL (DEM1:0) BITS 3-2.
Gain
dB
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
T1=50 µs
0dB
T2 = 15 µs
Frequency
-10dB
Function:
Selects the appropriate digital filter to maintain the stan-
dard 15 µs/50 µs digital de-emphasis filter response at
32, 44.1 or 48 kHz sample rates. (see Figure 11)
F1
3.183 kHz
F2
10.61 kHz
Figure 11. De-Emphasis Curve
Note: De-emphasis is only available in Single Speed Mode
6.2.3 FUNCTIONAL MODE (FM) BITS 1-0
Default = 00
00 - Auto speed mode detect
01 - Single-Speed Mode (4 to 50 kHz sample rates)
10 - Double-Speed Mode (50 to 100 kHz sample rates)
11 - Quad-Speed Mode (100 to 200 kHz sample rates)
Function:
Selects the required range of input sample rates or DSD Mode.
6.3
Volume Mixing and Inversion Control - Register 03h
B7
VOLB=A
0
B6
INVERT A
0
B5
INVERT B
0
B4
Reserved
0
B3
ATAPI3
1
B2
ATAPI2
0
B1
ATAPI1
0
B0
ATAPI0
1
6.3.1 CHANNEL A VOLUME = CHANNEL B VOLUME (VOLB=A) BIT 7
Function:
When set to 0 (default) the AOUTA and AOUTB volume levels are independently controlled by the A and
the B Channel Volume Control Bytes.
When set to 1 the volume on both AOUTA and AOUTB are determined by the A Channel Attenuation and
Volume Control Bytes, and the B Channel Bytes are ignored.
6.3.2 INVERT SIGNAL POLARITY (INVERT_A) BIT 6
Function:
When set to 1, this bit inverts the signal polarity of channel A.
When set to 0 (default), this function is disabled.
DS566PP2
29
CS4351
6.3.3 INVERT SIGNAL POLARITY (INVERT_B) BIT 5
Function:
When set to 1, this bit inverts the signal polarity of channel B.
When set to 0 (default), this function is disabled.
6.3.4 ATAPI CHANNEL MIXING AND MUTING (ATAPI3:0) BITS 3-0
Default = 1001 - AOUTA=aL, AOUTB=bR (Stereo)
Function:
The CS4351 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Ta-
ble 9 and Figure 12 for additional information.
A Channel
Volume
Control
Left Channel
Audio Data
MUTE
AoutA
Σ
Σ
B Channel
Volume
Control
Right Channel
Audio Data
MUTE
AoutB
Figure 12. ATAPI Block Diagram
ATAPI3 ATAPI2 ATAPI1 ATAPI0
AOUTA
MUTE
MUTE
MUTE
MUTE
aR
AOUTB
MUTE
bR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
bL
b[(L+R)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
bL
b[(L+R)/2]
Table 9. ATAPI Decode
30
DS566PP2
CS4351
6.4
Mute Control - Register 04h
7
6
Reserved
0
5
4
MUTE_A
0
3
MUTE_B
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
AMUTE
1
MUTEC A=B
0
6.4.1 AUTO-MUTE (AMUTE) BIT 7
Function:
When set to 1 (default) the Digital-to-Analog converter output will mute following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.
Detection and muting is done independently for each channel. The quiescent voltage on the output will
be retained and the Mute Control pin will go active during the mute period.
When set to 0 this function is disabled
6.4.2 AMUTEC = BMUTEC (MUTEC A=B) BIT 5
Function:
When set to 0 (default) the AMUTEC and BMUTEC pins operate independently.
When set to 1, the individual controls for AMUTEC and BMUTEC are internally connected through an
AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC pins will go active only
when the requirements for both AMUTEC and BMUTEC are valid.
6.4.3 A CHANNEL MUTE (MUTE_A) BIT 4
B CHANNEL MUTE (MUTE_B) BIT 3
Function:
When set to 1, the Digital-to-Analog converter output will mute. The quiescent voltage on the output will
be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero Cross
bits in the Volume and Mixing Control register. The corresponding MUTEC pin will go active following any
ramping due to the soft and zero cross function.
When set to 0 (default) this function is disabled.
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31
CS4351
6.5
Channel A Volume Control - Register 05h
Channel B Volume Control - Register 06h
7
VOL7
0
6
VOL6
0
5
VOL5
0
4
VOL4
0
3
VOL3
0
2
VOL2
0
1
VOL1
0
0
VOL0
0
6.5.1 DIGITAL VOLUME CONTROL (VOL7:0) BITS 7-0
Default = 00h (0 dB)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1/2 dB increments
from 0 to -127.5 dB. Volume settings are decoded as shown in Table 10. The volume changes are im-
plemented as dictated by the Soft and Zero Cross bits in the Power and Muting Control register.
The actual attenuation is determined by taking the decimal value of the volume register and multiplying
by 6.02/12.
Binary Code
00000000
00000001
00000110
11111111
Decimal Value
Volume Setting
0 dB
0
1
6
-0.5 dB
-3.0 dB
-127.5 dB
255
Table 10. Example Digital Volume Settings
6.6
Ramp and Filter Control - Register 07h
7
SZC1
1
6
SZC0
0
5
RMP_UP
1
4
RMP_DN
1
3
Reserved
0
2
FILT_SEL
0
1
Reserved
0
0
Reserved
1
6.6.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC1:0) BITS 7-6
Default = 10
SZC1 SZC0
Description
Immediate Change
Zero Cross
0
0
1
1
0
1
0
1
Soft Ramp
Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-
out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal
32
DS566PP2
CS4351
does not encounter a zero crossing. The zero cross function is independently monitored and implemented
for each channel.
Soft Ramp PCM
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp and Zero Cross
Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
6.6.2 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP) BIT 5
Function:
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after a
LRCK/MCLK ratio change or error, and after changing the Functional Mode. This un-mute is affected,
similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note: for best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
6.6.3 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN) BIT 4
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note: for best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
6.6.4 INTERPOLATION FILTER SELECT (FILT_SEL) BIT 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the “Combined Interpolation & On-chip Analog Filter Re-
sponse” on page 9, and response plots can be found in figures 15 to 36.
DS566PP2
33
CS4351
6.7
Misc Control - Register 08h
7
PDN
1
6
CPEN
0
5
FREEZE
0
4
Reserved
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
6.7.1 POWER DOWN (PDN) BIT 7
Function:
When set to 1 (default) the entire device will enter a low-power state and the contents of the control reg-
isters will be retained. The power-down bit defaults to ‘1’ on power-up and must be disabled before normal
operation in Control Port mode can occur. This bit is ignored if CPEN is not set.
6.7.2 CONTROL PORT ENABLE (CPEN) BIT 6
Function:
This bit is set to 0 by default, allowing the device to power-up in Stand-Alone Mode. Control Port Mode
can be accessed by setting this bit to 1. This will allow operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode.
6.7.3 FREEZE CONTROLS (FREEZE) BIT 5
Function:
When set to 1, this function allows modifications to be made to the registers without the changes taking
effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect
simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
When set to 0 (default), register changes take effect immediately.
34
DS566PP2
CS4351
7. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Intra-channel Phase Deviation
The deviation from linear phase within a given channel.
Inter-channel Phase Deviation
The difference in phase between channels.
DS566PP2
35
CS4351
8. PACKAGE DIMENSIONS
20L TSSOP (4.4 mm BODY) PACKAGE DRAWING
N
D
E11
A2
A
E
∝
A1
b2
e
L
END VIEW
SEATING
PLANE
SIDE VIEW
1
2 3
TOP VIEW
INCHES
MILLIMETERS
NOTE
DIM
A
A1
A2
b
D
E
E1
e
L
MIN
NOM
--
MAX
0.043
0.006
0.037
0.012
0.259
0.256
0.177
0.026
0.028
8°
MIN
--
NOM
--
--
0.90
0.245
6.50
6.40
4.40
--
MAX
1.10
0.15
0.95
0.30
6.60
6.50
4.50
0.65
0.70
8°
--
0.002
0.03346
0.00748
0.252
0.248
0.169
--
0.004
0.0354
0.0096
0.256
0.2519
0.1732
--
0.05
0.85
0.19
6.40
6.30
4.30
--
2,3
1
1
0.020
0°
0.024
4°
0.50
0°
0.60
4°
∝
JEDEC #: MO-153
Controlling Dimension is Millimeters.
Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold
mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per
side.
2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be
0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not
reduce dimension “b” by more than 0.07 mm at least material condition.
3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
Parameters
Package Thermal Resistance
Symbol
Min
Typ
Max
Units
20L TSSOP
θ
-
72
-
°C/Watt
JA
36
DS566PP2
CS4351
9. APPENDIX
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−100
−120
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 13. Single Speed (fast) Stopband Rejection
Figure 14. Single Speed (fast) Transition Band
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.02
0.015
0.01
0.005
0
−0.005
−0.01
−0.015
−0.02
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 15. Single Speed (fast) Transition Band (detail)
Figure 16. Single Speed (fast) Passband Ripple
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 17. Single Speed (slow) Stopband Rejection
DS566PP2
Figure 18. Single Speed (slow) Transition Band
37
CS4351
0.02
0.015
0.01
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.005
0
−0.005
−0.01
−0.015
−0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 19. Single Speed (slow) Transition Band (detail)
Figure 20. Single Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 21. Double Speed (fast) Stopband Rejection
Figure 22. Double Speed (fast) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 23. Double Speed (fast) Transition Band (detail)
Figure 24. Double Speed (fast) Passband Ripple
38
DS566PP2
CS4351
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 26. Double Speed (slow) Transition Band
Figure 25. Double Speed (slow) Stopband Rejection
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 27. Double Speed (slow) Transition Band (detail)
Figure 28. Double Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 29. Quad Speed (fast) Stopband Rejection
DS566PP2
Figure 30. Quad Speed (fast) Transition Band
39
CS4351
0
0.2
0.15
0.1
1
2
3
0.05
0
4
5
6
0.05
7
0.1
0.15
0.2
8
9
10
0
0.05
0.1
0.15
0.2
0.25
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 31. Quad Speed (fast) Transition Band (detail)
Figure 32. Quad Speed (fast) Passband Ripple
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 33. Quad Speed (slow) Stopband Rejection
Figure 34. Quad Speed (slow) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 35. Quad Speed (slow) Transition Band (detail)
Figure 36. Quad Speed (slow) Passband Ripple
40
DS566PP2
CS4351
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic,
Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change
without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of
third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here-
in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM-
ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may
be trademarks or service marks of their respective owners.
I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies
conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
DS566PP2
41
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