CDB4382 [CIRRUS]
114 dB, 192 kHz 8-Channel D/A Converter; 114分贝192千赫8声道D / A转换器型号: | CDB4382 |
厂家: | CIRRUS LOGIC |
描述: | 114 dB, 192 kHz 8-Channel D/A Converter |
文件: | 总42页 (文件大小:985K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CS4382
114 dB, 192 kHz 8-Channel D/A Converter
Features
Description
The CS4382 is a complete 8-channel digital-to-analog
system including digital interpolation, fifth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control and analog filtering. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
z 24-bit Conversion
z Up to 192 kHz Sample Rates
z 114 dB Dynamic Range
z -100 dB THD+N
z Supports PCM and DSD Data Formats
z Selectable Digital Filters
z Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-free Transitions
z Dedicated DSD inputs
z Low Clock Jitter Sensitivity
The CS4382 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players,
SACD players, A/V receivers, digital TV’s, mixing con-
soles, effects processors, and automotive audio
systems.
z Simultaneous Support for Two Synchronous
Sample Rates for DVD Audio
z µC or Stand-alone Operation
ORDERING INFORMATION
CS4382-KQZ, Lead Free -10 to 70 °C
48-pin LQFP
CDB4382
Evaluation Board
I
S D A /C D IN (M 2) A D 0/C S (M 0)
D S D _S C LK (M 3)
S C L/C C LK (M 1)
V LC
M U T E C 1
M U TE C 234
R S T
V LS
C ontrol P ort(S tand-A lone M ode S elect)
E x t e r n a l
M u t e C o n t r o l
A O U T A 1+
A O U T A 1-
V o l u m e C o n t r o l
M i x e r
I n t e r p o la t i o n F i lt e r
∆ Σ
A n a lo g F i lt e r
D A C
1
S C L K
L R
A O U T B 1+
A O U T B 1-
1
C K
I n t e r p o la t i o n F i lt e r
I n t e r p o la t i o n F i lt e r
V o l u m e C o n t r o l
∆ Σ
∆ Σ
A n a lo g F i lt e r
A n a lo g F i lt e r
D A C
D A C
S C L K 2
L R C K 2
S D I N 1
A O U T A 2+
A O U T A 2-
V o l u m e C o n t r o l
M i x e r
A O U T B 2+
A O U T B 2-
S D
S D
I
I
N 2
N 3
I n t e r p o la t i o n F i lt e r
I n t e r p o la t i o n F i lt e r
V o l u m e C o n t r o l
∆ Σ
∆ Σ
A n a lo g F i lt e r
A n a lo g F i lt e r
D A C
D A C
A O U T A 3+
A O U T A 3-
V o l u m e C o n t r o l
M i x e r
S D I N 4
A O U T B 3+
A O U T B 3-
I n t e r p o la t i o n F i lt e r
I n t e r p o la t i o n F i lt e r
V o l u m e C o n t r o l
∆ Σ
∆ Σ
A n a lo g F i lt e r
A n a lo g F i lt e r
D A C
D A C
M C L K
A O U T A 4+
A O U T A 4-
V o l u m e C o n t r o l
M i x e r
2
÷
A O U T B 4+
A O U T B 4-
8
∆ Σ
D A C
I n t e r p o la t i o n F i lt e r
V o l u m e C o n t r o l
A n a lo g F i lt e r
D S D xx
V Q
F ILT +
V A
G N D
V D
G N D
Copyright © Cirrus Logic, Inc. 2004
NOV ‘04
DS514F1
http://www.cirrus.com
(All Rights Reserved)
CS4382
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
ANALOG CHARACTERISTICS................................................................................................ 4
POWER AND THERMAL CHARACTERISTICS....................................................................... 5
ANALOG FILTER RESPONSE................................................................................................. 6
DIGITAL CHARACTERISTICS................................................................................................. 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 7
RECOMMENDED OPERATING CONDITIONS ....................................................................... 7
SWITCHING CHARACTERISTICS .......................................................................................... 8
DSD - SWITCHING CHARACTERISTICS................................................................................ 9
2
SWITCHING CHARACTERISTICS - CONTROL PORT - I C FORMAT................................ 10
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT............................ 11
2. REGISTER QUICK REFERENCE .......................................................................................... 14
3. REGISTER DESCRIPTION .................................................................................................... 15
4. PIN DESCRIPTION ................................................................................................................. 24
5. APPLICATIONS ...................................................................................................................... 27
5.1 Grounding and Power Supply Decoupling ....................................................................... 27
5.2 Oversampling Modes ....................................................................................................... 27
5.3 Recommended Power-up Sequence ............................................................................... 27
5.4 Analog Output and Filtering ............................................................................................. 27
5.5 Interpolation Filter ............................................................................................................ 27
5.6 Clock Source Selection .................................................................................................... 28
5.7 Using DSD mode ............................................................................................................. 28
6. CONTROL PORT INTERFACE .............................................................................................. 29
6.1 Enabling the Control Port ................................................................................................. 29
6.2 Format Selection .............................................................................................................. 29
2
6.3 I C Format ....................................................................................................................... 29
2
6.3.1 Writing in I C Format ........................................................................................... 29
2
6.3.2 Reading in I C Format ........................................................................................ 29
6.4 SPI Format ....................................................................................................................... 30
6.4.1 Writing in SPI ...................................................................................................... 30
6.5 Memory Address Pointer (MAP)
................................................................................. 31
7. PARAMETER DEFINITIONS .................................................................................................. 39
8. REFERENCES ........................................................................................................................ 40
9. PACKAGE DIMENSIONS ....................................................................................................... 41
LIST OF FIGURES
Figure 1. Serial Mode Input Timing ................................................................................................. 8
Figure 2. Direct Stream Digital - Serial Audio Input Timing............................................................. 9
2
Figure 3. Control Port Timing - I C Format ................................................................................... 10
Figure 4. Control Port Timing - SPI Format................................................................................... 11
Figure 5. Typical Connection Diagram Control Port...................................................................... 12
Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13
2
Figure 7. Control Port Timing, I C Format..................................................................................... 30
Figure 8. Control Port Timing, SPI Format.................................................................................... 30
Figure 9. Single Speed (fast) Stopband Rejection ........................................................................ 32
Figure 10. Single Speed (fast) Transition Band ............................................................................ 32
Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 32
Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 32
Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 32
Figure 14. Single Speed (slow) Transition Band........................................................................... 32
Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 33
Figure 16. Single Speed (slow) Passband Ripple......................................................................... 33
2
DS514F1
CS4382
Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 33
Figure 18. Double Speed (fast) Transition Band........................................................................... 33
Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 33
Figure 20. Double Speed (fast) Passband Ripple......................................................................... 33
Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 34
Figure 22. Double Speed (slow) Transition Band ......................................................................... 34
Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 34
Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 34
Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 34
Figure 26. Quad Speed (fast) Transition Band ............................................................................. 34
Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 35
Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 35
Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 35
Figure 30. Quad Speed (slow) Transition Band............................................................................ 35
Figure 31. Quad Speed (slow) Transition Band (detail)................................................................ 35
Figure 32. Quad Speed (slow) Passband Ripple.......................................................................... 35
Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 36
2
Figure 34. Format 1 - I S up to 24-bit Data................................................................................... 36
Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 36
Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 36
Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 37
Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 37
Figure 39. De-Emphasis Curve..................................................................................................... 37
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)................................... 37
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4).................................................. 38
Figure 42. Recommended Output Filter........................................................................................ 38
LIST OF TABLES
Table 1. Digital Interface Formats - PCM Mode............................................................................ 16
Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16
Table 3. ATAPI Decode ................................................................................................................ 21
Table 4. Example Digital Volume Settings.................................................................................... 22
Table 5. Common Clock Frequencies........................................................................................... 26
Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26
Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................... 26
Table 9. Revision History ............................................................................................................. 42
DS514F1
3
CS4382
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth
10 Hz to 20 kHz, unless otherwise specified; Test load R = 3 kΩ, C = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5)
L
L
For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;
For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).
Parameters
Symbol
Min
Typ
Max
Unit
CS4382-KQZ Dynamic Performance - All PCM modes and DSD (Note 1)
Specified Temperature Range
Dynamic Range (Note 2)
TA
-10
-
70
°C
24-bit unweighted
A-Weighted
16-bit unweighted
(Note 3) A-Weighted
105
108
-
-
111
114
94
-
-
-
-
dB
dB
dB
dB
97
Total Harmonic Distortion + Noise
(Note 2) THD+N
0 dB
24-bit
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-94
dB
dB
dB
dB
dB
dB
-20 dB
-60 dB
0 dB
-20 dB
-
-
-
-
-
16-bit
(Note 3)
-60 dB
Idle Channel Noise / Signal-to-noise ratio
Interchannel Isolation
-
-
114
90
-
-
dB
dB
(1 kHz)
Notes: 1. CS4382-KQZ parts are tested at 25 °C.
2. One-half LSB of triangular PDF dither is added to data.
3. Performance limited by 16-bit quantization noise.
4
DS514F1
CS4382
ANALOG CHARACTERISTICS (Continued)
Parameters
Symbol
Min
86% V
Typ
91% V
Max
96% V
Units
Analog Output - All PCM modes and DSD
Full Scale Differential Output Voltage (Note 4)
Quiescent Voltage
V
Vpp
VDC
µA
FS
A
A
A
V
-
-
50% V
-
-
Q
A
Max Current from V
I
1
Q
QMAX
Interchannel Gain Mismatch
Gain Drift
-
-
0.1
100
100
-
-
dB
ppm/°C
Ω
-
Output Impedance
AC-Load Resistance
Load Capacitance
(Note 4)
Z
-
-
-
OUT
R
C
3
-
kΩ
pF
L
L
-
100
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
(Note 5)
normal operation, V = 5 V
I
I
I
-
-
-
-
-
-
60
45
30
2
84
200
66
70
46
-
-
-
mA
mA
mA
µA
A
A
V = 5 V
D
D
D
V = 3.3 V
D
I
LC
Interface current, VLC=5 V (Note 6, 7)
VLS=5 V
I
µA
LS
I
µA
pd
power-down state (all supplies) (Note 8)
Power Dissipation
VA = 5 V, VD = 3.3 V
(Note 5)
normal operation
-
-
-
-
400
1
525
1
485
mW
mW
mW
mW
power-down (Note 8)
normal operation
power-down (Note 8)
-
680
-
VA = 5 V, VD = 5 V
Package Thermal Resistance
θ
θ
-
-
48
15
-
-
°C/Watt
°C/Watt
JA
JC
Power Supply Rejection Ratio (Note 9)
(1 kHz) PSRR
(60 Hz)
-
-
60
40
-
-
dB
dB
Notes: 4. V is tested under load R and includes attenuation due to Z
OUT
FS
L
5. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
6. I measured with no external loading on the SDA pin.
LC
7. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.
8. Power down mode is defined as RST pin = Low with all clock and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
DS514F1
5
CS4382
ANALOG FILTER RESPONSE
Fast Roll-Off
Typ
Slow Roll-Off (Note 10)
Parameter
Min
Max
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 11)
Passband (Note 12)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.454
.499
+0.01
-
0
0
-
-
-
-
0.417
0.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
-0.01
.547
90
-
-0.01
.583
64
(Note 13)
-
-
-
-
-
-
Group Delay
12/Fs
-
6.5/Fs
Passband Group Delay Deviation 0 - 20 kHz
-
-
-
-
-
-
-
-
±0.41/Fs
±0.23
±0.14
±0.09
-
-
-
-
±0.14/Fs
±0.23
±0.14
±0.09
s
De-emphasis Error (Note 14)
(Relative to 1 kHz)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
dB
dB
dB
Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96 kHz (Note 11)
Passband (Note 12)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.430
.499
0.01
-
-
-
0
0
-
-
-
-
.296
.499
0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
Passband Group Delay Deviation 0 - 20 kHz
-0.01
.583
80
-
-0.01
.792
70
(Note 13)
-
4.6/Fs
-
-
3.9/Fs
-
-
-
±0.03/Fs
±0.01/Fs
s
Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192 kHz (Note 11)
Passband (Note 12)
to -0.01 dB corner
to -3 dB corner
0
0
-
-
-
-
.105
.490
0.01
-
-
-
0
0
-
-
-
-
.104
.481
0.01
-
-
-
Fs
Fs
dB
Fs
dB
s
Frequency Response 10 Hz to 20 kHz
StopBand
StopBand Attenuation
Group Delay
Passband Group Delay Deviation 0 - 20 kHz
-0.01
.635
90
-
-0.01
.868
75
(Note 13)
-
4.7/Fs
-
-
4.2/Fs
-
-
-
±0.01/Fs
±0.01/Fs
s
Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 11)
Passband (Note 12)
to -0.1 dB corner
to -3 dB corner
-
-
-
-
-
-
-
-
-
0
0
-.01
-
-
-
20
120
0.1
kHz
kHz
dB
Frequency Response 10 Hz to 20 kHz
Notes: 10. Slow Roll-Off interpolation filter is only available in control port mode.
11. Filter response is not tested but is guaranteed by design.
12. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
13. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.
14. De-emphasis is available only in Single Speed Mode; Only 44.1 kHz De-emphasis is available in Stand-
Alone Mode
6
DS514F1
CS4382
DIGITAL CHARACTERISTICS (For KQZ T = -10 to +70 °C; VLC = VLS = 1.8 V to 5.5 V)
A
Parameters
Symbol
Min
Typ
Max
Units
V
V
70% VLS
70% VLC
-
-
-
-
V
V
High-Level Input Voltage
Low-Level Input Voltage
Serial Data Port
Control Port
IH
IH
V
V
-
-
-
-
20% VLS
20% VLC
V
V
Serial Data Port
Control Port
IL
IL
Input Leakage Current
Input Capacitance
(Note 7)
I
-
-
-
-
-
-
8
±10
µA
pF
mA
V
in
-
-
-
-
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
3
V
VA
0
OH
V
V
OL
ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
6.0
6.0
6.0
6.0
V
V
V
V
Input Current, Any Pin Except Supplies
Digital Input Voltage Serial data port interface
Control port interface
I
-
±10
mA
in
V
V
-0.3
-0.3
VLS+ 0.4
VLC+ 0.4
V
V
IND-S
IND-C
Ambient Operating Temperature (power applied)
Storage Temperature
T
-55
-65
125
150
°C
°C
A
T
stg
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
VA
VD
VLS
VLC
4.5
3.0
1.8
1.8
5.0
3.3
5.0
5.0
5.5
5.5
5.5
5.5
V
V
V
V
DS514F1
7
CS4382
SWITCHING CHARACTERISTICS (For KQZ T = -10 to +70 °C; VLS = 1.8 V to 5.5 V; Inputs: Logic
A
0 = GND, Logic 1 = VLS, C = 30 pF)
L
Parameters
Symbol
Min
Typ
Max
Units
MCLK Frequency
(Note 15)
Single Speed Mode
Double Speed Mode
Quad Speed Mode
1.024
6.400
6.400
40
-
-
51.2
51.2
51.2
60
MHz
MHz
MHz
%
-
MCLK Duty Cycle
Input Sample Rate
50
Single Speed Mode
Double Speed Mode
Quad Speed Mode
Fs
Fs
Fs
4
50
100
-
-
-
50
100
200
kHz
kHz
kHz
LRCK Duty Cycle
45
20
20
50
-
55
-
%
ns
ns
ns
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
t
sclkl
t
-
-
sclkh
sclkw
t
-
-
2
-----------------
MCLK
(Note 16)
t
-
-
ns
4
sclkw
-----------------
MCLK
SCLK rising to LRCK edge delay
t
20
20
-
-
ns
ns
ns
ns
slrd
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
t
-
-
slrs
t
20
-
-
-
-
sdlrs
t
20
sdh
LRCK1 to LRCK2 frequency ratio
(Note 17)
0.25
1.00
4.00
Notes: 15. See Table 5 on page 26 for suggested MCLK frequencies
16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LRCK
t
t
sclkh
slrs
t
slrd
t
sclkl
SCLK
t
t
sdh
sdlrs
SDATA
Figure 1. Serial Mode Input Timing
8
DS514F1
CS4382
DSD - SWITCHING CHARACTERISTICS (For KQZ T = -10 to +70 °C; Logic 0 = GND; VLS =
A
1.8 V to 5.5 V; Logic 1 = VLS Volts; C = 30 pF)
L
Parameter
Symbol
Min
4.096
40
Typ
Max
38.4
60
-
Unit
MHz
%
Master Clock Frequency
(Note 18)
-
50
-
MCLK Duty Cycle
(All DSD modes)
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
t
20
ns
sclkl
t
20
-
-
ns
sclkh
(64x Oversampled)
(128x Oversampled)
1.024
2.048
-
-
3.2
6.4
MHz
MHz
DSD_L / _R valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_L or DSD_R hold time
t
20
20
-
-
-
-
ns
ns
sdlrs
t
sdh
Note: 18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The
proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins
t
sclkh
t
sclkl
DSD_SCLK
t
t
sdlrs
sdh
DSD_L, DSD_R
Figure 2. Direct Stream Digital - Serial Audio Input Timing
DS514F1
9
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(For KQZ T = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
A
L
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
f
-
100
kHz
scl
RST Rising Edge to Start
t
500
4.7
4.0
4.7
4.0
4.7
0
-
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
irs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
t
-
buf
t
-
hdst
t
-
low
Clock High Time
t
-
high
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
t
-
sust
(Note 19)
(Note 20)
t
-
hdd
t
250
-
-
1
sud
t , t
rc rc
Fall Time SCL and SDA
t , t
-
300
-
fc fc
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
t
4.7
-
susp
t
(Note 21)
ack
Notes: 19. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
15
256 × Fs
15
128 × Fs
15
64 × Fs
--------------------
--------------------
-----------------
21.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode.
Note 1
DATA
ADDR
AD0
DATA
1-8
001100
R/W
ACK
ACK
ACK
SDA
SCL
1-8
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
2
Figure 3. Control Port Timing - I C Format
10
DS514F1
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(For KQZ T = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
A
L
Parameter
Symbol
Min
Max
Unit
CCLK Clock Frequency
f
-
MHz
MCLK
-----------------
sclk
2
-
-
-
-
-
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t
500
500
1.0
20
ns
ns
µs
ns
ns
srs
(Note 22)
t
spi
t
csh
t
css
t
1
scl
-----------------
MCLK
CCLK High Time
t
-
ns
1
sch
dsu
-----------------
MCLK
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
t
40
15
-
-
ns
ns
ns
ns
(Note 23)
(Note 24)
(Note 24)
t
-
dh
t
100
100
r2
t
-
f2
Notes: 22. t only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi
spi
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For F
< 1 MHz.
SCK
RST
t
t
srs
spi
CS
t
t
t
css
scl
sch
t
csh
CCLK
t
t
r2
f2
C DIN
t
t
dsu
dh
Figure 4. Control Port Timing - SPI Format
DS514F1
11
CS4382
+3.3 V to +5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
32
VA
VD
39
40
AOUTA1+
AOUTA1-
Analog Conditioning
and Muting
6
7
MCLK
38
37
AOUTB1+
AOUTB1-
Analog Conditioning
and Muting
LRCK1
SCLK1
LRCK2
SCLK2
9
PCM
Digital
Audio
10
35
36
AOUTA2+
AOUTA2-
Analog Conditioning
and Muting
12
8
Source
SDIN1
SDIN2
11
34
33
AOUTB2+
AOUTB2-
Analog Conditioning
and Muting
13
14
SDIN3
SDIN4
29
30
AOUTA3+
AOUTA3-
Analog Conditioning
and Muting
43
+1.8 V to +5 V
VLS
CS4382
0.1 µF
28
27
AOUTB3+
AOUTB3-
Analog Conditioning
and Muting
3
25
26
DSDA1
DSDB1
DSDA2
AOUTA4+
AOUTA4-
Analog Conditioning
and Muting
2
1
48
24
23
DSD
Audio
Source
AOUTB4+
AOUTB4-
DSDB2
Analog Conditioning
and Muting
47
46
DSDA3
DSDB3
45
44
41
22
DSDA4
DSDB4
MUTEC1
Mute
Drive
MUTEC234
42
DSD_SCLK
19
RST
15
16
Micro-
Controller
SCL/CCLK
SDA/CDIN
17
ADO/CS
Note*
20
21
FILT+
VQ
+
18
0.1 µF
+1.8 V to +5 V
VLC
F
47 µF
0.1 µ
F
1 µF
0.1 µ
+
GND
5
GND
31
Note: Necessary for I2C
control port operation
Figure 5. Typical Connection Diagram Control Port
12
DS514F1
CS4382
+3.3 V to +5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
32
V A
V D
47 K
Ω
N oteD SD
39
40
A O U TA 1+
A O U TA 1-
V LS
A nalog C onditioning
and M uting
6
M C LK
38
37
A O U TB 1+
A O U TB 1-
7
9
A nalog C onditioning
and M uting
LR CK 1
S C LK 1
LR CK 2
S C LK 2
S D IN 1
S D IN 2
P C M
D igital
A udio
S ource
10
12
8
M ute
D rive
41
M U TE C 1
11
35
36
13
14
A O U TA 2+
A O U TA 2-
S D IN 3
S D IN 4
A nalog C onditioning
and M uting
34
33
43
A O U TB 2+
A nalog C onditioning
and M uting
+1.8 V to +5 V
V LS
C S 4382 A O U TB 2-
0.1 µF
29
30
A O U TA 3+
A O U TA 3-
A nalog C onditioning
and M uting
3
D S D A 1
D S D B 1
D S D A 2
28
27
2
A O U TB 3+
A O U TB 3-
A nalog C onditioning
and M uting
1
48
D S D
A udio
S ource
D S D B 2
25
26
47
46
A O U TA 4+
A O U TA 4-
A nalog C onditioning
and M uting
D S D A 3
D S D B 3
45
44
D S D A 4
D S D B 4
24
23
A O U TB 4+
A O U TB 4-
A nalog C onditioning
and M uting
N oteD SD
47 K
Ω
M ute
D rive
22
42
M UTE C 234
M 3(D S D _S C LK )
15
16
M 2
M 1
S tand-A lone
M ode
Configuration
17
19
M 0
R S T
N oteVLC
20
21
FILT+
V Q
+
F
47 µF
0.1 µ
18
F
1 µF
0.1 µ
+
+1.8 V to +5 V
V LC
0.1 µF
G N D
5
G N D
31
N oteVLC: If series resistors are
used they m ust be <1 kO hm . If
possible tie V LC to the V D supply
to reduce possible excess current
consum ption from V LC .
N oteD SD: For D S D operation:
1) LR C K 1 m ust be tied to V LS and
rem ain static high.
2) M 3 P C M stand-alone configuration
pin becom es D S D_S CLK
Figure 6. Typical Connection Diagram Stand-Alone
DS514F1
13
CS4382
2. REGISTER QUICK REFERENCE
Addr
Function
7
6
5
4
3
2
1
0
01h Mode Control 1
CPEN
FREEZE
DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS
PDN
1
MCLKDIV
0
0
DIF2
0
0
DIF0
0
0
0
0
default
02h Mode Control 2
default
0
DIF1
0
Reserved
SDIN4CLK SDIN3CLK SDIN2CLK SDIN1CLK
0
SZC1
1
0
0
0
Reserved
0
0
MUTEC
0
03h Mode Control 3
default
SZC0
0
SNGLVOL RMP_UP MUTEC+/- AMUTE
0
0
0
1
DEM1
0
04h Filter Control
default
Reserved Reserved Reserved FILT_SEL Reserved
DEM0
0
RMP_DN
0
0
INV_B4
0
0
INV_A4
0
0
INV_B3
0
0
INV_A3
0
0
INV_B2
0
05h Invert Control
default
INV_A2
0
INV_B1
0
INV_A1
0
06h Mixing Control
Pair 1 (AOUTx1)
P1_A=B P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0
P1FM1
P1FM0
0
0
1
0
0
1
0
0
default
07h Vol. Control A1
default
A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0
0
0
0
0
0
0
0
0
08h Vol. Control B1
default
B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0
0
0
0
0
0
0
0
0
09h Mixing Control
Pair 2 (AOUTx2)
P2_A=B P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0
P2FM1
P2FM0
0
0
1
0
0
1
0
0
default
0Ah Vol. Control A2
default
A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0
0
0
0
0
0
0
0
0
0Bh Vol. Control B2
default
B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0
0
0
0
0
0
0
0
0
0Ch Mixing Control
Pair 3 (AOUTx3)
P3_A=B P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0
P3FM1
P3FM0
0
0
1
0
0
1
0
0
default
0Dh Vol. Control A3
default
A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0
0
0
0
0
0
0
0
0
0Eh Vol. Control B3
default
B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0
0
0
0
0
0
0
0
0
0Fh Mixing Control
Pair 4 (AOUTx4)
P4_A=B P4ATAPI4 P4ATAPI3 P4ATAPI2 P4ATAPI1 P4ATAPI0
P4FM1
P4FM0
0
0
1
0
0
1
0
0
default
10h Vol. Control A4
default
A4_MUTE A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0
0
0
0
0
0
0
0
0
11h Vol. Control B4
default
B4_MUTE B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0
0
PART3
1
0
PART2
0
0
PART1
1
0
PART0
0
0
0
0
0
12h Chip Revision
default
Reserved Reserved Reserved Reserved
-
-
-
-
14
DS514F1
CS4382
3. REGISTER DESCRIPTION
2
Note: All registers are read/write in I C mode and write only in SPI, unless otherwise noted.
3.1
Mode Control 1 (address 01h)
7
CPEN
0
6
FREEZE
0
5
MCLKDIV
0
4
DAC4_DIS
0
3
DAC3_DIS
0
2
DAC2_DIS
0
1
DAC1_DIS
0
0
PDN
1
3.1.1 CONTROL PORT ENABLE (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode
can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by
the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-
up, the user should write this bit within 10 ms following the release of Reset.
3.1.2 FREEZE CONTROLS (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until
the FREEZE is disabled. To make multiple changes in the Control port registers take effect simulta-
neously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
3.1.3 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all
other internal circuitry.
3.1.4 DAC PAIR DISABLE (DACX_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power down bit is enabled to eliminate the
possibility of audible artifacts.
DS514F1
15
CS4382
3.1.5 POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation in Control Port mode can occur.
3.2
Mode Control 2 (address 02h)
7
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
SDIN4CLK
0
2
SDIN3CLK
0
1
SDIN2CLK
0
0
SDIN1CLK
0
Reserved
0
3.2.1 DIGITAL INTERFACE FORMAT (DIF)
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 33-38.
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
33
34
35
36
37
38
Left Justified, up to 24-bit data
I S, up to 24-bit data
2
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
Reserved
Table 1. Digital Interface Formats - PCM Mode
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required
Master clock to DSD data rate is defined by the Digital Interface Format pins. An additional write of 99h
to register 00h and 80h to register 1Ah is required to access the modes denoted with *.
DIF2
DIF1
DIFO
DESCRIPTION
Note
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
*
*
*
*
*
*
Table 2. Digital Interface Formats - DSD Mode
16
DS514F1
CS4382
3.2.2 SERIAL AUDIO DATA CLOCK SOURCE (SDINXCLK)
Default = 0
0 - SDINx clocked by SCLK1 and LRCK1
1 - SDINx clocked by SCLK2 and LRCK2
Function:
The SDINxCLK bit specifies which SCLK/LRCK input pair is used to clock in the data on the given
SDINx line. For more details see “Clock Source Selection” on page 28.
3.3
Mode Control 3 (address 03h)
7
SZC1
1
6
SZC0
0
5
SNGLVOL
0
4
RMP_UP
0
3
Reserved
0
2
AMUTE
1
1
Reserved
0
0
MUTEC
0
3.3.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-
itored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
DS514F1
17
CS4382
3.3.2 SINGLE VOLUME CONTROL (SNGLVOL)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel
Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.
3.3.3 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change
or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is ef-
fected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
When disabled, an immediate un-mute is performed in these instances.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN
bit.
3.3.4 MUTEC POLARITY (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the
MUTEC pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Note: When the on board mute circuitry is designed for active low, the MUTEC outputs will be high
(un-muted) for the period of time during reset and before this bit is enabled to 1.
3.3.5 AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio
samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and
muting is done independently for each channel. The quiescent voltage on the output will be retained
and the Mute Control pin will go active during the mute period. The muting function is affected, similar
to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.
18
DS514F1
CS4382
3.3.6 MUTEC PIN CONTROL(MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to
‘0’, a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the
mute control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND
of all DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For
more information on the use of the mute control function see the MUTEC1 and MUTEC234 pins in
section 4.
3.4
Filter Control (address 04h)
7
6
Reserved
0
5
Reserved
0
4
FILT_SEL
0
3
Reserved
0
2
DEM1
0
1
DEM0
0
0
RMP_DN
0
Reserved
0
3.4.1 INTERPOLATION FILTER SELECT (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For
filter characteristics please see Section 1.
3.4.2 DE-EMPHASIS CONTROL (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 39)
De-emphasis is only available in Single Speed Mode.
DS514F1
19
CS4382
3.4.3 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed prior to executing a filter mode change. When this feature is enabled, this
mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control
3 register. When disabled, an immediate mute is performed prior to executing a filter mode change.
Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP
bit.
3.5
Invert control (address 05h)
7
INV_B4
0
6
INV_A4
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
3.5.1 INVERT SIGNAL POLARITY (INV_XX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
3.6
Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)
7
6
PxATAPI4
0
5
PxATAPI3
1
4
PxATAPI2
0
3
PxATAPI1
0
2
PxATAPI0
1
1
PxFM1
0
0
PxFM0
0
Px_A=B
0
3.6.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel
Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are
determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Chan-
nel Bytes are ignored when this function is enabled.
20
DS514F1
CS4382
3.6.2 ATAPI CHANNEL MIXING AND MUTING (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The CS4382 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information
.
ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
AOUTBx
MUTE
bR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
bL
b[(L+R)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
bL
b[(L+R)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
bL
[(aL+bR)/2]
Table 3. ATAPI Decode
DS514F1
21
CS4382
3.6.3 FUNCTIONAL MODE (FM)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. When DSD mode is selected for any
channel pair then all pairs will switch to DSD mode.
3.7
Volume control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h)
7
6
xx_VOL6
0
5
xx_VOL5
0
4
xx_VOL4
0
3
xx_VOL3
0
2
xx_VOL2
0
1
xx_VOL1
0
0
xx_VOL0
0
xx_MUTE
0
3.7.1 MUTE (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output
will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero
Cross bits. The MUTEC pins will go active during the mute period according to the MUTEC register.
3.7.2 VOLUME CONTROL (XX_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments
from 0 to -127 dB. Volume settings are decoded as shown in Table 4. The volume changes are imple-
mented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent
to enabling the MUTE bit.
Binary Code
0000000
0010100
0101000
0111100
Decimal Value
Volume Setting
0 dB
0
20
40
60
90
-20 dB
-40 dB
-60 dB
-90 dB
1011010
Table 4. Example Digital Volume Settings
22
DS514F1
CS4382
3.8
Chip Revision (address 12h)
7
PART3
1
6
PART2
0
5
PART1
1
4
PART0
0
3
2
1
0
Reserved
-
Reserved
-
Reserved
-
Reserved
-
3.8.1 PART NUMBER ID (PART) [READ ONLY]
1010 - CS4382
Function:
This read-only register can be used to identify the model number of the device.
DS514F1
23
CS4382
4. PIN DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
36
DSDA2
DSDB1
AOUTA2-
1
2
35
34
33
32
AOUTA2+
AOUTB2+
AOUTB2-
DSDA1
VD
3
4
5
GND
VA
31
MCLK
GND
6
CS4382
LRCK1(DSD_EN)
SDIN1
AOUTA3-
AOUTA3+
AOUTB3+
7
30
29
28
27
26
25
8
SCLK1
9
LRCK2
10
11
12
AOUTB3-
AOUTA4-
AOUTA4+
SDIN2
SCLK2
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
VD
#
Pin Description
4
Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operat-
ing Conditions for appropriate voltages.
GND
5
Ground (Input) - Ground reference. Should be connected to analog ground.
31
MCLK
6
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates
several standard audio sample rates and the required master clock frequency.
LRCK1
LRCK2
7
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
10 data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
SDIN1
SDIN2
SDIN3
SDIN4
8
11
13
14
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK1
SCLK2
9
12
Serial Clock (Input) - Serial clock for the serial audio interface.
VLC
RST
FILT+
VQ
18 Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Rec-
ommended Operating Conditions for appropriate voltages.
19 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.
21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively
coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is
specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source
impedance and any current drawn from this pin will alter device performance. However, VQ can be
used to bias the analog circuitry assuming there is no AC signal component and the DC current is less
than the maximum specified in the Analog Characteristics and Specifications section.
24
DS514F1
CS4382
Pin Name
#
Pin Description
MUTEC1
MUTEC234
41
22
Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset, muting,
power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended
to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any sin-
gle supply system. The use of external mute circuits are not mandatory but may be desired for designs
requiring the absolute minimum in extraneous clicks and pops.
AOUTA1 +,- 39, 40 Differential Analog Output (Output) - The full scale differential analog output level is specified in the
AOUTB1 +,- 38, 37 Analog Characteristics specification table.
AOUTA2 +,- 35, 36
AOUTB2 +,- 34, 33
AOUTA3 +,- 29, 30
AOUTB3 +,- 28, 27
AOUTA4 +,- 25, 26
AOUTB4 +,- 24, 23
VA
32
Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Oper-
ating Conditions for appropriate voltages.
VLS
43 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
Control Port Definitions
SCL/CCLK
15 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I2C mode as shown in the Typical Connection Diagram.
SDA/CDIN
16 Serial Control Data (Input/Output) - SDA is a data I/O line in I2C mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input
data line for the control port interface in SPI mode.
AD0/CS
Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I2C mode;
CS is the chip select signal for SPI format.
17
Stand-Alone Definitions
M0
M1
M2
M3
17
16
15
42
Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 6 and 7.
DSD Definitions
DSD_SCLK
42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.
DSD_EN
DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone mode only).
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
7
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
3
2
1
48
47
46
45
44
DS514F1
25
CS4382
Control port
only modes
Mode
(sample-rate range)
Sample
Rate
MCLK (MHz)
(kHz)
MCLK Ratio
256x
8.1920
11.2896
12.2880
128x
384x
512x
768x*
24.5760
33.8688
36.8640
384x
1024x*
32.7680
45.1584
49.1520
512x*
32
44.1
48
12.2880
16.9344
18.4320
192x
16.3840
22.5792
24.5760
256x
Single Speed
(4 to 50 kHz)
MCLK Ratio
64
88.2
96
8.1920
11.2896
12.2880
64x
12.2880
16.9344
18.4320
96x
16.3840
22.5792
24.5760
128x
24.5760
33.8688
36.8640
192x
32.7680
45.1584
49.1520
256x*
Double Speed
(50 to 100 kHz)
MCLK Ratio
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Quad Speed
(100 to 200 kHz)
Table 5. Common Clock Frequencies
*Note: These modes are only available in control port mode by setting the MCLKDIV bit = 1.
M1
M0
DESCRIPTION
FORMAT
FIGURE
(DIF1)
(DIF0)
Left Justified, up to 24-bit data
0
0
0
1
0
1
33
34
2
I S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
1
1
0
1
2
3
35
36
Table 6. Digital Interface Format, Stand-Alone Mode Options
M3
M2
DESCRIPTION
(DEM)
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 39
Double-Speed (50 to 100 kHz sample rates)
0
0
1
1
0
1
0
1
Quad-Speed (100 to 200 kHz sample rates)
Table 7. Mode Selection, Stand-Alone Mode Options
DSD_Mode
M2
M1
M0
DESCRIPTION
(LRCK1)
64x oversampled DSD data with a 4x MCLK to DSD data rate
Reserved
Reserved
Reserved
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
128x oversampled DSD data with a 2x MCLK to DSD data rate
Reserved
Reserved
Reserved
Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options
26
DS514F1
CS4382
quence, approximately 512 LRCK cycles in Sin-
gle-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode). Writing this bit will halt the Stand-
Alone power-up sequence and initialize the control
port to its default settings. The desired register set-
tings can be loaded while keeping the PDN bit set
to 1.
5. APPLICATIONS
5.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4382
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figures 5 & 6 show the recommended power ar-
rangement with VA, VD, VLS and VLC connected
to clean supplies. Decoupling capacitors should be
located as close to the device package as possible.
If desired, all supply pins may be connected to the
same supply, but a decoupling capacitor should still
be placed on each supply pin (see Section 1 for rec-
ommended voltages).
3. If Control Port Mode is selected via the CPEN
bit, set the PDN bit to 0 which will initiate the pow-
er-up sequence.
5.4 Analog Output and Filtering
The application note “Design Notes for a 2-Pole
Filter with Differential Input” discusses the sec-
ond-order Butterworth filter and differential to sin-
gle-ended converter which was implemented on the
CS4382 evaluation board, CDB4382, as seen in
Figure 42. The CS4382 does not include phase or
amplitude compensation for an external filter.
Therefore, the DAC system phase and amplitude
response will be dependent on the external analog
circuitry.
5.2 Oversampling Modes
The CS4382 operates in one of three oversampling
modes based on the input sample rate. Mode selec-
tion is determined by the M3 and M2 pins in Stand-
Alone mode or the FM bits in Control Port mode.
Single-Speed mode supports input sample rates up
to 50 kHz and uses a 128x oversampling ratio.
Double-Speed mode supports input sample rates up
to 100 kHz and uses an oversampling ratio of 64x.
Quad-Speed mode supports input sample rates up
to 200 kHz and uses an oversampling ratio of 32x.
5.5 Interpolation Filter
To accommodate the increasingly complex re-
quirements of digital audio systems, the CS4382
incorporates selectable interpolation filters for each
mode of operation. A “fast” and a “slow” roll-off
filter is available in each of Single, Double, and
Quad Speed modes. These filters have been de-
signed to accommodate a variety of musical tastes
and styles. The FILT_SEL bit is used to select
which filter is used (see the control port section for
more details).
5.3 Recommended Power-up
Sequence
1. Hold RST low until the power supply, master,
and left/right clocks are stable. In this state, the
control port is reset to its default settings and VQ
will remain low.
2. Bring RST high. The device will remain in a low
power state with VQ low and will initiate the
Stand-Alone power-up sequence. The control port
will be accessible at this time. If Control Port oper-
ation is desired, write the CPEN bit prior to the
completion of the Stand-Alone power-up se-
When in stand-alone mode, only the “fast” roll-off
filter is available.
Filter specifications can be found in Section 1, and
filter response plots can be found in Figures 9 to 32.
DS514F1
27
CS4382
DSD data and clocks to the appropriate pins. The
M2:0 pins set the expected DSD rate and MCLK
ratio.
5.6 Clock Source Selection
The CS4382 has two serial clock and two left/right
clock inputs. The SDINxCLK bits in the control
port allow the user to set which SCLK/LRCK pair
is used to latch the data for each SDINx pin. The
In control-port mode the FM bits set the device into
DSD mode (DSD_EN pin is not required to be held
clocks applied to LRCK1 and LRCK2 must be de- high). The DIF register then controls the expected
rived from the same MCLK and must be exact fre- DSD rate and MCLK ratio. To access the full range
quency multiples of each other as specified in the of DSD clocking modes (other than 64x DSD 4x
“Switching Characteristics” table on page 8. When MCLK and 128x DSD 2x MCLK) the following
using both SCLK1/LRCK1 and SCLK2/LRCK2, if
additional register sequence needs to be written:
either SCLK/LRCK pair loses synchronization 99h to register 00h
then both SCLK/LRCK pairs will go through a re- 80h to register 1Ah
time period where the device is re-evaluating clock 00h to register 00h
ratios. During the retime period all DAC pairs are
When exiting DSD mode the following additional
sequence needs to be written:
99h to register 00h
temporarily inactive, outputs are muted, and the
mute control pins will go active according to the
MUTEC register.
00h to register 1Ah
If unused, SCLK2 and LRCK2 should be tied static
low and SDINx bits should all be set to
SCLK1/LRCK1.
00h to register 00h
During DSD operation, the PCM related pins
should either be tied low or remain active with
In stand-alone mode all DAC pairs use SCLK1 and clocks (except LRCK1 in Stand-Alone mode).
LRCK1 for timing and SCLK2/LRCK2 should be
tied to ground.
When the DSD related pins are not being used they
should either be tied static low, or remain active
with clocks (except M3 in Stand-Alone mode).
5.7 Using DSD mode
In stand-alone mode, DSD operation is selected by
holding DSD_EN(LRCK1) high and applying the
28
DS514F1
CS4382
to low transition on AD0/CS after power-up and af-
ter the control port is activated, SPI format will be
selected.
6. CONTROL PORT INTERFACE
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
2
6.3 I C Format
2
In I C Format, SDA is a bidirectional data line.
Data is clocked into and out of the part by the clock,
SCL, with a clock to data relationship as shown in
Figure 7. The receiving device should send an ac-
knowledge (ACK) after each byte received. There
is no CS pin. Pin AD0 forms the partial chip ad-
dress and should be tied to VLC or GND as re-
quired. The upper 6 bits of the 7 bit address field
must be 001100.
The CS4382 has MAP auto increment capability,
enabled by the INCR bit in the MAP register,
which is the MSB. If INCR is 0, then the MAP will
stay constant for successive writes. If INCR is set
to 1, then MAP will auto increment after each byte
is written from register 01h to 08h and then from
09h and 11h, allowing block reads or writes of suc-
cessive registers in two separate sections (the
counter will not auto-increment to register 09h
from register 08h).
2
Note: MCLK is required during all I C transac-
tions. Please see reference 4 for further details.
2
6.3.1 Writing in I C Format
6.1 Enabling the Control Port
To communicate with the CS4382, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (low for a write). The next byte is the
Memory Address Pointer, MAP, which selects the
register to be read or written. The MAP is then fol-
lowed by the data to be written. To write multiple
registers, continue providing a clock and data,
waiting for the CS4382 to acknowledge between
each byte. To end the transaction, send a STOP
condition.
On the CS4382 the control port pins are shared
with stand-alone configuration pins. To enable the
control port, the user must set the CPEN bit. This
2
is done by performing a I C or SPI write. Once the
control port is enabled, these pins are dedicated to
control port functionality.
To prevent audible artifacts the CPEN bit (see Sec-
tion 3.1.1) should be set prior to the completion of
the Stand-Alone power-up sequence, approximate-
ly 1024 LRCK cycles. Writing this bit will halt the
Stand-Alone power-up sequence and initialize the
control port to its default settings. Note, the CP_EN
bit can be set any time after RST goes high; how-
ever, setting this bit after the Stand-Alone power-
up sequence has completed can cause audible arti-
facts.
2
6.3.2 Reading in I C Format
To communicate with the CS4382, initiate a
START condition of the bus. Next, send the chip
address. The eighth bit of the address byte is the
R/W bit (high for a read). The contents of the reg-
ister pointed to by the MAP will be output after the
chip address. To read multiple registers, continue
providing a clock and issue an ACK after each
byte. To end the transaction, send a STOP condi-
tion.
6.2 Format Selection
2
The control port has 2 formats: SPI and I C, with
the CS4382 operating as a slave device.
2
If I C operation is desired, AD0/CS should be tied
to VLC or GND. If the CS4382 ever detects a high
DS514F1
29
CS4382
SPI format. To write to a register, bring CS low.
The first 7 bits on CDIN form the chip address and
must be 0011000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. The
next 8 bits form the Memory Address Pointer
(MAP), which is set to the address of the register
that is to be updated. The next 8 bits are the data
which will be placed into register designated by the
MAP. To write multiple registers, keep CS low and
continue providing clocks on CCLK. End the read
transaction by setting CS high.
6.4 SPI Format
In SPI format, CS is the CS4382 chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0011000. CS, CCLK and CDIN are all
inputs and data is clocked in on the rising edge of
CCLK.
Note that the CS4382 is write-only when in SPI
format.
6.4.1 Writing in SPI
Figure 8 shows the operation of the control port in
N o te 1
A D D R
A D 0
D A T A
1-8
D A T A
1-8
0 01 1 0 0
R /W
A C K
A C K
A C K
S D A
S C L
S ta rt
S top
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
2
Figure 7. Control Port Timing, I C Format
C S
C C L K
C H IP
A D D R E S S
M A P
D A T A
0 0 1 1 0 0 0
L S B
C D IN
M S B
R /W
b y te 1
b y te n
M A P = M e m o ry A d d re s s P o in te r
Figure 8. Control Port Timing, SPI Format
30
DS514F1
CS4382
6.5
Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
6.5.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
Note: When Auto Map Increment is enabled, the register must be written it two separate blocks:
from register 01h to 08h and then from 09h and 11h. The counter will not auto-increment to register
09h from register 08h
6.5.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
DS514F1
31
CS4382
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 9. Single Speed (fast) Stopband Rejection
Figure 10. Single Speed (fast) Transition Band
0
0.02
1
0.015
0.01
0.005
0
2
3
4
5
6
0.005
0.01
0.015
0.02
7
8
9
10
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 11. Single Speed (fast) Transition Band
(detail)
Figure 12. Single Speed (fast) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 13. Single Speed (slow) Stopband Rejection
Figure 14. Single Speed (slow) Transition Band
32
DS514F1
CS4382
0.02
0.015
0.01
0
1
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 15. Single Speed (slow) Transition Band
(detail)
Figure 16. Single Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 17. Double Speed (fast) Stopband Rejection
Figure 18. Double Speed (fast) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 19. Double Speed (fast) Transition Band
(detail)
Figure 20. Double Speed (fast) Passband Ripple
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CS4382
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 21. Double Speed (slow) Stopband Rejection
Figure 22. Double Speed (slow) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 23. Double Speed (slow) Transition Band
(detail)
Figure 24. Double Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 25. Quad Speed (fast) Stopband Rejection
Figure 26. Quad Speed (fast) Transition Band
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DS514F1
CS4382
0
0.2
0.15
0.1
1
2
3
0.05
0
4
5
6
0.05
7
0.1
0.15
0.2
8
9
10
0
0.05
0.1
0.15
0.2
0.25
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 27. Quad Speed (fast) Transition Band
(detail)
Figure 28. Quad Speed (fast) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 29. Quad Speed (slow) Stopband Rejection
Figure 30. Quad Speed (slow) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 31. Quad Speed (slow) Transition Band
(detail)
Figure 32. Quad Speed (slow) Passband Ripple
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CS4382
Left Channel
Right Channel
LRCK
SCLK
MSB
LSB
MSB
LSB
SDINx
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 33. Format 0 - Left Justified up to 24-bit Data
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
-1 -2 -3 -4 -5
2
Figure 34. Format 1 - I S up to 24-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
9
8
7
6
5
4
3
2
1
0
9
15 14 13 12 11 10
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
Figure 35. Format 2 - Right Justified 16-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
23 22 21 20 19 18
32 clocks
23 22 21 20 19 18
Figure 36. Format 3 - Right Justified 24-bit Data
36
DS514F1
CS4382
Right Channel
LRCK
SCLK
Left Channel
SDINx
1
0
19 18 17 16
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
19 18 17 16 9
Figure 37. Format 4 - Right Justified 20-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
1
0
17 16
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
17 16 9
Figure 38. Format 5 - Right Justified 18-bit Data
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 39. De-Emphasis Curve
L
AOUTAx+
AOUTAx-
DAC
Channel
Pair x
SDINx
Control
AOUTBx+
AOUTBx-
R
DAC
Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)
DS514F1
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CS4382
A Channel
Volume
Control
Left Channel
Audio Data
MUTE
AoutAx
Σ
Σ
SDINx
B Channel
Volume
Control
Right Channel
Audio Data
MUTE
AoutBx
Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
Figure 42. Recommended Output Filter
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DS514F1
CS4382
7. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement
to full scale. This technique ensures that the distortion components are below the noise level and do not
effect the measurement. This measurement technique has been accepted by the Audio Engineering So-
ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
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CS4382
8. REFERENCES
1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2. CDB4382 Evaluation Board Datasheet
3. “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note
AN48
2
4. “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
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CS4382
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D1
D
1
e
B
∝
A
A1
L
INCHES
NOM
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
MILLIMETERS
NOM
DIM
A
A1
B
D
D1
E
E1
e*
L
∝
MIN
---
MAX
MIN
---
MAX
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
1.40
0.10
0.22
0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
4°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm.
JEDEC Designation: MS022
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CS4382
Table 9. Revision History
Date
Release
Changes
F1
NOV 2004
Removed -BQ ordering option
Corrected specifications for Full Scale Differential Output Voltage
Updated Table 2 on page 16
Updated Section 5.7 Using DSD mode
Updated legal text
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by
Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights
of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work
rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and
gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This
consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
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USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER
CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SE-
CURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIR-
RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD-
ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys
a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
SPI is a trademark of Motorola, Inc.
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DS514F1
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