CDB4383_技术文档

CS4383

114 dB, 192 kHz 8-Channel D/A Converter

Features

Description

The CS4383 is a complete 8-channel digital-to-analog

system including digital interpolation, fifth-order delta-

sigma digital-to-analog conversion, digital de-emphasis,

volume control and analog filtering. The advantages of

this architecture include: ideal differential linearity, no

distortion mechanisms due to resistor matching errors,

no linearity drift over time and temperature and a high

tolerance to clock jitter.

24-Bit Conversion

Up to 192 kHz Sample Rates

114 dB Dynamic Range

-100 dB THD+N

Supports PCM and DSD Data Formats

Selectable Digital Filters

Volume Control with Soft Ramp

– 1 dB Step Size

– Zero Crossing Click-Free Transitions

Dedicated DSD inputs

Low Clock Jitter Sensitivity

The CS4383 accepts PCM data at sample rates from

4 kHz to 192 kHz, DSD audio data, and operates over a

wide power supply range. These features are ideal for

multi-channel audio systems including DVD players,

SACD players, A/V receivers, digital TV’s and VCR’s,

mixing consoles, effects processors, set-top boxes, and

automotive audio systems.

µC or Stand-Alone Operation

3 Mute Control pins for Left, Right, and

Surrounds

ORDERING INFORMATION

CS4383-KQ -10 to 70 °C

CS4383-BQ -40 to 85 °C

CDB4383

48-pin LQFP

Evaluation Board

I

S D A /C D IN (M 2) A D 0/C S (M 0)

D S D _S C L K (M 3 )

S C L/C C L K (M 1 )

V L C

M U T E C 1

M U T E C 2

M U T E C 3

R S T

C o ntro l P ort(S ta nd -A lo ne M o de S e le ct)

E x t e r n a l

M u t e C o n t r o l

A O U T A 1+

A O U T A 1-

V o l u m

e C o n t r o l

I n t e r p o la t i o n F i lt e r

∆ Σ

A n a lo g F ilt e r

D

A C

M i x e r

V L S

S C L K

L R C K

A O U T B 1+

A O U T B 1-

I n t e r p o la t i o n F i lt e r

V o l u m e C o n t r o l

∆ Σ

A n a lo g F i lt e r

A n a lo g F ilt e r

D

A C

A O U T A 2+

A O U T A 2-

V o l u m

e C o n t r o l

D

S D

I

N 1

N 2

N 3

M i x e r

I

A O U T B 2+

A O U T B 2-

I n t e r p o la t i o n F i lt e r

V o l u m e C o n t r o l

∆ Σ

A n a lo g F i lt e r

A n a lo g F ilt e r

D

A C

I

S D

I

N 4

A O U T A 3+

A O U T A 3-

V o l u m

e C o n t r o l

D

M i x e r

A O U T B 3+

A O U T B 3-

I n t e r p o la t i o n F i lt e r

V o l u m e C o n t r o l

∆ Σ

A n a lo g F i lt e r

A n a lo g F ilt e r

D

A C

M

C L K

A O U T A 4+

A O U T A 4-

V o l u m

e C o n t r o l

D

2

÷

M i x e r

A O U T B 4+

A O U T B 4-

8

∆ Σ

D

A C

I n t e r p o la t i o n F i lt e r

V o l u m e C o n t r o l

A n a lo g F i lt e r

D S D xx

V Q

F ILT +

V A

G N D

V D

G N D

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

Preliminary Product Information

Copyright Cirrus Logic, Inc. 2002

MAR ‘02

DS548PP2

1

P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581

http://www.cirrus.com

CS4383

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ................................................................. 4

2. REGISTER QUICK REFERENCE ................................................................................... 14

3. REGISTER DESCRIPTION ............................................................................................. 15

4. PIN DESCRIPTION .......................................................................................................... 24

5. APPLICATIONS .............................................................................................................. 27

5.1 Grounding and Power Supply Decoupling ........................................................... 27

5.2 Oversampling Modes ........................................................................................... 27

5.3 Recommended Power-up Sequence ................................................................... 27

5.4 Analog Output and Filtering ................................................................................. 27

5.5 Interpolation Filter ................................................................................................ 27

5.6 Using DSD mode ................................................................................................. 28

6. CONTROL PORT INTERFACE ....................................................................................... 28

6.1 Enabling the Control Port ..................................................................................... 28

6.2 Format Selection .................................................................................................. 28

2

6.3 I C Format ............................................................................................................ 28

2

6.3.1 Writing in I C Format .......................................................................28

2

6.3.2 Reading in I C Format ....................................................................29

6.4 SPI Format ........................................................................................................... 29

6.4.1 Writing in SPI ..................................................................................29

6.5 Memory Address Pointer (MAP)

..................................................................... 30

7. PARAMETER DEFINITIONS ........................................................................................... 38

8. REFERENCES ................................................................................................................. 38

9. PACKAGE DIMENSIONS ............................................................................................... 39

LIST OF FIGURES

Figure 1. Serial Mode Input Timing ................................................................................................. 8

Figure 2. Direct Stream Digital - Serial Audio Input Timing............................................................. 9

2

Figure 3. Control Port Timing - I C Format ................................................................................... 10

Figure 4. Control Port Timing - SPI Format................................................................................... 11

Figure 5. Typical Connection Diagram Control Port...................................................................... 12

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts

IMPORTANT NOTICE

"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product informa-

tion describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information

contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any

kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied

on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining

to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as

the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing

this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property

rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization

with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising

or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material

and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained

from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law

and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-

ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE

SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH

APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Purchase of I²C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I²C Patent Rights to use

those components in a standard I²C system.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

2

CS4383

Figure 6. Typical Connection Diagram Stand-Alone ..................................................................... 13

2

Figure 7. Control Port Timing, I C Format .................................................................................... 29

Figure 8. Control Port Timing, SPI Format.................................................................................... 29

Figure 9. Single Speed (fast) Stopband Rejection........................................................................ 31

Figure 10. Single Speed (fast) Transition Band ............................................................................ 31

Figure 11. Single Speed (fast) Transition Band (detail) ................................................................ 31

Figure 12. Single Speed (fast) Passband Ripple .......................................................................... 31

Figure 13. Single Speed (slow) Stopband Rejection..................................................................... 31

Figure 14. Single Speed (slow) Transition Band........................................................................... 31

Figure 15. Single Speed (slow) Transition Band (detail)............................................................... 32

Figure 16. Single Speed (slow) Passband Ripple......................................................................... 32

Figure 17. Double Speed (fast) Stopband Rejection..................................................................... 32

Figure 18. Double Speed (fast) Transition Band........................................................................... 32

Figure 19. Double Speed (fast) Transition Band (detail)............................................................... 32

Figure 20. Double Speed (fast) Passband Ripple......................................................................... 32

Figure 21. Double Speed (slow) Stopband Rejection ................................................................... 33

Figure 22. Double Speed (slow) Transition Band ......................................................................... 33

Figure 23. Double Speed (slow) Transition Band (detail) ............................................................. 33

Figure 24. Double Speed (slow) Passband Ripple ....................................................................... 33

Figure 25. Quad Speed (fast) Stopband Rejection ....................................................................... 33

Figure 26. Quad Speed (fast) Transition Band ............................................................................. 33

Figure 27. Quad Speed (fast) Transition Band (detail) ................................................................. 34

Figure 28. Quad Speed (fast) Passband Ripple ........................................................................... 34

Figure 29. Quad Speed (slow) Stopband Rejection...................................................................... 34

Figure 30. Quad Speed (slow) Transition Band ............................................................................ 34

Figure 31. Quad Speed (slow) Transition Band (detail) ................................................................ 34

Figure 32. Quad Speed (slow) Passband Ripple .......................................................................... 34

Figure 33. Format 0 - Left Justified up to 24-bit Data.................................................................... 35

2

Figure 34. Format 1 - I S up to 24-bit Data................................................................................... 35

Figure 35. Format 2 - Right Justified 16-bit Data .......................................................................... 35

Figure 36. Format 3 - Right Justified 24-bit Data .......................................................................... 35

Figure 37. Format 4 - Right Justified 20-bit Data .......................................................................... 36

Figure 38. Format 5 - Right Justified 18-bit Data .......................................................................... 36

Figure 39. De-Emphasis Curve..................................................................................................... 36

Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)................................... 36

Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) .................................................. 37

Figure 42. Recommended Output Filter........................................................................................ 37

LIST OF TABLES

Table 1. Digital Interface Formats - PCM Mode............................................................................ 16

Table 2. Digital Interface Formats - DSD Mode ............................................................................ 16

Table 3. ATAPI Decode ................................................................................................................ 21

Table 4. Example Digital Volume Settings.................................................................................... 22

Table 5. Common Clock Frequencies........................................................................................... 26

Table 6. Digital Interface Format, Stand-Alone Mode Options...................................................... 26

Table 7. Mode Selection, Stand-Alone Mode Options .................................................................. 26

Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................... 26

3

CS4383

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth

10 Hz to 20 kHz, unless otherwise specified; Test load R = 3 kΩ, C = 100 pF, VA = 5 V, VD = 3.3V (see Figure 5)

L

For Single speed Mode Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;

For Double Speed Mode Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;

For Quad Speed Mode Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;

For Direct Stream Digital Mode Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).

Parameters

Symbol

Min

Typ

Max

Unit

CS4383-KQ Dynamic Performance - All PCM modes and DSD (Note 1)

Specified Temperature Range

Dynamic Range (Note 2)

T_A

-10

-

70

°C

24-bit unweighted

A-Weighted

16-bit unweighted

(Note 3) A-Weighted

105

108

-

111

114

94

-

dB

97

Total Harmonic Distortion + Noise

(Note 2) THD+N

0 dB

24-bit

-

-100

-91

-51

-94

-74

-34

-94

dB

-20 dB

-60 dB

0 dB

-20 dB

-

16-bit

(Note 3)

-60 dB

Idle Channel Noise / Signal-to-noise ratio

Interchannel Isolation

-

114

90

-

dB

(1 kHz)

CS4383-BQ Dynamic Performance - All PCM modes and DSD (Note 4)

Specified Temperature Range

Dynamic Range (Note 2)

T_A

-40

-

85

°C

24-bit unweighted

A-Weighted

16-bit unweighted

(Note 3) A-Weighted

102

105

-

111

114

94

-

dB

97

Total Harmonic Distortion + Noise

(Note 2) THD+N

0 dB

24-bit

-

-100

-91

-51

-94

-74

-34

-91

dB

-20 dB

-60 dB

0 dB

-20 dB

-

16-bit

(Note 3)

-60 dB

Idle Channel Noise / Signal-to-noise ratio

Interchannel Isolation

-

114

90

-

dB

(1 kHz)

Notes: 1. CS4383-KQ parts are tested at 25 °C.

2. One-half LSB of triangular PDF dither is added to data.

3. Performance limited by 16-bit quantization noise.

4. CS4383-BQ parts are tested at the extremes of the specified temperature range and Min/Max

performance numbers are guaranteed across the specified temperature range, T_A. Typical numbers are

taken at 25 °C.

4

CS4383

ANALOG CHARACTERISTICS (Continued)

Parameters

Symbol

Min

88% V

Typ

92% V

Max

94% V

Units

Analog Output - All PCM modes and DSD

Full Scale Differential Output Voltage (Note 5)

Quiescent Voltage

V

Vpp

VDC

µA

FS

A

V

-

50% V

-

Q

A

Max Current from V

I

1

Q

QMAX

Interchannel Gain Mismatch

Gain Drift

-

0.1

100

-

dB

ppm/°C

Ω

-

Output Impedance

AC-Load Resistance

Load Capacitance

(Note 5)

Z

-

OUT

R

C

3

-

kΩ

L

-

100

pF

POWER AND THERMAL CHARACTERISTICS

Parameters

Symbol

Min

Typ

Max

Units

Power Supplies

Power Supply Current

(Note 6)

normal operation, V = 5V

I

-

60

45

30

2

84

200

66

70

46

-

mA

µA

A

D

V = 5V

D

V = 3.3V

D

I

LC

Interface current, VLC=5V (Note 7, 8)

VLS=5V

I

LS

I

pd

power-down state (all supplies) (Note 9)

Power Dissipation

VA = 5 V, VD = 3.3 V

(Note 6)

normal operation

-

400

1

525

1

485

mW

power-down (Note 9)

normal operation

power-down (Note 9)

-

680

-

VA = 5 V, VD = 5 V

Package Thermal Resistance

θ

-

48

15

-

°C/Watt

JA

JC

Power Supply Rejection Ratio (Note 10)

(1 kHz) PSRR

(60 Hz)

-

60

40

-

dB

Notes: 5.

V

is tested under load R and includes attenuation due to Z

FS L OUT

6. Current consumption increases with increasing FS within a given speed mode and is signal dependant.

Max values are based on highest FS and highest MCLK.

7.

I

measured with no external loading on the SDA pin.

LC

8. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied

or pulled low. Logic tied to pin 16 needs to be able to sink this current.

9. Power down mode is defined as RST pin = Low with all clock and data lines held static.

10. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.

5

CS4383

ANALOG FILTER RESPONSE

Fast Roll-Off

Typ

Slow Roll-Off (Note 11)

Parameter

Min

Max

Min

Typ

Max

Unit

Combined Digital and On-chip Analog Filter Response - Single Speed Mode (Note 12)

Passband (Note 13)

to -0.01 dB corner

to -3 dB corner

0

-

.454

.499

+0.01

-

0

-

0.417

0.499

+0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

-0.01

.547

90

-

-0.01

.583

64

(Note 14)

-

Group Delay

12/Fs

-

6.5/Fs

Passband Group Delay Deviation 0 - 20 kHz

-

±0.41/Fs

±0.23

±0.14

±0.09

-

±0.14/Fs

±0.23

±0.14

±0.09

s

De-emphasis Error (Note 15)

(Relative to 1kHz)

Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

-

dB

Combined Digital and On-chip Analog Filter Response - Double Speed Mode - 96kHz (Note 12)

Passband (Note 13)

to -0.01 dB corner

to -3 dB corner

0

-

.430

.499

0.01

-

0

-

.296

.499

0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Group Delay

Passband Group Delay Deviation 0 - 20 kHz

-0.01

.583

80

-

-0.01

.792

70

(Note 14)

-

4.6/Fs

-

3.9/Fs

-

±0.03/Fs

±0.01/Fs

s

Combined Digital and On-chip Analog Filter Response - Quad Speed Mode - 192kHz (Note 12)

Passband (Note 13)

to -0.01 dB corner

to -3 dB corner

0

-

.105

.490

0.01

-

0

-

.104

.481

0.01

-

Fs

dB

Fs

dB

s

Frequency Response 10 Hz to 20 kHz

StopBand

StopBand Attenuation

Group Delay

Passband Group Delay Deviation 0 - 20 kHz

-0.01

.635

90

-

-0.01

.868

75

(Note 14)

-

4.7/Fs

-

4.2/Fs

-

±0.01/Fs

s

Combined Digital and On-chip Analog Filter Response - DSD Mode (Note 12)

Passband (Note 13)

to -0.1 dB corner

to -3 dB corner

-

0

-.01

-

20

120

0.1

kHz

dB

Frequency Response 10 Hz to 20 kHz

Notes: 11. Slow Roll-Off interpolation filter is only available in control port mode.

12. Filter response is not tested but is guaranteed by design.

13. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 9 to 32) have

been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

14. Single and Double Speed Mode Measurement Bandwidth is from stopband to 3 Fs.

Quad Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.

15. De-emphasis is available only in Single Speed Mode; Only 44.1kHz De-emphasis is available in Stand-

Alone Mode

6

CS4383

DIGITAL CHARACTERISTICS (For KQ T = -10 to +70 °C; For BQ T = -40 to +85 °C; VLC = VLS =

A

1.8 V to 5.5 V)

Parameters

Symbol

Min

Typ

Max

Units

V

70% VLS

70% VLC

-

V

High-Level Input Voltage

Low-Level Input Voltage

Serial Data Port

Control Port

IH

V

-

20% VLS

20% VLC

V

Serial Data Port

Control Port

IL

Input Leakage Current

Input Capacitance

(Note 8)

I

-

8

±10

µA

pF

mA

V

in

-

Maximum MUTEC Sink Current

MUTEC High-Level Output Voltage

MUTEC Low-Level Output Voltage

3

V

VA

0

OH

V

OL

ABSOLUTE MAXIMUM RATINGS (GND = 0V; all voltages with respect to ground.)

Parameters

Symbol

Min

Max

Units

DC Power Supply

Analog power

Digital internal power

Serial data port interface power

Control port interface power

VA

VD

VLS

VLC

-0.3

6.0

V

Input Current, Any Pin Except Supplies

Digital Input Voltage Serial data port interface

Control port interface

I

-

±10

mA

in

V

-0.3

VLS+ 0.4

VLC+ 0.4

V

IND-S

IND-C

Ambient Operating Temperature (power applied)

Storage Temperature

T

-55

-65

125

150

°C

A

T

stg

WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is

not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground.)

Parameters

Symbol

Min

Typ

Max

Units

DC Power Supply

Analog power

Digital internal power

Serial data port interface power

Control port interface power

VA

VD

VLS

VLC

4.5

3.0

1.8

5.0

3.3

5.0

5.5

V

7

CS4383

SWITCHING CHARACTERISTICS (For KQ T = -10 to +70 °C; For BQ T = -40 to +85 °C; VLS =

A

1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLS, C = 30pF)

L

Parameters

Symbol

Min

Typ

Max

Units

MCLK Frequency

(Note 16)

Single Speed Mode

Double Speed Mode

Quad Speed Mode

1.024

6.400

40

-

51.2

60

MHz

%

-

MCLK Duty Cycle

Input Sample Rate

50

Single Speed Mode

Double Speed Mode

Quad Speed Mode

Fs

4

50

100

-

50

100

200

kHz

LRCK Duty Cycle

45

20

50

-

55

-

%

ns

SCLK Pulse Width Low

SCLK Pulse Width High

SCLK Period

t

sclkl

t

-

sclkh

-

2

sclkw

-----------------

MCLK

(Note 17)

t

-

ns

4

-----------------

MCLK

SCLK rising to LRCK edge delay

t

20

-

ns

slrd

SCLK rising to LRCK edge setup time

SDATA valid to SCLK rising setup time

SCLK rising to SDATA hold time

t

slrs

t

sdlrs

t

sdh

Notes: 16. See Table 5 on page 26 for suggested MCLK frequencies

17. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.

.

LRCK

t

sclkh

slrs

t

slrd

t

sclkl

SCLK

t

sdh

sdlrs

SDATA

Figure 1. Serial Mode Input Timing

8

CS4383

DSD - SWITCHING CHARACTERISTICS (For KQ T = -10 to +70 °C; For BQ T = -40 to +85 °C;

A

Logic 0 = GND; VLS = 1.8 V to 5.5 V; Logic 1 = VLS Volts; C = 30 pF)

L

Parameter

Symbol

Min

4.096

40

Typ

Max

Unit

MHz

%

Master Clock Frequency

MCLK Duty Cycle

(Note 18)

-

50

-

38.4

(All DSD modes)

60

-

DSD_SCLK Pulse Width Low

DSD_SCLK Pulse Width High

DSD_SCLK Frequency

t

20

ns

sclkl

t

20

-

ns

sclkh

(64x Oversampled)

(128x Oversampled)

1.024

2.048

-

3.2

6.4

MHz

DSD_L / _R valid to DSD_SCLK rising setup time

DSD_SCLK rising to DSD_L or DSD_R hold time

t

20

-

ns

sdlrs

t

sdh

Note: 18. Min is 4 times 64x DSD or 2 times 128x DSD, and Max is 12 times 64x DSD or 6 times 128x DSD. The

proper MCLK to DSD_SCLK ratio must be set either by the DIF registers or the M0:2 pins

t

sclkh

t

sclkl

DSD_SCLK

t

sdlrs

sdh

DSD_L, DSD_R

Figure 2. Direct Stream Digital - Serial Audio Input Timing

9

CS4383

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (For KQ T

A

= -10 to +70 °C; For BQ T = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,

A

C = 30 pF)

L

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

f

-

100

kHz

scl

RST Rising Edge to Start

t

500

4.7

4.0

4.7

4.0

4.7

0

-

ns

µs

ns

µs

ns

µs

ns

irs

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)

Clock Low time

t

-

buf

t

-

hdst

t

-

low

Clock High Time

t

-

high

Setup Time for Repeated Start Condition

SDA Hold Time from SCL Falling

SDA Setup time to SCL Rising

Rise Time of SCL and SDA

t

-

sust

(Note 17)

(Note 18)

t

-

hdd

t

250

-

sud

t , t

1

rc rc

Fall Time SCL and SDA

t , t

-

300

-

fc fc

Setup Time for Stop Condition

Acknowledge Delay from SCL Falling

t

4.7

-

susp

t

(Note 21)

ack

Notes: 19. Data must be held for sufficient time to bridge the transition time, t , of SCL.

fc

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

15

256 × Fs

15

128 × Fs

15

64 × Fs

--------------------

-----------------

21.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

R S T

t

irs

R e p e a te d

S ta rt

Stop

S t a rt

Stop

t

rd

fd

S D A

S C L

t

buf

t

susp

high

hdst

fc

hdst

t

sust

sud

ack

rc

lo w

hdd

2

Figure 3. Control Port Timing - I C Format

10

CS4383

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(For KQ T = -10 to +70 °C; For BQ T = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,

A

C = 30 pF)

L

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

f

-

MHz

MCLK

-----------------

sclk

2

-

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

t

500

1.0

20

ns

µs

ns

srs

(Note 20)

t

spi

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

t

csh

css

t

1

scl

sch

dsu

-----------------

MCLK

CCLK High Time

t

-

ns

1

-----------------

MCLK

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

t

40

15

-

ns

(Note 21)

(Note 22)

t

-

dh

t

100

r2

t

-

f2

Notes: 22. t only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.

spi

23. Data must be held for sufficient time to bridge the transition time of CCLK.

24. For F

< 1 MHz.

SCK

RS T

t

srs

spi

CS

t

css

scl

sch

t

csh

C CLK

t

r2

f2

C DIN

t

dsu

dh

Figure 4. Control Port Timing - SPI Format

11

CS4383

2. REGISTER QUICK REFERENCE

Addr

Function

7

6

5

4

3

2

1

0

01h Mode Control 1

default

CPEN

FREEZE

DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS

PDN

1

MCLKDIV

0

DIF2

0

DIF0

0

DIF1

0

02h Mode Control 2

default

Reserved

Reserved Reserved Reserved Reserved

0

SZC1

1

0

03h Mode Control 3

default

SZC0

0

SNGLVOL RMP_UP MUTEC+/-

AMUTE

Reserved Reserved

0

1

DEM1

0

DEM0

0

RMP_DN

0

04h Filter Control

default

Reserved Reserved Reserved FILT_SEL Reserved

0

INV_A4

0

INV_B3

0

INV_A3

0

INV_B2

0

05h Invert Control

default

INV_B4

0

INV_A2

0

INV_B1

0

INV_A1

0

06h Mixing Control

Pair 1 (AOUTx1)

P1_A=B

P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0

P1FM1

P1FM0

0

1

0

1

0

default

07h Vol. Control A1

default

A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

0

08h Vol. Control B1

default

B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

0

09h Mixing Control

Pair 2 (AOUTx2)

P2_A=B

P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0

P2FM1

P2FM0

0

1

0

1

0

default

0Ah Vol. Control A2

default

A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

0

0Bh Vol. Control B2

default

B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

0

0Ch Mixing Control

Pair 3 (AOUTx3)

P3_A=B

P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0

P3FM1

P3FM0

0

1

0

1

0

default

0Dh Vol. Control A3

default

A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0

0

0Eh Vol. Control B3

default

B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

0

0Fh Mixing Control

Pair 4 (AOUTx4)

P4_A=B

P4ATAPI4 P4ATAPI3 P4ATAPI2 P4ATAPI1 P4ATAPI0

P4FM1

P4FM0

0

1

0

1

0

default

10h Vol. Control A4

default

A4_MUTE A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0

0

11h Vol. Control B4

default

B4_MUTE B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0

0

PART3

1

0

PART2

0

PART1

1

0

PART0

0

12h Chip Revision

default

Reserved Reserved Reserved Reserved

-

14

CS4383

3. REGISTER DESCRIPTION

2

Note: All registers are read/write in I C mode and write only in SPI, unless otherwise noted.

3.1

Mode Control 1 (address 01h)

7

CPEN

0

6

FREEZE

0

5

MCLKDIV

0

4

DAC4_DIS

0

3

DAC3_DIS

0

2

1

0

PDN

1

DAC2_DIS

0

DAC1_DIS

0

3.1.1 CONTROL PORT ENABLE (CPEN)

Default = 0

0 - Disabled

1 - Enabled

Function:

This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode

can be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by

the registers and the pin definitions will conform to Control Port Mode. To accomplish a clean power-

up, the user should write this bit within 10 ms following the release of Reset.

3.1.2 FREEZE CONTROLS (FREEZE)

Default = 0

0 - Disabled

1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until

the FREEZE is disabled. To make multiple changes in the Control port registers take effect simulta-

neously, enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.

3.1.3 MASTER CLOCK DIVIDE ENABLE (MCLKDIV)

Default = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all

other internal circuitry.

3.1.4 DAC PAIR DISABLE (DACX_DIS)

Default = 0

0 - Enabled

1 - Disabled

Function:

When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.

It is advised that changes to these bits be made while the power down bit is enabled to eliminate the

possibility of audible artifacts.

15

CS4383

3.1.5 POWER DOWN (PDN)

Default = 1

0 - Disabled

1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the

control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and

must be disabled before normal operation in Control Port mode can occur.

3.2

Mode Control 2 (address 02h)

7

6

DIF2

0

5

DIF1

0

4

DIF0

0

3

Reserved

0

2

Reserved

0

1

Reserved

0

Reserved

0

Reserved

0

3.2.1 DIGITAL INTERFACE FORMAT (DIF)

Default = 000 - Format 0 (Left Justified, up to 24-bit data)

Function:

These bits select the interface format for the serial audio input. The Functional Mode bits determine

whether PCM or DSD mode is selected.

PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined

by the Digital Interface Format and the options are detailed in Figures 33-38.

DIF2

DIF1

DIF0

DESCRIPTION

Format

FIGURE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

33

34

35

36

37

38

Left Justified, up to 24-bit data

I S, up to 24-bit data

2

Right Justified, 16-bit data

Right Justified, 24-bit data

Right Justified, 20-bit data

Right Justified, 18-bit data

Reserved

Table 1. Digital Interface Formats - PCM Mode

DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required

Master clock to DSD data rate is defined by the Digital Interface Format pins.

DIF2

DIF1

DIFO

DESCRIPTION

0

1

0

1

0

1

0

1

0

1

0

1

0

1

64x oversampled DSD data with a 4x MCLK to DSD data rate

64x oversampled DSD data with a 6x MCLK to DSD data rate

64x oversampled DSD data with a 8x MCLK to DSD data rate

64x oversampled DSD data with a 12x MCLK to DSD data rate

128x oversampled DSD data with a 2x MCLK to DSD data rate

128x oversampled DSD data with a 3x MCLK to DSD data rate

128x oversampled DSD data with a 4x MCLK to DSD data rate

128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 2. Digital Interface Formats - DSD Mode

16

CS4383

3.3

Mode Control 3 (address 03h)

7

SZC1

1

6

SZC0

0

5

SNGLVOL

0

4

RMP_UP

0

3

MUTEC+/-

0

2

AMUTE

1

Reserved

0

Reserved

0

3.3.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)

Default = 10

00 - Immediate Change

01 - Zero Cross

10 - Soft Ramp

11 - Soft Ramp on Zero Crossings

Function:

Immediate Change

When Immediate Change is selected all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will

occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur

after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample

rate) if the signal does not encounter a zero crossing. The zero cross function is independently mon-

itored and implemented for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally

ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock

periods.

Soft Ramp on Zero Crossing

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes

or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level

change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms

at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is

independently monitored and implemented for each channel.

17

CS4383

3.3.2 SINGLE VOLUME CONTROL (SNGLVOL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control

Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel

Volume Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.

3.3.3 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)

Default = 0

0 - Disabled

1 - Enabled

Function:

An un-mute will be performed after executing a filter mode change, after a LRCK/MCLK ratio change

or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is ef-

fected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control 3 register.

When disabled, an immediate un-mute is performed in these instances.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_DN

bit.

3.3.4 MUTEC POLARITY (MUTEC +/-)

Default = 0

0 - Active Low

1 - Active High

Function:

The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the

MUTEC pins are low when active. When set to 1 the MUTEC pin(s) are high when active.

Note: When the on board mute circuitry is designed for active high, the MUTEC outputs will be low

(un-muted) for the period of time during reset and before this bit is enabled to 1.

3.3.5 AUTO-MUTE (AMUTE)

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio

samples of static 0 or -1. A single sample of non-static data will release the mute. Detection and

muting is done independently for each channel. The quiescent voltage on the output will be retained

and the Mute Control pin will go active during the mute period. The muting function is affected, similar

to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register.

18

CS4383

3.4

Filter Control (address 04h)

7

6

Reserved

0

5

Reserved

0

4

FILT_SEL

0

3

Reserved

0

2

DEM1

0

1

DEM0

0

RMP_DN

0

Reserved

0

3.4.1 INTERPOLATION FILTER SELECT (FILT_SEL)

Default = 0

0 - Fast roll-off

1 - Slow roll-off

Function:

This Function allows the user to select whether the interpolation filter has a fast or slow roll off. For

filter characteristics please see Section 1.

3.4.2 DE-EMPHASIS CONTROL (DEM)

Default = 00

00 - Disabled

01 - 44.1 kHz

10 - 48 kHz

11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-

sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 39)

De-emphasis is only available in Single Speed Mode.

3.4.3 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)

Default = 0

0 - Disabled

1 - Enabled

Function:

A mute will be performed prior to executing a filter mode change. When this feature is enabled, this

mute is effected, similar to attenuation changes, by the Soft and Zero Cross bits in the Mode Control

3 register. When disabled, an immediate mute is performed prior to executing a filter mode change.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP

bit.

19

CS4383

3.5

Invert control (address 05h)

7

INV_B4

0

6

INV_A4

0

5

INV_B3

0

4

INV_A3

0

3

INV_B2

0

2

INV_A2

0

1

INV_B1

0

INV_A1

0

3.5.1 INVERT SIGNAL POLARITY (INV_XX)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

3.6

Mixing Control Pair 1 (Channels A1 & B1)(address 06h)

Mixing Control Pair 2 (Channels A2 & B2)(address 09h)

Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)

Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)

7

Px_A=B

0

6

PxATAPI4

0

5

PxATAPI3

1

4

PxATAPI2

0

3

PxATAPI1

0

2

PxATAPI0

1

PxFM1

0

PxFM0

0

3.6.1 CHANNEL A VOLUME = CHANNEL B VOLUME (A=B)

Default = 0

0 - Disabled

1 - Enabled

Function:

The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel

Volume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are

determined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Chan-

nel Bytes are ignored when this function is enabled.

3.6.2 ATAPI CHANNEL MIXING AND MUTING (ATAPI)

Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)

Function:

The CS4383 implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI

functions are applied per A-B pair. Refer to Table 3 and Figure 41 for additional information

20

CS4383

.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0

AOUTAx

MUTE

aR

AOUTBx

MUTE

bR

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

bL

b[(L+R)/2]

MUTE

bR

aR

aL

bL

b[(L+R)/2]

MUTE

bR

bL

b[(L+R)/2]

MUTE

bR

a[(L+R)/2]

MUTE

aR

bL

b[(L+R)/2]

MUTE

bR

bL

[(aL+bR)/2]

MUTE

bR

aR

aL

bL

[(bL+aR)/2]

MUTE

bR

bL

[(aL+bR)/2]

MUTE

bR

[(aL+bR)/2]

[(bL+aR)/2]

[(aL+bR)/2]

bL

[(aL+bR)/2]

Table 3. ATAPI Decode

3.6.3 FUNCTIONAL MODE (FM)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates)

01 - Double-Speed Mode (50 to 100 kHz sample rates)

10 - Quad-Speed Mode (100 to 200 kHz sample rates)

11 - Direct Stream Digital Mode

Function:

Selects the required range of input sample rates or DSD Mode. When DSD mode is selected for any

channel pair then all pairs will switch to DSD mode.

21

CS4383

3.7

Volume control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh, 10h, 11h)

7

6

xx_VOL6

0

5

xx_VOL5

0

4

xx_VOL4

0

3

xx_VOL3

0

2

xx_VOL2

0

1

xx_VOL1

0

xx_VOL0

0

xx_MUTE

0

3.7.1 MUTE (MUTE)

Default = 0

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output

will be retained. The muting function is effected, similar to attenuation changes, by the Soft and Zero

Cross bits. The MUTEC pins will go active during the mute period according to the MUTEC register.

3.7.2 VOLUME CONTROL (XX_VOL)

Default = 0 (No attenuation)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments

from 0 to -127 dB. Volume settings are decoded as shown in Table 4. The volume changes are imple-

mented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent

to enabling the MUTE bit.

Binary Code

0000000

0010100

0101000

0111100

Decimal Value

Volume Setting

0 dB

0

20

40

60

90

-20 dB

-40 dB

-60 dB

-90 dB

1011010

Table 4. Example Digital Volume Settings

22

CS4383

3.8

Chip Revision (address 12h)

7

PART3

1

6

PART2

0

5

PART1

1

4

PART0

1

3

2

1

0

Reserved

-

Reserved

-

Reserved

-

Reserved

-

3.8.1 PART NUMBER ID (PART) [READ ONLY]

1011 - CS4383

Function:

This read-only register can be used to identify the model number of the device.

23

CS4383

4. PIN DESCRIPTION

48 47 46 4 5 44 43 42 41 40 39 38 37

36

AOUTA2-

DSDA2

DSDB1

1

2

35

34

33

32

AOUTA2+

AOUTB2+

AOUTB2-

DSDA1

VD

3

4

5

GND

VA

31

MCLK

GND

6

CS4383

LRCK (DSD_EN)

SDIN1

7

AOUTA3-

AOUTA3+

AOUTB3+

30

29

28

27

26

25

8

SCLK

9

10

11

12

TST

AOUTB3-

AOUTA4-

AOUTA4+

SDIN2

SDIN3

13 14 15 1 6 17 18 19 20 21 22 23 24

Pin Name

VD

#

Pin Description

4

Digital Power (Input) - Positive power supply for the digital section. Refer to the Recommended Operat-

ing Conditions for appropriate voltages.

GND

5

Ground (Input) - Ground reference. Should be connected to analog ground.

31

MCLK

LRCK

6

Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Table 5 illustrates

several standard audio sample rates and the required master clock frequency.

7

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio

data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

SDIN1

SDIN2

SDIN3

SDIN4

8

11

12

13

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

SCLK

VLC

RST

FILT+

VQ

9

Serial Clock (Input) - Serial clock for the serial audio interface.

17 Control Port Power (Input) - Determines the required signal level for the control port. Refer to the Rec-

ommended Operating Conditions for appropriate voltages.

18 Reset (Input) - The device enters a low power mode and all internal registers are reset to their default

settings when low.

20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

Requires the capacitive decoupling to analog ground, as shown in the Typical Connection Diagram.

21

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively

coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is

specified in the Analog Characteristics and Specifications section. VQ presents an appreciable source

impedance and any current drawn from this pin will alter device performance. However, VQ can be

used to bias the analog circuitry assuming there is no AC signal component and the DC current is less

than the maximum specified in the Analog Characteristics and Specifications section.

24

CS4383

Pin Name

#

Pin Description

MUTEC1

MUTEC2

MUTEC3

41

22

19

Mute Control (Output) - The Mute Control pins go low during power-up initialization, reset, muting,

power-down or if the master clock to left/right clock frequency ratio is incorrect. These pins are intended

to be used as a control for external mute circuits to prevent the clicks and pops that can occur in any sin-

gle supply system. The use of external mute circuits are not mandatory but may be desired for designs

requiring the absolute minimum in extraneous clicks and pops.

AOUTA1 +,- 39, 40 Differential Analog Output (Output) - The full scale differential analog output level is specified in the

AOUTB1 +,- 38, 37 Analog Characteristics specification table.

AOUTA2 +,- 35, 36

AOUTB2 +,- 34, 33

AOUTA3 +,- 29, 30

AOUTB3 +,- 28, 27

AOUTA4 +,- 25, 26

AOUTB4 +,- 24, 23

VA

32

Analog Power (Input) - Positive power supply for the analog section. Refer to the Recommended Oper-

ating Conditions for appropriate voltages.

VLS

43 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-

face. Refer to the Recommended Operating Conditions for appropriate voltages.

Control Port Definitions

SCL/CCLK

14 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up

2

resistor to the logic interface voltage in I C mode as shown in the Typical Connection Diagram.

2

SDA/CDIN

15 Serial Control Data (Input/Output) - SDA is a data I/O line in I C mode and requires an external pull-up

resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input

data line for the control port interface in SPI mode.

2

AD0/CS

16 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I C mode;

CS is the chip select signal for SPI format.

Stand-Alone Definitions

M0

M1

M2

M3

16

15

14

42

Mode Selection (Input) - Determines the operational mode of the device as detailed in Tables 6 and 7.

DSD Definitions

DSD_SCLK

42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.

DSD_EN

7

DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone mode only).

Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.

DSDA1

DSDB1

DSDA2

DSDB2

DSDA3

DSDB3

DSDA4

DSDB4

3

2

1

48

47

46

45

44

TST

10 Test - This pin needs to be tied to analog ground.

25

CS4383

Control port

only modes

Mode

(sample-rate range)

Sample

Rate

MCLK (MHz)

(kHz)

MCLK Ratio

256x

8.1920

11.2896

12.2880

128x

384x

512x

768x

1024x*

32.7680

45.1584

49.1520

512x*

32

44.1

48

12.2880

16.9344

18.4320

192x

16.3840

22.5792

24.5760

256x

24.5760

33.8688

36.8640

384x

Single Speed

(4 to 50 kHz)

MCLK Ratio

64

88.2

96

8.1920

11.2896

12.2880

64x

12.2880

16.9344

18.4320

96x

16.3840

22.5792

24.5760

128x

24.5760

33.8688

36.8640

192x

32.7680

45.1584

49.1520

256x*

Double Speed

(50 to 100 kHz)

MCLK Ratio

176.4

192

11.2896

12.2880

16.9344

18.4320

22.5792

24.5760

33.8688

36.8640

45.1584

49.1520

Quad Speed

(100 to 200 kHz)

Table 5. Common Clock Frequencies

*Note: These modes are only available in control port mode by setting the MCLKDIV bit = 1.

M1

M0

DESCRIPTION

FORMAT

FIGURE

(DIF1)

(DIF0)

Left Justified, up to 24-bit data

0

1

0

1

33

34

2

I S, up to 24-bit data

Right Justified, 16-bit Data

Right Justified, 24-bit Data

1

0

1

2

3

35

36

Table 6. Digital Interface Format, Stand-Alone Mode Options

M3

M2

DESCRIPTION

(DEM)

Single-Speed without De-Emphasis (4 to 50 kHz sample rates)

Single-Speed with 44.1kHz De-Emphasis; see Figure 39

Double-Speed (50 to 100 kHz sample rates)

0

1

0

1

0

1

Quad-Speed (100 to 200 kHz sample rates)

Table 7. Mode Selection, Stand-Alone Mode Options

DSD_Mode

M2

M1

M0

DESCRIPTION

(LRCK1)

64x oversampled DSD data with a 4x MCLK to DSD data rate

64x oversampled DSD data with a 6x MCLK to DSD data rate

64x oversampled DSD data with a 8x MCLK to DSD data rate

64x oversampled DSD data with a 12x MCLK to DSD data rate

128x oversampled DSD data with a 2x MCLK to DSD data rate

128x oversampled DSD data with a 3x MCLK to DSD data rate

128x oversampled DSD data with a 4x MCLK to DSD data rate

128x oversampled DSD data with a 6x MCLK to DSD data rate

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Table 8. Direct Stream Digital (DSD), Stand-Alone Mode Options

26

CS4383

gle-Speed Mode (1024 LRCK cycles in Double-

Speed Mode, and 2048 LRCK cycles in Quad-

Speed Mode). Writing this bit will halt the Stand-

Alone power-up sequence and initialize the control

port to its default settings. The desired register set-

tings can be loaded while keeping the PDN bit set

to 1.

5. APPLICATIONS

5.1 Grounding and Power Supply

Decoupling

As with any high resolution converter, the CS4383

requires careful attention to power supply and

grounding arrangements to optimize performance.

Figures 5 & 6 show the recommended power ar-

rangement with VA, VD, VLS and VLC connected

to clean supplies. Decoupling capacitors should be

located as close to the device package as possible.

If desired, all supply pins may be connected to the

same supply, but a decoupling capacitor should still

be placed on each supply pin (see Section 1 for rec-

ommended voltages).

3. If Control Port Mode is selected via the CPEN

bit, set the PDN bit to 0 which will initiate the pow-

er-up sequence.

5.4

Analog Output and Filtering

The application note “Design Notes for a 2-Pole

Filter with Differential Input” discusses the sec-

ond-order Butterworth filter and differential to sin-

gle-ended converter which was implemented on the

CS4383 evaluation board, CDB4383, as seen in

Figure 42. The CS4383 does not include phase or

amplitude compensation for an external filter.

Therefore, the DAC system phase and amplitude

response will be dependent on the external analog

circuitry.

5.2

Oversampling Modes

The CS4383 operates in one of three oversampling

modes based on the input sample rate. Mode selec-

tion is determined by the M3 and M2 pins in Stand-

Alone mode or the FM bits in Control Port mode.

Single-Speed mode supports input sample rates up

to 50 kHz and uses a 128x oversampling ratio.

Double-Speed mode supports input sample rates up

to 100 kHz and uses an oversampling ratio of 64x.

Quad-Speed mode supports input sample rates up

to 200 kHz and uses an oversampling ratio of 32x.

5.5

Interpolation Filter

To accommodate the increasingly complex re-

quirements of digital audio systems, the CS4383

incorporates selectable interpolation filters for each

mode of operation. A “fast” and a “slow” roll-off

filter is available in each of Single, Double, and

Quad Speed modes. These filters have been de-

signed to accommodate a variety of musical tastes

and styles. The FILT_SEL bit is used to select

which filter is used (see the control port section for

more details).

5.3

Recommended Power-up Sequence

1. Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the

control port is reset to its default settings and VQ

will remain low.

2. Bring RST high. The device will remain in a low

power state with VQ low and will initiate the

Stand-Alone power-up sequence. The control port

will be accessible at this time. If Control Port oper-

ation is desired, write the CPEN bit prior to the

completion of the Stand-Alone power-up se-

quence, approximately 512 LRCK cycles in Sin-

When in stand-alone mode, only the “fast” roll-off

filter is available.

Filter specifications can be found in Section 1, and

filter response plots can be found in Figures 9 to 32.

27

CS4383

control port is enabled, these pins are dedicated to

control port functionality.

5.6

Using DSD mode

In stand-alone mode, DSD operation is selected by

holding DSD_EN(LRCK) high and applying the

DSD data and clocks to the appropriate pins. The

M2:0 pins set the expected DSD rate and MCLK

ratio.

To prevent audible artifacts the CPEN bit (see Sec-

tion 3.1.1) should be set prior to the completion of

the Stand-Alone power-up sequence, approximate-

ly 1024 LRCK cycles. Writing this bit will halt the

Stand-Alone power-up sequence and initialize the

control port to its default settings. Note, the CP_EN

bit can be set any time after RST goes high; how-

ever, setting this bit after the Stand-Alone power-

up sequence has completed can cause audible arti-

facts.

In control-port mode the FM bits set the device into

DSD mode (DSD_EN pin is not required to be held

high). The DIF register then controls the expected

DSD rate and MCLK ratio.

During DSD operation, the PCM related pins

should either be tied low or remain active with

clocks (except LRCK in Stand-Alone mode).

When the DSD related pins are not being used they

should either be tied static low, or remain active

with clocks (except M3 in Stand-Alone mode).

6.2

Format Selection

The control port has 2 formats: SPI and I²C, with

the CS4383 operating as a slave device.

If I²C operation is desired, AD0/CS should be tied

to VLC or GND. If the CS4383 ever detects a high

to low transition on AD0/CS after power-up and af-

ter the control port is activated , SPI format will be

selected.

6. CONTROL PORT INTERFACE

The control port is used to load all the internal set-

tings. The operation of the control port may be

completely asynchronous with the audio sample

rate. However, to avoid potential interference prob-

lems, the control port pins should remain static if

no operation is required.

6.3

I²C Format

In I²C Format, SDA is a bidirectional data line.

Data is clocked into and out of the part by the clock,

SCL, with a clock to data relationship as shown in

Figure 7. The receiving device should send an ac-

knowledge (ACK) after each byte received. There

is no CS pin. Pin AD0 forms the partial chip ad-

dress and should be tied to VLC or GND as re-

quired. The upper 6 bits of the 7 bit address field

must be 001100.

The CS4383 has MAP auto increment capability,

enabled by the INCR bit in the MAP register,

which is the MSB. If INCR is 0, then the MAP will

stay constant for successive writes. If INCR is set

to 1, then MAP will auto increment after each byte

is written from register 01h to 08h and then from

09h and 11h, allowing block reads or writes of suc-

cessive registers in two separate sections (the

counter will not auto-increment to register 09h

from register 08h).

Note: MCLK is required during all I²C transac-

tions. Please see reference 4 for further details.

6.3.1 Writing in I²C Format

6.1

Enabling the Control Port

To communicate with the CS4383, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (low for a write). The next byte is the

Memory Address Pointer, MAP, which selects the

register to be read or written. The MAP is then fol-

On the CS4383 the control port pins are shared

with stand-alone configuration pins. To enable the

control port, the user must set the CPEN bit. This

is done by performing a I²C or SPI write. Once the

28

CS4383

lowed by the data to be written. To write multiple

registers, continue providing a clock and data,

waiting for the CS4383 to acknowledge between

each byte. To end the transaction, send a STOP

condition.

address is 0011000. CS, CCLK and CDIN are all

inputs and data is clocked in on the rising edge of

CCLK.

Note that the CS4383 is write-only when in SPI

format.

6.3.2 Reading in I²C Format

6.4.1 Writing in SPI

To communicate with the CS4383, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (high for a read). The contents of the reg-

ister pointed to by the MAP will be output after the

chip address. To read multiple registers, continue

providing a clock and issue an ACK after each

byte. To end the transaction, send a STOP condi-

tion.

Figure 8 shows the operation of the control port in

SPI format. To write to a register, bring CS low.

The first 7 bits on CDIN form the chip address and

must be 0011000. The eighth bit is a read/write in-

dicator (R/W), which must be low to write. The

next 8 bits form the Memory Address Pointer

(MAP), which is set to the address of the register

that is to be updated. The next 8 bits are the data

which will be placed into register designated by the

MAP. To write multiple registers, keep CS low and

continue providing clocks on CCLK. End the read

transaction by setting CS high.

6.4

SPI Format

In SPI format, CS is the CS4383 chip select signal,

CCLK is the control port bit clock, CDIN is the in-

put data line from the microcontroller and the chip

N o te 1

A D DR

D ATA

1-8

D A TA

1-8

001100

R /W

A C K

AC K

S D A

S C L

AD 0

S ta rt

S top

N o te: If o peratio n is a w rite , th is byte co nta in s the M em o ry A dd ress P o inte r, M A P .

2

Figure 7. Control Port Timing, I C Format

C S

C C L K

C H IP

A D D R E S S

M A P

D A TA

0 0 1 1 0 00

LS B

C D IN

M S B

R /W

b y te 1

b yte n

M A P = M e m o ry A d d re s s P o in te r

Figure 8. Control Port Timing, SPI Format

29

CS4383

6.5

Memory Address Pointer (MAP)

7

INCR

0

6

Reserved

0

5

Reserved

0

4

MAP4

0

3

MAP3

0

2

MAP2

0

1

MAP1

0

MAP0

0

6.5.1 INCR (AUTO MAP INCREMENT ENABLE)

Default = ‘0’

0 - Disabled

1 - Enabled

Note: When Auto Map Increment is enabled, the register must be written it two separate blocks: from

register 01h to 08h and then from 09h and 11h. The counter will not auto-increment to register 09h from

register 08h

6.5.2 MAP4-0 (MEMORY ADDRESS POINTER)

Default = ‘00000’

30

CS4383

0

20

40

20

40

60

80

100

120

100

120

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 9. Single Speed (fast) Stopband Rejection

Figure 10. Single Speed (fast) Transition Band

0

1

0.02

0.015

0.01

2

3

0.005

0

4

5

6

0.005

0.01

7

8

0.015

0.02

9

10

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

Frequency(normalized to Fs)

Figure 11. Single Speed (fast) Transition Band (detail)

Figure 12. Single Speed (fast) Passband Ripple

0

20

40

60

80

100

120

100

120

0.4

0.5

0.6

0.7

0.8

0.9

1

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

Frequency(normalized to Fs)

Figure 13. Single Speed (slow) Stopband Rejection

Figure 14. Single Speed (slow) Transition Band

31

CS4383

0.02

0.015

0.01

0

1

2

3

0.005

0

4

5

6

0.005

0.01

7

8

0.015

0.02

9

10

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

Frequency(normalized to Fs)

Figure 15. Single Speed (slow) Transition Band (detail)

Figure 16. Single Speed (slow) Passband Ripple

0

20

40

60

80

100

120

100

120

0.4

0.42

0.44

0.46

0.48

0.5

0.52

0.54

0.56

0.58

0.6

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 17. Double Speed (fast) Stopband Rejection

Figure 18. Double Speed (fast) Transition Band

0

1

0.02

0.015

0.01

2

3

0.005

0

4

5

6

0.005

0.01

7

8

0.015

0.02

9

10

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency(normalized to Fs)

Figure 19. Double Speed (fast) Transition Band (detail)

Figure 20. Double Speed (fast) Passband Ripple

32

CS4383

0

20

40

20

40

60

80

100

120

100

120

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 21. Double Speed (slow) Stopband Rejection

Figure 22. Double Speed (slow) Transition Band

0

1

0.02

0.015

0.01

2

3

0.005

0

4

5

6

0.005

0.01

7

8

0.015

0.02

9

10

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Frequency(normalized to Fs)

Figure 23. Double Speed (slow) Transition Band (detail)

Figure 24. Double Speed (slow) Passband Ripple

0

20

40

60

80

100

120

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 25. Quad Speed (fast) Stopband Rejection

Figure 26. Quad Speed (fast) Transition Band

33

CS4383

0

0.2

0.15

0.1

1

2

3

0.05

0

4

5

6

0.05

7

0.1

0.15

0.2

8

9

10

0

0.05

0.1

0.15

0.2

0.25

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

Frequency(normalized to Fs)

Figure 27. Quad Speed (fast) Transition Band (detail)

Figure 28. Quad Speed (fast) Passband Ripple

0

20

40

20

40

60

80

100

120

100

120

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency(normalized to Fs)

Figure 29. Quad Speed (slow) Stopband Rejection

Figure 30. Quad Speed (slow) Transition Band

0

1

0.02

0.015

0.01

0.005

0

2

3

4

5

6

0.005

0.01

0.015

0.02

7

8

9

10

0.45

0.46

0.47

0.48

0.49

0.5

0.51

0.52

0.53

0.54

0.55

0

0.02

0.04

0.06

0.08

0.1

0.12

Frequency(normalized to Fs)

Figure 31. Quad Speed (slow) Transition Band (detail)

Figure 32. Quad Speed (slow) Passband Ripple

34

CS4383

Left Channel

Right Channel

LRCK

SCLK

MSB

LSB

MSB

LSB

SDINx

-1 -2 -3 -4 -5

+5 +4 +3 +2 +1

-2 -3 -4

+5 +4 +3 +2 +1

-1

Figure 33. Format 0 - Left Justified up to 24-bit Data

Left Channel

Right Channel

LRCK

SCLK

LSB

MSB

LSB

SDINx

MSB

+5 +4 +3 +2 +1

-1 -2 -3 -4 -5

-1 -2 -3 -4

2

Figure 34. Format 1 - I S up to 24-bit Data

Right Channel

LRCK

SCLK

Left Channel

SDINx

9

8

7

6

5

4

3

2

1

0

9

15 14 13 12 11 10

8

7

6

5

4

3

2

1

0

15 14 13 12 11 10

32 clocks

Figure 35. Format 2 - Right Justified 16-bit Data

Right Channel

LRCK

SCLK

Left Channel

SDINx

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

23 22 21 20 19 18

32 clocks

23 22 21 20 19 18

Figure 36. Format 3 - Right Justified 24-bit Data

35

CS4383

Right Channel

LRCK

SCLK

Left Channel

SDINx

1

0

19 18 17 16

9

8

7

6

5

4

3

2

1

0

19 18 17 16

9

15 14 13 12 11 10

8

7

6

5

4

3 2 1 0

15 14 13 12 11 10

32 clocks

Figure 37. Format 4 - Right Justified 20-bit Data

Right Channel

LRCK

SCLK

Left Channel

SDINx

1

0

17 16 15 14 13 12 11 10

32 clocks

9

8

7

6

5

4

3

2

1

0

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Figure 38. Format 5 - Right Justified 18-bit Data

Gain

dB

T1=50 µs

0dB

T2 = 15 µs

-10dB

F1

F2

Frequency

3.183 kHz

10.61 kHz

Figure 39. De-Emphasis Curve

L

AOUTAx+

AOUTAx-

DAC

Channel

Pair x

Control

SDINx

AOUTBx+

AOUTBx-

R

Figure 40. Channel Pair Routing Diagram (x = Channel Pair 1, 2, 3, or 4)

36

CS4383

A Channel

Volume

Control

Left Channel

Audio Data

MUTE

AoutAx

Σ

SDINx

B Channel

Volume

Control

Right Channel

Audio Data

MUTE

AoutBx

Figure 41. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)

Figure 42. Recommended Output Filter

37

CS4383

7. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified

bandwidth (typically 10Hz to 20kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth

made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement

to full scale. This technique ensures that the distortion components are below the noise level and do not

effect the measurement. This measurement technique has been accepted by the Audio Engineering So-

ciety, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full scale analog output for a full scale digital input.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

8. REFERENCES

1. "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.

Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.

2. CDB4383 Evaluation Board Datasheet

3. “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note

AN48

2

4. “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.

http://www.semiconductors.philips.com

38

CS4383

9. PACKAGE DIMENSIONS

48L LQFP PACKAGE DRAWING

E

E1

D1

D

1

e

B

A

A1

L

INCHES

NOM

0.055

0.004

0.009

0.354

0.28

0.354

0.28

0.020

0.24

MILLIMETERS

NOM

DIM

A

A1

B

D

D1

E

E1

e*

L

MIN

---

MAX

MIN

---

MAX

1.60

0.15

0.27

9.30

7.10

9.30

7.10

0.60

0.75

7.00°

0.063

0.006

0.011

0.366

0.280

0.366

0.280

0.024

0.030

7.000°

1.40

0.10

0.22

0.002

0.007

0.343

0.272

0.343

0.272

0.016

0.018

0.000°

0.05

0.17

8.70

6.90

8.70

6.90

0.40

0.45

0.00°

9.0 BSC

7.0 BSC

9.0 BSC

7.0 BSC

0.50 BSC

0.60

4°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm.

JEDEC Designation: MS022

39


型号：	CDB4383
厂家：	CIRRUS LOGIC
描述：	114 dB, 192 kHz 8-Channel D/A Converter 114分贝192千赫8声道D / A转换器转换器
文件：	总40页 (文件大小：918K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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