CDB4382A [CIRRUS]
114 dB, 192 kHz 8-channel D/A Converter; 114分贝192千赫8声道D / A转换器
| 型号： | CDB4382A |
| 厂家： | 
CIRRUS LOGIC |
| 描述： | 114 dB, 192 kHz 8-channel D/A Converter |
| 文件： | 总47页 (文件大小：686K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CS4382A
114 dB, 192 kHz 8-channel D/A Converter
Features
Description
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
The CS4382A is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
one-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch shaping technology that
eliminates distortion due to capacitor mismatch. Follow-
ing this stage is a multi-element switched capacitor
stage and low-pass filter with differential analog
outputs.
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital Mode
– On-chip 50 kHz filter
– Matched PCM and DSD analog output
levels
The CS4382A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in-
termediate decimation stage.
Selectable Digital Filters
Volume Control with 1-dB Step Size and Soft
The CS4382A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers, digital TV’s, mixing consoles, effects
processors, sound cards and automotive audio
systems.
Ramp
Low Clock Jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
ORDERING INFORMATION
See page 41.
Control & Serial Audio Port
Supplies = 1.8 V to 5 V
Digital Supply = 2.5 V
Analog Supply = 5 V
Hardware Mode or
I2C/SPI Software Mode
Control Data
Internal Voltage
Reference
Register/Hardware
Configuration
Reset
Switch-Cap
DAC and
Analog Filters
8
8
Differential
Outputs
PCM Serial
Audio Input
Volume
Controls
Digital
Filters
Multi-bit ∆Σ
Modulators
8
External Mute
Control
Mute Signals
DSD Processor
-50 kHz filter
DSD Audio
Input
2
Copyright © Cirrus Logic, Inc. 2005
APR '05
DS618PP1
(All Rights Reserved)
http://www.cirrus.com
CS4382A
TABLE OF CONTENTS
1. PIN DESCRIPTION..................................................................................................................... 6
2. CHARACTERISTICS AND SPECIFICATIONS.......................................................................... 8
3. APPLICATIONS ....................................................................................................................... 20
3.1 Master Clock..................................................................................................................... 20
3.2 Mode Select...................................................................................................................... 20
3.3 Digital Interface Formats .................................................................................................. 22
3.4 Oversampling Modes........................................................................................................ 23
3.5 Interpolation Filter............................................................................................................. 23
3.6 De-Emphasis .................................................................................................................... 23
3.7 ATAPI Specification.......................................................................................................... 24
3.8 Direct Stream Digital (DSD) Mode.................................................................................... 25
3.9 Grounding and Power Supply Arrangements ................................................................... 25
3.9.1 Capacitor Placement............................................................................................ 25
3.10 Analog Output and Filtering............................................................................................ 25
3.11 Mute Control................................................................................................................... 26
3.12 Recommended Power-Up Sequence............................................................................. 27
3.12.1 Hardware Mode ................................................................................................. 27
3.12.2 Software Mode................................................................................................... 27
3.13 Recommended Procedure for Switching Operational Modes......................................... 27
3.14 Control Port Interface ..................................................................................................... 28
3.14.1 MAP Auto Increment.......................................................................................... 28
2
3.14.2 I C Mode............................................................................................................ 28
2
3.14.2.1 I C Write ............................................................................................ 28
2
3.14.2.2 I C Read ............................................................................................ 29
3.14.3 SPI™ Mode........................................................................................................ 30
3.14.3.1 SPI Write............................................................................................ 30
3.15 Memory Address Pointer (MAP)
............................................................................... 30
4. REGISTER QUICK REFERENCE............................................................................................ 31
5. REGISTER DESCRIPTION ...................................................................................................... 32
5.1 Mode Control 1 (address 01h).......................................................................................... 32
5.1.1 Control Port Enable (CPEN) ................................................................................ 32
5.1.2 Freeze Controls (Freeze)..................................................................................... 32
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv) ............................................................ 32
5.1.4 DAC Pair Disable (DACx_DIS) ............................................................................ 32
5.1.5 Power Down (PDN).............................................................................................. 33
5.2 Mode Control 2 (address 02h)......................................................................................... 33
5.2.1 Digital Interface Format (dif) ................................................................................ 33
5.2.2 Mode Control 3 (address 03h) ............................................................................ 34
5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC) ................................................... 34
5.2.4 Single Volume Control (Snglvol).......................................................................... 34
5.2.5 Soft Volume Ramp-Up after Error (RMP_UP) ..................................................... 35
5.2.6 MUTEC Polarity (MUTEC+/-)............................................................................... 35
5.2.7 Auto-Mute (AMUTE) ........................................................................................... 35
5.3 Mutec Pin Control (MUTEC)............................................................................................. 35
5.4 Filter Control (address 04h)............................................................................................. 36
5.4.1 Interpolation Filter Select (FILT_SEL).................................................................. 36
5.4.2 De-Emphasis Control (DEM) ............................................................................... 36
5.4.3 Soft Ramp-Down before Filter Mode Change (RMP_DN) ................................... 36
5.5 Invert Control (address 05h)............................................................................................ 37
5.5.1 Invert Signal Polarity (Inv_Xx).............................................................................. 37
5.6 Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
2
DS618PP1
CS4382A
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh) ............................................. 37
5.6.1 Channel A Volume = Channel B Volume (A=B)................................................... 37
5.6.2 ATAPI Channel Mixing and Muting (ATAPI) ........................................................ 37
5.6.3 Functional Mode (FM).......................................................................................... 38
5.7 Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh) .......................................... 39
5.7.1 Mute (MUTE) ....................................................................................................... 39
5.7.2 Volume Control (xx_VOL).................................................................................... 39
5.8 Chip Revision (address 12h) ........................................................................................... 40
5.8.1 Part Number ID (part) [Read Only] ...................................................................... 40
6. PARAMETER DEFINITIONS.................................................................................................... 41
7. REFERENCES.......................................................................................................................... 41
8. ORDERING INFORMATION .................................................................................................... 41
9. PACKAGE DIMENSIONS ........................................................................................................ 42
10. APPENDIX ............................................................................................................................. 43
DS618PP1
3
CS4382A
LIST OF FIGURES
Figure 1. Serial Audio Interface Timing..................................................................................................... 14
Figure 2. Direct Stream Digital - Serial Audio Input Timing....................................................................... 15
2
Figure 3. Control Port Timing - I C Format ............................................................................................... 16
Figure 4. Control Port Timing - SPI Format............................................................................................... 17
Figure 5. Typical Connection Diagram, Software Mode............................................................................ 18
Figure 6. Typical Connection Diagram, Hardware Mode .......................................................................... 19
Figure 7. Format 0 - Left-Justified up to 24-bit Data ................................................................................. 22
2
Figure 8. Format 1 - I S up to 24-bit Data................................................................................................. 22
Figure 9. Format 2 - Right-Justified 16-bit Data........................................................................................ 22
Figure 10. Format 3 - Right-Justified 24-bit Data...................................................................................... 22
Figure 11. Format 4 - Right-Justified 20-bit Data...................................................................................... 23
Figure 12. Format 5 - Right-Justified 18-bit Data...................................................................................... 23
Figure 13. De-Emphasis Curve................................................................................................................. 24
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, or 3) .................................................................. 24
Figure 15. Full-Scale Output ..................................................................................................................... 26
Figure 16. Recommended Output Filter.................................................................................................... 26
2
Figure 17. Control Port Timing, I C Mode................................................................................................. 29
Figure 18. Control Port Timing, SPI mode ................................................................................................ 30
Figure 19. Single-Speed (fast) Stopband Rejection.................................................................................. 43
Figure 20. Single-Speed (fast) Transition Band........................................................................................ 43
Figure 21. Single-Speed (fast) Transition Band (detail)............................................................................ 43
Figure 22. Single-Speed (fast) Passband Ripple...................................................................................... 43
Figure 23. Single-Speed (slow) Stopband Rejection ................................................................................ 43
Figure 24. Single-Speed (slow) Transition Band....................................................................................... 43
Figure 25. Single-Speed (slow) Transition Band (detail)........................................................................... 44
Figure 26. Single-Speed (slow) Passband Ripple..................................................................................... 44
Figure 27. Double-Speed (fast) Stopband Rejection ................................................................................ 44
Figure 28. Double-Speed (fast) Transition Band....................................................................................... 44
Figure 29. Double-Speed (fast) Transition Band (detail)........................................................................... 44
Figure 30. Double-Speed (fast) Passband Ripple..................................................................................... 44
Figure 31. Double-Speed (slow) Stopband Rejection............................................................................... 45
Figure 32. Double-Speed (slow) Transition Band ..................................................................................... 45
Figure 33. Double-Speed (slow) Transition Band (detail) ......................................................................... 45
Figure 34. Double-Speed (slow) Passband Ripple ................................................................................... 45
Figure 35. Quad-Speed (fast) Stopband Rejection................................................................................... 45
Figure 36. Quad-Speed (fast) Transition Band ......................................................................................... 45
Figure 37. Quad-Speed (fast) Transition Band (detail) ............................................................................. 46
Figure 38. Quad-Speed (fast) Passband Ripple ....................................................................................... 46
Figure 39. Quad-Speed (slow) Stopband Rejection.................................................................................. 46
Figure 40. Quad-Speed (slow) Transition Band........................................................................................ 46
Figure 41. Quad-Speed (slow) Transition Band (detail)............................................................................ 46
Figure 42. Quad-Speed (slow) Passband Ripple...................................................................................... 46
4
DS618PP1
CS4382A
LIST OF TABLES
Table 1. Common Clock Frequencies........................................................................................... 20
Table 2. Digital Interface Format, Stand-Alone Mode Options...................................................... 21
Table 3. Mode Selection, Stand-Alone Mode Options .................................................................. 21
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options............................................... 21
Table 5. Digital Interface Formats - PCM Mode............................................................................ 33
Table 6. Digital Interface Formats - DSD Mode ............................................................................ 33
Table 7. ATAPI Decode ................................................................................................................ 38
Table 8. Example Digital Volume Settings.................................................................................... 39
Table 9. Revision History ............................................................................................................. 47
DS618PP1
5
CS4382A
1. PIN DESCRIPTION
48 47 46 45 44 43 42 41 40 39 38 37
DSDA2
DSDB1
DSDA1
VD
36
35
34
33
AOUTA2-
AOUTA2+
AOUTB2+
AOUTB2-
1
2
3
4
GND
5
32
31
30
29
28
27
26
25
VA
MCLK
6
GND
CS4382A
LRCK(DSD_EN)
SDIN1
7
AOUTA3-
AOUTA3+
AOUTB3+
AOUTB3-
AOUTA4-
AOUTA4+
8
SCLK
9
10
11
TST
SDIN2
TST
2
1
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
VD
#
Pin Description
4
Digital Power (Input) - Positive power supply for the digital section.
GND
5
Ground (Input) - Ground reference. Should be connected to analog ground.
31
MCLK
LRCK
6
7
Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on
the serial audio data line. The frequency of the left/right clock must be at the audio sample
rate, Fs.
SDIN1
SDIN2
SDIN3
SDIN4
8
11
13
14
Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SCLK
VLC
9
Serial Clock (Input) - Serial clock for the serial audio interface.
18
Control Port Power (Input) - Determines the required signal level for the control port.
Refer to the Recommended Operating Conditions for appropriate voltages.
RST
19
20
Reset (Input) - The device enters a low power mode and all internal registers are reset to
their default settings when low.
FILT+
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
circuits. Requires the capacitive decoupling to analog ground, as shown in the Typical Con-
nection Diagram.
VQ
21
Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be
capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The
nominal voltage level is specified in the Analog Characteristics and Specifications section.
VQ presents an appreciable source impedance and any current drawn from this pin will
alter device performance. However, VQ can be used to bias the analog circuitry assuming
there is no AC signal component and the DC current is less than the maximum specified in
the Analog Characteristics and Specifications section.
6
DS618PP1
CS4382A
Pin Name
#
Pin Description
MUTEC1
MUTEC234
41
22
Mute Control (Output) - The Mute Control pins go high during power-up initialization, reset,
muting, power-down or if the master clock to left/right clock frequency ratio is incorrect.
These pins are intended to be used as a control for external mute circuits to prevent the
clicks and pops that can occur in any single supply system. The use of external mute cir-
cuits are not mandatory but may be desired for designs requiring the absolute minimum in
extraneous clicks and pops.
AOUTA1 +,- 39, 40 Differential Analog Output (Output) - The full scale differential analog output level is spec-
AOUTB1 +,- 38, 37 ified in the Analog Characteristics specification table.
AOUTA2 +,- 35, 36
AOUTB2 +,- 34, 33
AOUTA3 +,- 29, 30
AOUTB3 +,- 28, 27
AOUTA4 +,- 25, 26
AOUTB4 +,- 24, 23
VA
32
43
Analog Power (Input) - Positive power supply for the analog section.
VLS
Serial Audio Interface Power (Input) - Determines the required signal level for the serial
audio interface. Refer to the Recommended Operating Conditions for appropriate voltages.
Test - These pins need to be tied to analog ground.
TST
10
12
Software Mode Definitions
SCL/CCLK
SDA/CDIN
AD0/CS
15
16
17
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an
2
external pull-up resistor to the logic interface voltage in I C mode as shown in the Typical
Connection Diagram.
2
Serial Control Data (Input/Output) - SDA is a data I/O line in I C mode and requires an
external pull-up resistor to the logic interface voltage, as shown in the Typical Connection
Diagram. CDIN is the input data line for the control port interface in SPI mode.
2
Address Bit 0 (I C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in
2
I C mode; CS is the chip select signal for SPI format.
Stand-Alone Definitions
M0
M1
M2
M3
17
16
15
42
Mode Selection (Input) - Determines the operational mode of the device.
DSD Definitions
DSD_SCLK
DSD_EN
42
7
DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.
DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD mode (Stand-Alone
mode only).
DSDA1
DSDB1
DSDA2
DSDB2
DSDA3
DSDB3
DSDA4
DSDB4
3
2
1
48
47
46
45
44
Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.
DS618PP1
7
CS4382A
2. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltage
and T = 25°C.
A
SPECIFIED OPERATING CONDITIONS
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Typ
Max
Units
DC Power Supply
Analog power
Digital internal power
Serial data port interface power
Control port interface power
VA
VD
VLS
VLC
4.75
2.37
1.71
1.71
5.0
2.5
5.0
5.0
5.25
2.63
5.25
5.25
V
V
V
V
Specified Temperature Range
Absolute Maximum Ratings
-CQZ
-EQZ
T
-10
-40
-
-
+70
+105
°C
°C
A
(GND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
DC Power Supply
Analog power
VA
VD
VLS
VLC
-0.3
-0.3
-0.3
-0.3
6.0
3.2
6.0
6.0
V
V
V
V
Digital internal power
Serial data port interface power
Control port interface power
Input Current
Any Pin Except Supplies
I
-
±10
mA
in
Digital Input Voltage
Serial data port interface
Control port interface
V
V
-0.3
-0.3
VLS+ 0.4
VLC+ 0.4
V
V
IND-S
IND-C
Ambient Operating Temperature (power applied)
Storage Temperature
T
-55
-65
125
150
°C
°C
op
T
stg
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
8
DS618PP1
CS4382A
DAC ANALOG CHARACTERISTICS
Full-Scale Output Sine Wave, 997 Hz (Note 1); Fs = 48/96/192 kHz; Test load R = 3 kΩ, C = 100 pF; Measure-
L
L
ment Bandwidth 10 Hz to 20 kHz, unless otherwise specified.
Parameters
Symbol
Min
Typ
Max
Unit
CS4382A-CQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range
T
-10
-
70
°C
A
24-bit A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
108
105
-
-
114
111
97
-
-
-
-
dB
dB
dB
dB
94
Total Harmonic Distortion + Noise
THD+N
24-bit
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-94
-
-45
-
-
-
dB
dB
dB
dB
dB
dB
(Note 2) 16-bit
Idle Channel Noise / Signal-to-noise ratio
-
114
-
dB
CS4382A-EQZ Dynamic Performance - All PCM modes and DSD
Specified Temperature Range
Dynamic Range (Note 1)
T
-40
-
105
°C
A
24-bit A-weighted
unweighted
16-bit A-weighted
(Note 2) unweighted
105
102
-
-
114
111
97
-
-
-
-
dB
dB
dB
dB
94
Total Harmonic Distortion + Noise
(Note 1) THD+N
0 dB
24-bit
-
-
-
-
-
-
-100
-91
-51
-94
-74
-34
-91
-
-42
-
-
-
dB
dB
dB
dB
dB
dB
-20 dB
-60 dB
0 dB
-20 dB
(Note 2) 16-bit
-60 dB
Idle Channel Noise / Signal-to-noise ratio
-
114
-
dB
Notes:
1. One-half LSB of triangular PDF dither is added to data.
2. Performance limited by 16-bit quantization noise.
DS618PP1
9
CS4382A
DAC ANALOG CHARACTERISTICS - ALL MODES (CONTINUED)
Parameters
Symbol
Min
Typ
Max
Units
Interchannel Isolation
(1 kHz)
-
110
-
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
-
-
0.1
-
-
dB
100
ppm/°C
Analog Output
Full Scale Differential-
Output Voltage
PCM, DSD processor
Direct DSD mode
V
132%•V
134%•V
136%•V
A
Vpp
Vpp
FS
A
A
94%•V
96%•V
98%•V
A
A
A
Output Impedance
(Note 3)
Z
-
-
-
-
-
-
130
1.0
3
-
-
-
-
-
-
Ω
mA
kΩ
OUT
Max DC Current draw from an AOUT pin
Min AC-Load Resistance
Max Load Capacitance
I
OUTmax
R
L
C
100
pF
L
Quiescent Voltage
V
50% V
VDC
µA
Q
A
Max Current draw from V
I
10
Q
QMAX
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol
Min
Typ
Max
Units
Power Supplies
Power Supply Current
(Note 4)
normal operation, VA= 5 V
I
I
-
-
-
-
-
75
20
2
84
200
83
26
-
-
-
mA
mA
µA
µA
µA
A
D
VD= 2.5 V
(Note 5) Interface current, VLC=5 V
VLS=5 V
I
LC
I
LS
(Note 6) power-down state (all supplies)
I
pd
Power Dissipation (Note 4)
VA = 5 V, VD = 2.5 V
normal operation
-
-
426
1
482
-
mW
mW
(Note 6) power-down
Package Thermal Resistance
θ
θ
-
-
48
15
-
-
°C/Watt
°C/Watt
JA
JC
Power Supply Rejection Ratio (Note 7)
(1 kHz) PSRR
(60 Hz)
-
-
60
40
-
-
dB
dB
Notes:
3.
V
is tested under load R and includes attenuation due to Z
FS L OUT
4. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
5.
I
measured with no external loading on the SDA pin.
LC
6. Power down mode is defined as RST pin = Low with all clock and data lines held static.
7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
10
DS618PP1
CS4382A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam-
ple rate by multiplying the given characteristic by Fs.
(See note 12.)
Fast Roll-Off
Parameter
Min
Typ
Max
Unit
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
.454
.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
Frequency Response
StopBand
StopBand Attenuation
Group Delay
De-emphasis Error (Note 11)
(Relative to 1 kHz)
-0.01
0.547
102
(Note 10)
-
-
-
-
-
-
-
10.4/Fs
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
±0.23
±0.14
±0.09
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
.430
.499
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.583
80
-
-
-
(Note 10)
-
-
6.15/Fs
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.105
.490
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.635
90
-
-
-
(Note 10)
-
7.1/Fs
Notes:
8. Slow Roll-off interpolation filter is only available in software mode.
9. Response is clock dependent and will scale with Fs.
10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.
For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode; Only 44.1 kHz De-emphasis is available in hard-
ware mode.
12. Amplitude vs. Frequency plots of this data are available starting on page 43.
DS618PP1
11
CS4382A
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(CONTINED)
Slow Roll-Off (Note 8)
Parameter
Min
Typ
Max
Unit
Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
0.417
0.499
+0.01
-
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.583
64
-
(Note 10)
-
-
-
7.8/Fs
De-emphasis Error (Note 11)
(Relative to 1 kHz)
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
-
-
-
-
-
-
±0.36
±0.21
±0.14
dB
dB
dB
Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.296
.499
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.792
70
-
-
-
(Note 10)
-
5.4/Fs
Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
to -3 dB corner
10 Hz to 20 kHz
0
0
-
-
-
-
-
.104
.481
+0.01
Fs
Fs
dB
Fs
dB
s
Frequency Response
StopBand
StopBand Attenuation
Group Delay
-0.01
.868
75
-
-
-
(Note 10)
-
6.6/Fs
DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE
Parameter
Min
Typ
Max
Unit
DSD Processor mode
Passband (Note 9)
Frequency Response
Roll-off
to -3 dB corner
10 Hz to 20 kHz
0
-
-
-
50
+0.05
-
kHz
dB
dB/Oct
-0.05
27
12
DS618PP1
CS4382A
DIGITAL CHARACTERISTICS
Parameters
Input Leakage Current
Symbol
Min
Typ
Max
Units
µA
pF
(Note 13)
I
-
-
-
±10
-
in
Input Capacitance
8
High-Level Input Voltage
Serial I/O
Control I/O
V
V
70%
70%
-
-
-
-
V
V
IH
IH
LS
LC
Low-Level Input Voltage
Serial I/O
Control I/O
V
V
-
-
-
-
30%
30%
V
V
IL
IL
LS
LC
High-Level Output Voltage (I = -1.2 mA)
Control I/O
Control I/O
V
80%
-
-
-
-
V
V
OH
OH
LC
LC
Low-Level Output Voltage (I = 1.2 mA)
V
20%
OL
OL
Maximum MUTEC Drive Current
MUTEC High-Level Output Voltage
MUTEC Low-Level Output Voltage
I
-
-
-
3
VA
0
-
-
-
mA
V
max
V
OH
V
V
OL
13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-
up
DS618PP1
13
CS4382A
SWITCHING CHARACTERISTICS - PCM
(Inputs: Logic 0 = GND, Logic 1 = VLS, C = 30 pF)
L
Parameters
Symbol
Min
Max
Units
RST pin Low Pulse Width
(Note 14)
1
-
ms
MCLK Frequency
1.024
45
55.2
55
MHz
%
MCLK Duty Cycle
(Note 15)
Input Sample Rate - LRCK
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
F
F
F
4
50
100
54
108
216
kHz
kHz
kHz
s
s
s
LRCK Duty Cycle
45
45
8
55
55
-
%
%
SCLK Duty Cycle
SCLK High Time
t
ns
ns
ns
ns
ns
sckh
SCLK Low Time
t
8
-
sckl
LRCK Edge to SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
t
5
-
lcks
t
3
-
ds
t
5
-
dh
Notes:
14. After powering up, RST should be held low until after the power supplies and clocks are settled.
15. See Table 1 on page 20 for suggested MCLK frequencies.
LRCK
tlcks
tsckh
tsckl
SCLK
tds
tdh
MSB
SDINx
MSB-1
Figure 1. Serial Audio Interface Timing
14
DS618PP1
CS4382A
SWITCHING CHARACTERISTICS - DSD
(Logic 0 = AGND = DGND; Logic 1 = VLS; C = 20 pF)
L
Parameter
MCLK Duty Cycle
Symbol
Min
40
Typ
Max
Unit
%
-
-
-
60
-
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
t
160
160
ns
sclkl
t
-
ns
sclkh
DSD_SCLK Frequency
(64x Oversampled)
(128x Oversampled)
1.024
2.048
-
-
3.2
6.4
MHz
MHz
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
t
20
20
-
-
-
-
ns
ns
sdlrs
t
sdh
t
sclkh
t
sclkl
DSD_SCLK
DSDxx
t
t
sdlrs
sdh
Figure 2. Direct Stream Digital - Serial Audio Input Timing
DS618PP1
15
CS4382A
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
L
Parameter
SCL Clock Frequency
Symbol
Min
-
Max
Unit
kHz
ns
f
100
scl
RST Rising Edge to Start
t
500
4.7
4.0
4.7
4.0
4.7
0
-
-
-
-
-
-
-
irs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
t
µs
buf
t
µs
hdst
t
µs
low
Clock High Time
t
µs
high
Setup Time for Repeated Start Condition
t
µs
sust
SDA Hold Time from SCL Falling
(Note 16)
t
µs
hdd
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
t
250
-
-
1
ns
µs
ns
µs
ns
sud
t , t
rc rc
t , t
-
300
-
fc fc
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
t
4.7
300
susp
t
1000
ack
Notes:
16. Data must be held for sufficient time to bridge the transition time, t , of SCL.
fc
RST
t
irs
Repeated
Start
Stop
Start
Stop
SDA
SCL
t
t
t
t
t
buf
t
high
hdst
f
susp
hdst
t
t
t
t
t
sust
sud
r
low
hdd
Figure 3. Control Port Timing - I2C Format
16
DS618PP1
CS4382A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, C = 30 pF)
L
Parameter
CCLK Clock Frequency
Symbol
Min
-
Max
Unit
MHz
ns
f
6
-
sclk
RST Rising Edge to CS Falling
t
500
500
srs
CCLK Edge to CS Falling
(Note 17)
t
-
ns
spi
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t
1.0
20
66
66
40
15
-
-
-
-
-
-
µs
ns
ns
ns
ns
ns
csh
t
css
t
scl
CCLK High Time
t
sch
dsu
CDIN to CCLK Rising Setup Time
t
CCLK Rising to DATA Hold Time
(Note 18)
t
dh
Rise Time of CCLK and CDIN
(Note 19)
t
-
-
100
100
ns
ns
r2
Fall Time of CCLK and CDIN
(Note 19)
t
f2
Notes:
17.
18. Data must be held for sufficient time to bridge the transition time of CCLK.
19. For F < 1 MHz.
t
only needed before first falling edge of CS after RST rising edge. t = 0 at all other times.
spi spi
SCK
RST
t
t
srs
CS
t
t
t
spi css
scl
sch
t
csh
CCLK
t
t
r2
f2
CDIN
t
t
dsu
dh
Figure 4. Control Port Timing - SPI Format
DS618PP1
17
CS4382A
+2.5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
32
VA
VD
39
40
AOUTA1+
AOUTA1-
Analog Conditioning
and Muting
38
37
AOUTB1+
AOUTB1-
Analog Conditioning
and Muting
220 Ω
6
7
9
MCLK
LRCK
SCLK
35
36
AOUTA2+
AOUTA2-
PCM
Digital
Audio
Analog Conditioning
and Muting
8
SDIN1
SDIN2
Source
11
34
33
AOUTB2+
AOUTB2-
Analog Conditioning
and Muting
13
14
SDIN3
SDIN4
29
30
470 Ω
470 Ω
AOUTA3+
AOUTA3-
Analog Conditioning
and Muting
43
+1.8 V to +5 V
VLS
CS4382A
0.1 µF
28
27
AOUTB3+
AOUTB3-
Analog Conditioning
and Muting
3
2
1
DSDA1
DSDB1
DSDA2
25
26
AOUTA4+
AOUTA4-
Analog Conditioning
and Muting
DSD
Audio
Source
48
47
DSDB2
DSDA3
DSDB3
24
23
AOUTB4+
AOUTB4-
Analog Conditioning
and Muting
46
45
44
DSDA4
DSDB4
41
22
MUTEC1
Mute
Drive
MUTEC234
42
DSD_SCLK
19
RST
15
16
Micro-
Controller
SCL/CCLK
SDA/CDIN
17
ADO/CS
Note*
20
21
FILT+
VQ
+
18
+1.8 V to +5 V
VLC
F
47 µF
0.1 µ
F
1 µF
0.1 µ
+
0.1 µF
GND
5
GND TST*
31
Note: Necessary for I2C
control port operation
NOTETST: Pins 10 and 12
Figure 5. Typical Connection Diagram, Software Mode
18
DS618PP1
CS4382A
+2.5 V
+5 V
+
+
1 µF
0.1 µF
0.1 µF
1 µF
4
32
VA
VD
39
40
AOUTA1+
AOUTA1-
Analog Conditioning
and Muting
47 K
Ω
NoteDSD
VLS
38
37
AOUTB1+
AOUTB1-
220 Ω
Analog Conditioning
and Muting
6
7
9
MCLK
LRCK
SCLK
PCM
Digital
Audio
Source
Mute
Drive
41
MUTEC1
8
SDIN1
SDIN2
11
35
36
13
14
AOUTA2+
AOUTA2-
SDIN3
SDIN4
Analog Conditioning
and Muting
470 Ω
470 Ω
34
33
AOUTB2+
Analog Conditioning
and Muting
43
CS4382A AOUTB2-
VLS
+1.8 V to +5 V
0.1 µF
29
30
AOUTA3+
AOUTA3-
Analog Conditioning
and Muting
3
2
DSDA1
DSDB1
DSDA2
28
27
AOUTB3+
AOUTB3-
Analog Conditioning
and Muting
1
DSD
Audio
Source
48
DSDB2
25
26
47
AOUTA4+
AOUTA4-
Analog Conditioning
and Muting
DSDA3
DSDB3
46
45
44
DSDA4
DSDB4
24
23
AOUTB4+
AOUTB4-
Analog Conditioning
and Muting
NoteDSD
Optional
47 KΩ
Mute
Drive
22
42
MUTEC234
M3(DSD_SCLK)
15
16
M2
M1
Stand-Alone
Mode
Configuration
17
19
M0
RST
20
21
FILT+
VQ
+
F
47 µF
0.1 µ
18
F
+
1 µF
0.1 µ
+1.8 V to +5 V
VLC
0.1 µF
GND
5
GND TST
31 10, 12
NoteDSD: For DSD operation:
1) LRCK must be tied to VLS and
remain static high.
2) M3 PCM stand-alone configuration
pin becomes DSD_SCLK
Figure 6. Typical Connection Diagram, Hardware Mode
DS618PP1
19
CS4382A
3. APPLICATIONS
The CS4382A serially accepts twos complement formatted PCM data at standard audio sample rates including 48,
44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via
the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input
on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer.
The CS4382A can be configured in hardware mode by the M0, M1, M2 , M3 and DSD_EN pins and in software
2
mode through I C or SPI.
3.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-
cy at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected
automatically during the initialization sequence by counting the number of MCLK transitions during a single
LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several
standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-
quired phase relationship, but MCLK, LRCK and SCLK must be synchronous.
Software
mode only
Speed Mode
(sample-rate range)
Sample
Rate
MCLK (MHz)
(kHz)
MCLK Ratio
256x
8.1920
11.2896
12.2880
128x
384x
512x
768x
1024x*
32.7680
45.1584
49.1520
512x*
32
44.1
48
12.2880
16.9344
18.4320
192x
16.3840
22.5792
24.5760
256x
24.5760
33.8688
36.8640
384x
Single-Speed
(4 to 50 kHz)
MCLK Ratio
64
88.2
96
8.1920
11.2896
12.2880
64x
12.2880
16.9344
18.4320
96x
16.3840
22.5792
24.5760
128x
24.5760
33.8688
36.8640
192x
32.7680
45.1584
49.1520
256x*
Double-Speed
(50 to 100 kHz)
MCLK Ratio
176.4
192
11.2896
12.2880
16.9344
18.4320
22.5792
24.5760
33.8688
36.8640
45.1584
49.1520
Quad-Speed
(100 to 200 kHz)
Note: These modes are only available in software mode by setting the MCLKDIV bit = 1.
Table 1. Common Clock Frequencies
3.2
Mode Select
In hardware mode operation is determined by the Mode Select pins. The state of these pins are continually
scanned for any changes. These pins require connection to supply or ground as outlined in figure 6. For
M0, M1, M2 supply is VLC and for M3 and DSD_EN supply is VLS. Tables 2 - 4 show the decode of these
pins.
In software mode the operational mode and data format are set in the FM and DIF registers. “Parameter
Definitions” on page 41.
20
DS618PP1
CS4382A
M1
M0
DESCRIPTION
FORMAT
FIGURE
(DIF1)
(DIF0)
Left Justified, up to 24-bit data
0
0
0
1
0
1
33
34
2
I S, up to 24-bit data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
1
1
0
1
2
3
35
36
Table 2. Digital Interface Format, Stand-Alone Mode Options
M3
M2
DESCRIPTION
(DEM)
Single-Speed without De-Emphasis (4 to 50 kHz sample rates)
Single-Speed with 44.1 kHz De-Emphasis; see Figure 13
Double-Speed (50 to 100 kHz sample rates)
0
0
1
1
0
1
0
1
Quad-Speed (100 to 200 kHz sample rates)
Table 3. Mode Selection, Stand-Alone Mode Options
DSD_EN
(LRCK)
M2
M1
M0
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options
DS618PP1
21
CS4382A
3.3
Digital Interface Formats
The serial port operates as a slave and supports the I²S, Left-Justified, and Right-Justified digital interface
formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the
rising edge.
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
LSB
MSB
LSB
+5 +4 +3 +2 +1
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
-1 -2 -3 -4
Figure 7. Format 0 - Left-Justified up to 24-bit Data
Left Channel
Right Channel
LRCK
SCLK
SDINx
MSB
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
LSB
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
Figure 8. Format 1 - I2S up to 24-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
9 8 7
6
5 4
3
2 1
0
9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
32 clocks
15 14 13 12 11 10
Figure 9. Format 2 - Right-Justified 16-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
7
6
5 4
3
2 1
0
7 6 5 4 3 2 1 0
0
23 22 21 20 19 18
32 clocks
23 22 21 20 19 18
Figure 10. Format 3 - Right-Justified 24-bit Data
22
DS618PP1
CS4382A
Right Channel
LRCK
SCLK
Left Channel
SDINx
1 0
19 18 17 16
8
7
6
5
4 3
2
1
0
19 18 17 16
15 14 13 12 11 10 9
32 clocks
15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
Figure 11. Format 4 - Right-Justified 20-bit Data
Right Channel
LRCK
SCLK
Left Channel
SDINx
1 0
17 16
17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
32 clocks
Figure 12. Format 5 - Right-Justified 18-bit Data
3.4
Oversampling Modes
The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the DSD_EN, M3 and M2 pins in hardware mode or the FM bits in software mode. Single-
Speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed
mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed mode
supports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
3.5
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorpo-
rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available
in each of Single, Double, and Quad-Speed modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit is used to select which filter is used (see the “Param-
eter Definitions” on page 41 for more details).
When in hardware mode, only the “fast” roll-off filter is available.
Filter specifications can be found in Section 2, and filter response plots can be found in Figures 19 to 42.
3.6
De-Emphasis
The CS4382A includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accom-
modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. Figure
13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportion-
ally with changes in sample rate, Fs if the input sample rate does not match the coefficient which has been
selected.
DS618PP1
23
CS4382A
In software mode the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected
via the de-emphasis control bits.
In hardware mode only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sam-
ple rate is not 44.1 kHz and de-emphasis has been selected then the corner frequencies of the de-emphasis
filter will be scaled by a factor of the actual Fs over 44,100.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
F2
Frequency
3.183 kHz
10.61 kHz
Figure 13. De-Emphasis Curve
3.7
ATAPI Specification
The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 7 on page 38 and Figure 14 for additional informa-
tion.
A Channel
Volume
Control
Left Channel
Audio Data
MUTE
AoutAx
Σ
Σ
SDINx
B Channel
Volume
Control
Right Channel
Audio Data
MUTE
AoutBx
Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4)
24
DS618PP1
CS4382A
3.8
Direct Stream Digital (DSD) Mode
In stand-alone mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.
In control-port mode the FM bits set the device into DSD mode (DSD_EN pin is not required to be held high).
The DIF register then controls the expected DSD rate and MCLK ratio.
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK in Stand-alone mode). When the DSD related pins are not being used they should either be tied static
low, or remain active with clocks (except M3 in Stand-alone mode).
3.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS4382A requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the
recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4382A should be con-
nected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
3.9.1 Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same sup-
ply, but a decoupling capacitor should still be placed on each supply pin.
Notes: All decoupling capacitors should be referenced to analog ground.
The CDB4382A evaluation board demonstrates the optimum layout and power supply arrangements.
3.10 Analog Output and Filtering
The application note “Design Notes for a 2-Pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential to single-ended converter which was implemented on the CS4382A eval-
uation board, CDB4382A, as seen in Figure 16. The CS4382A does not include phase or amplitude com-
pensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent
on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale out-
put level to below 2 Vrms.
Figure 15 shows how the full-scale differential analog output level specification is derived.
DS618PP1
25
CS4382A
3.85 V
2.5 V
AOUT+
AOUT-
1.15 V
3.85 V
2.5 V
1.15 V
Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp
Figure 15. Full-Scale Output
Figure 16. Recommended Output Filter
3.11 Mute Control
The Mute Control pins go active during power-up initialization, reset, muting, or if the MCLK to LRCK ratio
is incorrect. These pins are intended to be used as control for external mute circuits to prevent the clicks
and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
Please see the CDB4382A data sheet for a suggested mute circuit.
26
DS618PP1
CS4382A
3.12 Recommended Power-Up Sequence
3.12.1 Hardware Mode
1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in section 3.1. In this state, the registers
are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
3.12.2 Software Mode
1. Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in section 3.1. In this state, the registers are reset to the default
settings, FILT+ will remain low, and VQ will be connected to VA/2.
2. Bring RST high. The device will remain in a low power state with FILT+ low for 512 LRCK cycles in
Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-
Speed Mode).
3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-
Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1, then set the format
and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written then the chip will
enter Hardware mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be
written at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit can
not be set in time then the SDINx pins should remain static low (this way no audio data can be
converted incorrectly by the hardware mode settings).
4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.
3.13 Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK can not be met
during clock source changes.
DS618PP1
27
CS4382A
3.14 Control Port Interface
The control port is used to load all the internal register settings in order to operate in software mode (see
the “Parameter Definitions” on page 41). The operation of the control port may be completely asynchronous
with the audio sample rate. However, to avoid potential interference problems, the control port pins should
remain static if no operation is required.
2
The control port operates in one of two modes: I C or SPI.
3.14.1 MAP Auto Increment
The device has MAP (memory address pointer) auto increment capability enabled by the INCR bit (also the
2
MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I C writes or reads and SPI
writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or writes
of successive registers.
2
3.14.2 I C Mode
2
In the I C mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
control port clock, SCL (see Figure 17 for the clock to data relationship). There is no CS pin. Pin AD0 en-
ables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND as required,
before powering up the device. If the device ever detects a high to low transition on the AD0/CS pin after
power-up, SPI mode will be selected.
2
3.14.2.1 I C Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifi-
cations in section 2.
2
1. Initiate a START condition to the I C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part, then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part, then write the desired data to the register pointed to
by the MAP.
4. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then initiate a STOP condition to the bus.
2
5. If the INCR bit is set to 0 and further I C writes to other registers are desired, it is necessary to ini-
tiate a repeated START condition and follow the procedure detailed from step 1. If no further writes to
other registers are desired, initiate a STOP condition to the bus.
28
DS618PP1
CS4382A
2
3.14.2.2 I C Read
To read from the device, follow the procedure below while adhering to the control port Switching Spec-
ifications.
2
1. Initiate a START condition to the I C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP,
2
or the default address (see section 3.14.1) if an I C read is the first operation performed on the device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then
initiate a STOP condition to the bus.
2
5. If the INCR bit is set to 0 and further I C reads from other registers are desired, it is necessary to
2
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I C
2
Write instructions followed by step 1 of the I C Read section. If no further reads from other registers are
desired, initiate a STOP condition to the bus.
Note 1
ADDR
AD0
DATA
1-8
DATA
1-8
001100
R/W
ACK
ACK
ACK
SDA
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 17. Control Port Timing, I2C Mode
DS618PP1
29
CS4382A
3.14.3 SPI™ Mode
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK
(see Figure 18 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the control port. When the device detects a high to low transition on the
AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
3.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the control port Switching Specifi-
cations in Section 2.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see section 3.14.1) is set to 1, repeat the previous step until all the desired registers
are written, then bring CS high.
6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring
CS high, and follow the procedure detailed from step 1. If no further writes to other registers are desired,
bring CS high.
CS
CCLK
CHIP
ADDRESS
MAP
DATA
0011000
LSB
CDIN
MSB
R/W
byte 1
byte n
MAP = Memory Address Pointer
Figure 18. Control Port Timing, SPI mode
3.15 Memory Address Pointer (MAP)
7
INCR
0
6
Reserved
0
5
Reserved
0
4
MAP4
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
3.15.1 INCR (AUTO MAP INCREMENT ENABLE)
Default = ‘0’
0 - Disabled
1 - Enabled
3.15.2 MAP4-0 (MEMORY ADDRESS POINTER)
Default = ‘00000’
30
DS618PP1
CS4382A
4. REGISTER QUICK REFERENCE
Addr
Function
7
6
5
4
3
2
1
0
01h Mode Control 1
CPEN
FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS
PDN
1
0
0
DIF2
0
0
DIF0
0
0
0
0
default
02h Mode Control 2
default
0
DIF1
0
Reserved
Reserved Reserved Reserved Reserved
0
SZC1
1
0
0
0
Reserved
0
0
MUTEC
0
03h Mode Control 3
default
SZC0
0
SNGLVOL RMP_UP MUTEC+/-
AMUTE
0
0
0
1
DEM1
0
04h Filter Control
default
05h Invert Control
default
Reserved Reserved Reserved FILT_SEL Reserved
DEM0
0
RMP_DN
0
0
INV_B4
0
0
INV_A4
0
0
INV_B3
0
0
INV_A3
0
0
INV_B2
0
INV_A2
0
INV_B1
0
INV_A1
0
06h Mixing Control
Pair 1 (AOUTx1)
P1_A=B P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0
FM1
FM0
0
0
1
0
0
1
0
0
default
07h Vol. Control A1
default
A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0
0
0
0
0
0
0
0
0
08h Vol. Control B1
B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0
0
0
0
0
0
0
0
0
default
09h Mixing Control
Pair 2 (AOUTx2)
P2_A=B P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 Reserved Reserved
0
0
1
0
0
1
0
0
default
0Ah Vol. Control A2
default
A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0
0
0
0
0
0
0
0
0
0Bh Vol. Control B2
default
B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0
0
0
0
0
0
0
0
0
0Ch Mixing Control
Pair 3 (AOUTx3)
P3_A=B P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 Reserved Reserved
0
0
1
0
0
1
0
0
default
0Dh Vol. Control A3
default
A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0
0
0
0
0
0
0
0
0
0Eh Vol. Control B3
default
B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0
0
0
0
0
0
0
0
0
0Fh Mixing Control
Pair 4 (AOUTx4)
P4_A=B P4ATAPI4 P4ATAPI4 P4ATAPI2 P4ATAPI1 P4ATAPI0 Reserved Reserved
0
0
1
0
0
1
0
0
default
10h Vol. Control A4
default
A4_MUTE A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0
0
0
0
0
0
0
0
0
11h Vol. Control B4
default
12h Chip Revision
default
B4_MUTE B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0
0
PART4
0
0
PART3
1
0
PART2
1
0
PART1
1
0
PART0
0
0
REV
x
0
REV
x
0
REV
x
DS618PP1
31
CS4382A
5. REGISTER DESCRIPTION
2
Note: All registers are read/write in I C mode and write only in SPI, unless otherwise noted.
5.1
Mode Control 1 (address 01h)
7
CPEN
0
6
FREEZE
0
5
MCLKDIV
0
4
3
2
1
0
PDN
1
DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS
0
0
0
0
5.1.1 Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone mode. The Control port mode can be
accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the registers
and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user should
write this bit within 10 ms following the release of Reset.
5.1.2 Freeze Controls (Freeze)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control port registers take effect simultaneously, en-
able the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
5.1.3 Master Clock DIVIDE ENABLE (mclkdiv)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
5.1.4 DAC Pair Disable (DACx_DIS)
Default = 0
0 - Enabled
1 - Disabled
Function:
When enabled the respective DAC channel pairx (AOUTAx and AOUTBx) will remain in a reset state. It is
advised that changes to these bits be made while the power down bit is enabled to eliminate the possibility
of audible artifacts.
32
DS618PP1
CS4382A
5.1.5 Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be dis-
abled before normal operation in Control Port mode can occur.
5.2
Mode Control 2 (address 02h)
7
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
Reserved
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
Reserved
0
5.2.1 Digital Interface Format (dif)
Default = 000 - Format 0 (Left Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine wheth-
er PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in Figures 7-12.
DIF2
DIF1
DIF0
DESCRIPTION
Format
FIGURE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
-
7
Left Justified, up to 24-bit data
I S, up to 24-bit data
2
8
9
Right Justified, 16-bit data
Right Justified, 24-bit data
Right Justified, 20-bit data
Right Justified, 18-bit data
Reserved
10
11
12
-
Reserved
Table 5. Digital Interface Formats - PCM Mode
DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required Mas-
ter clock to DSD data rate is defined by the Digital Interface Format pins.
DIF2
DIF1
DIFO
DESCRIPTION
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 6. Digital Interface Formats - DSD Mode
DS618PP1
33
CS4382A
5.2.2 Mode Control 3 (address 03h)
7
SZC1
1
6
SZC0
0
5
SNGLVOL
0
4
RMP_UP
0
3
MUTEC+/-
0
2
AMUTE
1
1
Reserved
0
0
MUTEC
0
5.2.3 Soft Ramp AND Zero Cross CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout
period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does
not encounter a zero crossing. The zero cross function is independently monitored and implemented for
each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping,
in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or mut-
ing, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will
occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored
and implemented for each channel.
5.2.4 Single Volume Control (Snglvol)
Default = 0
0 - Disabled
1 - Enabled
Function:
The individual channel volume levels are independently controlled by their respective Volume Control Bytes
when this function is disabled. The volume on all channels is determined by the A1 Channel Volume Con-
trol Byte, and the other Volume Control Bytes are ignored when this function is enabled.
34
DS618PP1
CS4382A
5.2.5 Soft Volume Ramp-Up after Error (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional
Mode. When this feature is enabled, this un-mute is affected, similarly to attenuation changes, by the Soft
and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed in
these instances.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
5.2.6 MUTEC Polarity (MUTEC+/-)
Default = 0
0 - Active High
1 - Active Low
Function:
The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default) the MUTEC
pins are high when active. When set to 1 the MUTEC pin(s) are low when active.
Notes: When the on board mute circuitry is designed for active low, the MUTEC outputs will be high (un-muted)
for the period of time during reset and before this bit is enabled to 1.
5.2.7 Auto-Mute (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio samples
of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is done
independently for each channel. The quiescent voltage on the output will be retained and the Mute Control
pin will go active during the mute period. The muting function is affected, similar to volume control changes,
by the Soft and Zero Cross bits in the Mode Control 3 register.
5.3
Mutec Pin Control (MUTEC)
Default = 0
0 - Two Mute control signals
1 - Single mute control signal on MUTEC1
Function:
Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’, a
logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute con-
trol signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all DAC
pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more information
on the use of the mute control function see the MUTEC1 and MUTEC234 pins in section 8.
DS618PP1
35
CS4382A
5.4
Filter Control (address 04h)
7
6
Reserved
0
5
Reserved
0
4
FILT_SEL
0
3
Reserved
0
2
DEM1
0
1
DEM0
0
0
RMP_DN
0
Reserved
0
5.4.1 Interpolation Filter Select (FILT_SEL)
Default = 0
0 - Fast roll-off
1 - Slow roll-off
Function:
This function allows the user to select whether the interpolation filter has a fast or slow roll off. For filter
characteristics please see Section 2.
5.4.2 De-Emphasis Control (DEM)
Default = 00
00 - Disabled
01 - 44.1 kHz
10 - 48 kHz
11 - 32 kHz
Function:
Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter response
at 32, 44.1 or 48 kHz sample rates. (see Figure 13)
De-emphasis is only available in Single Speed Mode.
5.4.3 Soft Ramp-Down before Filter Mode Change (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
If either the FILT_SEL or DEM bits are changed the DAC will stop conversion for a period of time to change
filter values. This bit selects how the data is effected prior to and after the change of the filter values. When
this bit is enabled the DAC will ramp down the volume prior to a filter mode change and ramp from mute to
the original volume value after a filter mode change according to the settings of the Soft and Zero Cross
bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is performed.
Loss of clocks or a change in the FM bits will always cause an immediate mute; Unmute in these conditions
is affected by the RMP_UP bit.
Notes: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
36
DS618PP1
CS4382A
5.5
Invert Control (address 05h)
7
6
INV_A4
0
5
INV_B3
0
4
INV_A3
0
3
INV_B2
0
2
INV_A2
0
1
INV_B1
0
0
INV_A1
0
INV_B4
0
5.5.1 Invert Signal Polarity (Inv_Xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
5.6
Mixing Control Pair 1 (Channels A1 & B1)(address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(address 0Fh)
7
6
PxATAPI4
0
5
PxATAPI3
1
4
PxATAPI2
0
3
PxATAPI1
0
2
PxATAPI0
1
1
PxFM1
0
0
PxFM0
0
Px_A=B
0
5.6.1 Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Volume
Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are determined
by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ig-
nored when this function is enabled.
5.6.2 ATAPI Channel Mixing and Muting (ATAPI)
Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo)
Function:
The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI
functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.
DS618PP1
37
CS4382A
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTAx
MUTE
MUTE
MUTE
MUTE
aR
AOUTBx
MUTE
bR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
bL
b[(L+R)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
bL
b[(L+R)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
aR
aR
aR
aL
aL
aL
aL
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
bL
[(aL+bR)/2]
Table 7. ATAPI Decode
5.6.3 Functional Mode (FM)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 200 kHz sample rates)
11 - Direct Stream Digital Mode
Function:
Selects the required range of input sample rates or DSD Mode. All DAC pairs are required to be set to the
same functional mode setting before a speed mode change is accepted. When DSD mode is selected for
any channel pair then all pairs will switch to DSD mode.
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DS618PP1
CS4382A
5.7
Volume Control (addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)
7
6
xx_VOL6
0
5
xx_VOL5
0
4
xx_VOL4
0
3
xx_VOL3
0
2
xx_VOL2
0
1
xx_VOL1
0
0
xx_VOL0
0
xx_MUTE
0
Note: These eight registers provide individual volume and mute control for each of the eight channels.
The values for “xx” in the bit fields above are as follows:
Register address 07h - xx = A1
Register address 08h - xx = B1
Register address 0Ah - xx = A2
Register address 0Bh - xx = B2
Register address 0Dh - xx = A3
Register address 0Eh - xx = B3
Register address 10h - xx = A4
Register address 11h - xx = B4
5.7.1 Mute (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be
retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits.
The MUTE pins will go active during the mute period according to the MUTEC bit.
5.7.2 Volume Control (xx_VOL)
Default = 0 (No attenuation)
Function:
The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments from
0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are implemented
as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent to enabling
the MUTE bit.
Binary Code
0 0 0 0 0 0 0
0 0 1 0 1 0 0
0 1 0 1 0 0 0
0 1 1 1 1 0 0
1 0 1 1 0 1 0
Decimal Value
Volume Setting
0 dB
0
20
40
60
90
-20 dB
-40 dB
-60 dB
-90 dB
Table 8. Example Digital Volume Settings
DS618PP1
39
CS4382A
5.8
Chip Revision (address 12h)
7
PART4
0
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
0
2
Reserved
0
1
Reserved
0
0
Reserved
0
5.8.1 Part Number ID (part) [Read Only]
01110 - CS4382A
000 - Revision A
Function:
This read-only register can be used to identify the model and revision number of the device.
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CS4382A
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the
specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth
made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure-
ment to full scale. This technique ensures that the distortion components are below the noise level and
do not affect the measurement. This measurement technique has been accepted by the Audio Engineer-
ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
Note: "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris. Paper
presented at the 93rd Convention of the Audio Engineering Society, October 1992.
Note: CDB4382A Datasheet
Note: “Design Notes for a 2-Pole Filter with Differential Input” by Steven Green. Cirrus Logic Application Note AN48
2
Note: “The I C-Bus Specification: Version 2.0” Philips Semiconductors, December 1998.
http://www.semiconductors.philips.com
8. ORDERING INFORMATION
Product
Description
Package Pb-Free
Grade
Temp Range
Container Order #
Tray
CS4382A-CQZ
Commercial -10° to +70° C
Automotive -40° to +105° C
Tape & Reel CS4382A-CQZR
114 dB, 192 kHz 8-
channel D/A Converter
48-pin
YES
CS4382A
LQFP
Tray
Tape & Reel CS4382A-EQZR
CDB4382A
CS4382A-EQZ
CDB4382A CS4382A Evaluation Board
-
-
-
-
DS618PP1
41
CS4382A
9. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E
E1
D1
D
1
e
B
∝
A
A1
L
INCHES
NOM
MILLIMETERS
NOM
DIM
MIN
MAX
MIN
MAX
A
A1
B
D
D1
E
E1
e*
L
∝
---
0.055
0.004
0.009
0.354
0.28
0.354
0.28
0.020
0.24
0.063
0.006
0.011
0.366
0.280
0.366
0.280
0.024
0.030
7.000°
---
1.40
0.10
0.22
1.60
0.15
0.27
9.30
7.10
9.30
7.10
0.60
0.75
7.00°
0.002
0.007
0.343
0.272
0.343
0.272
0.016
0.018
0.000°
0.05
0.17
8.70
6.90
8.70
6.90
0.40
0.45
0.00°
9.0 BSC
7.0 BSC
9.0 BSC
7.0 BSC
0.50 BSC
0.60
4°
4°
* Nominal pin pitch is 0.50 mm
Controlling dimension is mm.
JEDEC Designation: MS022
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DS618PP1
CS4382A
10.APPENDIX
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−100
−120
−120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 19. Single-Speed (fast) Stopband Rejection
Figure 20. Single-Speed (fast) Transition Band
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.02
0.015
0.01
0.005
0
−0.005
−0.01
−0.015
−0.02
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 21. Single-Speed (fast) Transition Band (detail)
Figure 22. Single-Speed (fast) Passband Ripple
0
−20
0
−20
−40
−40
−60
−60
−80
−80
−100
−120
−100
−120
0.4
0.5
0.6
0.7
0.8
0.9
1
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 23. Single-Speed (slow) Stopband Rejection
Figure 24. Single-Speed (slow) Transition Band
DS618PP1
43
CS4382A
0.02
0.015
0.01
0
−1
−2
−3
−4
−5
−6
−7
−8
−9
−10
0.005
0
−0.005
−0.01
−0.015
−0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 25. Single-Speed (slow) Transition Band (detail)
Figure 26. Single-Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
0.54
0.56
0.58
0.6
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 27. Double-Speed (fast) Stopband Rejection
Figure 28. Double-Speed (fast) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 29. Double-Speed (fast) Transition Band (detail)
Figure 30. Double-Speed (fast) Passband Ripple
44
DS618PP1
CS4382A
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 31. Double-Speed (slow) Stopband Rejection
Figure 32. Double-Speed (slow) Transition Band
0
1
0.02
0.015
0.01
2
3
0.005
0
4
5
6
0.005
0.01
7
8
0.015
0.02
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 33. Double-Speed (slow) Transition Band (detail)
Figure 34. Double-Speed (slow) Passband Ripple
0
0
20
20
40
40
60
60
80
80
100
120
100
120
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 35. Quad-Speed (fast) Stopband Rejection
Figure 36. Quad-Speed (fast) Transition Band
DS618PP1
45
CS4382A
0
0.2
0.15
0.1
1
2
3
0.05
0
4
5
6
0.05
7
0.1
0.15
0.2
8
9
10
0
0.05
0.1
0.15
0.2
0.25
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 37. Quad-Speed (fast) Transition Band (detail)
Figure 38. Quad-Speed (fast) Passband Ripple
0
0
20
40
20
40
60
60
80
80
100
120
100
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 39. Quad-Speed (slow) Stopband Rejection
Figure 40. Quad-Speed (slow) Transition Band
0
1
0.02
0.015
0.01
0.005
0
2
3
4
5
6
0.005
0.01
0.015
0.02
7
8
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
0.52
0.53
0.54
0.55
0
0.02
0.04
0.06
0.08
0.1
0.12
Frequency(normalized to Fs)
Frequency(normalized to Fs)
Figure 41. Quad-Speed (slow) Transition Band (detail)
Figure 42. Quad-Speed (slow) Passband Ripple
46
DS618PP1
CS4382A
Table 9. Revision History
Release
A1
PP1
Date
NOV 2004
APR 2005
Changes
Initial Release
Updated output impedance spec on page 10
Improved interchannel isolation spec on page 10
Updated Legal text
Re-formatted ordering information
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice
and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before
placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order
acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this infor-
mation, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document
is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks,
trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be
made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to
other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-
ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR
USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY
DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-
STOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUD-
ING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT
IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
DS618PP1
47
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