ACPL-C87A-000E [AVAGO]
Precision Optically Isolated Voltage Sensor; 精密光学隔离电压传感器
| 型号： | ACPL-C87A-000E |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Precision Optically Isolated Voltage Sensor |
| 文件： | 总14页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-C87B, ACPL-C87A, ACPL-C870
Precision Optically Isolated Voltage Sensor
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-C87B/C87A/C87± voltage sensors are optical Advanced Sigma-Delta (-) Modulation Technology
isolation amplifiers designed specifically for voltage
sensing0 Its 2 V input range and high 1 G input impe-
dance, makes it well suited for isolated voltage sensing
UnityGain1V/V,±±0.5ꢀighGainAccuracy(ACPL-C87B)
1 G Input Impedence
requirements in electronic power converters applications ± to 2 V Nominal Input Range
including motor drives and renewable energy systems0
In a typical voltage sensing implementation, a resistive
voltage divider is used to scale the DC-link voltage to suit
-3. ppm/°C Low Gain Drift
21V /°C Offset Voltage Drift
the input range of the voltage sensor0 A differential output ±015 Non-Linearity Max
voltage that is proportional to the input voltage is created
on the other side of the optical isolation barrier0
Active-ꢀigh Shutdown Pin
1±± kꢀz Wide Bandwidth
For general applications, the ACPL-C87A (±15 gain
3 V to .0. V Wide Supply Range for Output Side
tolerance) and the ACPL-C87± (±35 gain tolerance)
-4±° C to +1±.° C Operating Temperature Range
1. kV/s Common-Mode Transient Immunity
Compact, Auto-Insertable Stretched SO-8 Package
Safety and Regulatory Approvals (pending):
are recommended0 For high precision requirements,
the ACPL-C87B (±±0.5 gain tolerance) can be used0 The
ACPL-C87B/C87A/C87± family operates from a single . V
supply and provides excellent linearity0 An active-high
shutdown pin is available which reduces the IDD1 current
to only 1. A, making them suitable for battery-powered
and other power-sensitive applications0
– IEC/EN/DIN EN 6±747-.-.: 123± Vpeak working
insulation voltage
The high common-mode transient immunity (1. kV/s)
of the ACPL-C87B/C87A/C87± provides the precision and
stability needed to accurately monitor DC-link voltage in
high noise environments0 Combined with superior optical
coupling technology, the ACPL-C87B/C87A/C87± imple-
ments sigma-delta (-) modulation, chopper stabilized
amplifiers, and differential outputs to provide unequaled
isolation-mode noise rejection, low offset, high gain
accuracy and stability0 This performance is delivered in a
compact, auto-insertable Stretched SO-8 (SSO-8) package
that meets worldwide regulatory safety standards0
– UL 1.77: .±±± Vrms/1 min double protection rating
– CSA: Component Acceptance Notice #.
Applications
Isolated Voltage Sensing in AC and Servo Motor Drives
Isolated DC-Bus Voltage Sensing in Solar Inverters,
Wind Turbine Inverters
Isolated Sensor Interfaces
Signal Isolation in Data Acquisition Systems
General Purpose Voltage Isolation
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
Table 1. Pin Description
8
7
VDD2
VDD1
VIN
1
2
Pin No. Symbol Description
VOUT+
1
VDD1
Supply voltage for input side
(40. V to .0. V), relative to GND1
6
5
VOUT–
GND2
SHDN
GND1
3
4
2
3
4
.
6
7
8
VIN
Voltage input
SꢀDN
GND1
GND2
VOUT-
Shutdown pin (Active ꢀigh)
Input side ground
Output side ground
Negative output
SHIELD
Figure 1.
NOTE: A ±01 F bypass capacitor must be connected between pins 1 and
4 and between pins . and 80
VOUT+ Positive output
VDD2 Supply voltage for output side
(3 V to .0. V), referenced to GND2
Ordering Information
ACPL-C87B/C87A/C87± is UL recognized with .±±± Vrms/1 minute rating per UL 1.77 (pending)0
Table 2.
Option
Tape &
Reel
IEC/EN/DIN EN
60747-5-5
Part number
(RoHS Compliant)
-±±±E
Package
Surface Mount
Quantity
ACPL-C87B
ACPL-C87A
ACPL-C87±
Stetched
SO-8
X
X
X
X
8± per tube
1±±± per reel
-.±±E
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry0
Example:
ACPL-C87A-.±±E to order product of Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 6±747-.-.
Safety Approval and RoꢀS compliance0
Contact your Avago sales representative or authorized distributor for information0
2
Package Outline Drawing
Stretched SO-8 Package (SSO-8)
RECOMMENDED LAND PATTERN
5.850 0.254
(0.230 0.010)
PART NUMBER
DATE CODE
8
1
7
6
5
12.650
(0.498)
C87B
YWW
6.807 0.127
(0.268 0.005)
RoHS-COMPLIANCE
INDICATOR
1.905
(0.075)
2
3
4
0.64
(0.025)
1.590 0.127
(0.063 0.005)
7°
45°
0.450
(0.018)
3.180 0.127
(0.125 0.005)
0.750 0.250
0.254 0.100
(0.010 0.004)
0.200 0.100
(0.008 0.004)
(0.0295 0.010)
0.381 0.127
(0.015 0.005)
11.50 0.250
(0.453 0.010)
1.270
(0.050) BSG
Dimensions in millimeters and (inches)0
Note:
Lead coplanarity = ±01 mm (±0±±4 inches)0
Floating lead protrusion = ±02.mm (1±mils) max0
Figure 2. SSO-8 Package
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-±2± (latest revision)0 Non-ꢀalide Flux should be used0
Regulatory Information
The ACPL-C87B/C87A/C87± is pending approval by the following organizations:
IEC/EN/DIN EN 60747-5-5
Approval with Maximum Working Insulation Voltage V
= 123± Vpeak0
IORM
UL
Approval under UL 1.77, component recognition program up to V = .±±± Vrms/1 min0 File ..3610
ISO
CSA
Approval under CSA Component Acceptance Notice #., File CA 88324
3
Table 3. Insulation and Safety Related Specifications
Parameter
Symbol
Value
Unit
Conditions
Minimum External Air Gap
(External Clearance)
L(1±1)
80±
mm
Measured from input terminals to output terminals,
shortest distance through air
Minimum External
Tracking (External Creepage)
L(1±2)
CTI
80±
±0.
mm
mm
Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Plastic Gap
(Internal Clearance)
Through insulation distance, conductor to conductor,
usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity
Tracking Resistance
(Comparative Tracking Index)
> 17.
IIIa
V
DIN IEC 112/VDE ±3±3 Part 1
Isolation Group
Material Group (DIN VDE ±11±, 1/89, Table 1)
[1]
Table 4. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Value
Units
Installation classification per DIN VDE ±11±/1089, Table 1
for rated mains voltage ≤ 1.± Vrms
I-IV
I-IV
I-IV
I-IV
I-III
for rated mains voltage ≤ 3±± Vrms
for rated mains voltage ≤ 4.± V rms
for rated mains voltage ≤ 6±± Vrms
for rated mains voltage ≤ 1±±± Vrms
Climatic Classification
../1±./21
2
Pollution Degree (DIN VDE ±11±/1089)
Maximum Working Insulation Voltage (Pending Qualification)
VIORM
VPR
123±
23±6
Vpeak
Vpeak
Input to Output Test Voltage, Method b
VIORM x 1087. = VPR, 1±±5 Production Test with tm = 1 sec, Partial Discharge < . pC
Input to Output Test Voltage, Method a
VIORM x 106 = VPR, Type and Sample Test, tm = 1± sec, Partial Discharge < . pC
VPR
1968
8±±±
Vpeak
Vpeak
ꢀighest Allowable Overvoltage (Transient Overvoltage, tini = 6± sec)
VIOTM
Safety-limiting values (Maximum values allowed in the event of a failure)
Case Temperature
Input Current [2]
Output Power [2]
TS
17.
23±
6±±
°C
mA
mW
IS,INPUT
PS,OUTPUT
Insulation Resistance at TS, VIO = .±± V
Notes:
RS
≥ 1±9
10 Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application0
4
Table 5. Absolute Maximum Rating
Parameter
Symbol
Min.
-..
-4±
-±0.
-2
Max.
Units
°C
°C
V
Storage Temperature
Ambient Operating Temperature
Supply Voltage
Steady-State Input Voltage [1, 3]
Two-Second Transient Input Voltage [2]
Logic Input
TS
+12.
TA
+1±.
VDD1, VDD2
VIN
60±
VDD1 + ±0.
VDD1 + ±0.
VDD1 + ±0.
VDD2 + ±0.
V
VIN
-6
V
VSD
-±0.
-±0.
V
Output Voltages
VOUT+, VOUT−
V
Lead Solder Temperature
Notes:
26±° C for 1± sec0, 106 mm below seating plane
10 DC voltage of up to -2 V on the inputs does not cause latch-up or damage to the device0
20 Transient voltage of 2 seconds up to -6 V on the inputs does not cause latch-up or damage to the device0
30 Absolute maximum DC current on the inputs = 1±± mA, no latch-up or device damage occurs0
Table 6. Recommended Operating Conditions
Parameter
Symbol
TA
Min.
Max.
+1±.
.0.
Units
°C
V
Ambient Operating Temperature
VDD1 Supply Voltage
VDD2 Supply Voltage
Input Voltage Range[1]
Shutdown Enable Voltage
Notes:
-4±
VDD1
VDD2
VIN
40.
30±
.0.
V
±
20±
V
VSD
VDD1 – ±0.
VDD1
V
10 2 V is the nominal input range0 Full scale input range (FSR) is 2046 V0
.
Table 7. Electrical Specifications
Unless otherwise noted, T = -4±° C to +1±.° C, V
= 40. V to .0. V, V
= 303 V to .0. V, V = ± – 2 V, and V = ± V0
A
DD1
DD2
IN
SD
[1]
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test Conditions/Notes
Fig.
DC CHARACTERISTICS
Input Offset Voltage
VOS
-909
-±03
21
909
mV
TA = 2.° C
3, 4
.
Magnitude of Input Offset
Change vs0 Temperature
|dVOS/dTA|
V/°C
TA = –4±° C to +1±.° C
; Direct short across inputs0
Gain (ACPL-C87B, ±±0.5)
G±
±099.
±0994
1
10±±.
10±±4
V/V
V/V
TA = 2.° C; VDD2 = . V;
Note 20
6, 7
6, 7
±0999
TA = 2.° C; VDD2 = 303 V;
Note 20
Gain (ACPL-C87A, ±15)
Gain (ACPL-C87±, ±35)
G1
±099
±097
1
10±1
10±3
V/V
V/V
TA = 2.° C; Note 20
TA = 2.° C; Note 20
6, 7
6, 7
8
G3
1
Magnitude of Gain Change
vs0 Temperature
dG/dTA
-3.
ppm/°C TA = -4±° C to +1±.° C
Nonlinearity
NL
±0±.
±01
5
VIN = ± to 2 V, TA = 2.° C
TA = -4±° C to +1±.° C
9, 1±
11
Magnitude of NL Change
vs0 Temperature
|dNL/dTA|
±0±±±2
5/°C
INPUTS AND OUTPUTS
Recommended Input Range
VINR
FSR
2
V
V
Referenced to GND1
Referenced to GND1
Full-Scale Differential Voltage
Input Range
2046
Shutdown Logic Low
Input Voltage
VIL
±08
.
TA = 2.° C
TA = 2.° C
VIN = ± V
Shutdown Logic ꢀigh
Input Voltage
VIꢀ
VDD – ±0.
-±01
Input Bias Current
IIN
-±0±±1.
1
A
Magnitude of IIN Change
vs0 Temperature
dIIN/dTA
nA/°C
Equivalent Input Impedance
RIN
1±±±
1023
M
Output Common-Mode
Voltage
VOCM
V
VOUT+ or VOUT–
Output Voltage Range
Output Short-Circuit Current
Output Resistance
VOUTR
Vocm ±
1023
V
VSD = ± V0 Note 40
13
|IOSC
|
3±
mA
VOUT+ or VOUT–,
shorted to GND2 or VDD2
ROUT
36
VOUT+ or VOUT–
6
Table 7. Electrical Specifications (continued)
Unless otherwise noted, T = -4±° C to +1±.° C, V
= 40. V to .0. V, V
= 303 V to .0. V, V = ± – 2 V, and V = ± V0
A
DD1
DD2
IN
SD
[1]
Parameter
Symbol
Min.
Typ.
Max. Unit
Test Conditions/Notes
Fig.
AC CHARACTERISTICS
Vout Noise
Nout
±0±13
mVrms Vin = ± V;
12
Output low-pass filtered
to 18± Kꢀz0 Note 30
Small-Signal Bandwidth (-3 dB)
f–3 dB
tPD1±
tPD.±
tPD9±
tR/F
7±
1±±
202
307
.03
207
2.
kꢀz
s
Guaranteed by design
Step input0
Input to Output
.±5-1±5
30±
.0.
60.
40±
4±
18
18
18
Propagation Delay
.±5-.±5
.±5-9±5
s
Step input0
s
Step input0
Output Rise/Fall Time (1±5-9±5)
Shutdown Delay
s
Step input (tPD9± - tPD1±
)
tSD
s
Vin = 2 V
17
Enable Delay
tON
1.±
1.
2±±
s
Common Mode Transient Immunity
Power Supply Rejection
CMTI
PSR
1±
kV/s
dB
VCM = 1 kV, TA = 2.° C
1 Vpp 1 kꢀz sine wave
-78
ripple on VDD1
,
differential output
POWER SUPPLIES
Input Side Supply Current
IDD1
1±0.
1.
1.
mA
A
VSD = ± V
VSD = . V
IDD2
60.
601
12
11
mA
mA
. V supply
303 V supply
Notes:
10 All Typical values are under Typical Operating Conditions at T = 2.° C, V
= . V, V = . V0
DD2
A
DD1
20 Gain is defined as the slope of the best-fit line of differential output voltage (V
error adjusted0
– V
) versus input voltage over the nominal range, with offset
OUT-
OUT+
30 Noise is measured at the output of the differential to single ended post amplifier0
40 When is V = . V or when shutdown is enabled, V
is close to ±V and V
is at close to 2046 V0 This is similar to when VDD1 is not supplied0
SD
out+
out-
Table 8. Package Characteristics
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Note
Input-Output Momentary
Withstand Voltage
VISO
.±±±
Vrms
Rꢀ < .±5, t = 1 min0,
TA = 2.° C
1, 2
Resistance (Input-Output)
Capacitance (Input-Output)
Notes:
RI-O
CI-O
> 1±12
±0.
V
I-O = .±± VDC
3
3
pF
f = 1 Mꢀz
10 In accordance with UL 1.77, each optocoupler is proof tested by applying an insulation test voltage ≥ 6±±± Vrms for 1 second (leakage detection
current limit, I ≤ . mA)0 This test is performed before the 1±±5 production test for partial discharge (method b) shown in IEC/EN/DIN EN 6±747-
I-O
.-. Insulation Characteristic Table0
20 The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating0 For the continuous voltage rating, refer to the IEC/EN/DIN EN 6±747-.-. insulation characteristics table and your equipment level
safety specification0
30 This is a two-terminal measurement: pins 1–4 are shorted together and pins .–8 are shorted together0
7
Typical Performance Plots
All ±3(sigma symbol) plots are based on characterization test result at the point of product release0 For guaranteed
specification, refer to the respective Electrical Specifications section0
5
4
3
2
1.5
1
2
0.5
0
1
0
-1
-2
-3
-4
-5
-0.5
-1
-1.5
-2
4.5
5
5.5
3
3.5
4
4.5
5
5.5
Vdd1(V)
Vdd2 (V)
Figure 3. Input Offset vs Supply VDD1
Figure 4. Input Offset vs Supply VDD2
10
8
6
4
2
1.003
1.002
1.001
1.000
0.999
0.998
M+3
Mean
M-3
0
-2
-4
-6
-8
- 10
0.997
4.5
5
Vdd1 (V)
5.5
-55 -35 -15
5
25
45
65
85 105 125
Temp (qC)
Figure 5. Input Offset vs Temperature
Figure 6. Gain vs Supply VDD1
1.00300
1.00200
1.00100
1.00000
0.99900
0.99800
0.99700
1.003
1.002
1.001
1.000
0.999
0.998
0.997
3
3.5
4
4.5
5
5.5
-55 -35 -15
5
25 45 65 85 105 125
Vdd2 (V)
Temp (qC)
Figure 7. Gain vs Supply VDD2
Figure 8. Gain vs Temperature
8
0.1
0.08
0.06
0.04
0.02
0
0.1
0.08
0.06
0.04
0.02
0
4.5
5
5.5
3
3.5
4
4.5
5
5.5
Vdd1 (V)
Vdd2 (V)
Figure 9. Non-Linearity vs Supply VDD1
Figure 10. Non-Linearity vs Supply VDD2
0.1
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
17
Vin = 0 V
15
Vin = 1 V
13
11
9
Vin = 2 V
7
5
3
1
-1
-55 -35 -15
5
25
45
65
85 105 125
0
20
40
60
80
100 120 140 160
Temp (qC)
Freq Filter (khz)
Figure 11. Non-Linearity vs Temperature
Figure 12. AC noise vs Filter Freq vs Vin
3
1
0
VOUT+
VOUT–
2.5
2
-1
-2
-3
-4
-5
-6
1.5
1
0.5
0
1000
10000
Bandwidth (Hz)
100000
0
0.5
1
1.5
VIN
2
2.5
3
Figure 13 VIN vs VOUT+, VOUT-
Figure 14. Frequency Response
9
200
180
160
140
120
100
80
60
40
20
0
6
5
4
3
2
1
0
TPLH 50-10
TPLH 50-50
TPLH 50-90
1000
10000
100000
-55 -35 -15
5
25
45
65
85 105 125
Bandwidth (Hz)
Temp (qC)
Figure 15. Phase Response
Figure 16. Propagation Delay vs Temperature
5V
VSD
Vin
0 V
2 V
tSD
tON
0 V
+2 V
VOutDiff
0 V
-2.46 V
Figure 17. Shutdown And Wakeup Input To Output Timing Diagram. VOut Diff = VOut+ - VOut-
2 V
VIN
0 V
2 V
VOut Diff
0 V
TPLH50-10
TPLH50-50
TPLH50-90
Figure 18. Input to Output Propagation Delay Timing Diagram. VOut Diff = VOut+ - VOut-
1±
Definitions
Gain
Application Information
Application Circuit
Gain is defined as the slope of the best-fit line of differen- The typical application circuit is shown in Figure 190
tial output voltage (V
range, with offset error adjusted out0
– V
) over the nominal input
The ACPL-C87X voltage sensor is often used in photo-
voltaic (PV) panel voltage measurement and tracking in
PV inverters, and DC bus voltage monitoring in motor
drivers0 The high voltage across rails needs to be scaled
down to fit the input range of the iso-amp by choosing R1
and R2 values according to appropriate ratio0
OUT+
OUT-
Nonlinearity
Nonlinearity is defined as half of the peak-to-peak output
deviation from the best-fit gain line, expressed as a per-
centage of the full-scale differential output voltage0
The ACPL-C87X senses the single-ended input signal
and produces differential outputs across the galvanic
isolation barrier0 The differential outputs (Vout+, Vout-)
can be connected to an op-amp to convert to a single-
Common Mode Transient Immunity, CMTI, also known
as Common Mode Rejection
CMTI is tested by applying an exponentially rising/falling ended signal or directly to two ADCs0 The op-amp used in
voltage step on pin 4 (GND1) with respect to pin . (GND2)0 the external post-amplifier circuit should be of sufficiently
The rise time of the test waveform is set to approximately high precision so that it does not contribute a significant
.± ns0 The amplitude of the step is adjusted until the dif- amount of offset or offset drift relative to the contribu-
ferential output (V
– V
) exhibits more than a 2±± tion from the isolation amplifier0 Generally, op-amps with
OUT+
OUT-
mV deviation from the average output voltage for more bipolar input stages exhibit better offset performance
than 1μs0 The ACPL-C87x will continue to function if more than op-amps with JFET or MOSFET input stages0
than 1± kV/s common mode slopes are applied, as long
In addition, the op-amp should also have enough
as the breakdown voltage limitations are observed0
bandwidth and slew rate so that it does not adversely
affect the response speed of the overall circuit0 The post-
amplifier circuit includes a pair of capacitors (C4 and C.)
that form a single-pole low-pass filter; these capacitors
allow the bandwidth of the post-amp to be adjusted in-
dependently of the gain and are useful for reducing the
output noise from the isolation amplifier0
Power Supply Rejection, PSR
PSRR is the ratio of differential amplitude of the ripple
outputs over power supply ripple voltage, referred to the
input, expressed in dB0
The gain-setting resistors in the post-amp should have a
tolerance of 15 or better to ensure adequate CMRR and
adequate gain tolerance for the overall circuit0 Resistor
networks can be used that have much better ratio toler-
ances than can be achieved using discrete resistors0 A
resistor network also reduces the total number of compo-
nents for the circuit as well as the required board space0
C5
100 pF
L1
U1
VDD1
VDD1
VDD2
R6
10K, 1%
V+
U2
1
2
3
4
8
7
6
5
VDD2
R1
R3
VIN
VOUT+
10K,1%
Vout
C3
100 nF
R4
10K,1%
ACPL-C87X
SHDN
GND1
VOUT-
R2
10K
C1
C2
OPA237
100 pF 100 nF
GND2
V-
GND1
GND2
R5
10K, 1%
C4
100 pF
L2
GND2
Figure 19. Typical application circuit.
11
Measurement Accuracy and Power Dissipation of the Resistive Divider
The input stage of the typical application circuit in Figure consumes about 12 mW, assuming V is set at 2 V0 If the R2
IN
19 can be simplified as the diagram shown in Figure 2±0 is reduced to 1± k to reduce error to ±0±±15, the power
R2 and R , input resistance of the ACPL-C87X, create a consumption will increase to about 12± mW0 In energy
IN
current divider that results in an additional measurement efficiency critical applications such as PV inverters and
error component that will add on to the tot on top of the battery-powered applications, this trade-off between
device gain error0 With the assumption that R1 and R
measurement accuracy and power dissipation in the
resistive string provides flexibility in design priority0
IN
have a much higher value than R2, the resulting error can
be estimated to be R2/R 0
IN
Isolated Temperature Sensing using Thermistor
With R of 1 GW for the ACPL-C87X, this additional mea-
IN
IGBTs are an integral part of a motor or servo drive system
and because of the high power that they usually handle,
it is essential that they have proper thermal management
and are sufficiently cooled0 Long term overload conditions
could raise the IGBT module temperature permanently or
failure of the thermal management system could subject
the module to package overstress and lead to catastrophic
failures0 One common way to monitor the temperature
of the module is through using a NTC type thermistor
mounted onto the IGBT module0 Some IGBT module man-
ufacturers also have IGBTs that comes with the thermistor
integrated inside the module0 In some cases, it is necessary
to isolate this thermistor to provide added isolation and
insulation due to the high power nature of the IGBTs0 The
ACPL-C87x voltage sensor can be used to easily meet
such a requirement, while providing good accuracy and
non-linearity0 Figure0 21 shows an example of such an
implementation0 The ACPL-C87x is used to isolate the
thermistor voltage which is later fed by the post amp
stage to an ADC onboard the microcontroller (MCU) to
determine the module temperature0 The thermistor needs
to be biased in way that its voltage output will optimize
the 2 V input range of the ACPL-C87x across the intended
temperature measurement range0
surement error is negligible with R2 up to 1 M, where the
error is approximately ±0150 Though small, it can be further
reduced by reducing the R2 to 1±± k (error of ±0±15
approximately), or 1± k (error of ±0±±15 approximately)0
ꢀowever with lower R2, a drawback of higher power dis-
sipation in the resistive divider string needs to be consid-
ered, especially in higher voltage sensing applications0 For
example, with 6±± V DC across L1 and L2 and R2 of 1±± k
for ±0±15 measurement error, the resistive divider string
R1
RIN
+
R2
GND
ACPL-C87x
Figure 20. Simplified Input Stage.
HV+
U
V
W
Vdd
+
GND
ADC
Post
Amp
HV-
ACPL-C87x
NTC Thermistor
IGBT Module
MCU
Figure 21. Thermistor sensing in IGBT Module
12
Power Supplies and Bypassing
As shown in Figure 22, 1±± nF bypass capacitors (C2, C3)
should be located as close as possible to the pins of the
isolation amplifier0 The bypass capacitors are required
because of the high-speed digital nature of the signals
inside the isolation amplifier0 A 1±± pF bypass capacitor
(Cin) is also recommended at the input pins due to the
switched-capacitor nature of the input circuit0 The input
bypass capacitor Cin also forms part of the anti-aliasing
filter, which is recommended to prevent high-frequency
noise from aliasing down to lower frequencies and inter-
fering with the input signal0 When R1 is far greater than R2,
the low-pass anti-aliasing filter corner frequency can be
calculated by 1/(2R2Cin)0 The input filter also performs
an important reliability function – it reduces transient
spikes from ESD events flowing through the high voltage
rails0
A power supply of . V is required to power the ACPL-C87x
input side VDD10 In many motor drive DC bus voltage
sensing applications, this .V supply is most often obtained
from the same supply used to power the power transistor
gate drive circuit using an inexpensive 78L±. three-ter-
minal regulator0 To help attenuate high frequency power
supply noise or ripple, a resistor or inductor can be used
in series with the input of the regulator to form a low-pass
filter with the regulator’s input bypass capacitor0
In some other applications a dedicated supply might be
required to supply the VDD10 These applications include
photovoltaic (PV) inverter voltage tracking and measure-
ment, temperature sensor signal isolation0 In these cases
it is possible to add an additional winding on an existing
transformer0 Otherwise, some sort of simple isolated
supply can be used, such as a line powered transformer or
a high-frequency DC-DC converter module0
HV+
R1
Floating
PositiveSupply
OUT
IN
78L05
5V
C2
0.1μF
C1
0.1μF
VDD2
VDD1
VIN
VOUT+
GateDrive
Circuit
C3
ACPL-C87A
0.1μF
Cin
0.1nF
R2
VOUT-
SHDN
GND1
GND2
HV-
Figure 22. Recommended Power Supply and Bypassing
13
PC Board Layout
The design of the printed circuit board (PCB) should
follow good layout practices, such as keeping bypass
capacitors close to the supply pins, keeping output signals
away from input signals, the use of ground and power
planes, etc0 In addition, the layout of the PCB can also
affect the isolation transient immunity (CMTI) of the ACPL-
C87x, primarily due to stray capacitive coupling between
the input and the output circuits0 To obtain optimal CMTI
performance, the layout of the PC board should minimize
any stray coupling by maintaining the maximum possible
distance between the input and output sides of the circuit
and ensuring that any ground or power plane on the PC
board does not pass directly below or extend much wider
than the body of the ACPL-C87A0 The placement of the
input capacitor which forms part of the anti-aliasing filter
together with the resistor network should also be placed
as close as possible to the Vin pin0
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-3563EN - July 24, 2012
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