ACPL-C87AT [AVAGO]
Automotive High Precision DC Voltage Isolation Sensor;
| 型号： | ACPL-C87AT |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Automotive High Precision DC Voltage Isolation Sensor |
| 文件： | 总14页 (文件大小：1429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ACPL-C87AT/ACPL-C87BT
Automotive High Precision DC Voltage Isolation Sensor
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-C87AT/C87BT isolation sensors utilize superior •ꢀ Unity Gain
optical coupling technology, with sigma-delta (S-D)
•ꢀ +/-0.5% (ACPL-C87BT) and +/-1% (ACPL-C87AT) Gain
analog-to-digital converter, chopper stabilized amplifiers,
and a fully differential circuit topology to provide
unequaled isolation-mode noise rejection, low offset,
high gain accuracy and stability.
Tolerance @ 25° C
•ꢀ -0.3 mV Input Offset Voltage
•ꢀ 0.05% Non Linearity
•ꢀ 25 ppm/°C Gain Drift vs. Temperature
•ꢀ 100 kHz Bandwidth
ACPL-C87AT ( 1% gain tolerance) and ACPL-C87BT
( 0.5% gain tolerance) are designed for high precision
DC voltage sensing in electronic motor drives, DC/DC
and AC/DC converter and battery monitoring system. The
ACPL-C87AT/C87BT features high input impedance and
operate with full span of analog input voltage up to 2.46 V.
The shutdown feature provides power saving and can be
controlled from external source, such as microprocessor.
•ꢀ 0 to 2 V Nominal Input Range
•ꢀ Qualified to AEC-Q100 Grade 1 Test Guidelines
•ꢀ Operating Temperature: -40° C to +125° C
•ꢀ Shutdown Feature (Active High)
•ꢀ 15 kV/ms Common-Mode Rejection at V = 1 kV
CM
The high common-mode transient immunity (15 kV/ms)
of the ACPL-C87AT/C87BT maintains the precision and
•ꢀ Working Voltage, V
= 1414 V
peak
IORM
stability needed to accurately monitor DC rail voltage in •ꢀ Compact, Surface Mount Stretched SO8 Package
high noise motor control environments. This galvanic safe
isolation solution is delivered in a compact, surface mount
stretched SO-8 (SSO-8) package that meets worldwide
regulatory safety standards.
•ꢀ Worldwide Safety Approval:
– UL 1577 (5000 V
– CSA
/ 1 min.)
RMS
2
– IEC/EN/DIN EN 60747-5-5
Avago R Coupler isolation products provide the rein-
forced insulation and reliability needed for critical auto-
motive and high temperature industrial applications.
Applications
•ꢀ Automotive BMS Battery Pack Voltage Sensing
•ꢀ Automotive DC/DC Converter Voltage Sensing
•ꢀ Automotive Motor Inverter DC Bus Voltage Sensing
•ꢀ Automotive AC/DC (Charger) DC Output Voltage Sensing
•ꢀ Isolation Interface for Temperature Sensing
Functional Diagram
VDD1
VDD2
8
7
6
1
2
VIN
VOUT+
VOUT-
0.1 µF
0.1 µF
SHDN
3
4
•ꢀ General Purpose Voltage Sensing and Monitoring
5
SHIELD
GND1
GND2
Figure 1. Functional Diagram
0.1 mF bypass capacitor must be connected between pin 1 and pin 4, and
pin 5 and pin 8 as shown.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram (Cont.)
VDD1
VDD2
VIN
VOUT = VOUT+ − VOUT-
0 − 2 V
VOUT+
VOUT-
0 − 2 V
VIN
SHDN
Isolation
GND1
GND2
Figure 2. Functional Diagram 2
5 V
15 V
V+
MEV1S1505DC
IN OUT
5 V
Gate
Driver
1 nF
R1
M
0.1 µF
20 kΩ
39 Ω
Gate
Driver
0.1 µF
R4 20 kΩ
R5 20 kΩ
VOUT
R2
10 nF
V-
1 nF
20 kΩ
ACPL-C87AT/BT
Figure 3. Typical Voltage Sensing Circuit
1
2
8
VDD1
VIN
VDD2
VOUT+
7
SHDN
GND1
VOUT-
3
4
6
5
GND2
Figure 4. Package Pinout
Pin Description
Pin No. Pin Name Description
Pin No. Pin Name Description
1
VDD1
Input power supply
When VDD1 = 0, then VOUT+ = 0 V, VOUT- = 2.6 V
8
VDD2
Output power supply
2
3
VIN
Voltage input, Full scale Range = 2.46 V
7
6
VOUT+
VOUT-
Positive output voltage
Negative output voltage
SHDN
Shutdown (Active High)
When active, then VOUT+ = 0 V, VOUT- = 2.6 V
4
GND1
Input Side Ground
5
GND2
Output Side Ground
2
Ordering Information
Option
Surface
Mount
Tape &
Reel
UL 5000 V
1 Minute rating
/
IEC/EN/DIN EN
60747-5-5
rms
Part number
(RoHS Compliant)
-000E
Package
Quantity
ACPL-C87AT
ACPL-C87BT
Stetched
SO-8
X
X
X
X
X
X
80 per tube
1000 per reel
-500E
X
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example:
ACPL-C87AT-500E to order product of SSO-8 Surface Mount package in Tape and Reel packaging with RoHS compliant.
Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawing (Stretched SO8)
RECOMMENDED LAND PATTERN
5.850 0.ꢀ5ꢁ
(0.ꢀ30 0.0ꢂ0ꢃ
PART NUMBER
DATE CODE
8
7
6
5
ꢂꢀ.650
(0.ꢁ98ꢃ
C87BT
YWW
EE
6.807 0.ꢂꢀ7
(0.ꢀ68 0.005ꢃ
RoHS-COMPLIANCE
INDICATOR
ꢂ.905
(0.075ꢃ
ꢂ
ꢀ
3
ꢁ
EXTENDED DATECODE
FOR LOT TRACKING
0.6ꢁ
(0.0ꢀ5ꢃ
ꢂ.590 0.ꢂꢀ7
(0.063 0.005ꢃ
7°
ꢁ5°
0.ꢁ50
(0.0ꢂ8ꢃ
3.ꢂ80 0.ꢂꢀ7
(0.ꢂꢀ5 0.005ꢃ
0.750 0.ꢀ50
0.ꢀ5ꢁ 0.ꢂ00
(0.0ꢂ0 0.00ꢁꢃ
0.ꢀ00 0.ꢂ00
(0.008 0.00ꢁꢃ
(0.0ꢀ95 0.0ꢂ0ꢃ
0.38ꢂ 0.ꢂꢀ7
(0.0ꢂ5 0.005ꢃ
ꢂꢂ.50 0.ꢀ50
(0.ꢁ53 0.0ꢂ0ꢃ
ꢂ.ꢀ70
(0.050ꢃ BSG
Dimensions in millimeters and (inches).
Note:
Lead coplanarity = 0.1 mm (0.004 inches).
Floating lead protrusion = 0.25mm (10mils) max.
Figure 5. Package Outline Drawing
3
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision).
Note: Non-halide flux should be used
Regulatory Information
The ACPL-C87AT and ACPL-C87BT are approved by the following organizations:
UL
CSA
IEC/EN/DIN EN 60747-5-5
UL 1577, component recognition
Approved under CSA Component
Acceptance Notice #5.
IEC 60747-5-5
EN 60747-5-5
program up to V = 5kV
ISO
RMS
DIN EN 60747-5-5
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Description
Symbol
Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms
I – IV
I – IV
I - IV
I - IV
I - III
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 450 Vrms
for rated mains voltage ≤ 600 Vrms
for rated mains voltage ≤ 1000 Vrms
Climatic Classification
40/125/21
2
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
VIORM
VPR
1414
2651
Vpeak
Vpeak
Input to Output Test Voltage, Method b
VIORM X 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC
Input to Output Test Voltage, Method a
VIORM X 1.6 = VPR, Type and Sample Test with tm = 10 sec, Partial discharge < 5 pC
VPR
2262
8000
Vpeak
Vpeak
Highest Allowable Overvoltage
VIOTM
(Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values allowed in the event of a failure,
also see Figure 6.
Case Temperature
Input Current
Ts
175
230
600
°C
mA
mW
IS, INPUT
PS,OUTPUT
Output Power
Insulation Resistance at TS, VIO = 500 V
RS
> 109
W
700
PS (mW)
IS (mW)
600
500
400
300
200
100
0
0
25
50
75
100
125 150 175 200
TS – CASE TEMPERATURE – °C
Figure 6. Dependence of safety limiting values on temperature
4
Insulation and Safety Related Specifications
Parameter
Symbol
Value
Unit
Conditions
Minimum External Air Gap
(External Clearance)
L(101)
8.0
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External
Tracking (External Creepage)
L(102)
CTI
8.0
0.5
mm
mm
Measured from input terminals to output terminals,
shortest distance path along body.
Minimum Internal Plastic Gap
(Internal Clearance)
Through insulation distance conductor to conductor,
usually the straight line distance thickness between
the emitter and detector.
Tracking Resistance
(Comparative Tracking Index)
> 175
IIIa
Volts
DIN IEC 112/VDE 0303 Part 1
Isolation Group
(DIN BDE0109)
Material Group (DIN VDE 0110)
Absolute Maximum Ratings
Parameter
Symbol
Min.
-55
Max.
Units
°C
Note
Storage Temperature
Ambient Operating Temperature
Supply Voltages
TS
150
TA
-40
125
°C
VDD1, VDD2
VIN
-0.5
-2.0
-0.5
-0.5
6.0
Volts
Volts
Volts
Volts
Input Voltage
VDD1 + 0.5
VDD1 + 0.5
VDD2 + 0.5
Shutdown Voltage
Output Voltages
VSD
VOUT+, VOUT-
Recommended Operating Conditions
Parameter
Symbol
TA
Min.
-40
4.5
3.0
0
Max.
125
5.5
Units
°C
Notes
Ambient Operating Temperature
Input Supply Voltage
Output Supply Voltage
Input Voltage
VDD1
VDD2
VIN
Volts
Volts
Volts
Volts
5.5
2.0
Shutdown Voltage
VSD
VDD1 – 0.5
VDD1
5
Electrical Specifications
Unless otherwise noted, all typical values at T = 25 °C, V
specifications are at recommended voltage supply conditions: 4.5V < V
= V
= 5 V, V = 0 to 2 V, V = 0 V; all Minimum/Maximum
A
DD1
DD2 IN SD
< 5.5V, 4.5V < V
< 5.5V
DD2
DD1
Parameter
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Fig.
Note
POWER SUPPLIES
Input Supply Current
IDD1
10.5
20
15
mA
VSD = 0 V
VSD = 5 V
18, 19
Input Supply Current
(Shutdown Mode)
IDD1(SD)
mA
Output Supply Current
IDD2
G0
6.5
1
12
mA
V/V
18, 20
8
DC CHARACTERISTICS
Gain
0.995
0.99
1.005
TA = 25 °C,
VIN = 0 – 2 V,
VDD1 = VDD2 = 5.0 V
1
1
(ACPL-C87BT, +/- 0.5%)
Gain
G1
1
1.01
V/V
TA = 25 °C,
8, 11
(ACPL-C87AT, +/- 1%)
VIN = 0 – 2 V,
VDD1 = VDD2 = 5.0 V
Magnitude of Gain
Change vs Temperature
|dG/dTA|
|dG/dVDD1
|dG/dVDD2
NL
25
ppm/°C TA = -40 °C to +125 °C
11
Magnitude of Gain
Change vs VDD1
|
|
0.05
0.02
0.05
-0.3
21
%/V
%/V
%
TA = 25 °C
TA = 25 °C
12
Magnitude of Gain
Change vs VDD2
12, 13
15, 16
Nonlinearity
0.12
10
VIN = 0 to 2 V,
TA = -40 °C to +125 °C
Input Offset Voltage
VOS
-10
mV
VIN is shorted to GND1,
TA = 25 °C
7, 9,
10
Magnitude of Input
Offset Change vs.
Temperature
|dVOS/dTA|
mV/°C
VIN is shorted to GND1,
TA = -40 °C to +125 °C
7, 9
INPUTS AND OUTPUTS
Full-Scale Differential
Voltage Input Range
FSR
2.46
V
Referenced to GND1
VIN = 0 V
Input Bias Current
IIN
-0.1
-0.001
1000
0.1
mA
22
22
Equivalent Input
Impedance
RIN
MW
Output Common-Mode
Voltage
VOCM
1.23
V
VIN =0 V, VSD = 0 V
VOUT+ Range
VOUT - Range
VOUT+
VOUT-
|IOSC
VOCM+1.23
VOCM-1.23
30
V
VIN = 2.5 V
VIN = 2.5 V
V
Output Short-Circuit
Current
|
mA
VOUT+ or VOUT-,
shorted to GND2 or VDD2
Output Resistance
ROUT
36
W
VIN = 0 V
6
Electrical Specifications (continued)
Unless otherwise noted, all typical values at T = 25 °C, V
specifications are at recommended voltage supply conditions: 4.5V < V
= V
= 5 V, V = 0 to 2 V, V = 0 V; all Minimum/Maximum
IN SD
A
DD1
DD2
< 5.5V, 4.5V < V
< 5.5V
DD1
DD2
Parameter
Symbol Min.
Typ.
Max.
Unit
Test Conditions
Fig.
Note
AC CHARACTERISTICS
Small-Signal Bandwidth (-3 dB)
VOUT Noise
f–3 dB
NOUT
tPD10
100
1.3
2.2
kHz
mVRMS VIN = 2 V; BW = 1 kHz
23
5
Input to Output Propagation
Delay (10%-10%)
3.5
6.0
7.0
4.0
ms
ms
ms
ms
VIN = 0 to 2 V Step
VIN = 0 to 2 V Step
VIN = 0 to 2 V Step
Step Input
21, 26
Input to Output Propagation
Delay (50%-50%)
tPD50
tPD90
tR/F
3.7
5.3
2.7
21, 26
21, 26
Input to Output Propagation
Delay (90%-90%)
Output Rise / Fall Time
(10%-90%)
Shutdown Time
tSD
25
ms
ms
dB
25
25
Shutdown Recovery Time
Power Supply Rejection
tON
PSR
150
-78
1 Vp-p, 1 kHz sine wave
ripple on VDD1
,
differential output
Common Mode Transient
Immunity
CMTI
10
15
kV/ms
VCM = 1 kV, TA = 25 °C
24
2
Package Characteristics
Unless otherwise noted, all typical values are at T = 25 °C; all Minimum/Maximum specifications are at Recommended
A
Operating Conditions.
Parameter
Symbol Min.
Typ.
Max.
Units
Test Conditions
Fig.
Note
Input-Output Momentary
Withstand Voltage *
VISO
5000
VRMS
RH < 50%, t = 1 min.,
TA = 25 °C
3, 4
Input-Output Resistance
Input-Output Capacitance
RI-O
CI-O
1014
0.5
W
VI-O = 500 VDC
f =1 MHz
3
3
pF
*
The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating.
Notes:
1. Gain is defined as the slope of the best-fit line of differential output voltage (V
- V
) versus input voltage over the nominal range, with offset
OUT+ OUT-
error adjusted. 0.5% Gain tolerance for ACPL-C87BT and 1% tolerance for ACPL-C87AT.
2. Common mode transient immunity (CMTI) is tested by applying a fast rising/falling voltage pulse across GND1 (pin 4) and GND2 (pin 5). The output
glitch observed is less than 0.2 V from the average output voltage for less than 1 ms.
3. Device considered a two terminal device: pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8 shorted together.
4. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage > 6000 V
5. Noise is measured at the output of the differential to single ended post amplifier.
for 1 second.
RMS
7
Typical Characteristic Plots and Test Conditions
All ±3s plots are based on characterization test result at the point of product release. For guaranteed specification, refer
to the respective Electrical Specifications section.
VDD1
VDD2
VDD1
VDD2
8
8
1
2
1
2
0.1 µF
0.1 µF
V VOLTMETER
0.1 µF
7
6
5
7
6
5
VIN
ACPL-C87AT/BT
ACPL-C87AT/BT
V VOLTMETER
3
4
0.1 µF
3
4
GND1
GND2
GND1
GND2
Figure 7. Input Offset Voltage Test Circuit
Figure 8. Gain and Nonlinearity Test Circuit
10
8
0
-1
-2
-3
-4
-5
-6
-7
vs Vdd1
vs Vdd2
+3 SIGMA
MEAN
-3 SIGMA
6
4
2
0
-2
-4
-6
-8
-10
-40 -20
0
20
40
60
80 100 120 140
4.5
4.75
5
5.25
5.5
TA - TEMPERATURE - °C
VDD - SUPPLY VOLTAGE - V
Figure 9. Input Offset Voltage vs Temperature
Figure 10. Input Offset vs Supply Voltage
1.003
1.002
1.001
1.000
0.999
0.998
0.997
1.006
1.004
1.002
1.000
0.998
0.996
0.994
vs Vdd1
vs Vdd2
MEAN
0.992
0.990
0.988
+3 SIGMA
-
3 SIGMA
-40 -20
0
20
40 60
TA - TEMPERATURE - °C
80 100 120 140
4.5
4.75
5
5.25
5.5
VDD - SUPPLY VOLTAGE - V
Figure 11. Gain vs Temperature
Figure 12. Gain vs Supply Voltage
8
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
0.988
0.08
0.07
0.06
0.05
0.04
VDD2 = 3.3 V
VDD2 = 5 V
vs Vdd1
vs Vdd2
VDD2 = 5.5 V
-40 -20
0
20 40 60 80 100 120 140
TA - TEMPERATURE - °C
4.5
4.75
5
5.25
5.5
VDD - SUPPLY VOLTAGE - V
Figure 13. Gain vs Temperature at Different VDD2
Figure 14. Nonlinearity vs Supply Voltage
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.12
0.10
0.08
0.06
0.04
0.02
0.00
VDD2 = 3.3 V
VDD2 = 5.0 V
VDD2 = 5.5 V
MEAN
+3 SIGMA
-3 SIGMA
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
Figure 15. Nonlinearity vs Temperature
Figure 16. Nonlinearity vs Temperature at Different VDD2
12
2.5
2
VOUT+
VOUT-
IDD1
IDD2
10
8
1.5
1
6
0.5
0
4
0
1
2
3
4
5
6
0
0.5
1
1.5
2
2.5
VIN - INPUT VOLTAGE - V
VIN - INPUT VOLTAGE - V
Figure 17. Output Voltage vs Input Voltage
Figure 18. Typical Supply Current vs Input Voltage.
9
9
8
7
6
5
4
14
13
12
11
10
9
8
V
V
V
= 4.5 V
= 5.0 V
= 5.5 V
V
V
V
= 3.3 V
= 5.0 V
= 5.5 V
DD1
DD1
DD1
DD2
DD2
DD2
7
6
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
TA - TEMPERATURE - °C
TA - TEMPERATURE - °C
Figure 19. Typical Input Supply Current vs Temperature at Different VDD1
Figure 20. Typical Output Supply Current vs Temperature at Different VDD2
6
5
4
3
2
0.5
0
-0.5
-1
T
T
T
50-10
50-50
50-90
PD
PD
PD
-1.5
-2
1
0
-40 -20
0
20
40
60
80 100 120 140
0
0.5
1
1.5
2
2.5
TA - TEMPERATURE - °C
VIN - INPUT VOLTAGE - V
Figure 21. Typical Propagation Delay vs Temperature
Figure 22. Input Current vs Input Voltage
16
0
-20
-40
-60
-80
V
= 2.0 V
IN
14
12
10
8
-100
-120
-140
-160
-180
-200
6
4
2
0
1000
10000
100000
Frequency (Hz)
1000000
0
20
40
60
80
100
FILTER BANDWIDTH - kHz
Figure 23. AC Noise vs Filter Bandwidth
Figure 24. Phase vs Frequency
10
5 V
5 V
1 nF
20 kΩ
39 Ω
0.1 µF
0.1 µF
20 kΩ
20 kΩ
VOUT
10 nF
1 nF
20 kΩ
ACPL-C87AT/BT
+
–
VCM
Figure 25. Common Mode Transient Immunity Test Circuit
5 V
VSHDN
0 V
2 V
VIN
tSD
tON
0 V
2.4 V
VOUT+ – VOUT-
0 V
-2.4 V
Figure 26. Shutdown Timing Diagram
2 V
VIN
0 V
2 V
90%
50%
1 V
VO+ – VO-
10%
0 V
TPD10
TPD50
TPD90
Figure 27. Propagation Delay Diagram
11
Application Information
The circuit shown in the Figure 28 is a high voltage sensing
application using ACPL-C87AT/BT (isolation amplifier)
and ACPL-M49T (optocoupler). The high voltage input is
sensed by the precision voltage divider resistors R1 and
sensing resistor R2. The ratio of the voltage divider is de-
termined by the allowable input range of the isolation
amplifier (0 to 2 V). This small analog input goes through
a 39 W and 10 nF anti aliasing filter (ACPL-C87AT/BT utilize
SD modulation).
Inside the isolation amplifier: the analog input signal is
digitized and optically transmitted to the output side of
the amplifier. The detector will then decode the signal
and converted back to analog signal. The output differen-
tial signals of ACPL-C87AT/BT go through an op-amp to
convert the differential signals to a single ended output.
SWITCH
MODE
POWER
SUPPLY
R12
10 kΩ
V+
Battery Cells
C7 1 nF
R13
ACPL-M49T
20 Ω
R1
R2
R7 20 kΩ
C4
0.1 µF
C2
0.1 µF
M
C
R4 20 kΩ
U
V
OUT
R3 39 Ω
V-
R5 20 kΩ
C6
1 nF
R6 20 kΩ
C1
10 nF
ACPL-C87AT/BT
Vref
0.1 µF
Figure 28. Typical Application Circuit for Battery Voltage Sensing
Bypass Capacitor
0.1 mF bypass capacitor must be connected as near as
possible between V
(Figure 29).
to GND1 and V
to GND2
DD1
DD2
C2
0.1 µF
C4
0.1 µF
Anti-aliasing Filter
39 W resistor and 10 nF capacitor are recommended to be
ACPL-C87AT/BT
connected to the input (V ) as anti-aliasing filter because
IN
Fig 29. Bypass Capacitors C2, C4
ACPL-C87AT/BT uses sigma data modulation (Figure 30).
The value of the capacitor must be greater than 1 nF and
bandwidth must be less than 410 kHz.
R3
39 Ω
R4
20 kΩ
C1
10 nF
R5
20 kΩ
ACPL-C87AT/BT
ACPL-C87AT/BT
Fig 31. Loading Resistors R4, R5
Fig 30. Anti aliasing Filter C1 , R3
12
Designing the input resistor divider
1. Choose the sensing current (Isense) for bus voltage. E.g., 1 mA
2. Determine R2,
Voltage input range
2 V
1 mA
R =
2
=
= 2 kΩ
I
SENSE
3. Determine R1 using voltage divider formula:
R
2
(V+ – V-) •
= Voltage input range, or
R + R
1
2
(V+ – V-) • R
Voltage input range
2
R =
1
– R
2
where (V+ – V-) is the high voltage input , E.g.: 0 to 600 V,
(600 V – 0 V) • 2 kΩ
R =
1
– 2 kΩ = 598 kΩ
2 V
To reduce the voltage stress of a sole resistor, R1 can be a series of several resistors.
Post Amplifier Circuit
Shutdown Function
The output of ACPL-C87AT/BT is a differential output ACPL-C87AT/BT has a shutdown function to disable the
(V and V pins). A post amplifier circuit is needed device and make the output (V - V ) low. A voltage
OUT+
OUT-
OUT+ OUT-
to convert the differential output to single ended output of 5V on SHDN pin will shutdown the device producing an
with a reference ground. The post amplifier circuit can output (V - V ) of -2.6 V. To be able to control the
OUT+
OUT-
also be configured to establish a desired gain if needed.
It also functions as filter to high frequency chopper
noise. The bandwidth can be adjusted by changing the
feedback resistor and capacitor (R7 and C7). Adjusting this
bandwidth to a minimum level helps minimize the output
noise.
SHDN function (example, from microprocessor), an opto-
coupler (ACPL-M49T) is used.
Total System Error
Total system error is the sum of the resistor divider error,
isolation amplifier error and post amplifier error. The
resistor divider error is due to the accuracy of the resistors
used. It is recommended to use high accuracy resistor of
0.1%. Post Amplifier Error is due to the resistor matching
and the voltage offset characteristic which can be found
on the supplier datasheet.
Post op-amp resistive loading (R4, R5) should be equal
or greater than 20 kW (Figure 31). Resistor values lower
than this can affect the overall system error due to output
impedance of isolation amplifier.
The application circuit in Figure 28 features two op-amps
to improve the linearity at voltage near 0 V caused by the
limited headroom of the amplifier. The second op-amp
can set the reference voltage to above 0 V.
Isolation Amplifier Error is shown in the table below:
Isolation Amplifier Error Calculation
3s distribution or specification *
Typical ACPL-C87AT
ACPL-C87BT
Fig
A Error due to offset voltage (25 °C)
0.015% 0.5%
0.5%
Offset Voltage /Recommended specs
input voltage range (2.0 V)
B Error due to offset voltage drift
(across temperature)
0.1% 0.4%
0.4%
Offset Voltage /Recommended
input voltage range (2.0 V)
C Error due to gain tolerance (25 °C)
0%
1%
0.5%
specs
specs
D Error due to gain drift (across temperature)
0.25% 0.8%
0.8%
E
Error due to Nonlinearity (across temperature) 0.05% 0.12%
0.12%
2.32%
1.82%
1.32%
F
0.415% 2.82%
Total uncalibrated error (A+B+C+D+E)
Total offset calibrated error (F – A)
G
H
0.4%
0.4%
2.32%
1.32%
Total gain and offset calibrated error (G – C)
* 3s distribution is based on corner wafers.
13
PCB Layout Recommendations
GND1 and GND2 must be totally isolated in the PCB
layout (Figure 33). Distance of separation depends on
the high voltage level of the equipment. The higher the
voltage level the larger the distance of separation needed.
Designers can refer to specific IEC standard of their
equipment for the creepage/clearance requirements.
Bypass capacitor C2 and C4 must be located close to
ACPL-C87xT Pins 1 and Pin 8 respectively. Grounded
pins of C4 and C5 can be connected by vias through the
respective ground layers. If the design has multiple layers,
a dedicated layer for ground is recommended for flexibility
in component placement.
R1 which is directly connected to the high voltage input
must have sufficient clearance with the low voltage com-
ponents. Clearance depends on the high voltage level of
the input. Designers can refer to specific IEC standards of
their equipment for the clearance requirements.
Anti aliasing filters R3 and C1 also need to be connected as
close as possible to Pin 2 of ACPL-C87AT/BT. See Figure 32
for actual component placement of the anti-aliasing filter
and bypass capacitors.
R1 (Series Resistors)
Isolation
BYPASS CAPACITORS
Clearance
GND1
GND2
ANTI ALIASING FILTER
ACPL-C87AT/BT
Figure 32. Component Placement Recommendation
Figure 33. Bottom Layer Layout Recommendation
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-3563EN - August 2, 2013
©2020 ICPDF网 联系我们和版权申明