EVB-EP5357HUI [ALTERA]
600mA PowerSoC Synchronous Buck Regulator With Integrated Inductor;
| 型号： | EVB-EP5357HUI |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | 600mA PowerSoC Synchronous Buck Regulator With Integrated Inductor |
| 文件： | 总19页 (文件大小：879K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Enpirion® Power Datasheet
EP5357xUI 600mA PowerSoC
Synchronous Buck Regulator
With Integrated Inductor
Description
Features
The EP5357xUI (x = L or H) is a 600mA
PowerSoC. The EP5357xUI integrates MOSFET
switches, control, compensation, and the
magnetics in an advanced 2.5mm x 2.25mm
QFN Package.
• Integrated Inductor Technology
• 2.5mm x 2.25mm x 1.1mm package
• Total Solution Footprint 14mm2
• Low VOUT ripple for RF compatibility
• High efficiency, up to 93%
Integrated magnetics enables a tiny solution
footprint, low output ripple, low part-count, and
high reliability, while maintaining high efficiency.
The complete solution can be implemented in as
little as 14mm2.
• 600mA continuous output current
• 55µA quiescent current
• Less than 1µA standby current
A proprietary light load mode (LLM) provides high • 5 MHz switching frequency
efficiency in light load conditions.
• 3 pin VID for glitch free voltage scaling
The EP5357xUI uses a 3-pin VID to easily select
the output voltage setting. Output voltage
settings are available in 2 optimized ranges
providing coverage for typical VOUT settings.
• VOUT Range 0.6V to V – 0.25V
IN
• Short circuit and over current protection
• UVLO and thermal protection
• IC level reliability in a PowerSOC solution
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP5357LUI further has
the option to use an external voltage divider.
Application
• Wireless and RF applications
• Wireless broad band data cards
• Smart phone and portable media players
• Advanced Low Power Processors, DSP, IO,
Memory, Video, Multimedia Engines
AVIN
PVIN
VOUT
4.7uF
EP5357LUI
10uF
EP5357xUI
VSENSE
VSO
VS1
VS2
VFB
ENABLE
LLM
AGND
PGND
4.75mm
Figure 1: Total Solution Footprint.
Figure 2: Typical Application Schematic.
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October 11, 2013
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EP5357LUI/EP5357HUI
Ordering Information
Pin Assignments(Top View)
Part Number
Comment
Package
EP5357LUI
LOW VID Range 16-pin QFN T&R
HIGH VID Range 16-pin QFN T&R
EP5357LUI Evaluation Board
16
15
EP5357HUI
1
2
3
4
5
6
NC(SW)
PGND
LLM
14 PVIN
13 AVIN
12 ENABLE
11 VS0
EVB-EP5357LUI
EVB-EP5357HUI
EP5357HUI Evaluation Board
VFB
VSENSE
AGND
10 VS1
VS2
9
7
8
Figure 3: EP5357LUI Pin Out Diagram (Top View)
16
15
1
2
3
4
5
6
NC(SW)
PGND
LLM
14 PVIN
13 AVIN
12 ENABLE
11 VS0
NC
VSENSE
AGND
10 VS1
VS2
9
7
8
Figure 4: EP5357HUI Pin Out Diagram (Top View)
Pin Description
PIN
NAME
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal,
ground, or voltage. However, they must be soldered to the PCB. Failure to follow this
guideline may result in part malfunction or damage to the device.
Power ground. Connect this pin to the ground electrode of the Input and output filter
capacitors.
LLM (Light Load Mode – “LLM”) pin. Logic-High enables automatic LLM/PWM and logic-
low places the device in fixed PWM operation. LLM pin should be connected to ENABLE,
or should be disabled before ENABLE is pulled low.
1, 15,
16
NC(SW)
2
3
PGND
LLM
EP5357LUI: Feed back pin for external divider option.
EP5357HUI: No Connect
Sense pin for preset output voltages. Refer to application section for proper configuration.
4
5
VFB/NC
VSENSE
2
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EP5357LUI/EP5357HUI
PIN
NAME
AGND
VOUT
FUNCTION
Analog ground. This is the quiet ground for the internal control circuitry, and the ground
return for external feedback voltage divider
Regulated Output Voltage. Refer to application section for proper layout and decoupling.
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
EP5357LUI: Selects one of seven preset output voltages or an external resistor divider.
EP5357HUI: Selects one of eight preset output voltages.
6
7, 8
9, 10,
11
VS2, VS1,
VS0
(Refer to section on output voltage select for more details.)
12
13
14
ENABLE
AVIN
PVIN
Output Enable. Enable = logic high; Disable = logic low
Input power supply for the controller circuitry.
Input Voltage for the MOSFET switches.
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
SYMBOL MIN
MAX
UNITS
Input Supply Voltage
VIN
-0.3
-0.3
-0.3
6.0
V
VIN+ 0.3
2.7
V
V
Voltages on: ENABLE, VSENSE, VSO – VS2
Voltages on: VFB (EP5357LUI)
Maximum Operating Junction Temperature
Storage Temperature Range
TJ-ABS
TSTG
150
150
°C
°C
°C
V
-65
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
260
2000
Recommended Operating Conditions
PARAMETER
Input Voltage Range
SYMBOL MIN
MAX UNITS
VIN
TA
TJ
2.4
-40
-40
5.5
V
Operating Ambient Temperature
+85
°C
°C
Operating Junction Temperature
+125
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient –0 LFM (Note 1)
SYMBOL
θJA
TYP
UNITS
°C/W
85
+155
25
Thermal Overload Trip Point
TJ-TP
°C
°C
Thermal Overload Trip Point Hysteresis
Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards
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EP5357LUI/EP5357HUI
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V.
CIN = 4.7µF MLCC, COUT = 10µF MLCC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Operating Input Voltage
Range
VIN
2.4
5.5
V
Under Voltage Lock-out –
VIN Rising
VUVLO_R
2.0
V
Under Voltage Lock-out –
VIN Falling
VUVLO_F
RDO
1.9
V
Drop Out Resistance
Input to Output Resistance
350
500
mΩ
0.6
1.8
VIN-VDO
3.3
EP5357LUI (VDO = ILOAD X RDO
EP5357HUI
)
Output Voltage Range
V
VOUT
Dynamic VoltageSlew
Rate
EP5357LUI (VID MODE)
EP5357HUI (VID MODE)
4
8
V/mS
VSLEW
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
VID Preset VOUT Initial
Accuracy
-2
+2
%
∆VOUT
Line Regulation
Load Regulation
2.4V ≤ VIN ≤ 5.5V
0.03
0.48
%/V
%/A
∆VOUT_LINE
∆VOUT_LOAD
∆VOUT_TEMPL
IOUT
0A ≤ ILOAD ≤ 600mA
Temperature Variation
Output Current
24
ppm/°C
mA
-40°C ≤ TA ≤ +85°C
600
Shut-down Current
ISD
Enable = Low
0.75
55
µA
EP5357HUI Operating
Quiescent Current
ILOAD=0; Preset Output Voltages,
IQ
µA
µA
A
LLM=High
EP5357LUI Operating
Quiescent Current
ILOAD=0; Preset Output Voltages,
IQ
65
LLM=High
2.4V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V
OCP Threshold
ILIM
1.4
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
Feedback Pin Voltage
Initial Accuracy
VFB
.588
.582
0.6
0.612
V
-40°C ≤ TA ≤ +85°C;
2.4V ≤ VIN ≤ 5.5V
Feedback Pin Voltage
variation over Line, Load,
and Temperature
VFB
0.6
0.618.
V
0mA ≤ ILOAD ≤ 600mA
Feedback Pin Input
Current
IFB
Note 1
<100
nA
VS0-VS2, Pin Logic Low
VS0-VS2, Pin Logic High
VVSLO
VVSHI
0.0
1.4
0.3
VIN
V
V
VS0-VS2, Pin Input
Current
IVSX
Note 1
Note 1
<100
<100
nA
Enable Pin Logic Low
Enable Pin Logic High
Enable Pin Current
VENLO
VENHI
IENABLE
0.3
V
V
1.4
nA
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EP5357LUI/EP5357HUI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Minimum VIN-VOUT to ensure
proper LLM operation
LLM Engage Headroom
600
mV
LLM Pin Logic Low
LLM Pin Logic High
LLM Pin Current
VLLMLO
VLLMHI
ILLM
0.3
V
V
1.4
<100
5
nA
MHz
Operating Frequency
Soft Start Operation
FOSC
EP5357HUI (VID MODE)
EP5357LUI (VID MODE)
8
4
Soft Start Slew Rate
VOUT Rise Time
∆VSS
V/mS
uSec
TRISE
Time to 90% VOUT (VFB MODE)
180
250
Note 1: Parameter guaranteed by design
Typical PerformanceCharacteristics
95
90
95
90
85
80
75
70
65
60
55
50
45
LLM
LLM
85
80
75
70
65
60
55
50
45
PWM
PWM
10
100
1000
10
100
Load Current (mA)
1000
Load Current (mA)
Efficiency vs. Load Current: VIN = 5.0V, VOUT (from
top to bottom) = 3.3, 2.5, 1.8, 1.2V
Efficiency vs. Load Current: VIN = 3.7V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
95
90
85
80
75
70
65
60
55
50
45
LLM
PWM
10
100
Load Current (mA)
1000
Efficiency vs. Load Current: VIN = 3.3V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
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EP5357LUI/EP5357HUI
Start Up Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 1000mA (VID MODE)
Start Up Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA (VID MODE)
Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 500mA, PWM
Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA, PWM
5mV/Div
50mV/Div
Output Ripple: VIN = 5.0V, VOUT = 1.2V, Load = 10mA
LLM enabled
Output Ripple: VIN = 5.0V, VOUT = 1.2V,
Load = 500mA
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EP5357LUI/EP5357HUI
50mV/Div
5mV/Div
Output Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 10mA
LLM enabled
Output Ripple: VIN = 5.0V, VOUT = 3.3V,
Load = 500mA
50mV/Div
5mV/Div
Output Ripple: VIN = 3.3V, VOUT = 1.8V
Load = 500mA
Output Ripple: VIN = 3.3V, VOUT = 1.8V, Load = 10mA
LLM enabled
5mV/Div
50mV/Div
Output Ripple: VIN = 3.3V, VOUT = 1.2V, Load = 10mA
LLM enabled
Output Ripple: VIN = 3.3V, VOUT = 1.2V,
Load = 500mA
7
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Rev E
EP5357LUI/EP5357HUI
Load Transient: VIN = 5.0V, VOUT = 1.2V
Load stepped from 10mA to 500mA
Load Transient: VIN = 5.0V, VOUT = 1.2V
Load stepped from 0mA to 500mA, LLM enabled
Load Transient: VIN = 3.3V, VOUT = 1.8V
Load stepped from 0mA to 500mA, LLM enabled
Load Transient: VIN = 3.3V, VOUT = 1.8V
Load stepped from 10mA to 500mA
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Rev E
EP5357LUI/EP5357HUI
Functional Block Diagram
LLM
PVIN
UVLO
Thermal Limit
Current Limit
Mode Logic
NC(SW)
VOUT
ENABLE
Soft Start
P-Drive
N-Drive
Logic
(-)
PWM
Comp
(+)
PGND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
VFB
Error
Amp
(+)
DAC
Voltage
Select
VREF
Package Boundry
AVIN AGND
VS0 VS1 VS2
Figure 5: Functional Block Diagram
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EP5357LUI/EP5357HUI
Detailed Description
Functional Overview
Integrated Inductor
The EP5357xUI utilizes a proprietary low loss
integrated inductor. The integration of the
inductor greatly simplifies the power supply
design process. The inherent shielding and
compact construction of the integrated inductor
reduces the conducted and radiated noise that
can couple into the traces of the printed circuit
The EP5357xUI requires only 2 small MLCC
capacitors for a complete DC-DC converter
solution.
switches,
The device integrates MOSFET
PWM controller, Gate-drive,
compensation, and inductor into a tiny 2.5mm x
2.25mm x 1.1mm QFN package. Advanced
package design, along with the high level of
integration, provides very low output ripple and
noise. The EP5357xUI uses voltage mode
control for high noise immunity and load
matching to advanced ≤90nm loads. A 3-pin
VID allows the user to choose from one of 8
board.
Further, the package layout is
optimized to reduce the electrical path length
for the high di/dT input AC ripple currents that
are a major source of radiated emissions from
DC-DC converters. The integrated inductor
provides the optimal solution to the complexity,
output ripple, and noise that plague low power
DCDC converter design.
output voltage settings.
The EP5357xUI
comes with two VID output voltage ranges.
The EP5357HUI provides VOUT settings from
1.8V to 3.3V, the EP5357LUI provides VID
settings from 0.8V to 1.5V, and also has an
external resistor divider option to program
Voltage Mode Control
The EP5357xUI utilizes an integrated type III
compensation network. Voltage mode control
is inherently impedance matched to the sub
90nm process technology that is used in
today’s advanced ICs. Voltage mode control
also provides a high degree of noise immunity
at light load currents so that low ripple and high
accuracy are maintained over the entire load
output setting over the 0.6V to V -0.25V
IN
range. The EP5357xUI provides the industry’s
highest power density of any 600mA DCDC
converter solution.
The key enabler of this revolutionary
integration is Altera Enpirion’s proprietary
power MOSFET technology. The advanced
MOSFET switches are implemented in deep-
submicron CMOS to supply very low switching
loss at high switching frequencies and to allow
a high level of integration. The semiconductor
process allows seem-less integration of all
switching, control, and compensation circuitry.
range.
The very high switching frequency
allows for a very wide control loop bandwidth
and hence excellent transient performance.
Light Load Mode (LLM) Operation
The EP5357xUI uses a proprietary light load
mode to provide high efficiency in the low load
operating condition. When the LLM pin is high,
the device is in automatic LLM/PWM mode.
When the LLM pin is low, the device is in PWM
mode. In automatic LLM/PWM mode, when a
light load condition is detected, the device will
(1) step VOUT up by approximately 1.5% above
the nominal operating output voltage setting,
The proprietary magnetics design provides
high-density/high-value magnetics in a very
small footprint. Altera Enpirion magnetics are
carefully matched to the control and
compensation circuitry yielding an optimal
solution with assured performance over the
entire operating range.
V
NOM, and then (2) shut down unnecessary
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
circuitry, and (3) monitor VOUT. When VOUT falls
below VNOM, the device will repeat (1), (2), and
(3). The voltage step up, or pre-positioning,
improves transient droop when a load transient
causes a transition from LLM mode to PWM
mode. If a load transient occurs, causing VOUT
to fall below the threshold VMIN, the device will
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EP5357LUI/EP5357HUI
exit LLM operation and begin normal PWM
operation. Figure demonstrates VOUT
behavior during transition into and out of LLM
LLM Threshold Current vs. VOUT
6
250
200
150
100
50
operation.
LLM
Ripple
VIN=5V (top curve)
VMAX
VIN=4.2V
PWM
Ripple
VIN=3.7V
VNOM
VIN=3.3V (bottom curve)
VOUT
0
VMIN
0.8
1.1
1.4
1.7
2.0
2.3
2.6
2.9
3.2
VOUT (V)
Load
Step
Figure 8: Typical load current for LLM engage and
disengage versus VOUT for selected input voltages
IOUT
Table 1: Load current below which the device can be
certain to be in LLM operation. These values are
guaranteed by design
Figure 6: VOUT Behavior in LLM Operation
VIN
VOUT
3.30
3.00
2.90
2.60
2.50
2.20
2.10
1.80
1.50
1.45
1.20
1.15
1.10
1.05
0.80
3.3
3.7
4.3
105
122
126
136
138
141
141
138
130
128
117
114
111
108
92
5.0
147
156
158
162
162
160
158
150
138
136
122
119
116
113
94
62
89
56
69
106
111
120
122
124
120
119
111
108
106
104
89
101
105
111
111
111
105
103
101
99
Device exits LLM,
tests load current
Figure 7: VOUT Droop during Periodic LLM Exit
Many multi-mode DCDC converters suffer from
a condition that occurs when the load current
increases only slowly so that there is no load
transient driving VOUT below the VMIN threshold.
In this condition, the device would never exit
LLM operation. This could adversely affect
efficiency and cause unwanted ripple. To
prevent this from occurring, the EP5357xUI
periodically exits LLM mode into PWM mode
and measures the load current. If the load
current is above the LLM threshold current, the
device will remain in PWM mode. If the load
current is below the LLM threshold, the device
will re-enter LLM operation. There will be a
small droop in VOUT at the point where the
device exits and re-enters LLM, as shown in
Figure 7.
87
The load current at which the device will enter
LLM mode is a function of input and output
voltage. Figure 8 shows the typical value at
which the device will enter LLM operation. The
actual load current at which the device will
enter LLM operation can vary by +/-30%. Table
1 shows the minimum load current below which
the device is guaranteed to be in LLM
operating mode.
To ensure normal LLM operation, LLM mode
should be enabled/disabled with specific
sequencing. For applications with explicit LLM
pin control, enable LLM after VIN ramp up is
complete; disable LLM before VIN ramp
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EP5357LUI/EP5357HUI
EP5357HUI:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 100uF
down. For applications with ENABLE control,
tie LLM to ENABLE; enable device after VIN
ramp up is complete and disable device before
VIN ramp down begins. For devices with
ENABLE and LLM tied to VIN, contact Power
EP5357LUI in external divider mode:
C
OUT_TOTAL_MAX = 2.25x10-4/VOUT Farads
Applications
recommendations
support
for
specific
The nominal value for COUT is 10uF. See the
applications section for more details.
Increased output filter capacitance and/or
increased bulk capacitance at the load will
decrease the magnitude of the LLM ripple.
Refer to the section on output filter capacitance
for maximum values of output filter capacitance
and the Soft-Start section for maximum bulk
capacitance at the load.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for approximately 0.5mS and then a normal
NOTE: For proper LLM operation the
EP5357xUI requires a minimum difference
soft start is initiated.
If the over current
between V and VOUT of 600mV.
If this
IN
condition still persists, this cycle will repeat.
condition is not met, the device cannot be
assured proper LLM operation.
Under Voltage Lockout
NOTE: Automatic LLM/PWM is not available
when using the external resistor divider option
for VOUT programming.
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
operation.
A logic low will disable the
The EP5357HUI has a soft-start slew rate that
is twice that of the EP5357LUI.
converter and cause it to shut down. A logic
high will enable the converter into normal
operation.
When the EP5357LUI is configured in external
resistor divider mode, the device has a fixed
VOUT ramp time. Therefore, the ramp rate will
vary with the output voltage setting. Output
voltage ramp time is given in the Electrical
Characteristics Table.
NOTE: The ENABLE pin must not be left
floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. The maximum total capacitance on
the output, including the output filter capacitor
and bulk and decoupling capacitance, at the
load, is given as:
EP5357LUI:
C
OUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 200uF
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EP5357LUI/EP5357HUI
Application Information
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
which in turn is connected to the non-inverting
input of the error amplifier. This allows the use
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage selected.
VOUT
PVIN
VOUT
VSENSE
VIN
AVIN
ENABLE
10µF
4.7µF
LLM
VS0
VS1
VS2
AGND
PGND
NOTE: The VID pins must not be left floating.
EP5357L Low VID Range Programming
The EP5357LUI is designed to provide a high
degree of flexibility in powering applications
that require low VOUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitch-
free voltage scaling.
Figure 9: Application Circuit, EP5357HUI, configured
for LLM Enabled. Note that all control signalsshould
be connected to AVIN or AGND.
VOUT
PVIN
VOUT
VIN
VSENSE
AVIN
ENABLE
LLM
10µF
µF
VFB
VS0
VS1
VS2
AGND
PGND
Table 2: EP5357LUI VID Voltage Select Settings
VS2
0
0
0
0
1
1
1
1
VS1
0
0
1
1
0
0
1
1
VS0
0
1
0
1
0
1
0
1
VOUT
1.50
1.45
1.20
1.15
1.10
1.05
0.8
Figure 10: Application Circuit, EP5357LUI,
configured for LLM Enabled, showing the VFB
function.
Output Voltage Programming
The EP5357xUI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to
AVIN or to AGND to avoid noise coupling into
the device.
EXT
Table 2 shows the VS2-VS0 pin logic states for
the EP5357LUI and the associated output
voltage levels.
A logic “1” indicates a
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
also has an external divider option.
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
To specify this VID range, order part number
EP5357LUI.
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V.
This
version does not have an external divider
option. To specify this VID range, order part
number EP5357HUI.
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EP5357LUI External Voltage Divider
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
The external divider option is chosen by
connecting VID pins VS2-VS0 to V or a logic
IN
“1” or “high”. The EP5357LUI uses a separate
feedback pin, VFB, when using the external
divider. VSENSE must be connected to VOUT as
indicated in Figure 11. The output voltage is
selected by the following formula:
Ra
Rb
VOUT = 0.6V
(
1+
)
Ra must be chosen as 237KΩ to maintain loop
gain. Then Rb is given as:
Table 3: EP5357HUI VID Voltage Select Settings
VS2
0
VS1
0
VS0
0
VOUT
3.3
142.2x103
=
Ω
Rb
VOUT − 0.6
0
0
1
3.0
0
0
1
1
1
0
0
1
0
2.9
2.6
2.5
VOUT can be programmed over the range of
0.6V to (V – 0.25V).
IN
1
1
1
0
1
1
1
0
1
2.2
2.1
1.8
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
NOTE: LLM is not functional when using the
external divider option. Tie the LLM pin to
AGND.
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
PVIN
VSense
VOUT
VIN
AVIN
VOUT
10µF
ENABLE
4.7uF
Ra
Rb
VFB
VS0
VS1
VS2
PGND AGND
Pre-Bias Start-up
The EP5357xUI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5357xUI is not pre-biased when the
EP5357xUI is first enabled.
Figure 11: EP5357LUI using external divider
EP5357HUI High VID Range Programming
The EP5357HUI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP5357HUI does not have an
Input Filter Capacitor
For ILOAD ≤ 500mA, CIN = 2.2uF
For ILOAD > 500mA CIN = 4.7uF.
external divider option.
As with the
0402 capacitor case size is acceptable.
EP5357LUI, the VID pin settings can be
changed while the device is enabled.
The input capacitor must use a X5R or X7R or
equivalent dielectric formulation.
equivalent dielectric formulations
capacitance with frequency, bias, and with
Y5V or
lose
Table 3 shows the VS0-VS2 pin logic states for
the EP5357HUI and the associated output
voltage levels.
A logic “1” indicates a
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EP5357LUI/EP5357HUI
temperature, and are not suitable for switch-
mode DC-DC converter input filter applications.
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance.
Output Filter Capacitor
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance
on the output.
For VIN ≤ 4.3V, COUT_MIN = 10uF 0603 MLCC.
For VIN > 4.3V, COUT_MIN = 10uF 0805 MLCC.
Ripple performance can be improved by using
2x10µF 0603 MLCC capacitors (for any
allowed VIN).
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP5357xUI.
equivalent
dielectric
formulations
lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-
mode
DC-DC
converter
output
filter
applications
.
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EP5357LUI/EP5357HUI
Layout Recommendation
Figure 12 shows critical components and layer
1 traces of a recommended minimum footprint
EP5357LUI/EP5357HUI layout with ENABLE
tied to V . Alternate ENABLE configurations,
IN
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files
on
the
Altera
website
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figure 12
while reading the layout recommendations in
this section.
Recommendation 1: Input and output filter
Figure 12:Top PCB Layer Critical Components
and Copper for Minimum Footprint
capacitors should be placed on the same side
of the PCB, and as close to the EP5357xUI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP5357xUI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 4: Multiple small vias
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 12. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT, then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
connect these vias to the ground plane.
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 12
between the input and output GND circuits
helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Recommendation 5: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 12 this connection is
made at the input capacitor close to the VIN
connection.
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Rev E
EP5357LUI/EP5357HUI
Recommended PCB Footprint
Figure 13: EP5357 Package PCB Footprint
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October 11, 2013
Rev E
EP5357LUI/EP5357HUI
Package and Mechanical
Figure14: EP5357xUI Package Dimensions
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Rev E
EP5357LUI/EP5357HUI
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rightsreserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX,MEGACORE, NIOS,
QUARTUS and STRATIXwordsand logosare trademarksof Altera Corporation andregistered inthe U.S. Patent andTrademarkOffice and inother
countries. All other wordsand logosidentifiedastrademarksor service marks are the property of their respective holdersasdescribed at
www.altera.com/common/legal.html. Altera warrantsperformance of itssemiconductor productsto current specificationsin accordancewith Altera's
standard warranty, but reserves the right to make changesto any productsand servicesat any time without notice. Altera assumesno responsibility or
liability arisingout of the applicationor use of any information, product, or service described herein except asexpressly agreed to in writing by Altera.
Altera customersare advised to obtain thelatest version of device specificationsbefore relying on any publishedinformation andbefore placing orders
for products or services.
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Rev E
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