EVB-EP53A7LQI_技术文档

Enpirion^®Power Datasheet

EP53A7LQI/EP53A7HQI 1A PowerSoC

Light Load Mode Buck Regulator

with Integrated Inductor

Description

Features

The EP53A7xQI (x = L or H) is a 1000mA

PowerSOC. The EP53A7xQI integrates MOSFET

switches, control, compensation, and the

magnetics in an advanced 3mm x 3mm QFN

Package.

• Integrated Inductor Technology

• 3mm x 3mm x 1.1mm QFN package

• Total Solution Footprint < 21mm²

• Low V_OUTripple for RF compatibility

• High efficiency, up to 94%

Integrated magnetics enables a tiny solution

footprint, low output ripple, low part-count, and

high reliability, while maintaining high efficiency.

The complete solution can be implemented in as

little as 21mm².

• 1000mA continuous output current

• 55µA quiescent current

• Less than 1µA standby current

A proprietary light load mode (LLM) provides high • 5 MHz switching frequency

efficiency in light load conditions.

• 3 pin VID for glitch free voltage scaling

The EP53A7xQI uses a 3-pin VID to easily select

the output voltage setting. Output voltage

settings are available in 2 optimized ranges

providing coverage for typical V_OUTsettings.

• V_OUTRange 0.6V to V – 0.5V

IN

• Short circuit and over current protection

• UVLO and thermal protection

• IC level reliability in a PowerSOC solution

The VID pins can be changed on the fly for fast

dynamic voltage scaling. EP53A7LQI further has

the option to use an external voltage divider.

Application

• Portable wireless and RF applications

The EP53A7xQI offers the optimal combination

of very small solution footprint and advanced

performance features.

• Solid state storage applications

• Space constrained applications requiring high

efficiency and very small solution size

3.5mm

100 ohm

4.7uF

V_OUT

100 Ohm

PVIN

V_OUT

V_IN

V_SENSE

AVIN

ENABLE

LLM

10µF

4.7µF

V_FB

V_S0

EP53A7xQI

6mm

V_S1

V_S2

AGND

PGND

10uF

Figure 2: Typical Application Schematic

Figure 1: Total Solution Footprint

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Pin Assignments(Top View)

Ordering Information

Part Number

Comment

Package

EP53A7LQI

LOW VID Range 16-pin QFN T&R

HIGH VID Range 16-pin QFN T&R

EP53A7LQI Evaluation Board

EP53A7HQI

EVB-EP53A7LQI

EVB-EP53A7HQI

EP53A7HQI Evaluation Board

Figure 3: EP53A7LQI Pin Out Diagram (Top View)

Figure 4: EP53A7HQI Pin Out Diagram (Top View)

Pin Description

NAME

FUNCTION

NO CONNECT – These pins are internally connected to the common switching node of the

internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal,

ground, or voltage. However, they must be soldered to the PCB. Failure to follow this

guideline may result in part malfunction or damage to the device.

Power ground. Connect this pin to the ground electrode of the Input and output filter

capacitors.

1, 15,

16

NC(SW)

2

3

PGND

LLM

LLM ( Light load mode – “LLM”) pin. Logic-High enables automatic LLM/PWM and logic-

low places the device in fixed PWM operation.

VFB

NC

VSENSE

EP53A7LQI: Feed back pin for external resistor divider option.

EP53A7HQI: No Connect

Sense pin for preset output voltages. Refer to application section for proper configuration.

4

5

Analog ground. This is the quiet ground for the internal control circuitry, and the ground

return for external feedback voltage divider

Regulated Output Voltage. Refer to application section for proper layout and decoupling.

6

AGND

VOUT

7, 8

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NAME

FUNCTION

Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.

EP53A7LQI: Selects one of seven preset output voltages or an external resistor divider.

EP53A7HQI: Selects one of eight preset output voltages.

9, 10,

11

VS2, VS1,

VS0

(Refer to section on output voltage select for more details.)

Output Enable. Enable = logic high; Disable = logic low

Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor.

Input Voltage for the MOSFET switches.

12

13

14

ENABLE

AVIN

PVIN

Absolute Maximum Ratings

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the

recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may

cause permanent damage to the device. Exposure to absolute maximum rated conditions for

extended periods may affect device reliability.

PARAMETER

SYMBOL MIN

MAX

UNITS

Input Supply Voltage

V_IN

-0.3

6.0

V

V_IN+ 0.3

2.7

V

Voltages on: ENABLE, V_SENSE, V_SO– V_S2

Voltages on: V_FB(EP53A7LQI)

Maximum Operating Junction Temperature

Storage Temperature Range

T_J-ABS

T_STG

150

°C

V

-65

Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C

ESD Rating (based on Human Body Mode)

260

2000

Recommended Operating Conditions

PARAMETER

Input Voltage Range

SYMBOL MIN

MAX UNITS

V_IN

T_A

T_J

2.4

- 40

5.5

V

Operating Ambient Temperature

+85

°C

Operating Junction Temperature

+125

Thermal Characteristics

PARAMETER

Thermal Resistance: Junction to Ambient –0 LFM (Note 1)

SYMBOL

θ_JA

TYP

UNITS

°C/W

80

+155

25

Thermal Overload Trip Point

T_J-TP

°C

Thermal Overload Trip Point Hysteresis

Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards

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Electrical Characteristics

NOTE: T_A= -40°C to +85°C unless otherwise noted. Typical values are at T_A= 25°C, VIN = 3.6V.

C_IN= -4.7µF MLCC, C_OUT= 10µF MLCC

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX UNITS

Operating Input Voltage

V_IN

2.4

5.5

V

Under Voltage Lock-out –

V_INRising

V_{UVLO_R}

2.0

V

Under Voltage Lock-out –

V_INFalling

V_{UVLO_F}

R_DO

1.9

V

mΩ

V

Drop Out Resistance

Input to Output Resistance

350

500

V_IN-V_DO

3.3

0.6

1.8

EP53A7LQI (V_DO= I_LOADX R_DO

EP53A7HQI

)

Output Voltage Range

V_OUT

Dynamic VoltageSlew

Rate

EP53A7LQI

EP53A7HQI

4

8

V/mS

%

V_SLEW

T_A= 25°C, V_IN= 3.6V;

I_LOAD= 100mA ;

0.8V ≤ V_OUT≤ 3.3V

VID Preset V_OUTInitial

Accuracy

∆V_OUT

-2

+2

T_A= 25°C, V_IN= 3.6V;

I_LOAD= 100mA ;

0.8V ≤ V_OUT≤ 3.3V

Feedback Pin Voltage

Initial Accuracy

V_FB

.588

0.6

0.612

V

Line Regulation

2.4V ≤ V_IN≤ 5.5V

0.03

0.6

30

%/V

%/A

∆V_{OUT_LINE}

∆V_{OUT_LOAD}

∆V_{OUT_TEMPL}

Load Regulation

0A ≤ I_LOAD≤ 1000mA

Temperature Variation

ppm/°C

-40°C ≤ T_A≤ +85°C

Output Current

I_OUT

I_SD

1000

mA

µA

Shut-down Current

Enable = Low

0.75

55

EP53A7HQI Operating

Quiescent Current

I_LOAD=0; Preset Output Voltages,

I_Q

µA

LLM=High

EP53A7LQI Operating

Quiescent Current

I

_LOAD=0; Preset Output Voltages,

I_Q

65

1.4

µA

A

LLM=High

2.4V ≤ V_IN≤ 5.5V

0.6V ≤ V_OUT≤ 3.3V

OCP Threshold

I_LIM

I_FB

1.25

Feedback Pin Input

Current

Note 1

<100

nA

VS0-VS2, Pin Logic Low

VS0-VS2, Pin Logic High

V_VSLO

V_VSHI

0.0

1.4

0.3

V_IN

V

VS0-VS2, Pin Input

Current

I_VSX

<100

nA

Enable Pin Logic Low

Enable Pin Logic High

Enable Pin Current

V_ENLO

V_ENHI

I_ENABLE

0.3

V

1.4

700

1.4

Note 1

nA

Minimum difference between V_IN

LLM Engage Headroom

mV

and V_OUTto ensure proper LLM

operation

LLM Pin Logic Low

LLM Pin Logic High

V_LLMLO

V_LLMHI

0.3

V

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PARAMETER

LLM Pin Current

SYMBOL

I_LLM

TEST CONDITIONS

MIN

TYP

<100

5

MAX UNITS

nA

Operating Frequency

F_OSC

MHz

Soft Start Operation

EP53A7LQI (VID only)

EP53A7HQI (VID only)

4

8

Soft Start Slew Rate

V/mS

∆V_SS

∆T_SS

Soft Start Rise Time

EP53A7LQI (VFB mode); Note 2

170

225

280

µS

Note 1: Parameter guaranteed by design

Note 2: Measured from when V_IN≥ V_{UVLO_R}& ENABLE pin crosses its logic High threshold.

Typical PerformanceCharacteristics

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

LLM

V_OUT=1.2V

V_OUT=1.8V

PWM

10

100

Load Current (mA)

1000

10

100

Load Current (mA)

1000

Efficiency vs. Load Current: V_OUT= 1.2V, V_IN(from

top to bottom) = 2.5, 3.3, 3.7, 4.3, 5.0V

Efficiency vs. Load Current: V_OUT= 1.8V, V_IN(from

top to bottom) = 2.5, 3.3, 3.7, 4.3, 5.0V

95

90

85

80

75

70

65

60

55

50

45

95

LLM

90

85

80

75

70

65

60

55

50

45

V_OUT=2.5V

V_OUT=3.3V

PWM

10

100

Load Current (mA)

1000

10

100

1000

Load Current (mA)

Efficiency vs. Load Current: V_OUT= 2.5V, V_IN(from

top to bottom) = 3.3, 3.7, 4.3, 5.0V

Efficiency vs. Load Current: V_OUT= 3.3V, V_IN(from

top to bottom) = 3.7, 4.3, 5.0V

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Start Up Waveform: V_IN= 5.0V, V_OUT= 3.3V;

I_LOAD= 1000mA; VID Mode

Start Up Waveform: V_IN= 5.0V, V_OUT= 3.3V;

I_LOAD= 10mA; VID Mode

Shut-down Waveform: V_IN= 5.0V, V_OUT= 3.3V;

I_LOAD= 1000mA, PWM

Shut-down Waveform: V_IN= 5.0V, V_OUT= 3.3V;

I_LOAD= 10mA, PWM

5mV/Div

50mV/Div

Output Ripple: V_IN= 5.0V, V_OUT= 1.2V, Load = 10mA

LLM enabled

Output Ripple: V_IN= 5.0V, V_OUT= 1.2V,

Load = 1A

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50mV/Div

5mV/Div

Output Ripple: V_IN= 5.0V, V_OUT= 3.3V,

Load = 1A

Output Ripple: V_IN= 5.0V, V_OUT= 3.3V, Load = 10mA

LLM enabled

50mV/Div

5mV/Div

Output Ripple: V_IN= 3.3V, V_OUT= 1.8V, Load = 10mA

LLM enabled

Output Ripple: V_IN= 3.3V, V_OUT= 1.8V

Load = 1A

5mV/Div

50mV/Div

Output Ripple: V_IN= 3.3V, V_OUT= 1.2V,

Load = 1A

Output Ripple: V_IN= 3.3V, V_OUT= 1.2V, Load = 10mA

LLM enabled

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Load Transient: V_IN= 5.0V, V_OUT= 3.3V

Load stepped from 0mA to 1000mA

Load Transient: V_IN= 5.0V, V_OUT= 3.3V

Load steppedfrom 10mA to 1000mA, LLM enabled

Load Transient: V_IN= 5.0V, V_OUT= 1.2V

Load stepped from 0mA to 1000mA

Load Transient: V_IN= 5.0V, V_OUT= 1.2V

Load steppedfrom 10mA to 1000mA, LLM enabled

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Load Transient: V_IN= 3.7V, V_OUT= 1.2V

Load stepped from 0mA to 1000mA

Load Transient: V_IN= 3.7V, V_OUT= 1.2V

Load steppedfrom 10mA to 1000mA, LLM enabled

Load Transient: V_IN= 3.3V, V_OUT= 1.8V

Load steppedfrom 10mA to 1000mA, LLM enabled

Load Transient: V_IN= 3.3V, V_OUT= 1.8V

Load stepped from 0mA to 1000mA

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Functional Block Diagram

LLM

PVIN

UVLO

Thermal Limit

Current Limit

Mode Logic

NC(SW)

V_OUT

ENABLE

Soft Start

P-Drive

N-Drive

Logic

(-)

PWM

Comp

(+)

PGND

V_SENSE

Sawtooth

Generator

Compensation

Network

(-)

Switch

V_FB

Error

Amp

(+)

DAC

Voltage

Select

VREF

Package Boundry

AVIN AGND

VS0 VS1 VS2

Figure 5: Functional Block Diagram

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Detailed Description

Functional Overview

Integrated Inductor

The EP53A7xQI utilizes a proprietary low loss

integrated inductor. The integration of the

inductor greatly simplifies the power supply

design process. The integrated inductor

provides the optimal solution to the complexity,

output ripple, and noise that plague low power

DCDC converter design.

The EP53A7xQI requires only 2 small MLCC

capacitors and an 0201 resistor for a complete

DC-DC converter solution.

integrates MOSFET switches, PWM controller,

Gate-drive, compensation, and inductor into a

tiny 3mm x 3mm x 1.1mm QFN package.

Advanced package design, along with the high

level of integration, provides very low output

The device

Voltage Mode Control

ripple and noise.

The EP53A7xQI uses

voltage mode control for high noise immunity

and load matching to advanced ≤90nm loads.

A 3-pin VID allows the user to choose from one

of 8 output voltage settings. The EP53A7xQI

comes with two VID output voltage ranges.

The EP53A7HQI provides V_OUTsettings from

1.8V to 3.3V, the EP53A7LQI provides VID

settings from 0.8V to 1.5V, and also has an

external resistor divider option to program

The EP53A7xQI utilizes an integrated type III

compensation network. Voltage mode control

is inherently impedance matched to the sub

90nm process technology that is used in

today’s advanced ICs. Voltage mode control

also provides a high degree of noise immunity

at light load currents so that low ripple and high

accuracy are maintained over the entire load

range.

The very high switching frequency

output setting over the 0.6V to V -0.5V range.

allows for a very wide control loop bandwidth

IN

The EP53A7xQI provides the industry’s highest

power density of any 1A DCDC converter

solution.

and hence excellent transient performance.

Light Load Mode (LLM) Operation

The EP53A7xQI uses a proprietary light load

mode to provide high efficiency in the low load

operating condition. When the LLM pin is high,

the device is in automatic LLM/PWM mode.

When the LLM pin is low, the device is in PWM

mode. In automatic LLM/PWM mode, when a

light load condition is detected, the device will

(1) step V_OUTup by approximately 1.5% above

the nominal operating output voltage setting,

The key enabler of this revolutionary

integration is Altera Enpirion’s proprietary

power MOSFET technology. The advanced

MOSFET switches are implemented in deep-

submicron CMOS to supply very low switching

loss at high switching frequencies and to allow

a high level of integration. The semiconductor

process allows seamless integration of all

switching, control, and compensation circuitry.

V_NOM, and then (2) shut down unnecessary

The proprietary magnetics design provides

high-density/high-value magnetics in a very

small footprint. Altera Enpirion magnetics are

carefully matched to the control and

compensation circuitry yielding an optimal

solution with assured performance over the

entire operating range.

circuitry, and (3) monitor V_OUT. When V_OUTfalls

below V_NOM, the device will repeat (1), (2), and

(3). The voltage step up, or pre-positioning,

improves transient droop when a load transient

causes a transition from LLM mode to PWM

mode. If a load transient occurs, causing V_OUT

to fall below the threshold V_MIN, the device will

exit LLM operation and begin normal PWM

Protection features include under-voltage lock-

out (UVLO), over-current protection (OCP),

short circuit protection, and thermal overload

protection.

operation. Figure

6

demonstrates V_OUT

behavior during transition into and out of LLM

operation.

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LLM

LLM Threshold Current vs. VOUT

Ripple

V_MAX

250

200

150

100

50

PWM

Ripple

V_NOM

V_MIN

V_OUT

VIN=5V (top curve)

VIN=4.2V

Load

Step

VIN=3.7V

VIN=3.3V (bottom curve)

0

I_OUT

0.8

1.1

1.4

1.7

2.0

2.3

2.6

2.9

3.2

VOUT (V)

Figure 6: V_OUTBehavior in LLM Operation

Figure 8: Typical load current for LLM engage and

disengage versus V_OUTfor selected input voltages

Table 1: Load current below which the device can be

certain to be in LLM operation. These values are

guaranteed by design

VIN

VOUT

3.30

3.00

2.90

2.60

2.50

2.20

2.10

1.80

1.50

1.45

1.20

1.15

1.10

1.05

0.80

3.3

3.7

4.3

105

122

126

136

138

141

138

130

128

117

114

111

108

92

5.0

147

156

158

162

160

158

150

138

136

122

119

116

113

94

62

89

Device exits LLM,

tests load current

56

69

106

111

120

122

124

120

119

111

108

106

104

89

101

105

111

105

103

101

99

Figure 7: V_OUTDroop during Periodic LLM Exit

Many multi-mode DCDC converters suffer from

a condition that occurs when the load current

increases only slowly so that there is no load

transient driving V_OUTbelow the V_MINthreshold

(shown in Figure 6). In this condition, the

device would never exit LLM operation. This

could adversely affect efficiency and cause

unwanted ripple. To prevent this from

occurring, the EP53A7xQI periodically exits

LLM mode into PWM mode and measures the

load current. If the load current is above the

LLM threshold current, the device will remain in

PWM mode. If the load current is below the

LLM threshold, the device will re-enter LLM

operation. There will be a small droop in V_OUT

at the point where the device exits and re-

enters LLM, as shown in Figure 7.

87

which the device will enter LLM operation. The

actual load current at which the device will

enter LLM operation can vary by +/-30%. Table

1 shows the minimum load current below which

the device is guaranteed to be in LLM

operating mode.

To ensure normal LLM operation, LLM mode

should be enabled/disabled with specific

sequencing. For applications with explicit LLM

pin control, enable LLM after VIN ramp up

complete; disable LLM before VIN ramp down.

For applications with ENABLE control, tie LLM

to ENABLE; enable device after VIN ramp up

complete and disable device before VIN ramp

The load current at which the device will enter

LLM mode is a function of input and output

voltage. Figure 8 shows the typical value at

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down begins. For devices with ENABLE and

LLM tied to VIN, contact Altera Applications

engineering for specific recommendations.

EP53A7LUI in external divider mode:

_{OUT_TOTAL_MAX}= 2.25x10^-4/V_OUTFarads

C

Increased output filter capacitance and/or

increased bulk capacitance at the load will

decrease the magnitude of the LLM ripple.

Refer to the section on output filter capacitance

for maximum values of output filter capacitance

and the Soft-Start section for maximum bulk

capacitance at the load.

The nominal value for C_OUTis 10uF. See the

applications section for more details.

Over Current/Short Circuit Protection

The current limit function is achieved by

sensing the current flowing through a sense P-

MOSFET which is compared to a reference

current. When this level is exceeded the P-

FET is turned off and the N-FET is turned on,

pulling V_OUTlow. This condition is maintained

for approximately 0.5mS and then a normal

NOTE: For proper LLM operation the

EP53A7xQI requires a minimum difference

between V and V_OUTof 700mV.

If this

IN

condition is not met, the device cannot be

assured proper LLM operation.

soft start is initiated.

If the over current

NOTE: Automatic LLM/PWM is not available

when using the external resistor divider option

for V_OUTprogramming.

condition still persists, this cycle will repeat.

Under Voltage Lockout

During initial power up, an under voltage

lockout circuit will hold-off the switching

circuitry until the input voltage reaches a

sufficient level to insure proper operation. If

the voltage drops below the UVLO threshold,

the lockout circuitry will again disable the

switching. Hysteresis is included to prevent

chattering between states.

Soft Start

Internal soft start circuits limit in-rush current

when the device starts up from a power down

condition or when the “ENABLE” pin is

asserted “high”. Digital control circuitry limits

the V_OUTramp rate to levels that are safe for

the Power MOSFETS and the integrated

inductor.

Enable

The EP53A7HQI has a soft-start slew rate that

is twice that of the EP53A7LQI.

The ENABLE pin provides a means to shut

down the converter or enable normal

When the EP53A7LUI is configured in external

resistor divider mode, the device has a fixed

VOUT ramp time. Therefore, the ramp rate will

vary with the output voltage setting. Output

voltage ramp time is given in the Electrical

Characteristics Table.

operation.

A logic low will disable the

converter and cause it to shut down. A logic

high will enable the converter into normal

operation.

NOTE: The ENABLE pin must not be left

floating.

Excess bulk capacitance on the output of the

device can cause an over-current condition at

startup. The maximum total capacitance on

the output, including the output filter capacitor

and bulk and decoupling capacitance, at the

load, is given as:

Thermal Shutdown

When excessive power is dissipated in the

chip, the junction temperature rises. Once the

junction temperature exceeds the thermal

shutdown temperature, the thermal shutdown

circuit turns off the converter output voltage

thus allowing the device to cool. When the

junction temperature decreases by 25C°, the

device will go through the normal startup

process.

EP53A7LQI:

C

_{OUT_TOTAL_MAX}= C_{OUT_Filter}+ C_{OUT_BULK}= 200uF

EP53A7HQI:

_{OUT_TOTAL_MAX}= C_{OUT_Filter}+ C_{OUT_BULK}= 100uF

C

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Application Information

which in turn is connected to the non-inverting

input of the error amplifier. This allows the use

of a single feedback divider with constant loop

gain and optimum compensation, independent

of the output voltage selected.

100 ohm

V_OUT

PVIN

V_OUT

V_IN

V_SENSE

AVIN

ENABLE

10µF

4.7µF

LLM

V_S0

V_S1

V_S2

NOTE: The VID pins must not be left floating.

AGND

PGND

EP53A7L Low VID Range Programming

The EP53A7LQI is designed to provide a high

degree of flexibility in powering applications

that require low V_OUTsettings and dynamic

voltage scaling (DVS). The device employs a

3-pin VID architecture that allows the user to

choose one of seven (7) preset output voltage

settings, or the user can select an external

voltage divider option. The VID pin settings

can be changed on the fly to implement glitch-

free voltage scaling.

Figure 9: ApplicationCircuit, EP53A7HQI. Note that

all control signals should be connected to an

external control signal, AVIN or AGND.

100 ohm

V_OUT

PVIN

V_OUT

V_IN

V_SENSE

AVIN

ENABLE

LLM

10µF

4.7µF

V_FB

V_S0

V_S1

V_S2

Table 2: EP53A7LQI VID Voltage Select Settings

AGND

PGND

VS2

0

1

VS1

0

1

0

1

VS0

0

1

0

1

0

1

0

VOUT

1.50

1.45

1.20

1.15

1.10

1.05

0.8

Figure 10: Application Circuit, EP53A7LQI showing

the V_FBfunction.

Output Voltage Programming

1

EXT

The EP53A7xQI utilizes a 3-pin VID to program

the output voltage value. The VID is available

in two sets of output VID programming ranges.

The VID pins should be connected either to an

external control signal, AVIN or to AGND to

avoid noise coupling into the device. The VID

pins must not be left floating.

Table 2 shows the VS2-VS0 pin logic states for

the EP53A7LQI and the associated output

voltage levels.

A logic “1” indicates a

connection to AVIN or to a “high” logic voltage

level. A logic “0” indicates a connection to

AGND or to a “low” logic voltage level. These

pins can be either hardwired to AVIN or AGND

or alternatively can be driven by standard logic

levels. Logic levels are defined in the electrical

characteristics table. Any level between the

logic high and logic low is indeterminate.

The “Low” range is optimized for low voltage

applications. It comes with preset VID settings

ranging from 0.80V and 1.5V. This VID set

also has an external divider option.

To specify this VID range, order part number

EP53A7LQI.

EP53A7LQI External Voltage Divider

The external divider option is chosen by

connecting VID pins VS2-VS0 to AVIN or a

logic “1” or “high”. The EP53A7LQI uses a

separate feedback pin, V_FB, when using the

external divider. V_SENSEmust be connected to

V_OUTas indicated in Figure 11.

The “High” VID set provides output voltage

settings ranging from 1.8V to 3.3V.

This

version does not have an external divider

option. To specify this VID range, order part

number EP53A7HQI.

Internally, the output of the VID multiplexer

sets the value for the voltage reference DAC,

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EP53A7LQI/EP53A7HQI

or alternatively can be driven by standard logic

levels. Logic levels are defined in the electrical

characteristics table. Any level between the

logic high and logic low is indeterminate.

These pins must not be left floating.

100 Ohm

PVIN

V_Sense

V_OUT

V_IN

10µF

AVIN

4.7uF

Ra

Rb

ENABLE

Table 3: EP53A7HQI VID Voltage Select Settings

V_FB

V_S0

V_S1

V_S2

VS2

0

VS1

0

VS0

0

VOUT

3.3

LLM

PGND AGND

0

1

3.0

0

1

0

2.9

0

1

2.6

1

0

2.5

1

0

1

0

2.2

2.1

Figure 11: EP53A7LQI using external divider

1

1.8

The output voltage is selected by the following

formula:

Power-Up/Down Sequencing

Ra

Rb

V_OUT= 0.6V

(

1+

)

During power-up, ENABLE should not be

asserted before PVIN, and PVIN should not be

asserted before AVIN. The PVIN should never

be powered when AVIN is off. During power

down, the AVIN should not be powered down

before the PVIN. Tying PVIN and AVIN or all

three pins (AVIN, PVIN, ENABLE) together

during power up or power down meets these

requirements.

R_amust be chosen as 237KΩ to maintain loop

gain. Then R_bis given as:

142.2x10³

=

Ω

R_b

V_OUT− 0.6

V_OUTcan be programmed over the range of

0.6V to (V – 0.5V).

IN

NOTE: Dynamic Voltage Scaling is not allowed

between internal preset voltages and external

divider.

Pre-Bias Start-up

NOTE: LLM is not functional when using the

external divider option. Tie the LLM pin to

AGND when using this option.

The EP53A7xQI does not support startup into

a pre-biased condition. Be sure the output

capacitors are not charged or the output of the

EP53A7xQI is not pre-biased when the

EP53A7xQI is first enabled.

EP53A7HQI High VID Range

Programming

Input Filter Capacitor

The EP53A7HQI V_OUTsettings are optimized

for higher nominal voltages such as those

required to power IO, RF, or IC memory. The

preset voltages range from 1.8V to 3.3V.

There are eight (8) preset output voltage

settings. The EP53A7HQI does not have an

The input filter capacitor requirement is a

4.7µF 0402 or 0603 low ESR MLCC capacitor.

Output Filter Capacitor

The output filter capacitor requirement is a

external divider option.

As with the

minimum of 10µF 0805 MLCC.

Ripple

EP53A7LQI, the VID pin settings can be

changed while the device is enabled.

performance can be improved by using 2x10µF

0603 or 2x10µF 0805 MLCC capacitors.

Table 3 shows the VS0-VS2 pin logic states for

the EP53A7HQI and the associated output

The maximum output filter capacitance next to

the output pins of the device is 60µF low ESR

MLCC capacitance. V_OUThas to be sensed at

the last output filter capacitor next to the

EP53A7xQI.

voltage levels.

A logic “1” indicates a

connection to AVIN or to a “high” logic voltage

level. A logic “0” indicates a connection to

AGND or to a “low” logic voltage level. These

pins can be either hardwired to AVIN or AGND

Additional bulk capacitance for decoupling and

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Rev D

EP53A7LQI/EP53A7HQI

bypass can be placed at the load as long as

there is sufficient separation between the V_OUT

Sense point and the bulk capacitance. The

separation provides an inductance that isolates

the control loop from the bulk capacitance.

section on Soft-Start for the maximum total

capacitance on the output.

NOTE: The Input and Output capacitors must

use a X5R or X7R or equivalent dielectric

formulation.

Y5V or equivalent dielectric

NOTE: Excess total capacitance on the output

(Output Filter + Bulk) can cause an over-

formulations lose capacitance with frequency,

bias, and temperature and are not suitable for

switch-mode DC-DC converter filter applications.

current condition at startup.

Refer to the

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October 11, 2013

Rev D

EP53A7LQI/EP53A7HQI

Layout Recommendation

Figure 12 shows critical components and layer

1 traces of a recommended minimum footprint

EP53A7LQI/EP53A7HQI layout with ENABLE

tied to V . Alternate ENABLE configurations,

IN

and other small signal pins need to be

connected and routed according to specific

customer application. Please see the Gerber

files

on

the

Altera

website

www.altera.com/enpirion for exact dimensions

and other layers. Please refer to Figure 12

while reading the layout recommendations in

this section.

Figure 12:Top PCB Layer Critical Components

and Copper for Minimum Footprint

Recommendation 1: Input and output filter

capacitors should be placed on the same side

of the PCB, and as close to the EP53A7QI

package as possible. They should be

connected to the device with very short and

wide traces. Do not use thermal reliefs or

spokes when connecting the capacitor pads to

the respective nodes. The +V and GND traces

between the capacitors and the EP53A7QI

should be as close to each other as possible

so that the gap between the two nodes is

minimized, even under the capacitors.

Recommendation 4: Multiple small vias

should be used to connect the ground traces

under the device to the system ground plane

on another layer for heat dissipation. The drill

diameter of the vias should be 0.33mm, and

the vias must have at least 1 oz. copper plating

on the inside wall, making the finished hole

size around 0.20-0.26mm. Do not use thermal

reliefs or spokes to connect the vias to the

ground plane. It is preferred to put these vias

under the capacitors along the edge of the

GND copper closest to the +V copper. Please

see Figure 12. These vias connect the

input/output filter capacitors to the GND plane

and help reduce parasitic inductances in the

input and output current loops. If the vias

cannot be placed under C_INand C_OUT, then put

them just outside the capacitors along the

GND. Do not use thermal reliefs or spokes to

connect these vias to the ground plane.

Recommendation 2: Input and output grounds

are separated until they connect at the PGND

pins. The separation shown on Figure 12

between the input and output GND circuits

helps minimize noise coupling between the

converter input and output switching loops.

Recommendation 3: The system ground

plane should be the first layer immediately

below the surface layer. This ground plane

should be continuous and un-interrupted below

the converter and the input/output capacitors.

Please see the Gerber files on the Altera

website www.altera.com/enpirion.

Recommendation 5: AVIN is the power supply

for the internal small-signal control circuits. It

should be connected to the input voltage at a

quiet point. In Figure 12 this connection is

made with RAVIN at the input capacitor close

to the V connection.

IN

17

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October 11, 2013

Rev D

EP53A7LQI/EP53A7HQI

Recommended PCB Footprint

Figure 123: EP53A7xQI Package PCB Footprint

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October 11, 2013

Rev D

EP53A7LQI/EP53A7HQI

Package and Mechanical

Figure 14: EP53A7xQI Package Dimensions

Contact Information

Altera Corporation

101 Innovation Drive

San Jose, CA 95134

Phone: 408-544-7000

www.altera.com

QUARTUS and STRATIXwordsand logosare trademarksof Altera Corporation andregistered inthe U.S. Patent andTrademarkOffice and inother

countries. All other wordsand logosidentifiedastrademarksor service marks are the property of their respective holdersasdescribed at

www.altera.com/common/legal.html. Altera warrantsperformance of itssemiconductor productsto current specificationsin accordancewith Altera's

standard warranty, but reserves the right to make changesto any productsand servicesat any time without notice. Altera assumesno responsibility or

liability arisingout of the applicationor use of any information, product, or service described herein except asexpressly agreed to in writing by Altera.

Altera customersare advised to obtain thelatest version of device specificationsbefore relying on any publishedinformation andbefore placing orders

for products or services.

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October 11, 2013

Rev D


型号：	EVB-EP53A7LQI
厂家：	ALTERA CORPORATION
描述：	1A PowerSoC Light Load Mode Buck Regulator with Integrated Inductor
文件：	总19页 (文件大小：998K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EVB-EP53A7LQI [ALTERA]

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