EVB-EP53A8HQI [ALTERA]
1A PowerSoC Synchronous Buck Regulator with Integrated Inductor;
| 型号： | EVB-EP53A8HQI |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | 1A PowerSoC Synchronous Buck Regulator with Integrated Inductor |
| 文件： | 总14页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Enpirion® Power Datasheet
EP53A8LQI/EP53A8HQI 1A PowerSoC
Synchronous Buck Regulator
with Integrated Inductor
Description
Features
The EP53A8LQI and EP53A8HQI are a 1000mA
PowerSoC. The device integrates MOSFET
switches, control, compensation, and the
Inductor in an advanced 3mm x 3mm QFN
Package.
• Integrated Inductor Technology
• 3mm x 3mm x 1.1mm QFN package
• Total Solution Footprint ~ 21mm2
• Low VOUT ripple for IO compatibility
• High efficiency, up to 94%
Integrated inductor ensures the complete power
solution is fully characterized with the inductor
• 1000mA continuous output current
carefully
matched
to
the
silicon
and
• Less than 1µA standby current
• 5 MHz switching frequency
compensation network. It enables a tiny solution
footprint, low output ripple, low part-count, and
high reliability, while maintaining high efficiency.
The complete solution can be implemented in as
little as 21mm2.
• 3 pin VID for glitch free voltage scaling
• VOUT Range 0.6V to V – 0.5V
IN
• Short circuit and over current protection
The EP53A8xQI uses a 3-pin VID to easily select
the output voltage setting.
Output voltage • UVLO and thermal protection
settings are available in 2 optimized ranges
providing coverage for typical VOUT settings.
• IC level reliability in a PowerSoC solution
Applications
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP53A8LQI further has
the option to use an external voltage divider.
• Portable wireless and RF applications
• Wireless broad band data cards
• Solid state storage applications
• Noise and space sensitive applications
3.5mm
100 ohm
4.7uF
VOUT
100 Ohm
PVIN
VOUT
VIN
VSENSE
AVIN
ENABLE
10µF
0805
4.7µF
VFB
VS0
VS1
VS2
0603
EP53A8xQI
6mm
AGND
PGND
10uF
Figure 1. Total Solution Footprint
Figure 2. Typical Application Circuit.
www.altera.com/enpirion
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Ordering Information
Part Number
Comment
Package
EP53A8LQI
LOW VID Range 16-pin QFN T&R
HIGH VID Range 16-pin QFN T&R
EP53A8LQI Evaluation Board
EP53A8HQI
EVB-EP53A8LQI
EVB-EP53A8HQI
EP53A8HQI Evaluation Board
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments(Top View)
Figure 1: EP53A8LQI Pin Out Diagram (Top View)
Figure 4: EP53A8HQI Pin Out Diagram (Top View) Pin
Description
Pin Description
PIN
NAME
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal,
ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline
may result in part malfunction or damage to the device.
1, 15,
16
NC(SW)
Power ground. Connect this pin to the ground electrode of the Input and output filter
capacitors.
EP53A8LQI: Feed back pin for external divider option.
EP53A8HQI: No Connect
2,3
PGND
VFB
4
5
VSENSE Sense pin for preset output voltages. Refer to application section for proper configuration.
Analog ground. This is the quiet ground for the internal control circuitry, and the ground return
for external feedback voltage divider
6
AGND
7, 8
VOUT
Regulated Output Voltage. Refer to application section for proper layout and decoupling.
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
9, 10,
11
VS2, VS1, EP53A8LQI: Selects one of seven preset output voltages or an external resistor divider.
VS0
EP53A8HQI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.)
12
13
14
ENABLE Output Enable. Enable = logic high; Disable = logic low
AVIN
PVIN
Input power supply for the controller circuitry. Connect to PVIN through a 100 Ohm resistor.
Input Voltage for the MOSFET switches.
www.altera.com/enpirion, Page 2
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Supply Voltage
VIN
-0.3
6.0
V
-0.3
-0.3
VIN+ 0.3
2.7
V
V
Voltages on: ENABLE, VSENSE, VSO – VS2
Voltages on: VFB (EP53A8LQI)
Maximum Operating Junction Temperature
Storage Temperature Range
TJ-ABS
TSTG
150
150
°C
°C
°C
V
-65
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
260
2000
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
2.4
MAX
5.5
UNITS
Input Voltage Range
VIN
TA
TJ
V
Operating Ambient Temperature
Operating Junction Temperature
- 40
- 40
+85
°C
°C
+125
Thermal Characteristics
PARAMETER
SYMBOL
θJA
TYP
UNITS
°C/W
Thermal Resistance: Junction to Ambient –0 LFM (Note 1)
80
+155
25
Thermal Overload Trip Point
TJ-TP
°C
°C
Thermal Overload Trip Point Hysteresis
Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards.
www.altera.com/enpirion, Page 3
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V.
CIN = -4.7µF 0603 MLCC, COUT = 10µF 0805 MLCC.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input Voltage
VIN
2.4
5.5
V
Under Voltage Lock-out –
VIN Rising
VUVLO_R
2.0
V
Under Voltage Lock-out –
VIN Falling
VUVLO_F
RDO
1.9
V
mΩ
V
Drop Out Resistance
Input to Output Resistance
350
500
VIN-VDO
3.3
0.6
1.8
EP53A8LQI (VDO = ILOAD X RDO
EP53A8HQI
)
Output Voltage Range
VOUT
Dynamic VoltageSlew
Rate
EP53A8HQI
EP53A8LQI
8
4
V/mS
%
VSLEW
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
VID Preset VOUT Initial
Accuracy
∆VOUT
-2
+2
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
Feedback Pin Voltage
Initial Accuracy
VFB
.588
0.6
0.612
V
Line Regulation
2.4V ≤ VIN ≤ 5.5V
0.03
0.6
30
%/V
%/A
∆VOUT_LINE
∆VOUT_LOAD
∆VOUT_TEMPL
Load Regulation
0A ≤ ILOAD ≤ 1000mA
Temperature Variation
ppm/°C
-40°C ≤ TA ≤ +85°C
Output Current
IOUT
ISD
1000
1.25
mA
µA
Shut-down Current
Enable = Low
0.75
1.4
2.4V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V
OCP Threshold
ILIM
A
VS0-VS2, Pin Logic Low
VS0-VS2, Pin Logic High
VVSLO
VVSHI
0.0
1.4
0.3
VIN
V
V
VS0-VS2, Pin Input
Current
IVSX
Note 1
<100
nA
Enable Pin Logic Low
Enable Pin Logic High
Enable Pin Current
VENLO
VENHI
IENABLE
0.3
V
V
1.4
Note 1
Note 1
<100
<100
5
nA
Feedback Pin Input
Current
IFB
nA
Operating Frequency
FOSC
MHz
Soft Start Operation
EP53A8HQI (VID only)
EP53A8LQI (VID only)
8
4
Soft Start Slew Rate
Soft Start Rise Time
V/mS
∆VSS
∆TSS
EP53A8LQI (VFB mode); Note 2
170
225
280
µS
Note 1: Parameter guaranteed by design and characterization.
Note 2: Measured from when VIN ≥ VUVLO_R & ENABLE pin crosses its logic High threshold.
www.altera.com/enpirion, Page 4
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Typical PerformanceCharacteristics
Efficiency vs. Load Current: VIN = 5.0V, VOUT
(from top to bottom) = 3.7, 3.3, 2.5, 1.8, 1.2V
Efficiency vs. Load Current: VIN = 3.3V, VOUT
(from top to bottom) = 2.5, 1.8V,1.2V
95
85
75
65
55
45
35
25
95
85
75
65
55
45
35
25
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Load Current (A)
Load Current (A)
Shut-down Waveform:
Start Up Waveform:
VIN = 5.0V, VOUT = 3.3V; ILOAD = 1000mA
VIN = 5.0V, VOUT = 3.3V; ILOAD = 1000mA
Output Ripple: VIN = 5.0V, VOUT = 1.2V, Load = 1A
Output Ripple: VIN = 5.0V, VOUT = 3.3V, Load = 1A
www.altera.com/enpirion, Page 5
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Typical PerformanceCharacteristics (continued)
Output Ripple: VIN = 3.3V, VOUT = 1.8V, Load = 1A
Output Ripple: VIN = 3.3V, VOUT = 1.2V, Load= 1A
5mV/Div
Load Transient: VIN = 5.0V, VOUT = 3.3V
Load stepped from 0mA to 1000mA
Load Transient: VIN = 5.0V, VOUT = 1.2V
Load stepped from 0mA to 1000mA
Load Transient: VIN = 3.7V, VOUT = 1.2V
Load stepped from 0mA to 1000mA
Load Transient: VIN = 3.3V, VOUT = 1.8V
Load stepped from 0mA to 1000mA
www.altera.com/enpirion, Page 6
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Functional Block Diagram
PVIN
UVLO
Thermal Limit
Current Limit
NC(SW)
VOUT
ENABLE
Soft Start
P-Drive
N-Drive
Logic
(-)
PWM
Comp
(+)
PGND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
VFB
Error
Amp
(+)
DAC
Voltage
Select
VREF
Package Boundry
VS2
VS1
VS0
AVIN AGND
Figure 5: Functional Block Diagram
www.altera.com/enpirion, Page 7
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Functional Description
Functional Overview
inductor greatly simplifies the power supply
design process. The inherent shielding and
compact construction of the integrated inductor
reduces the conducted and radiated noise that
can couple into the traces of the printed circuit
The EP53A8xQI requires only 2 small MLCC
capacitors and an 0201MLC resistor for a
complete DC-DC converter solution.
The
device integrates MOSFET switches, PWM
controller, Gate-drive, compensation, and
inductor into a tiny 3mm x 3mm x 1.1mm QFN
package. Advanced package design, along
with the high level of integration, provides very
low output ripple and noise. The EP53A8xQI
uses voltage mode control for high noise
immunity and load matching to advanced
≤90nm loads. A 3-pin VID allows the user to
choose from one of 8 output voltage settings.
The EP53A8xQI comes with two VID output
board.
Further, the package layout is
optimized to reduce the electrical path length
for the high di/dT input AC ripple currents that
are a major source of radiated emissions from
DC-DC converters. The integrated inductor
provides the optimal solution to the complexity,
output ripple, and noise that plague low power
DCDC converter design.
Voltage Mode Control, High Bandwidth
The EP53A8xQI utilizes an integrated type III
compensation network. Voltage mode control
is inherently impedance matched to the sub
90nm process technology that is used in
today’s advanced ICs. Voltage mode control
also provides a high degree of noise immunity
at light load currents so that low ripple and high
accuracy are maintained over the entire load
voltage ranges.
The EP53A8HQI provides
VOUT settings from 1.8V to 3.3V, the
EP53A8LQI provides VID settings from 0.8V to
1.5V, and also has an external resistor divider
option to program output setting over the 0.6V
to V -0.5V range. The EP53A8xQI provides
IN
the industry’s highest power density of any 1A
DCDC converter solution.
range.
The very high switching frequency
allows for a very wide control loop bandwidth
and hence excellent transient performance.
The key enabler of this revolutionary
integration is Altera’s proprietary power
MOSFET technology. The advanced MOSFET
switches are implemented in deep-submicron
CMOS to supply very low switching loss at high
switching frequencies and to allow a high level
of integration. The semiconductor process
allows seamless integration of all switching,
control, and compensation circuitry.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The proprietary magnetics design provides
high-density/high-value magnetics in a very
small footprint. Altera Enpirion magnetics are
carefully matched to the control and
compensation circuitry yielding an optimal
solution with assured performance over the
entire operating range.
The EP53A8HQI has a soft-start slew rate that
is twice that of the EP53A8LQI.
When the EP53A8LQI is configured in external
resistor divider mode, the device has a fixed
VOUT ramp time. Therefore, the ramp rate will
vary with the output voltage setting. Output
voltage ramp time is given in the Electrical
Characteristics Table.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
Excess bulk capacitance on the output of the
device can cause an over-current condition at
Integrated Inductor: Low-Noise Low-EMI
startup.
Assuming no-load at startup, the
maximum total capacitance on the output,
including the output filter capacitor and bulk
The EP53A8xQI utilizes a proprietary low loss
integrated inductor.
The integration of the
www.altera.com/enpirion, Page 8
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Under Voltage Lockout
and decoupling capacitance, at the load, is
given as:
During initial power up, an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
EP53A8LQI:
C
OUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 250uF
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
EP53A8HQI:
OUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 125uF
C
Enable
EP53A8LQI (in external divider mode):
OUT_TOTAL_MAX = 2.25x10-4/VOUT Farads
The ENABLE pin provides a means to shut
down the converter or enable normal
C
operation.
A logic low will disable the
converter and cause it to shut down. A logic
high will enable the converter into normal
operation.
The nominal value for COUT is 10uF. See the
applications section for more details.
Over Current/Short Circuit Protection
NOTE: The ENABLE pin must not be left
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for approximately 0.5mS and then a normal
floating.
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature, the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 25C°, the
device will go through the normal startup
process.
soft start is initiated.
If the over current
condition still persists, this cycle will repeat.
Application Information
100 ohm
100 ohm
VOUT
VOUT
PVIN
PVIN
VOUT
VOUT
VIN
VIN
VSENSE
AVIN
VSENSE
AVIN
ENABLE
ENABLE
10µF
0805
10µF
0805
4.7µF
0603
4.7µF
0603
VFB
VS0
VS1
VS2
VS0
VS1
VS2
AGND
PGND
AGND
PGND
Figure 3: Application Circuit, EP53A8LQI showing
the VFB function.
Figure 2: Application Circuit, EP53A8HQI.
www.altera.com/enpirion, Page 9
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
can be changed on the fly to implement glitch-
free voltage scaling.
Output Voltage Programming
The EP53A8xQI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to an
external control signal, AVIN or to AGND to
avoid noise coupling into the device.
Table 1 shows the VS2-VS0 pin logic states for
the EP53A8LQI and the associated output
voltage levels.
A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
also has an external divider option.
To specify this VID range, order part number
EP53A8LQI.
EP53A8LQI External Voltage Divider
The “High” VID set provides output voltage
The external divider option is chosen by
settings ranging from 1.8V to 3.3V.
This
connecting VID pins VS2-VS0 to V or a logic
IN
version does not have an external divider
option. To specify this VID range, order part
number EP53A8HQI.
“1” or “high”. The EP53A8LQI uses a separate
feedback pin, VFB, when using the external
divider. VSENSE must be connected to VOUT as
indicated in Figure 8.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
which in turn is connected to the non-inverting
input of the error amplifier. This allows the use
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage selected.
The output voltage is selected by the following
formula:
Ra
Rb
VOUT = 0.6V
1+
100 Ohms
PVIN
VSense
VOUT
VOUT
VIN
NOTE: The VID pins must not be left floating.
AVIN
10µF
0805
4.7uF
0603
Ra
Rb
ENABLE
VFB
VS0
VS1
Table 1: EP53A8LQI VID Voltage Select Settings
VS2
PGND AGND
VS2
0
0
0
0
1
1
1
VS1
0
0
1
1
0
0
1
VS0
0
1
0
1
0
1
0
VOUT
1.50
1.45
1.20
1.15
1.10
1.05
0.8
Figure 4: EP53A8LQI using external divider
Ra must be chosen as 237KΩ to maintain loop
gain. Then Rb is given as:
142.2x103
1
1
1
EXT
=
Ω
Rb
VOUT − 0.6
EP53A8L Low VID Range Programming
VOUT can be programmed over the range of
The EP53A8LQI is designed to provide a high
degree of flexibility in powering applications
that require low VOUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
0.6V to (V – 0.5V).
IN
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
www.altera.com/enpirion, Page 10
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
EP53A8HQI High VID Range
Programming
Pre-Bias Start-up
The EP53A8xQI does not support startup into
a pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP53A8xQI is not pre-biased when the
EP53A8xQI is first enabled.
The EP53A8HQI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP53A8HQI does not have an
external divider option.
EP53A8LQI, the VID pin settings can be
changed while the device is enabled.
Input Filter Capacitor
The input filter capacitor requirement is a
4.7µF 0603 low ESR MLCC capacitor. The
input capacitor must use a X5R or X7R or
As with the
equivalent dielectric formulation.
equivalent dielectric formulations
capacitance with frequency, bias, and with
temperature, and are not suitable for switch-
mode DC-DC converter input filter applications.
Y5V or
lose
Table 2 shows the VS0-VS2 pin logic states for
the EP53A8HQI and the associated output
voltage levels.
A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
Output Filter Capacitor
The output filter capacitor requirement is a
minimum of 10µF 0805 MLCC.
performance can be improved by using 2x10µF
0603 or 2x10µF 0805 MLCC capacitors.
Ripple
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP53A8xQI.
Table 2: EP53A8HQI VID Voltage Select Settings
VS2
0
VS1
0
VS0
0
VOUT
3.3
0
0
1
3.0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
2.9
2.6
2.5
2.2
2.1
1.8
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance. The
separation provides an inductance that isolates
the control loop from the bulk capacitance.
Power-Up/Down Sequencing
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance
on the output.
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
The output capacitor must use a X5R or X7R or
equivalent dielectric formulation.
equivalent dielectric formulations
Y5V or
lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-mode
DC-DC converter output filter applications.
www.altera.com/enpirion, Page 11
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Layout Recommendation
Figure 9 shows critical components and layer 1
traces of a recommended minimum footprint
EP53A8LQI/EP53A8HQI layout with ENABLE
tied to V . Alternate ENABLE configurations,
IN
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files
on
the
Altera
website
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figure 9 while
reading the layout recommendations in this
section.
Figure 9: Top PCB Layer Critical Components
and Copper for Minimum Footprint
Recommendation 1: Input and output filter
Recommendation 4: Multiple small vias
capacitors should be placed on the same side
of the PCB, and as close to the EP53A8QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP53A8QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 9. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT, then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
connect these vias to the ground plane.
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 9
between the input and output GND circuits
helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Recommendation 5: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 9 this connection is made
with RAVIN at the input capacitor close to the
V connection.
IN
www.altera.com/enpirion, Page 12
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Recommended PCB Footprint
Figure 10: EP53A8xQI Package PCB Footprint
www.altera.com/enpirion, Page 13
03651
September 17, 2013
Rev D
EP53A8LQI/EP53A8HQI
Package and Mechanical
Figure 51: EP53A8xQI Package Dimensions
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right tomake changes toany products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advisedto obtainthe latest version of devicespecifications before relying on any publishedinformation and beforeplacing orders for
products or services.
www.altera.com/enpirion, Page 14
03651
September 17, 2013
Rev D
相关型号：
©2020 ICPDF网 联系我们和版权申明