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EVB-LAN9353 [MICROCHIP]

EVAL BOARD FOR LAN9353;
EVB-LAN9353
型号： EVB-LAN9353
厂家： MICROCHIP    MICROCHIP
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EVAL BOARD FOR LAN9353

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EVB-LAN9353  
Evaluation Board  
User’s Guide  
2015 Microchip Technology Inc.  
DS50002393A  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be  
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO  
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
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harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or  
otherwise, under any Microchip intellectual property rights unless otherwise stated.  
Trademarks  
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck,  
MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and  
UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.  
The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A.  
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial  
Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK,  
MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial  
Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.  
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.  
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in  
other countries.  
All other trademarks mentioned herein are property of their respective companies.  
© 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.  
ISBN: 978-1-63277-587-0  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ  
and India. The Company’s quality system processes and procedures  
CERTIFIEDꢀBYꢀDNVꢀ  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
== ISO/TSꢀ16949ꢀ==ꢀ  
DS50002393A-page 2  
2015 Microchip Technology Inc.  
EVB-LAN9353 Evaluation Board User’s Guide  
EVB-LAN9353  
Object of Declaration:  
2015 Microchip Technology Inc.  
DS50002393A-page 3  
EVB-LAN9353 Evaluation Board User’s Guide  
NOTES:  
2015 Microchip Technology Inc.  
DS50002393A-page 4  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Table of Contents  
Preface ........................................................................................................................... 7  
Introduction............................................................................................................ 7  
Document Layout .................................................................................................. 7  
Conventions Used in this Guide............................................................................ 8  
The Microchip Web Site ........................................................................................ 9  
Development Systems Customer Change Notification Service ............................ 9  
Customer Support ................................................................................................. 9  
Document Revision History................................................................................. 10  
Chapter 1. Overview  
1.1 Introduction ................................................................................................... 11  
1.1.1 References ................................................................................................ 13  
1.1.2 Terms and Abbreviations .......................................................................... 14  
Chapter 2. Board Details  
2.1 Board Details ................................................................................................ 15  
2.1.1 Power ........................................................................................................ 15  
2.1.2 Power-on Reset ......................................................................................... 15  
2.1.3 Clock .......................................................................................................... 16  
Chapter 3. Board Configuration  
3.1 Strap Options ............................................................................................... 17  
3.1.1 Jumpers J4:J15 ......................................................................................... 17  
3.1.1.1 GPIO/LED POL/LED Configurations ......................................... 18  
3.1.1.2 Serial Management Mode Configuration ................................... 19  
3.1.1.3 EEPROM Size Configuration ..................................................... 19  
3.1.1.4 Energy-Efficient Ethernet Configuration .................................... 19  
3.1.1.5 1588 Enable Configuration ........................................................ 20  
3.1.1.6 PHY Address Configuration ....................................................... 20  
3.1.2 GPIO 6 & GPIO 7 Input and Output Configurations .................................. 20  
3.1.3 Jumper Settings for CONFIG 9 or CONFIG 10 ......................................... 21  
3.1.4 Link Partner Duplex/Speed Configurations ............................................... 21  
3.1.5 P0/P1 Configurations ................................................................................ 22  
3.1.6 RMII RX Clock Configurations ................................................................... 24  
3.1.7 GPIO Header ............................................................................................. 24  
3.1.8 I2C Aardvark Header ................................................................................. 25  
3.1.9 Copper and Fiber Mode Selections ........................................................... 25  
3.1.9.1 Copper Mode ............................................................................. 25  
3.1.9.2 Fiber Mode ................................................................................ 25  
3.1.9.3 FX-LOS Fiber Mode Strap ......................................................... 26  
3.2 LEDs ............................................................................................................. 26  
3.3 Test Points ................................................................................................... 27  
2015 Microchip Technology Inc.  
DS50002393A-page 5  
EVB-LAN9353 Evaluation Board User’s Guide  
3.4 Mechanicals ................................................................................................. 27  
Appendix A. EVB-LAN9353 Evaluation Board  
A.1 Introduction .................................................................................................. 28  
Appendix B. EVB-LAN9353 Evaluation Board Schematics  
B.1 Introduction .................................................................................................. 29  
Appendix C. Bill of Materials (BOM)  
C.1 Introduction .................................................................................................. 39  
Wordwide Sales and Service ......................................................................................43  
DS50002393A-page 6  
2015 Microchip Technology Inc.  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Preface  
NOTICE TO CUSTOMERS  
All documentation becomes dated, and this manual is no exception. Microchip tools and  
documentation are constantly evolving to meet customer needs, so some actual dialogs  
and/or tool descriptions may differ from those in this document. Please refer to our web site  
(www.microchip.com) to obtain the latest documentation available.  
Documents are identified with a “DS” number. This number is located on the bottom of each  
page, in front of the page number. The numbering convention for the DS number is  
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the  
document.  
®
For the most up-to-date information on development tools, see the MPLAB IDE online help.  
Select the Help menu, and then Topics to open a list of available online help files.  
INTRODUCTION  
This chapter contains general information that will be useful to know before using the  
EVB-LAN9353. Items discussed in this chapter include:  
• Document Layout  
• Conventions Used in this Guide  
• The Microchip Web Site  
• Development Systems Customer Change Notification Service  
• Customer Support  
• Document Revision History  
DOCUMENT LAYOUT  
This document describes how to use the EVB-LAN9353 Evaluation Board as a  
development tool for the LAN9353 three-port 10/100 managed Ethernet switch. The  
manual layout is as follows:  
• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9353 Evalua-  
tion Board.  
• Chapter 2. “Getting Started” – Includes instructions on how to get started with  
the EVB-LAN9353 Evaluation Board.  
• Chapter 3. “Board Configuration” – Provides information about the  
EVB-LAN9353 Evaluation Board battery charging features.  
• Appendix A. “EVB-LAN9353 Evaluation Board” – This appendix shows the  
EVB-LAN9353 Evaluation Board.  
• Appendix B. “EVB-LAN9353 Evaluation Board Schematics” – This appendix  
shows the EVB-LAN9353 Evaluation Board schematics.  
• Appendix C. “Bill of Materials (BOM)” – This appendix includes the  
EVB-LAN9353 Evaluation Board Bill of Materials (BOM).  
2015 Microchip Technology Inc.  
DS50002393A-page 7  
EVB-LAN9353 Evaluation Board User’s Guide  
CONVENTIONS USED IN THIS GUIDE  
This manual uses the following documentation conventions:  
DOCUMENTATION CONVENTIONS  
Description  
Represents  
Examples  
Arial font:  
Italic characters  
Referenced books  
Emphasized text  
A window  
MPLAB® IDE User’s Guide  
...is the only compiler...  
the Output window  
Initial caps  
A dialog  
the Settings dialog  
A menu selection  
select Enable Programmer  
“Save project before build”  
Quotes  
A field name in a window or  
dialog  
Underlined, italic text with  
right angle bracket  
A menu path  
File>Save  
Bold characters  
A dialog button  
A tab  
Click OK  
Click the Power tab  
4‘b0010, 2‘hF1  
N‘Rnnnn  
A number in verilog format,  
where N is the total number of  
digits, R is the radix and n is a  
digit.  
Text in angle brackets < >  
Courier New font:  
A key on the keyboard  
Press <Enter>, <F1>  
Plain Courier New  
Sample source code  
Filenames  
#define START  
autoexec.bat  
c:\mcc18\h  
File paths  
Keywords  
_asm, _endasm, static  
-Opa+, -Opa-  
0, 1  
Command-line options  
Bit values  
Constants  
0xFF, ‘A’  
Italic Courier New  
Square brackets [ ]  
A variable argument  
file.o, where file can be  
any valid filename  
Optional arguments  
mcc18 [options] file  
[options]  
Curly brackets and pipe  
character: { | }  
Choice of mutually exclusive errorlevel {0|1}  
arguments; an OR selection  
Ellipses...  
Replaces repeated text  
var_name [,  
var_name...]  
Represents code supplied by void main (void)  
user  
{ ...  
}
DS50002393A-page 8  
2015 Microchip Technology Inc.  
Preface  
THE MICROCHIP WEB SITE  
Microchip provides online support via our web site at www.microchip.com. This web  
site is used as a means to make files and information easily available to customers.  
Accessible by using your favorite Internet browser, the web site contains the following  
information:  
• Product Support – Data sheets and errata, application notes and sample  
programs, design resources, user’s guides and hardware support documents,  
latest software releases and archived software  
• General Technical Support – Frequently Asked Questions (FAQs), technical  
support requests, online discussion groups, Microchip consultant program  
member listing  
• Business of Microchip – Product selector and ordering guides, latest Microchip  
press releases, listing of seminars and events, listings of Microchip sales offices,  
distributors and factory representatives  
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE  
Microchip’s customer notification service helps keep customers current on Microchip  
products. Subscribers will receive e-mail notification whenever there are changes,  
updates, revisions or errata related to a specified product family or development tool of  
interest.  
To register, access the Microchip web site at www.microchip.com, click on Customer  
Change Notification and follow the registration instructions.  
The Development Systems product group categories are:  
• Compilers – The latest information on Microchip C compilers, assemblers, linkers  
and other language tools. These include all MPLAB C compilers; all MPLAB  
assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK  
object linker); and all MPLAB librarians (including MPLIB object librarian).  
• Emulators – The latest information on Microchip in-circuit emulators.This  
includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.  
• In-Circuit Debuggers – The latest information on the Microchip in-circuit  
debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug  
express.  
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows  
Integrated Development Environment for development systems tools. This list is  
focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and  
MPLAB SIM simulator, as well as general editing and debugging features.  
• Programmers – The latest information on Microchip programmers. These include  
production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB  
ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included  
are nonproduction development programmers such as PICSTART Plus and  
PIC-kit 2 and 3.  
CUSTOMER SUPPORT  
Users of Microchip products can receive assistance through several channels:  
• Distributor or Representative  
• Local Sales Office  
• Field Application Engineer (FAE)  
• Technical Support  
2015 Microchip Technology Inc.  
DS50002393A-page 9  
EVB-LAN9353 Evaluation Board User’s Guide  
Customers should contact their distributor, representative or field application engineer  
(FAE) for support. Local sales offices are also available to help customers. A listing of  
sales offices and locations is included in the back of this document.  
Technical support is available through the web site at:  
http://www.microchip.com/support  
DOCUMENT REVISION HISTORY  
Revision A (July 2015)  
• Initial Release of this Document.  
DS50002393A-page 10  
2015 Microchip Technology Inc.  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Chapter 1. Overview  
1.1  
INTRODUCTION  
The LAN9353 is a fully featured, three-port 10/100 managed Ethernet switch designed  
for industrial and embedded applications where performance, flexibility, ease of inte-  
gration and system cost control are required.  
The LAN9353 combines all the functions of a 10/100 switch system, including the  
switch fabric, packet buffers, buffer manager, media access controllers (MACs), PHY  
transceivers, and serial management. IEEE 1588v2 is supported via the integrated  
IEEE 1588v2 hard-ware time stamp unit, which supports end-to-end and peer-to-peer  
transparent clocks.  
The LAN9353 complies with the IEEE 802.3 (full/half-duplex 10BASE-T and  
100BASE-TX) Ethernet protocol, IEEE 802.3az Energy Efficient Ethernet (EEE)  
(100Mbps only), and 802.1D/802.1Q management protocol specifications, enabling  
compatibility with industry standard Ethernet and Fast Ethernet applications.  
100BASE-FX is supported via an external fiber transceiver and cable diagnostics  
(short, open and length) is included on the internal twisted pair copper interface.  
The EVB-LAN9353 is an Evaluation Board (EVB) that utilizes the LAN9353 to provide  
a fully-functional three-port Ethernet switch with Single MII/RMII/Turbo MII or Dual  
RMII. The EVB-LAN9353 provides one fully integrated MAC/PHY internet port (Port 2)  
via on-board RJ45 connectors. Port 0 and Port 1 provides two MII port connectors  
which support the following:  
• An external “Dual RMII –Capable or singleMII / RMII / Turbo MII”-Capable MAC  
(with LAN9353 in PHY mode), via the on-board 40-pin male MII connector  
• An external “Dual RMII –Capable or singleMII / RMII / Turbo MII”-Capable PHY  
(with LAN9353 in MAC mode), via the on-board 40-pin female MII connector  
Power is supplied to the board via a +5V external wall mount power supply.  
The EVB-LAN9353 includes a 64K x 8 I2C EEPROM that may be used to automatically  
load configuration settings from the EEPROM into the device at reset. An I2C host  
adapter interface header (10-pin, 2x5) is provided to simplify I2C based configuration.  
A simplified block diagram of the EVB LAN9353 can be seen in Error! Reference  
source not found and LAN9353 supports for CONFIG 9 or CONFIG 10.  
CONFIG 9: used to configure the LAN9353 in Dual RMII mode for external ports.  
CONFIG 10: used to configure the LAN9353 in Single MII/RMII/TMII mode for external  
port.  
2015 Microchip Technology Inc.  
DS50002393A-page 11  
EVB-LAN9353 Evaluation Board User’s Guide  
FIGURE 1-1:  
EVB-LAN9353 BLOCK DIAGRAM (CONFIG 9)  
To External  
MAC  
To External  
PHY  
To External  
PHY  
To External  
MAC  
40 pin MII  
Connector  
(Male)  
40 pin MII  
Connector  
(Female)  
40 pin MII  
Connector  
(Female)  
40 pin MII  
Connector  
(Male)  
RMII  
RMII  
Port 1  
Port 0  
Mode  
Switch  
Power Supply  
Module  
5V  
Microchip  
LAN9353  
I2C EEPROM  
Reset  
Straps  
Jumpers  
Crystal  
Port 2  
10/100  
Ethernet  
Magnetics &  
RJ45  
Fiber  
Transceiver  
(SFP)  
Ethernet  
DS50002393A-page 12  
2015 Microchip Technology Inc.  
FIGURE 1-2:  
EVB-LAN9353 BLOCK DIAGRAM (CONFIG 10)  
To External  
PHY  
To External  
MAC  
40 pin MII  
Connector  
(Female)  
40 pin MII  
Connector  
(Male)  
MII/RMII/TMII  
Port 0  
Mode  
Switch  
Power Supply  
Module  
5V  
Microchip  
LAN9353  
I2C EEPROM  
Reset  
Straps  
Jumpers  
Crystal  
Port 1  
Port 2  
10/100  
Ethernet  
Magnetics &  
RJ45  
10/100  
Fiber  
Transceiver  
(SFP)  
Fiber  
Transceiver  
(SFP)  
Ethernet  
Magnetics &  
RJ45  
Ethernet  
Ethernet  
1.1.1  
References  
Concepts and material available in the following documents may be helpful when read-  
ing this document. Visit www.microchip.com for the latest documentation.  
Document  
Location  
LAN9353 datasheet  
Visit www.microchip.com  
AN8-13 Suggested Mag-  
netics  
http://www.microchip.com/wwwAp-  
pNotes/AppNotes.aspx?appnote=en562793  
EVB-LAN9353 Evalua-  
tion Board Schematic  
Visit www.microchip.com  
2015 Microchip Technology Inc.  
DS50002393A-page 13  
EVB-LAN9353 Evaluation Board User’s Guide  
1.1.2  
Terms and Abbreviations  
• EVB - Evaluation Board  
• DNP - Do Not Populate  
• 100BASE-TX - 100 Mbps Fast Ethernet, IEEE802.3u Compliant  
• GPIO - General Purpose I/O  
• MII - Media Independent Interface  
• RMII - Reduced Media Independent Interface  
• EEE - Energy-Efficient Ethernet  
• SFP - Small Form-factor Pluggable  
• SFF - Small Form Factor  
• SMI - Serial Management Interface  
DS50002393A-page 14  
2015 Microchip Technology Inc.  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Chapter 2. Board Details  
2.1  
BOARD DETAILS  
The following sections describe the various board features, including jumpers, LEDs,  
test points, system connections, and switches. A top view of the EVB-LAN9353 is  
shown in Figure 2-1.  
FIGURE 2-1:  
LAN9353 BOARD REV-A  
Strap  
Mode Switch  
Power  
Reset  
EEPROM  
Port 1** (Female)  
MII Connector  
Port 0 (Female)  
MII Connector  
Port 1** (Male)  
MII Connector  
Port 0 (Male)  
MII Connector  
Microchip  
LAN9353  
Port 1**  
(with integrated  
magnetics & LEDs)  
Port 2  
(with integrated  
magnetics & LEDs)  
Note: Config 10: Port 1 and Port 2 both are Internal, Port 0 External.  
Config 9: Only Port 2 Internal, Port 0 and Port 1 are External.  
2.1.1  
Power  
DC 5V is applied through (J1) DC Socket, powered by a +5V external wall adapter.  
switch (SW1) need to be ON position for the 5V to reach the 3.3V regulator. Glowing of  
Green LED (D1) indicates successful generation of 3.3V o/p. This Power is supplied to  
the LAN9353 and it has internal 1.2 V regulator which supplies power to the internal  
core logic.  
2.1.2  
Power-on Reset  
A power-on reset occurs whenever power is initially applied to the LAN9353 or if the  
power is removed and reapplied to the LAN9353. This event resets all circuitry within  
the LAN9353. After initial power-on, the LAN9353 can be reset by pressing the reset  
switch (SW2). The reset LED D2 will assert (red) when the LAN9353 is in reset condi-  
tion.  
2015 Microchip Technology Inc.  
DS50002393A-page 15  
EVB-LAN9353 Evaluation Board User’s Guide  
For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset  
release.  
2.1.3  
Clock  
The LAN9353 requires a fixed-frequency 25 MHz clock (±50 ppm) source for use by  
the internal clock oscillator and PLL. This is typically provided by attaching a 25 MHz  
crystal to the OSCI and OSCO pins. Optionally, this clock can be provided by driving  
the OSCI input pin with a single-ended 25 MHz clock source.  
DS50002393A-page 16  
2015 Microchip Technology Inc.  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Chapter 3. Board Configuration  
3.1  
STRAP OPTIONS  
The following tables describe the default settings and jumper descriptions for the  
EVB-LAN9353. These defaults are the recommended configurations for evaluation of  
the LAN9353. These settings may be changed as needed, however, any deviation from  
the defaults settings should be approached with care and knowledge of the schematics  
and datasheet. An incorrect jumper setting may disable the board.  
3.1.1  
Jumpers J4:J15  
Jumpers J4 through J15 set various functions of the LAN9353. They can also be used  
as GPIOs, LED drivers. When used as LED drivers, as they are on the EVB-LAN9353,  
they are connected a specific way to set the strap value to a “1”, and another way to  
set the strap value to a “0” Figure 3-1 illustrates the schematics connections with the  
D3 circuit as a pull-up, and the D4 circuit as a pull-down. To illuminate D3, the LAN9353  
will drive the cathode of the D3 low. To illuminate D4, the LAN9353 will drive the cath-  
ode of the D4 high.  
The J4 - J15 jumpers must be configured in pairs to identical settings in order to realize  
the D3 circuit or the D4 circuit. The pairings are as follows:  
- J4 & J7  
- J6 & J9  
- J5 & J8  
- J11 & J14  
- J10 & J13  
- J12 & J15  
The following subsections detail the jumper pair settings, their associated strap set-  
tings, and the functional effects of setting the straps. All strap values are read during  
power-up and on the rising edge of nRST signal. Once the strap value is set, the  
LAN9353 will drive the LED’s high or low for illumination according the strap value. For  
other designs which may use these pins as GPIOs refer to LAN9353 datasheet for  
additional information. In those cases, internal default straps must be changed by an  
I2C or SMI master or through EEPROM fields.  
2015 Microchip Technology Inc.  
DS50002393A-page 17  
EVB-LAN9353 Evaluation Board User’s Guide  
FIGURE 3-1:  
LED STRAP CIRCUIT  
3.1.1.1  
GPIO/LED POL/LED CONFIGURATIONS:  
GPIO/LED POL/LED configuration straps are used to configure the default polarity of  
LEDs, GPIOs through jumpers as shown below in Table 3-1.  
TABLE 3-1:  
Header  
GPIO/LED POL/LED CONFIGURATIONS  
Pin Settings  
Signal Name  
Strap Value  
Description  
J4 & J7  
1-2(default)  
LEDPOL0  
/GPIO0  
/LED0  
1
The LED (D3) is  
set as active  
LOW.  
2 -3  
1-2(default)  
2 -3  
0
1
0
1
0
1
0
The LED (D3) is  
set as active  
HIGH.  
J5 & J8  
J6 & J9  
LEDPOL1  
/GPIO1  
/LED1  
The LED (D4) is  
set as active  
LOW.  
The LED (D4) is  
set as active  
HIGH.  
1-2(default)  
2 -3  
LEDPOL2  
/GPIO2  
/LED2  
The LED (D5) is  
set as active  
LOW.  
The LED (D5) is  
set as active  
HIGH.  
J10 & J13  
1-2(default)  
2 -3  
LEDPOL3  
/GPIO3  
/LED3  
The LED (D6) is  
set as active  
LOW.  
The LED (D6) is  
set as active  
HIGH.  
DS50002393A-page 18  
2015 Microchip Technology Inc.  
TABLE 3-1:  
Header  
GPIO/LED POL/LED CONFIGURATIONS (CONTINUED)  
Pin Settings  
Signal Name  
Strap Value  
Description  
J11 & J14  
1-2(default)  
LEDPOL4  
/GPIO4  
/LED4  
1
The LED (D7) is  
set as active  
LOW.  
2 -3  
1-2(default)  
2 -3  
0
1
0
The LED (D7) is  
set as active  
HIGH.  
J12 & J15  
LEDPOL5  
/GPIO5  
/LED5  
The LED (D8) is  
set as active  
LOW.  
The LED (D8) is  
set as active  
HIGH.  
3.1.1.2  
SERIAL MANAGEMENT MODE CONFIGURATION  
Serial Management Mode selection strap (MNGT0) is used to configure the default  
value of the Serial Management Mode Strap hard-strap (serial_mngt_mode_strap)  
through jumpers as shown below in Table 3-2.  
TABLE 3-2:  
Header  
SERIAL MANAGEMENT MODE CONFIGURATION  
serial_mngt_mode_  
Pin Settings  
strap  
Description  
J4 & J7  
J4 & J7  
2-3  
0
1
SMI Managed Mode  
I2C Managed Mode  
1-2 (default)  
3.1.1.3  
EEPROM SIZE CONFIGURATION:  
The EEPROM size configuration strap (J6 & J9) determines the supported EEPROM  
size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high  
selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512 as  
shown below in Table 3-3.  
TABLE 3-3:  
Header  
J6 & J9  
EEPROM SIZE CONFIGURATION  
eeprom_size_strap  
Pin Settings  
Description  
Value  
1-2 (default)  
1
EEPROM size = 32K  
bits (4k x 8) through  
512K bits (64K x 8)  
2 -3  
0
EEPROM size = 1K  
bits (128 x 8) through  
16K bits (2K x 8)  
3.1.1.4  
ENERGY-EFFICIENT ETHERNET CONFIGURATION  
EEE_EN configuration strap is used to configure the default value of the EEE Enable  
2-1 soft-straps (EEE_enable_strap_[2:1]) through jumpers as shown below in  
Table 3-4.  
Note: “EEE_enable_strap_1” strap is used for the LAN9353 when in Port 1 inter-  
nal PHY mode.  
2015 Microchip Technology Inc.  
DS50002393A-page 19  
EVB-LAN9353 Evaluation Board User’s Guide  
TABLE 3-4:  
Header  
J10 & J13  
EEE_EN CONFIGURATION  
EEE_enable_strap_[  
Pin Settings  
Description  
2:1] Value  
1-2(default)  
2 -3  
1
0
EEE Enable  
EEE Disable  
3.1.1.5  
1588 ENABLE CONFIGURATION  
Energy Efficient Ethernet configuration strap is used to configure the default value of  
the 1588 Enable soft-strap (1588_enable_strap) through jumpers as shown below in  
Table 3-5.  
TABLE 3-5:  
Header  
J11 & J14  
1588 ENABLE CONFIGURATION  
1588_enable_strap  
Pin Settings  
Description  
Value  
1-2 (default)  
2 -3  
1
0
1588 Enable  
1588 Disable  
3.1.1.6  
PHY ADDRESS CONFIGURATION  
PHY Address selection strap is used to configure the default value of the Switch PHY  
Address Select soft-strap (phy_addr_sel_strap) through jumpers as shown below in  
Table 3-6.  
TABLE 3-6:  
PHY ADDRESSING  
VIRTUAL  
PHY 0 AND 1  
DEFAULT  
ADDRESS  
VALUE  
PHY A  
DEFAULT  
ADDRESS  
VALUE  
PHY B  
DEFAULT  
ADDRESS  
VALUE  
Pin  
Settings  
PHY_ADDR_SEL  
_STRAP Value  
Header  
J12 & J15  
1-2  
1
0
1
0
2
1
3
2
2-3 (default)  
3.1.2  
GPIO 6 & GPIO 7 Input and Output Configurations  
GPIO 6 & 7 configuration straps are used to configure the default input value of the  
GPIO 6 and 7 through jumpers as shown below in Table 3-7 and Table 3-8.  
TABLE 3-7:  
Header  
GPIO 6 & 7 INPUT CONFIGURATION  
Pin Settings  
Input  
Signal Name  
GPIO6  
J20  
1-2  
2-3  
1-2  
2-3  
1
0
1
0
J21  
GPIO7  
TABLE 3-8:  
GPIO 6 & 7 OUTPUT CONFIGURATION  
Header  
Pin  
Output  
Signal Name  
J20  
J21  
2
2
Push Pull  
Push Pull  
GPIO6  
GPIO7  
Note: By default, the jumpers settings for J20 & J21 will be OPEN.  
DS50002393A-page 20  
2015 Microchip Technology Inc.  
3.1.3  
Jumper Settings for CONFIG 9 or CONFIG 10  
CONFIG 9: Used to configure the LAN9353 in Dual RMII mode by using jumpers as  
shown below in Table 3-9.  
Port 0: RMII PHY, RMII MAC modes  
Port 1: RMII MAC, RMII PHY modes  
Port 2: Internal PHY  
CONFIG 10: Used to configure the LAN9353 in Single MII/RMII/TMII mode by using  
jumpers as shown below in Table 8  
Port 0: MII MAC, MII PHY, RMII PHY, RMII MAC, TMII MAC, TMII PHY modes  
Port 1: Internal PHY  
Port 2: Internal PHY  
TABLE 3-9:  
CONFIG 9 OR CONFIG 10 SETTINGS  
SW11 SW12 SW13 SW14 SW15 SW16 SW17 SW18  
Mode  
1-3 2 RMII  
Configurations  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
CONFIG 9  
1-2 1xMII/RMII/T CONFIG 10  
MII  
(DEFAULT)  
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.  
3.1.4  
Link Partner Duplex/Speed Configurations  
CONFIG 9 or CONFIG 10 must be configured before Link partner Duplex/Speed con-  
figurations. For a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section  
3.1.3.  
The “duplex_strap_0” strap from J28 is used to determine the link partners duplex abil-  
ity when in Port 0 MII MAC and RMII MAC modes as shown below in Table 3-10.  
The “speed_strap_0” strap from J29 is used to determine the link partners speed ability  
and to determine the parallel detect speed when in Port 0 “MII MAC and RMII MAC”  
modes as shown below in Table 3-10.  
TABLE 3-10: EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY  
FOR PORT 0  
ADVERTISED  
J28  
(P0_DUPLEX)  
J29 (P0_SPEED) duplex_strap_0 speed_strap_0 LINK PARTNER  
ABILITY  
1-2  
1-2  
2-3  
2-3  
2-3  
1-2  
2-3  
1-2  
1
1
0
0
0
1
0
1
10BASE-T  
full-duplex  
(0010)  
100BASE-X  
full-duplex  
(1000)  
10BASE-T  
half-duplex  
(0001)  
100BASE-X  
half-duplex  
(0100)  
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.  
2015 Microchip Technology Inc.  
DS50002393A-page 21  
EVB-LAN9353 Evaluation Board User’s Guide  
The “duplex_strap_1” strap from J30 is used to determine the link partners duplex abil-  
ity when in Port 1 RMII MAC mode as shown below in Table 10.  
The “speed_strap_1” strap from J31 is used to determine the link partners speed ability  
and to determine the parallel detect speed when in Port 1 “RMII MAC” mode as shown  
below in Table 3-11.  
TABLE 3-11: EMULATED LINK PARTNER DEFAULT ADVERTISED ABILITY  
FOR PORT 1  
ADVERTISED  
J30  
(P1_DUPLEX)  
J31 (P1_SPEED) duplex_strap_1 speed_strap_1 LINK PARTNER  
ABILITY  
1-2  
1-2  
2-3  
2-3  
2-3  
1-2  
2-3  
1-2  
1
1
0
0
0
1
0
1
10BASE-T  
full-duplex  
(0010)  
100BASE-X  
full-duplex  
(1000)  
10BASE-T  
half-duplex  
(0001)  
100BASE-X  
half-duplex  
(0100)  
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.  
3.1.5  
Port 0/Port 1 Mode Configurations  
CONFIG 9 or CONFIG 10 must be configured before P0/P1 mode configurations. For  
a detailed jumper settings for CONFIG 9 or CONFIG 10 refer to section 3.1.3  
P0 Mode configuration straps (SW5, SW6, SW7 & SW8) are used to configure the  
hard-straps such as Switch Port 0 Mode Strap (P0_mode_strap[1:0]), Switch Port 0  
RMII Clock Direction Strap (P0_rmii_clock_dir_strap) and Switch Port 0 Clock Strength  
Strap (P0_clock_strength_strap) as shown below in Table 3-12.  
TABLE 3-12: PORT 0 MODE STRAP MAPPING  
P1_  
INTPHY  
(J5 & J8)  
P0_MODE3 P0_MODE2 P0_MODE1 P0_MODE0  
MODE  
(SW8)  
(SW9)  
(SW7)  
(SW5)  
1-2  
1-2  
1-2  
1-2  
2-3  
1-2  
2-3  
1-2  
2-3  
1-2  
2-3  
1-2  
1-3  
1-3  
1-3  
1-3  
X
1-3  
1-2  
1-2  
1-2  
1-3  
X
X
X
MII MAC  
MII PHY  
1-3  
1-2  
1-2  
1-3  
1-3  
1-2  
X
Turbo MII PHY 12 ma  
Turbo MII PHY 16 ma  
RMII MAC clock in  
(default)  
1-2  
X
1-3  
1-3  
1-2  
1-2  
1-2  
1-3  
1-3  
1-2  
X
RMII MAC clock out  
12ma  
1-2  
X
RMII MAC clock out  
16ma  
1-2  
X
RMII PHY clock in  
1-2  
DS50002393A-page 22  
2015 Microchip Technology Inc.  
TABLE 3-12: PORT 0 MODE STRAP MAPPING (CONTINUED)  
P1_  
INTPHY  
(J5 & J8)  
P0_MODE3 P0_MODE2 P0_MODE1 P0_MODE0  
MODE  
(SW8)  
(SW9)  
(SW7)  
(SW5)  
2-3  
1-2  
2-3  
1-2  
X
1-2  
X
1-2  
1-2  
1-3  
RMII PHY clock out 12ma  
RMII PHY clock out 16ma  
1-2  
1-2  
1-2  
1-2  
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.  
Note: SW8 will be used for Port 0 when LAN9353 is configured in Single  
MII/TMII/RMII Mode and SW8 will be ignored when LAN9353 is in Dual  
RMII mode.  
P1 Mode configuration straps (SW10, SW8, SW6 & J5/J8) are used to configure the  
hard-straps such as Switch Port 1 Mode Strap (P1_mode_strap[1:0]), Switch Port 1  
RMII Clock Direction Strap (P1_rmii_clock_dir_strap) and Switch Port 1 Clock Strength  
Strap (P1_clock_strength_strap) as shown below in Table 3-13.  
TABLE 3-13: PORT 1 MODE STRAP MAPPING  
P1_INTPHY  
(J5 & J8)  
P1_MODE2  
(SW10)  
P1_MODE1  
(SW8)  
P1_MODE0  
(SW6)  
MODE  
2-3  
2-3  
2-3  
1-3  
1-3  
1-3  
1-3  
1-2  
1-2  
X
RMII MAC clock in  
(default)  
1-3  
1-2  
RMII MAC clock out  
12ma  
RMII MAC clock out  
16ma  
2-3  
2-3  
2-3  
1-2  
1-2  
1-2  
1-2  
X
1-3  
1-2  
1-2  
X
X
1-3  
1-2  
X
RMII PHY clock in  
RMII PHY clock out 12ma  
RMII PHY clock out 16ma  
Internal PHY  
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.  
Note: SW8 will be used for Port 1 when LAN9353 is configured in Dual RMII Mode  
and SW8 will be ignored when LAN9353 is in Single MII/TMII/RMII mode.  
2015 Microchip Technology Inc.  
DS50002393A-page 23  
EVB-LAN9353 Evaluation Board User’s Guide  
3.1.6  
RMII RX Clock Configurations  
When LAN9353 is in MAC/PHY mode the reference clock routed either through TX or  
RX Clock as shown in Table 3-14 for Port 0 and Table 3-15 for Port 1.  
TABLE 3-14: RX CLOCK CONFIGURATIONS FOR PORT 0  
Switch Settings  
DESCRIPTION  
Mode  
SW23 (1-3) (Default)  
TX Clock used as a Refer-  
ence Clock  
RMII MAC  
RMII MAC  
SW23 (1-2)  
RX Clock used as a Refer-  
ence Clock  
SW24 (1-3) (Default)  
SW24 (1-2)  
Reference clock used as a TX RMII PHY  
clock  
Reference clock used as a RX RMII PHY  
clock  
Note: When Port 0 configured in RMII mode, short Jumper J25 (1-2).  
TABLE 3-15: RMII RX CLOCK CONFIGURATIONS FOR PORT 1  
Switch Settings  
DESCRIPTION  
Mode  
SW25 (1-3) (Default)  
TX Clock used as a Refer-  
ence Clock  
RMII MAC  
RMII MAC  
SW25 (1-2)  
RX Clock used as a Refer-  
ence Clock  
SW26 (1-3) (Default)  
SW26 (1-2)  
Reference clock used as a TX RMII PHY  
clock  
Reference clock used as a RX RMII PHY  
clock  
Note: External PHY considered LAN8742.  
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa.  
3.1.7  
GPIO Header  
J27 header is used for GPIO. Pin details are given below in Table 3-16.  
TABLE 3-16: PIN NAMES FOR GPIO HEADER  
Signal Name  
Pin Number  
GPIO0  
GPIO1  
GPIO2  
GPIO3  
GPIO4  
GPIO5  
GPIO6  
GPIO7  
J27.1  
J27.2  
J27.3  
J27.4  
J27.5  
J27.6  
J27.7  
J27.8  
DS50002393A-page 24  
2015 Microchip Technology Inc.  
3.1.8  
I2C Aardvark® Header  
J16 connector is used for I2C Aardvark header. Respective pin details are given below  
in Table 3-17.  
TABLE 3-17: PIN NAMES FOR I2C AARDVARK HEADER  
Signal Name  
Pin Number  
I2C2_SCL  
I2C2_SDA  
GND  
J16.1  
J16.3  
J16.2 & J16.10  
3.1.9  
Copper and Fiber Mode Selections  
The LAN9353 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In  
100BASE-FX operation, the presence of the receive signal is indicated by the external  
transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL  
Signal Detect (SFF).  
This EVB supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) in SFP mode. By  
default Copper Mode is active. Fiber Mode is supported as an assembly option. To  
select the Copper or Fiber Mode, the respective strap and signal routing resister  
assembly options must to be configured.  
Note: Vendor part number for SFP Transceiver: Finisar/FTLF1217P2.  
3.1.9.1  
COPPER MODE  
The EVB-LAN9353 is set to Copper Mode by default. Table 3-18 details the required  
strap resistors settings for Copper Mode operation.  
TABLE 3-18: COPPER MODE STRAP RESISTORS  
Resistors  
R79 (10K)  
Signal Names  
Description  
FXLOSEN  
Copper twisted pair for ports A and B further determined  
by FXSDENA and FXSDENB  
R76, R80 (10K) FXSDA/FXSDB Configures Port 0 and Port 1 to Copper Mode  
Note: R75, R77, and R78 must not be populated (DNP).  
Additionally, the signal routing resistors detailed in Table 3-19 must be assembled for  
Copper Mode operation.  
TABLE 3-19: COPPER MODE SIGNAL ROUTING RESISTORS  
Resistors  
R17, R19, R21, R23  
R31, R33, R35, R37  
Description  
Port 0 Copper mode is Enabled  
Port 1 Copper mode is Enabled  
Note: R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be  
populated (DNP).  
3.1.9.2  
FIBER MODE  
The LAN9353 supports SFP type 100BASE-FX mode. To enable Fiber Mode, the  
respective strap and signal routing resisters must be configured.  
Note: Copper Mode related resistors must be DNP while Fiber Mode is active  
(See Section 3.1.9.1 “Copper Mode”).  
2015 Microchip Technology Inc.  
DS50002393A-page 25  
EVB-LAN9353 Evaluation Board User’s Guide  
Table 3-20 details the required strap resistor settings for Fiber Mode operation.  
TABLE 3-20: FIBER MODE STRAP RESISTORS  
Resistors  
Description  
R77 (10K)  
Configures Port 0 & 1 to FX_LOS Mode  
R75, R78 (10K)  
Configures Port 0 & 1 to Fiber mode, respectively  
Note: R76, R79, and R80 must not be populated (DNP).  
Additionally, the signal routing resistors detailed in Table 3-21 must be assembled for  
Fiber Mode operation.  
TABLE 3-21: FIBER MODE SIGNAL ROUTING RESISTORS  
Resistors  
R16, R18, R20, R22  
R30, R32, R34, R36  
Description  
Port 0 Fiber mode Enabled  
Port 1 Fiber mode Enabled  
Note: R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be  
populated (DNP).  
3.1.9.3  
FX-LOS FIBER MODE STRAP  
FX-LOS strap details are shown in Table 3-22. These strap settings determine if the  
ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.  
TABLE 3-22: FX-LOS MODE STRAP SETTINGS  
Reference  
R77 (10K) R79 (10K)  
Function  
Voltage (v)  
Populate DNP  
3.3  
A level above 2V selects FX-LOS for Port 0 and Port 1  
Populate Populate 1.5  
A level of 1.5V selects FX-LOS for Port 0 and FX-SD /  
Copper twisted pair for Port 1, further determined by  
FXSDB  
DNP  
Populate 0 (Default) A level of 0V selects FX-SD / Copper twisted pair for  
Ports 0 and 1, further determined by FXSDA, FXSDB  
Note: The above strap details describe the LAN9353 function. This EVB does not  
support SFF Fiber Mode. Therefore, FX-SD related straps are not applica-  
ble.  
3.2  
LEDS  
Table 3-23 describes the different LED references and their corresponding colors and  
indications  
TABLE 3-23: LEDS  
Reference  
Color  
Indication  
3.3V Power active  
D1  
D2  
D4  
D7  
Green  
Red  
LAN9353 is in reset condition  
Full-duplex / Collision Port 1  
Full-duplex / Collision Port 2  
Green  
Green  
Note: Assumes the LED_FUN field of the LED_CFG register is 00b.  
DS50002393A-page 26  
2015 Microchip Technology Inc.  
3.3  
TEST POINTS  
Table 3-24 describes the different test points and their corresponding connections.  
TABLE 3-24: TEST POINTS  
Test Points  
Description  
Connection  
5V_EXT  
TP1  
TP2  
TP3  
TP4  
TP5  
TP6  
TP7  
TP8  
TP9  
TP10  
Single pin populated 5V  
Single pin populated 3V3  
3V3  
Single pin unpopulated VDDCR  
Single pin unpopulated IRQ  
VDDCR  
IRQ  
Single pin unpopulated P0_MDC  
Single pin unpopulated P0_MDIO  
Single pin unpopulated P1_MDC  
Single pin unpopulated P1_MDIO  
Single pin populated GND  
P0_MDC  
P0_MDIO  
P1_MDC  
P1_MDIO  
GND  
Single pin populated GND  
GND  
3.4  
MECHANICALS  
Figure 3-2 displays details for EVB-LAN9353 mechanical dimensions. Dimension are  
in mm.  
FIGURE 3-2:  
LAN9353 EVB MECHANICAL DIMENSIONS  
2015 Microchip Technology Inc.  
DS50002393A-page 27  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Appendix A. EVB-LAN9353 Evaluation Board  
A.1 INTRODUCTION  
This appendix shows the EVB-LAN9353 Evaluation Board.  
FIGURE A-1: EVB-LAN9353 EVALUATION BOARD  
2015 Microchip Technology Inc.  
DS50002393A-page 28  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Appendix B. EVB-LAN9353 Evaluation Board Schematics  
B.1 INTRODUCTION  
This appendix shows the EVB-LAN9353 Evaluation Board Schematics.  
2015 Microchip Technology Inc.  
DS50002393A-page 29  
FIGURE B-1:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 1  
EVB-LAN9353 Block Diagram (Config 10)  
EVB-LAN9353 Block Diagram (Config 9)  
40 Pin MII  
Connector  
(Female)  
40 Pin MII  
Connector  
(Male)  
40 Pin MII  
Connector  
(Female)  
40 Pin MII  
Connector  
(Male)  
40 Pin MII  
Connector  
(Male)  
40 Pin MII  
Connector  
(Female)  
MII/RMII/TMII  
RMII  
RMII  
Port 0  
Power  
Supply  
Module  
Port 1  
Port 0  
Power  
Supply  
Module  
Mode  
Switch  
Mode  
Switch  
I2C  
EEPROM/  
Header  
I2C  
EEPROM/  
Header  
Reset  
Switch  
Reset  
Switch  
Microchip  
LAN9353  
Microchip  
LAN9353  
Straps  
Jumpers  
Straps  
Jumpers  
Crystal  
Crystal  
Port 1  
Port 2  
Port 2  
Fiber  
Trasnceiver-  
(SFP) Port 1  
10/100  
10/100  
Fiber  
Trasnceiver-  
(SFP) Port 2  
10/100  
Fiber  
Trasnceiver-  
(SFP) Port 2  
Ethernet  
Magnetics &  
RJ45  
Ethernet  
Magnetics &  
RJ45  
Ethernet  
Magnetics &  
RJ45  
FIGURE B-2:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 2  
POWER SUPPLY  
TP1  
RED  
TP2  
ORANGE  
3 .3V REGULATOR, 3A  
( 3V3 fixed when Rb=503e)  
3V3  
5V  
3V3  
SW1  
U1  
1
3
2
5V_EXT  
1
3
FB1  
R2  
1K  
2
5V_SW  
2
1
4
5
VOUT_3V3  
R4  
R4A  
VIN VOUT  
ENABLE TRIM  
R1  
0
EN12_1  
C3  
2A/0.05DCR  
C1  
3
Switch, SPDT, Slide  
P/N:1101M2S3CQE2  
R3  
3.30K  
1%  
GND  
C2  
10uF  
25V  
3_Amp  
470E  
1%  
C4  
C5  
4.7uF  
DNP  
33E  
1%  
J1  
D1  
GRN  
QEꢀꢁꢁ!6C  
0.1uF  
10uF  
0.1uF  
OKR-T/3-W12-C  
(Ra) (Rb)  
3V3  
3V3  
3V3  
C6  
R5  
4.75K  
1%  
R6  
0.1uF  
10.0K  
1/10W  
1%  
U2  
SW2  
3V3  
NDS355AN_NMOS  
1
R7  
100  
2
4
1
3
D
S
RST#  
MR#  
RESET#  
RESET  
1/10W  
1%  
Q1  
sw_pb_2P  
R8  
1K  
1
RED  
G
U3  
2
4
R9  
2.2K  
1
2
A
C
TPS3125  
74LVC1G14  
D2  
SOT23_5  
Threshold = 2.64V  
Delay = 180ms  
"Reset"  
Reset Generator  
TP9  
BLACK  
TP10  
BLACK  
FIGURE B-3:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 3  
Power Supply Filtering  
3V3  
VDD33TXRX1  
3V3  
FB2  
2A/0.05DCR  
VDDCR  
VDD12TX1  
VDD12TX2  
C7  
1.0uF  
DNP  
C8  
0.1uF  
VDD33TXRX2  
FB3  
2A/0.05DCR  
3V3  
TP3  
SMT  
3V3  
3V3  
VDDCR  
FB4  
2A/0.05DCR  
C23  
1.0uF  
DNP  
C24  
0.1uF  
BLM18EG221SN1D  
C25  
FB5  
2A/0.05DCR  
U4A  
Note:  
OSCVSS need to connect to Chip gnd.  
C26  
18pF  
3
25.000MHz  
25ppm  
OSCVDD12  
OSCI  
OSCO  
Y1  
OSCI  
OSCO  
1
2
4
9
FXSDA/FXLOSA  
FXSDENA/FXSDA/FXLOSA  
3V3  
OSCVSS  
C27  
18pF  
REG_EN  
RBIAS  
7
57  
11  
44  
8
52  
53  
54  
55  
TXNA  
TXPA  
RXNA  
RXPA  
REG_EN  
RBIAS  
TXNA  
TXPA  
RXNA  
RXPA  
R10  
12.1K  
1%  
RST#  
IRQ  
RST#  
TP4  
WHITE  
DNP  
IRQ  
ATEST/FXLOSEN  
ATEST/FXLOSEN  
TESTMODE  
41  
63  
62  
61  
60  
TXNB  
TXPB  
RXNB  
RXPB  
TXNB  
TXPB  
RXNB  
RXPB  
43  
42  
I2C2_SCL  
I2C2_SDA  
I2CSCL/EESCL/TCK  
I2CSDA/EESDA/TMS  
10  
FXSDB/FXLOSB  
FXSDENB/FXSDB/FXLOSB  
48  
46  
45  
34  
18  
17  
13  
12  
GPIO0  
GPIO1  
GPIO2  
GPIO3  
GPIO4  
GPIO5  
GPIO6  
GPIO7  
GPIO0/LED0/TDO/LEDPOL0/MNGT0  
GPIO1/LED1/TDI/LEDPOL1/P1_INTPHY  
GPIO2/LED2/LEDPOL2/E2PSIZE  
GPIO3/LED3/LEDPOL3/EEEEN  
GPIO4/LED4/LEDPOL4/1588EN  
GPIO5/LED5/LEDPOL5/PHYADD  
GPIO6  
GPIO7  
LAN9353  
FIGURE B-4:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 4  
R61  
330E  
GDIFꢂ68U  
LED2_ANODE  
LED2_CATHODE  
VDD33TXRX1  
FB6  
0E  
T1  
Pulse J0011D01BNL  
QPSU  
R11  
R12  
R13  
R14  
R15  
0
49.9  
1/10W  
1%  
49.9  
1/10W  
1%  
49.9  
1/10W  
1%  
49.9  
1/10W  
1%  
GRN  
75  
RJ45  
1
DNP  
R16  
R17  
0
0
XMIT  
TXPA  
FX_SFP-TXPA  
FX_SFP-TXNA  
COP-TXPA  
1
4
2
TD+  
TXCT  
TD-  
75  
DNP  
R18  
R19  
4 & 5  
2
0
0
TXNA  
COP-TXNA  
9rshˆy‡ꢃh††r€iy’  
LED1 (Green)  
= LINK/ACT  
DNP  
R20  
R21  
0
0
LED2 (Yellow) = SPEED  
RCV  
RXPA  
FX_SFP-RXPA  
FX_SFP-RXNA  
COP-RXPA  
COP-RXNA  
3
5
6
RD+  
RXCT  
RD-  
3
DNP  
R22  
R23  
75  
75  
0
0
7 & 8  
6
RXNA  
C32  
0.022uF  
7
8
1000 pF  
2 kV  
YEL  
C28  
C29  
C30  
C31  
10pF  
50V  
5%  
NC  
10pF  
50V  
5%  
10pF  
50V  
5%  
10pF  
50V  
5%  
50V  
10%  
CHS GND  
DNP  
DNP  
DNP  
DNP  
Note:  
Capacitors C10 through C13 are optional for EMI purposes  
and are not populated on the LAN8740/41 evaluation board.  
These capacitors are required for operation in an EMI  
constrained environment.  
R62  
330E  
LED0_CATHODE  
LED0_ANODE  
R24  
0
RES1210  
TQ@@9  
R102  
330E  
GDIFꢂ68U  
VDD33TXRX2  
LED5_ANODE  
LED5_CATHODE  
FB7  
0E  
QPSU!  
T2  
Pulse J0011D01BNL  
R25  
49.9  
1/10W  
1%  
R26  
R27  
R28  
R29  
0
49.9  
1/10W  
1%  
49.9  
1/10W  
1%  
49.9  
1/10W  
1%  
GRN  
75  
RJ45  
1
DNP  
R30  
R31  
0
0
XMIT  
TXPB  
FX_SFP-TXPB  
FX_SFP-TXNB  
COP-TXPB  
1
4
2
TD+  
TXCT  
TD-  
75  
DNP  
R32  
R33  
4 & 5  
2
0
0
TXNB  
COP-TXNB  
LED1 (Green)  
=
LINK/ACT  
DNP  
R34  
R35  
0
0
RCV  
LED2 (Yellow) = SPEED  
RXPB  
FX_SFP-RXPB  
FX_SFP-RXNB  
COP-RXPB  
COP-RXNB  
3
5
6
RD+  
RXCT  
RD-  
3
DNP  
R36  
R37  
75  
75  
0
0
7 & 8  
6
RXNB  
C37  
0.022uF  
7
8
1000 pF  
2 kV  
YEL  
C33  
C34  
C35  
C36  
10pF  
50V  
5%  
NC  
10pF  
50V  
5%  
10pF  
50V  
5%  
10pF  
50V  
5%  
50V  
10%  
CHS GND  
DNP  
DNP  
DNP  
DNP  
I‚‡r)ꢃA7%ꢃhqꢃA7&ꢃ‡‚ꢃirꢃ“rꢄ‚ꢃ‚u€†ꢃ  
Note:  
Capacitors C10 through C13 are optional for EMI purposes  
and are not populated on the LAN8740/41 evaluation board.  
These capacitors are required for operation in an EMI  
constrained environment.  
R103  
330E  
LED3_CATHODE  
LED3_ANODE  
R38  
0
TQ@@9  
RES1210  
FIGURE B-5:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 5  
3V3  
3V3  
Note:Place  
capacitors,  
and resistors  
close to FOT  
Note:Place  
capacitors,  
and resistors  
close to FOT  
Fiber Port 2 :SFP Interface  
Fiber Port 1 :SFP Interface  
R39  
82  
R40  
82  
R41  
49.9  
R42  
49.9  
R43  
82  
R44  
82  
R45  
49.9  
R46  
49.9  
Assemble 0E at C38,C40,C42,C44  
Assemble 0E at C39,C41,C43,C45  
C38  
0.1uF  
0.1uF  
C39  
0.1uF  
0.1uF  
FX_SFP-RXNA  
FX_SFP-RXPA  
FX_SFP-RXNB  
FX_SFP-RXPB  
C40  
C41  
C42  
FX_SFP-TXPA  
C43  
C45  
0.1uF  
0.1uF  
FX_SFP-TXPB  
FX_SFP-TXNB  
3V3  
3V3  
R47  
100  
DNP  
R48  
100  
DNP  
SFP_VCCT  
SFP_VCCT2  
SFP_VCCR2  
L1  
1uH  
C44  
L2  
1uH  
SFP_VCCR  
0.1uF  
FX_SFP-TXNA  
0.1uF  
+
+
C50  
10uF  
16V  
C51  
0.1uF  
C52  
10uF  
16V  
C53  
0.1uF  
C49  
+
+
C46  
10uF  
16V  
C47  
0.1uF  
C48  
10uF  
16V  
DNP  
R49  
130  
R50  
130  
0.1uF  
DNP  
R51  
130  
R52  
130  
L3  
1uH  
L4  
1uH  
+
C56  
31 10uF  
C57  
0.1uF  
+
C54  
10uF  
16V  
C55  
0.1uF  
31  
31  
30  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
30 16V  
29  
28  
27  
26  
25  
24  
23  
22  
Note:Place  
resistors  
close to  
ASIC  
Note:Place  
resistors  
close to  
ASIC  
30  
29  
29  
28  
28  
27  
27  
26  
26  
25  
25  
24  
J3  
24  
23  
J2  
23  
22  
FTLF1217P2  
FTLF1217P2  
21  
22  
21  
21  
SFP_VCCT2  
SFP_VCCT  
R56  
4.7K  
R57  
4.7K  
R58  
4.7K  
R59  
4.7K  
R60  
4.7K  
R53  
4.7K  
R54  
4.7K  
R55  
4.7K  
FXSDA/FXLOSA  
FXSDB/FXLOSB  
Note: Fiber mode related components are Not Populated on EVB (Default)  
FIGURE B-6:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 6  
GPIO [0:5] & LED_POL_Strap  
3V3  
3V3  
I2C EEPROM  
C58  
3V3  
3V3  
3V3  
3V3  
3V3  
3V3  
GPIO0  
GPIO2  
GPIO1  
GPIO4  
GPIO3  
GPIO5  
U5  
0.1uF  
J4  
J6  
J5  
J11  
J10  
J12  
R66  
4.7K  
1
2
3
5
6
I2C2_SDA  
I2C2_SCL  
A0  
A1  
A2  
SDA  
LED0_ANODE  
LED2_ANODE  
LED1_ANODE  
LED4_ANODE  
LED3_ANODE  
LED5_ANODE  
R69  
10.0K  
R70  
10.0K  
R71  
10.0K  
R81  
10.0K  
R82  
10.0K  
R83  
10.0K  
SCL  
7
LED0_CATHODE  
LED2_CATHODE  
LED1_CATHODE  
LED4_CATHODE  
LED3_CATHODE  
LED5_CATHODE  
WP  
Note: U5: IC DIP Socket. Different sizes can be mounted  
I2C EEPROM Lower size Below 16K(2K X 8)  
24FC512-I/P  
R72  
0E  
R73  
0E  
R74  
1K  
R84  
1K  
R85  
0E  
R86  
0E  
I2C EEPROM Higher size  
Above 16K(2K X 8)  
[Default-512KBIT]  
J7  
J9  
J14  
J13  
J15  
J8  
GPIO0  
GPIO2  
GPIO1  
GPIO4  
GPIO3  
GPIO5  
FX_Mode_Strap_1 & 2  
3V3  
Aardvark - I2C Connector  
R75  
R76  
DNP 10K  
10K  
Port 2 LEDs  
SPEED  
Port 1 LEDs  
QPSU  
HP9@  
ꢃ8‚ƒƒrꢄ  
ꢆ9rshˆy‡ꢇ  
Q‚ˆƒˆyh‡r  
S&%  
FXSDA/FXLOSA  
DNP  
D6  
GRN  
DNP  
D3  
GRN  
J16  
SPEED  
LED3_ANODE  
1
2
LED3_ANODE  
LED0_ANODE  
1
2
LED0_ANODE  
A
C
I2C2_SCL  
I2C2_SDA  
1
3
5
7
9
2
4
6
8
10  
A
C
LED3_CATHODE  
QPSU  
LED3_CATHODE  
LED0_CATHODE  
LED0_CATHODE  
Avirꢄ  
S&$  
S'ꢁ  
S&'  
3V3  
FULL DUPLEX / Collision  
D7  
FULL DUPLEX / Collision  
1
LED4_ANODE  
1
2
R78  
R80  
DNP 10K  
10K  
ꢃ8‚ƒƒrꢄ  
ꢆ9rshˆy‡ꢇ  
LED1_ANODE  
D4  
GRN  
2
GRN  
A
C
A
C
LED4_CATHODE  
QPSU!  
FXSDB/FXLOSB  
LED1_CATHODE  
HEADER 5X2  
Avirꢄ  
DNP  
D8  
GRN  
LINK/ACT  
DNP  
D5  
1
GRN  
LINK/ACT  
LED5_ANODE  
1
2
LED5_ANODE  
LED2_ANODE  
2
LED2_ANODE  
A
C
A
C
LED5_CATHODE  
LED5_CATHODE  
LED2_CATHODE  
3V3  
LED2_CATHODE  
1
3
GPIO6  
R99  
2
Strap Name  
Logic  
0
Connector  
LED Polarity Strap  
10K  
FX_Los_Strap_1 & 2  
J4,J7 (2&3)  
The LED is set as active high.  
The LED is set as active low,  
The LED is set as active high.  
J20  
LED0/GPIO0/MNGT0  
LED1/GPIO1  
3V3  
J4,J7 (1&2)  
(Default)  
1
0
1
0
1
0
1
0
1
0
S&&  
S&(  
SrsꢅW‚y‡htr  
"W"  
Aˆp‡v‚  
3V3  
Q‚ˆƒˆyh‡r  
9IQ  
6i‚‰rꢃ!ꢃWꢃ†ryrp‡†ꢃAYꢀGPTꢃs‚ꢄꢃƒ‚ꢄ‡†ꢃ ꢃhqꢃ!  
J5,J8 (2&3)  
1
3
R77  
10K  
DNP  
Gr‰ryꢃ‚sꢃ ꢅ$ꢃWꢃ†ryrp‡†ꢃAYꢀGPTꢃs‚ꢄꢃƒ‚ꢄ‡ꢃ ꢃhq  
AYꢀT9ꢂp‚ƒƒrꢄꢃ‡v†‡rqꢃƒhvꢄꢃs‚ꢄꢃƒ‚ꢄ‡ꢃ!  
sˆꢄ‡urꢄꢃqr‡rꢄ€vrqꢃi’ꢃAYT97  
J5,J8 (1&2)  
(Default)  
GPIO7  
R100  
2
The LED is set as active low,  
The LED is set as active high.  
EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)  
10K  
Q‚ˆƒˆyh‡r Q‚ˆƒˆyh‡r  
 W$  
J6,J9 (2&3)  
J21  
ATEST/FXLOSEN  
LED2/GPIO2/E2PSIZE  
Gr‰ryꢃ‚sꢃꢁWꢃTryrp‡†ꢃAYꢀT9ꢃꢂꢃp‚ƒƒrꢄꢃ‡v†‡rqꢃƒhvꢄꢃ  
s‚ꢄꢃƒ‚ꢄ‡†ꢃ6ꢃhqꢃ7  
sˆꢄ‡urꢄꢃqr‡rꢄ€vrqꢃi’ꢃAYT96ꢃhqꢃAYT97ꢅ  
J6,J9 (1&2)  
(Default)  
The LED is set as active low,  
EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)  
ꢃꢃ9IQ  
Q‚ˆƒˆyh‡r  
ꢃꢃꢃꢃꢃꢁ  
R79  
10K  
ꢆ9rshˆy‡ꢇ ꢆ9rshˆy‡ꢇ  
ꢆ9rshˆy‡ꢇ  
The LED is set as active high.  
EEE Disable  
J10,J13 (2&3)  
LED3/GPIO3/EEEEN  
LED4/GPIO4/1588EN  
J10,J13 (1&2) The LED is set as active low,  
EEE Enable  
1
2
3
4
5
6
7
8
GPIO0  
GPIO1  
GPIO2  
GPIO3  
GPIO4  
GPIO5  
GPIO6  
GPIO7  
(Default)  
The LED is set as active high.  
1588 Disable  
J11,J14 (2&3)  
J11,J14 (1&2) The LED is set as active low,  
(Default) 1588 Enable  
J12,J15 (2&3) The LED is set as active high.  
PHYADD=0,1,2  
(Default)  
LED5/GPIO5/PHYADD  
J27  
HEADER 8  
The LED is set as active low,  
PHYADD =1,2,3  
J12,J15 (1&2)  
1
FIGURE B-7:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 7  
3V3  
3V3  
3V3  
3V3  
SW5  
2
1
P0_OUT/REF_CLK_MODE0  
R104  
10.0K  
SW6  
1
P1_REFCLK_MODE0/P0_INCLK  
2
3
P0_MODE0  
P0_MODE1  
P0_MODE2  
R105  
10.0K  
Config 10  
Port 0 : External (MII/RMII/TMII)  
Port 1 and Port 2 : Internal  
3
P1_MODE0  
JS102011CQN  
JS102011CQN  
3V3  
SW7  
2
3
ꢀQ`ꢎꢇ ꢇꢈꢉꢊꢋꢇꢐꢄꢏꢑꢀꢇꢈ:]]1J$  
ꢐꢆZꢏ)*ꢐꢑꢒꢂ7 ꢐꢇZꢎ,-ꢓꢌ ꢐꢇZꢎ,-ꢓꢊ ꢐꢇZꢎ,-ꢓꢆ ꢐꢇZꢎ,-ꢓꢇ  
P0_OUTD0_MODE1  
R106  
10.0K  
SW8  
1
P1_OUTD0_MODE1/P0_OUTD2_MODE3  
2
3
R107  
10.0K  
1
P0_MODE3  
P1_MODE1  
&
ꢈꢉꢊꢋ  
JS102011CQN  
JS102011CQN  
ꢀꢁꢂ:JRꢂꢀꢃ  
ꢄꢅꢃ  
ꢇ
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢇ
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢇ
ꢄꢅꢔ  
ꢄꢅꢕ  
6
)#  
ꢇ
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢆ
ꢄꢅꢁ  
6
)#  
6
)#  
ꢇ
ꢆ
ꢇ
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢆ
3V3  
ꢏꢏꢂꢎ#$  
ꢏ ꢏ ꢂꢐꢑꢒ  
SW9  
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
2
3
P0_OUTD1_MODE2  
R108  
10.0K  
SW10  
2
10.0K  
P1_OUTD1_MODE2/P0_OUTD3  
1
R109  
1
P1_MODE2  
3
JS102011CQN  
JS102011CQN  
*%`GQꢂꢎꢏꢏꢂꢐꢑꢒꢂꢆꢊꢂI:  
*%`GQꢂꢎꢏꢏꢂꢐꢑꢒꢂꢆꢈꢂI:  
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢇ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢆ
Note: For Switches to short 1-3, Knob Position should be at 1-2 and vice versa .  
Note: CONFIG9 or CONFIG 10 must be configured before P0/P1 mode configurations  
ꢄ.Q`ꢉꢂꢆꢋꢌ  
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢇ
ꢆ
6
ꢆ
ꢇ
ꢇ
6
ꢍ ꢏꢏꢂꢎ#$ꢂHCQH@ꢂ1J  
ꢍ ꢏꢏꢂꢎ#$ꢂHCQH@ꢂQ%ꢉꢂꢆꢊI:  
ꢍ ꢏꢏꢂꢎ#$ꢂHCQH@ꢂQ%ꢉꢂꢆꢈI:  
ꢍ ꢏꢏꢂꢐꢑꢒꢂHCQH@ꢂ1J  
ꢄ.Q`ꢉꢂꢊꢋꢌ  
ꢇ
ꢆ
ꢄ.Q`ꢉꢂꢊꢋꢌ  
ꢇ
ꢆ
ꢄ.Q`ꢉꢂꢊꢋꢌ  
ꢇ
ꢆ
ꢄ.Q`ꢉꢂꢊꢋꢌ  
ꢇ
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
6
ꢆ
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Config 9 :  
Port 0 and Port 1 : External (RMII) and  
Port 2 : Internal  
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ꢍꢎꢏꢏꢂꢐꢑꢒꢂHCQH@ꢂ1J  
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P1_REFCLK_MODE0/P0_INCLK  
P1_OUTD1_MODE2/P0_OUTD3  
P1_OUTD0_MODE1/P0_OUTD2_MODE3  
P0_OUTD1_MODE2  
P0_OUTD0_MODE1  
ꢄ.Q`ꢉꢂꢊꢋꢌ  
ꢆ
ꢄ.Q`ꢉꢂꢆꢋꢊ  
ꢄ.Q`ꢉꢂꢆꢋꢊ  
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6
6
6
ꢄ.Q`ꢉꢂꢆꢋꢊ  
Q]VJ  
Q]VJ  
Q]VJ  
P0_OUT/REF_CLK_MODE0  
FIGURE B-8:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 8  
8
Jumpers  
Config9(2RMII)  
Config10 1-2 Short (2-3  
SW11  
JS102011CQN  
1
=
2-3 Short (1-2  
- open)  
open) (Default)  
P0_INCLK  
P1_REFCLK_MODE0  
P0_IND3  
2
3
=
-
Jumper settings for CONFIG 9 or CONFIG 10  
SW12  
1
SW11 SW12 SW13 SW14 SW15 SW16 SW17 SW18  
Mode  
Configuration  
2
3
JS102011CQN  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
1-3  
1-2  
2 RMII  
CONFIG 9  
P1_IND1  
P0_IND2  
P1_IND0  
P0_INER  
P1_INDV  
SW13  
JS102011CQN  
1
1 MII/RMII/TMII  
(Default)  
CONFIG 10  
2
3
U4B  
LAN9353  
25  
R116  
33  
P0_OUT/REF_CLK_MODE0  
P0_REFCLK/P0_MODE0[P0_OUTCLK/P0_REFCLK/P0_MODE0]  
SW14  
2
P1_REFCLK_MODE0/P0_INCLK R117  
33  
33  
33  
29  
31  
30  
33  
Note: For Switches to short 1-3, Knob Position should be  
at 1-2 and vice versa .  
P1_REFCLK/P1_MODE0[P0_INCLK]  
P1_IND1[P0_IND3]  
P1_IND0[P0_IND2]  
JS102011CQN  
3
1
P1_IND1/P0_IND3  
P1_IND0/P0_IND2  
P1_INDV/P0_INER  
R144  
R145  
28 R122  
27 R123  
26  
33 P0_IND1  
33  
P0_IND1  
P0_IND0  
P0_INDV  
P0_IND0  
P0_INDV  
P1_INDV[P0_INER]  
R146  
P1_OUTD1_MODE2/P0_OUTD3  
P1_OUTD0_MODE1/P0_OUTD2_MODE3R147  
SW15  
33  
33  
2
15  
16  
35  
21 R124  
22 R125  
23  
33 P0_OUTD1_MODE2  
33 P0_OUTD0_MODE1  
P0_OUTDV  
P1_OUTD1/P1_MODE2[P0_OUTD3]  
P1_OUTD0/P1_MODE1[P0_OUTD2/P0_MODE3]  
P1_OUTDV[RESERVED]  
P0_OUTD1/P0_MODE2  
P0_OUTD0/P0_MODE1  
P0_OUTDV  
P0_OUTD3  
2
JS102011CQN  
1
P1_OUTDV  
1
P1_OUTD1_MODE2  
P0_OUTD2  
3
J22  
SW16  
2
P1_MDC_DUPLEX/P0_CRS  
P1_MDIO_SPEED/P0_COL  
49  
50  
36  
19  
P0_DUPLEX  
P0_OUTER_SPEED  
P1_DUPLEX/P1_MDC[P0_CRS]  
P1_SPEED/P1_MDIO[P0_COL]  
P0_DUPLEX  
P0_SPEED[P0_OUTER/P0_SPEED]  
JS102011CQN  
P1_OUTD0_MODE1  
SW17  
1
3
39  
40  
P0_MDC  
P0_MDIO  
P0_MDC  
P0_MDIO  
CONFIG9[CONFIG10]  
P0_CRS  
P1_MDC_DUPLEX  
P0_COL  
2
3
JS102011CQN  
1
CONFIG9  
CONFIG10  
=
2RMII  
1 MII/RMII(Default)  
SW18  
2
=
JS102011CQN  
3
1
P1_MDIO_SPEED  
P1_MDIO_SPEED  
P1_MDC_DUPLEX  
P1_IND1  
P1_IND0  
P1_INDV  
P1_REFCLK_MODE0  
P1_OUTDV  
P1_OUTD0_MODE1  
P1_OUTD1_MODE2  
P0_INER  
P0_INCLK  
P0_INDV  
P0_IND0  
P0_IND1  
P0_IND2  
P0_IND3  
P0_COL  
P0_CRS  
3V3  
J30  
1
3V3  
J28  
1
P1_MDC_DUPLEX/P0_CRS  
R120  
2
P0_DUPLEX  
2
10.0K  
3
R118  
10.0K  
3
P0_MDIO  
P0_MDC  
P0_OUTD3  
P0_OUTD2  
Default -Open  
Default (1-2)  
P0_OUTD1_MODE2  
P0_OUTD0_MODE1  
P0_OUTDV  
3V3  
P0_OUT/REF_CLK_MODE0  
P0_OUTER_SPEED  
J31  
1
3V3  
J29  
1
3
P1_MDIO_SPEED/P0_COL  
R121  
2
P0_OUTER_SPEED  
R119  
2
10.0K  
3
P1_REFCLK_MODE0/P0_INCLK  
P1_OUTD1_MODE2/P0_OUTD3  
10.0K  
P1_OUTD0_MODE1/P0_OUTD2_MODE3  
P0_OUTD1_MODE2  
P0_OUTD0_MODE1  
Default -Open  
Default (1-2)  
P0_OUT/REF_CLK_MODE0  
Emulated Link Partner Default Advertised  
Ability for Port 0  
Emulated Link Partner Default Advertised  
Ability for Port 1  
J28  
(P0_DUPLEX)  
J29  
(P0_SPEED)  
Duplex Speed  
Strap_0 Strap_0  
ADVERTISED LINK PARTNER ABILITY  
(Bits 8,7,6,5)  
J30  
(P1_DUPLEX)  
J31  
(P1_SPEED)  
Duplex Speed  
Strap_1 Strap_1  
ADVERTISED LINK PARTNER ABILITY  
(Bits 8,7,6,5)  
1-2  
1-2  
2-3  
2-3  
2-3  
1-2  
2-3  
1-2  
1
1
0
0
0
1
0
1
10BASE-T full-duplex (0010)  
1-2  
1-2  
2-3  
2-3  
2-3  
1-2  
2-3  
1-2  
1
1
0
0
0
1
0
1
10BASE-T full-duplex (0010)  
100BASE-X full-duplex (1000)  
10BASE-T half-duplex (0001)  
100BASE-X half-duplex (0100)  
100BASE-X full-duplex (1000) (Default)  
10BASE-T half-duplex (0001)  
100BASE-X half-duplex (0100)  
FIGURE B-9:  
EVB-LAN9353 EVALUATION BOARD SCHEMATIC 9  
MII Male for External MAC Board  
Port 0 - RMII RX Clock Configurations  
SW23  
5V  
MII Female for External PHY Board  
AMP - 6-5174218-2  
MII_RA  
10uF  
C59  
FEMALE MII CONN  
AMP - 749069-4  
C60  
10uF  
2
3
MAC_RXCLK0  
5V  
0.1uF C61  
MAC_TXCLK0  
1
Default Short 2-3  
C62 0.1uF  
JS102011CQN  
SW24  
2
J23  
PHY_RXCLK0  
PHY_TXCLK0  
1
3
J24  
Default (1-3)  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
40  
+5V[1]  
39  
+5V[3]  
MDIO  
MDC  
JS102011CQN  
P0_MDIO  
COMMON[1]  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
P0_MDC  
P0_OUTD3  
P0_OUTD2  
COMMON[2]  
COMMON[3]  
COMMON[4]  
COMMON[5]  
COMMON[6]  
COMMON[7]  
COMMON[8]  
COMMON[9]  
COMMON[10]  
COMMON[11]  
COMMON[12]  
COMMON[13]  
COMMON[14]  
COMMON[15]  
COMMON[16]  
COMMON[17]  
COMMON[18]  
+5V[2]  
Switch  
Settings  
1
2
3
4
5
6
7
8
9
21  
22  
23  
24  
25  
26  
27  
28  
29  
P0_MDIO  
P0_MDC  
P0_IND3  
P0_IND2  
P0_IND1  
P0_IND0  
P0_INDV  
0E PHY_RXCLK0  
P0_INER  
0E TXER0  
0E PHY_TXCLK0  
P0_OUTDV  
P0_OUTD0_MODE1  
P0_OUTD1_MODE2  
P0_OUTD2  
P0_OUTD3  
P0_COL  
Description  
Mode  
RXD3  
RXD2  
RXD1  
RXD0  
RX_DV  
RX_CLK  
RX_ER  
TX_ER  
TX_CLK  
TX_EN  
TXD0  
TXD1  
TXD2  
TXD3  
COL  
CRS  
+5V[4]  
P0_OUTD1_MODE2  
P0_OUTD0_MODE1  
P0_OUTDV  
SW23 (1-3) TX Clock used as a Reference Clock  
Default  
RMII MAC  
R126  
R127  
0E MAC_TXCLK0  
0E MAC_RXCLK0  
P0_OUT/REF_CLK_MODE0  
P0_OUTER_SPEED  
P0_INER  
SW23 (1-2) RX Clock used as a Reference Clock  
RMII MAC  
RMII PHY  
P0_INCLK  
R128  
P0_INCLK  
P0_INDV  
P0_IND0  
P0_IND1  
P0_IND2  
P0_IND3  
P0_COL  
P0_CRS  
SW24 (1-3) Reference clock used as a TX clock  
Default  
10 30  
11 31  
12 32  
13 33  
14 34  
15 35  
16 36  
17 37  
18 38  
19 39  
20 40  
P0_OUTER_SPEED  
P0_OUT/REF_CLK_MODE0  
DNP R129  
R130  
SW24 (1-2)  
Reference clock used as a RX clock  
RMII PHY  
Note: 1. For Switches to short 1-3, Knob Position should be  
at 1-2 and vice versa .  
2. External PHY considered LAN8742  
P0_CRS  
PORT 0  
PORT 1  
MII Male for External MAC Board  
5V  
MII Female for External PHY Board  
AMP - 6-5174218-2  
MII_RA  
10uF  
C63  
Port 1 - RMII RX Clock Configurations  
FEMALE MII CONN  
AMP - 749069-4  
C65  
10uF  
5V  
0.1uF C64  
SW25  
C66 0.1uF  
2
3
MAC_RXCLK1  
MAC_TXCLK1  
1
Default Short 2-3  
J18  
JS102011CQN  
SW26  
2
J19  
PHY_RXCLK1  
1
2
3
40  
39  
PHY_TXCLK1  
1
+5V[3]  
MDIO  
MDC  
+5V[1]  
COMMON[1]  
P1_MDIO_SPEED  
P1_MDC_DUPLEX  
3
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
Default (1-3)  
COMMON[2]  
COMMON[3]  
COMMON[4]  
COMMON[5]  
COMMON[6]  
COMMON[7]  
COMMON[8]  
COMMON[9]  
COMMON[10]  
COMMON[11]  
COMMON[12]  
COMMON[13]  
COMMON[14]  
COMMON[15]  
COMMON[16]  
COMMON[17]  
COMMON[18]  
+5V[2]  
4
1
2
3
4
5
6
7
8
9
21  
22  
23  
24  
25  
26  
27  
28  
29  
P1_MDIO_SPEED  
P1_MDC_DUPLEX  
JS102011CQN  
RXD3  
RXD2  
RXD1  
RXD0  
RX_DV  
RX_CLK  
RX_ER  
TX_ER  
TX_CLK  
TX_EN  
TXD0  
TXD1  
TXD2  
TXD3  
COL  
CRS  
+5V[4]  
5
6
7
8
9
10  
11  
P1_OUTD1_MODE2  
P1_OUTD0_MODE1  
P1_OUTDV  
Switch  
Settings  
Description  
Mode  
P1_IND1  
P1_IND0  
P1_INDV  
R135  
0E MAC_TXCLK1  
P1_REFCLK_MODE0  
SW25 (1-3) TX Clock used as a Reference Clock  
Default  
RMII MAC  
RMII MAC  
PHY_TXCLK1  
MAC_RXCLK1 12  
SW25 (1-2) RX Clock used as a Reference Clock  
13  
14  
15  
16  
17  
18  
19  
20  
10 30  
11 31  
12 32  
13 33  
14 34  
15 35  
16 36  
17 37  
18 38  
19 39  
20 40  
P1_INDV  
P1_IND0  
P1_IND1  
P1_REFCLK_MODE0  
R136  
0E PHY_RXCLK1  
SW26 (1-3) Reference clock used as a TX clock  
Default  
P1_OUTDV  
P1_OUTD0_MODE1  
P1_OUTD1_MODE2  
RMII PHY  
RMII PHY  
SW26 (1-2)  
Reference clock used as a RX clock  
P1_CRS  
P1_CRS  
Note: 1. For Switches to short 1-3, Knob Position should be  
at 1-2 and vice versa .  
2. External PHY considered LAN8742  
P1_CRS  
P1_INDV  
For RMII  
3V3  
3V3  
Pullup for MDIO(common for all PHY) signal  
TP8  
Pullup for MDIO(common for all PHY) signal  
TP5 TP6  
3V3  
J28 = Default open  
Short for RMII mode  
J25  
TP7  
R133  
10K  
P0_OUTDV  
3V3  
J26 = Default open  
P0_INDV  
1
2
P0_CRS  
P0_MDIO  
2
1
J26  
1.5K  
10K  
R131  
R139  
R134  
10K  
P1_OUTDV  
TXER0  
P1_MDIO_SPEED  
P1_MDC_DUPLEX  
1.5K  
10K  
R137  
R138  
Short option for RXDV & CRS  
for RMII mode  
P0_MDC  
R132 DNP  
49.9K  
DNP  
EVB-LAN9353  
EVALUATION BOARD  
USER’S GUIDE  
Appendix C. Bill of Materials (BOM)  
C.1 INTRODUCTION  
This appendix includes the EVB-LAN9353 Evaluation Board Bill of Materials (BOM).  
2015 Microchip Technology Inc.  
DS50002393A-page 39  
Configuration: Config 10: Two internal copper mode with higher size EEPROM (24FC512)  
TABLE C-1: EVB-LAN9353 EVALUATION BOARD BILL OF MATERIALS  
Item  
Qty  
Reference Designator(s)  
Part  
PCB Footprint  
CAP0805  
Manufacturer  
Murata  
Manufacturer Part Number  
1
2
2
C2,C4  
10uF  
GRM21BR61E106KA73L  
GRM155R61E104KA7D  
21  
C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17 0.1uF  
CAP0603  
Murata  
,C18,C21,C22,C24,C25,C58,C61,C62,C64,C6  
6
3
4
1
1
2
2
4
3
1
5
1
C19  
1uF  
CAP0603  
CAP0603  
CAP0603  
CAP0603  
CAP0603  
LED0603  
LED0603  
RES0603  
Murata  
GRM188R61C105KA93D  
GRM033R71E471KA01D  
GRM1885C1H180JA01D  
C0603C223K5RACTU  
C1608X5R0J106K080AB  
150 060 GS7 500 0  
C20  
470pF  
18pF  
0.022uF  
10uF  
GRN  
Murata  
5
C26,C27  
Murata  
6
C32,C37  
Kemet  
7
C59,C60,C63,C65  
TDK  
8
D1,D4,D7  
Wurth electronics  
Wurth electronics  
Murata  
9
D2  
RED  
150 060 RS7 500 0  
10  
11  
FB1,FB2,FB3,FB4,FB5  
J1  
2A/0.05DCR  
BLM18EG221SN1D  
PJ-002AH  
SKT_P-  
th_conn_pwrjack_dc-210_rt Cui Stack  
WR_2R0mm_4A_THRU_R  
A
12  
18  
J4,J5,J6,J7,J8,J9,J10,J11,J12,J13,J14,J15,J2 HDR_1x3  
0,J21,J28,J29,J30,J31  
TH_CONN_1X3P  
FCI  
68000-103HLF  
13  
14  
1
2
J16  
HEADER 5X2  
th_conn_2x5p_BOX  
FCI  
TE  
67997-210HLF  
5173278-2-ND  
J18,J23  
MII_RA  
TH_CON-  
N_TE-5173278_40P  
15  
16  
17  
18  
19  
2
3
J19,J24  
J22,J25,J26  
J27  
FEMALE MII CONN  
CONN_2P  
TH_CONN_MII-749069-4  
th_conn_1x2p  
th_conn_1x8p  
sot23-NDS  
TE  
749069-4-ND  
68000-102HLF  
68000-108HLF  
NDS355AN  
FCI  
1
CONN_8P  
FCI  
1
Q1  
NDS355AN_NMOS  
Fairchild  
Panasonic  
15  
R1,R15,R29,R126,R127,R128,R130,R135,R1 0E  
36,FB6,FB7,R72,R73,R85,R86  
RES0603  
ERJ-3GEY0R00V  
20  
21  
22  
23  
24  
25  
4
1
R2,R8,R74,R84  
1K  
RES0603  
RES0603  
RES0603  
RES0603  
RES0603  
RES0603  
Panasonic  
Yageo America  
BOURNS  
ERJ-3GEYJ102V  
R3  
3.30K  
470E  
33E  
9C06031A3301FKHFT  
CR0603-FX-4700ELF  
CR0603-FX-33R0ELF  
ERJ-3EKF4751V  
1
R4  
1
R4A  
R5  
BOURNS  
1
4.75K  
Panasonic  
Panasonic  
25  
R6,R69,R70,R71,R81,R82,R83,R76,R79,R80, 10.0K  
R99,R100,R133,R138,R139,R104,R105,R106  
,R107,R108,R109,R118,R119,R120,R121  
ERJ-3EKF1002V  
TABLE C-1:  
EVB-LAN9353 EVALUATION BOARD BILL OF MATERIALS (CONTINUED)  
Item  
Qty  
Reference Designator(s)  
Part  
PCB Footprint  
RES0603  
Manufacturer  
Panasonic  
Manufacturer Part Number  
26  
27  
28  
29  
30  
31  
32  
33  
34  
1
1
R7  
100E  
2.2K  
12.1K  
49.9E  
0
ERJ-3EKF1000V  
R9  
RES0603  
RES0603  
RES0603  
RES0402  
RES1210  
RES0603  
RES0603  
RES0603  
Panasonic  
Rohm  
ERJ-3GEYJ222V  
1
R10  
MCR01MZPF1202  
9C06031A49R9FKHFT  
ERJ-2GE0R00X  
8
R11,R12,R13,R14,R25,R26,R27,R28  
R17,R19,R21,R23,R31,R33,R35,R37  
R24,R38  
Yageo America  
Panasonic  
Vishay  
8
2
0
CRCW12100000Z0EA  
ERJ-3GEYJ331V  
4
R61,R62,R102,R103  
R67,R68  
330E  
2K  
Panasonic  
Panasonic  
BOURNS  
2
ERJ-3GEYJ202V  
10  
R116,R117,R122,R123,R124,R125,R144,R14 33E  
5,R146,R147  
CR0603-FX-33R0ELF  
35  
36  
37  
38  
2
1
R131,R137  
SW1  
1.5K  
RES0603  
Panasonic  
C&K  
ERJ-3GEYJ152V  
1101M2S3CQE2  
EVQ-PJU04K  
SW-SPDT-SLIDE  
sw_pb_2P  
sw_ck_1101m2s3cqe2  
sw_pb_2P  
1
SW2  
Panasonic  
18  
SW5,SW6,SW7,SW8,SW9,SW10,SW11,SW1 450301014042  
2,SW13,SW14,SW15,SW16,SW17,SW18,SW  
23,SW24,SW25,SW26  
TH_SW_SPST_3P_10x2p5 Wurth electronics  
450301014042  
39  
40  
41  
42  
43  
1
1
TP1  
RED  
TH_TP_60D40  
Keystone  
5000  
TP2  
ORANGE  
BLACK  
TH_TP_60D40  
Keystone  
5003  
TP9,TP10  
T1,T2  
U1  
TH_TP_60D40  
Keystone  
5001  
2
1
Pulse - J0011D01BNL  
3_Amp  
th_conn_pulse_rj45_j0026  
Pulse Electronics  
553-1483-ND  
OKR-T/3-W12-C  
TH_DC-DC_VERT_5PIN_P Murata  
67  
44  
45  
46  
47  
48  
49  
50  
1
1
1
1
1
4
1
U2  
TPS3125  
74LVC1G14  
LAN9353  
Round Base  
24FC512  
GRN  
SOT23_5  
TI  
TPS3125L30DBVR  
SN74LVC1G14DCKR  
LAN9353  
U3  
SOT23_5  
TI  
U4  
IC_QFN64  
IC_DIP8_300  
IC_DIP8_300  
LED0603  
Microchip  
Assmann  
Microchip  
Wurth electronics  
U5  
AR08-HZL-TT-R  
U5  
24FC512-I/P  
D3,D5,D6,D8  
Y1  
150 060 GS7 500 0  
CSM1Z-A5B2C5-40-25.0D18-F  
25.000MHz  
XTAL_HCM49  
Cardinal Components  
Inc.  
EVB-LAN9353 Evaluation Board User’s Guide  
NOTES:  
DS50002393A-page 42  
2015 Microchip Technology Inc.  
Worldwide Sales and Service  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
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Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://www.microchip.com/  
support  
Asia Pacific Office  
China - Xiamen  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
Hong Kong  
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France - Paris  
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Fax: 33-1-69-30-90-79  
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Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Web Address:  
www.microchip.com  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
Germany - Dusseldorf  
Tel: 49-2129-3766400  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
China - Beijing  
Tel: 86-10-8569-7000  
Fax: 86-10-8528-2104  
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Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
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Fax: 86-28-8665-7889  
Austin, TX  
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Japan - Osaka  
Tel: 81-6-6152-7160  
Fax: 81-6-6152-9310  
Germany - Pforzheim  
Tel: 49-7231-424750  
Boston  
China - Chongqing  
Tel: 86-23-8980-9588  
Fax: 86-23-8980-9500  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Japan - Tokyo  
Tel: 81-3-6880- 3770  
Fax: 81-3-6880-3771  
China - Dongguan  
Tel: 86-769-8702-9880  
Italy - Venice  
Tel: 39-049-7625286  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
China - Hangzhou  
Tel: 86-571-8792-8115  
Fax: 86-571-8792-8116  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
Cleveland  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
China - Hong Kong SAR  
Tel: 852-2943-5100  
Fax: 852-2401-3431  
Poland - Warsaw  
Tel: 48-22-3325737  
Independence, OH  
Tel: 216-447-0464  
Fax: 216-447-0643  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
China - Nanjing  
Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
Sweden - Stockholm  
Tel: 46-8-5090-4654  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Detroit  
Novi, MI  
UK - Wokingham  
Tel: 44-118-921-5800  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Tel: 248-848-4000  
Fax: 44-118-921-5820  
Houston, TX  
Tel: 281-894-5983  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Indianapolis  
Noblesville, IN  
Tel: 317-773-8323  
Fax: 317-773-5453  
China - Shenzhen  
Tel: 86-755-8864-2200  
Fax: 86-755-8203-1760  
Taiwan - Hsin Chu  
Tel: 886-3-5778-366  
Fax: 886-3-5770-955  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Taiwan - Kaohsiung  
Tel: 886-7-213-7828  
Taiwan - Taipei  
Tel: 886-2-2508-8600  
Fax: 886-2-2508-0102  
New York, NY  
Tel: 631-435-6000  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
San Jose, CA  
Tel: 408-735-9110  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Canada - Toronto  
Tel: 905-673-0699  
Fax: 905-673-6509  
01/27/15  
DS50002393A-page 43  
2015 Microchip Technology Inc.  

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