EVB-EP5358LUI [ALTERA]
600mA PowerSoC Synchronous Buck Regulator with Integrated Inductor;
| 型号： | EVB-EP5358LUI |
| 厂家： | 
ALTERA CORPORATION |
| 描述： | 600mA PowerSoC Synchronous Buck Regulator with Integrated Inductor |
| 文件： | 总16页 (文件大小：757K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Enpirion® Power Datasheet
EP5358xUI 600mA PowerSoC
Synchronous Buck Regulator
with Integrated Inductor
Description
The EP5358xUI (x = L or H) is rated for up to
600mA of continuous output current. The
Features
• Integrated Inductor Technology
• 2.5mm x 2.25mm x 1.1mm uQFN package
• Total Solution Footprint 14mm2
• Low VOUT ripple for RF compatibility
• High efficiency, up to 93%
EP5358xUI
integrates
MOSFET
switches,
control, compensation, and the magnetics in an
advanced 2.5mm
Package.
x
2.25mm micro-QFN
Integrated magnetics enables a tiny solution
footprint, low output ripple, low part-count, and
high reliability, while maintaining high efficiency.
The complete solution can be implemented in as
little as 14mm2.
• Up to 600mA continuous output current
• Less than 1µA standby current
• 5 MHz switching frequency
• 3 pin VID for glitch free voltage scaling
The EP5358xUI uses a 3-pin VID to easily select
• VOUT Range 0.6V to V – 0.25V
IN
the output voltage setting.
Output voltage
• Short circuit and over current protection
• UVLO and thermal protection
settings are available in 2 optimized ranges
providing coverage for typical VOUT settings.
• IC level reliability in a PowerSOC solution
The VID pins can be changed on the fly for fast
dynamic voltage scaling. EP5358LUI further has
the option to use an external voltage divider.
Application
The EP5358xUI is a perfect solution for noise
sensitive and space constrained applications that
require high efficiency.
• Wireless and RF applications
• Wireless broad band data cards
• Small form factor optical modules
• Low noise FPGA IO and Transceivers
• Advanced Low Power Processors, DSP, IO,
Memory, Video, Multimedia Engines
AVIN
PVIN
VSENSE
VOUT
VIN
VOUT
ENABLE
10uF
EP5358xUI
2.2uF
EP5358HUI
VS0
VS1
VS2
AGND
PGND
4.75mm
Figure 1: Total Solution Footprint.
Figure 2: Typical Application Schematic
www.altera.com/enpirion
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Ordering Information
Pin Assignments(Top View)
Part Number
Comment
Package
EP5358LUI
LOW VID Range 16-pin QFN T&R
HIGH VID Range 16-pin QFN T&R
EP5358LUI Evaluation Board
16
15
EP5358HUI
1
2
3
4
5
6
NC(SW)
PGND
PGND
VFB
14 PVIN
13 AVIN
12 ENABLE
11 VS0
EVB-EP5358LUI
EVB-EP5358HUI
EP5358HUI Evaluation Board
VSENSE
AGND
10 VS1
VS2
9
7
8
Figure 3: EP5358LUI Pin Out Diagram (Top View)
16
15
1
2
3
4
5
6
NC(SW)
PGND
PGND
NC
14 PVIN
13 AVIN
12 ENABLE
11 VS0
VSENSE
AGND
10 VS1
VS2
9
7
8
Figure 4: EP5358HUI Pin Out Diagram (Top View)
Pin Description
PIN
NAME
FUNCTION
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. NC (SW) pins are not to be electrically connected to any external signal,
ground, or voltage. However, they must be soldered to the PCB. Failure to follow this
guideline may result in part malfunction or damage to the device.
Power ground. Connect these pins together and to the ground electrode of the Input and
output filter capacitors.
1, 15,
16
NC(SW)
2,3
PGND
EP5358LUI: Feed back pin for external divider option.
EP5358HUI: No Connect
Sense pin for preset output voltages. Refer to application section for proper configuration.
Analog ground. This is the quiet ground for the internal control circuitry, and the ground
return for external feedback voltage divider
4
5
VFB/NC
VSENSE
AGND
6
7, 8
VOUT
Regulated Output Voltage. Refer to application section for proper layout and decoupling.
Output voltage select. VS2 = pin 9, VS1 = pin 10, VS0 = pin 11.
9, 10,
11
VS2, VS1,
VS0
EP5358LUI: Selects one of seven preset output voltages or an external resistor divider.
EP5358HUI: Selects one of eight preset output voltages.
(Refer to section on output voltage select for more details.)
12
13
14
ENABLE
AVIN
PVIN
Output Enable. Enable = logic high; Disable = logic low
Input power supply for the controller circuitry.
Input Voltage for the MOSFET switches.
www.altera.com/enpirion Page 2
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the
recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
SYMBOL MIN
MAX
UNITS
Input Supply Voltage
VIN
-0.3
-0.3
-0.3
6.0
V
VIN+ 0.3
2.7
V
V
Voltages on: ENABLE, VSENSE, VSO – VS2
Voltages on: VFB (EP5358LUI)
Maximum Operating Junction Temperature
Storage Temperature Range
TJ-ABS
TSTG
150
150
°C
°C
°C
V
-65
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020C
ESD Rating (based on Human Body Mode)
260
2000
Recommended Operating Conditions
PARAMETER
Input Voltage Range
SYMBOL MIN
MAX UNITS
VIN
TA
TJ
2.4
-40
-40
5.5
V
Operating Ambient Temperature
+85
°C
°C
Operating Junction Temperature
+125
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient –0 LFM (Note 1)
SYMBOL
θJA
TYP
UNITS
°C/W
85
+155
25
Thermal Overload Trip Point
TJ-TP
°C
°C
Thermal Overload Trip Point Hysteresis
Note 1: Based on a four layer copper board and proper thermal design per JEDEC EIJ/JESD51 standards
www.altera.com/enpirion Page 3
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Electrical Characteristics
NOTE: TA = -40°C to +85°C unless otherwise noted. Typical values are at TA = 25°C, VIN = 3.6V.
CIN = 4.7µF MLCC, COUT = 10µF
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Operating Input Voltage
Range
VIN
2.4
5.5
V
Under Voltage Lock-out –
VIN Rising
VUVLO_R
VUVLO_F
RDO
2.0
1.9
350
V
Under Voltage Lock-out –
VIN Falling
V
Input to Output Resistance in 100%
duty cycle operation.
Drop Out Resistance
Output Voltage Range
500
mΩ
0.6
1.8
VIN-VDO
3.3
EP5358LUI (VDO = ILOAD X RDO
EP5358HUI
)
V
VOUT
Dynamic VoltageSlew
Rate (VID Change)
EP5358LUI
EP5358HUI
4
8
V/mS
VSLEW
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
VID Preset VOUT Initial
Accuracy
-2
+2
%
∆VOUT
Line Regulation
2.4V ≤ VIN ≤ 5.5V
0A ≤ ILOAD ≤ 600mA
-40°C ≤ TA ≤ +85°C
0.03
0.48
24
%/V
%/A
∆VOUT_LINE
∆VOUT_LOAD
∆VOUT_TEMPL
Load Regulation
Temperature Variation
ppm/°C
Output Current
IOUT
ISD
600
mA
µA
Shut-down Current
Enable = Low
0.75
1.4
2.4V ≤ VIN ≤ 5.5V
0.6V ≤ VOUT ≤ 3.3V
OCP Threshold
ILIM
1.25
.588
A
TA = 25°C, VIN = 3.6V;
ILOAD = 100mA ;
0.8V ≤ VOUT ≤ 3.3V
Feedback Pin Voltage
Initial Accuracy
VFB
0.6
0.612
V
Feedback Pin Input
Current
IFB
Note 1
<100
nA
VS0-VS2, Pin Logic Low
VS0-VS2, Pin Logic High
VVSLO
VVSHI
0.0
1.4
0.3
VIN
V
V
VS0-VS2, Pin Input
Current
IVSX
Note 1
Note 1
<100
nA
Enable Pin Logic Low
Enable Pin Logic High
Enable Pin Current
VENLO
VENHI
IENABLE
FOSC
0.3
V
V
1.4
<100
5
nA
MHz
Operating Frequency
Soft Start Operation
EP5358LUI (VID MODE)
EP5358HUI (VID MODE)
2.6
5.2
4
8
5.4
10.8
Soft Start Slew Rate
VOUT Rise Time
V/mS
uSec
∆VSS
TRISE
EP5358LUI VFB MODE
146
225
304
Note 1: Parameter guaranteed by design
www.altera.com/enpirion Page 4
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Typical PerformanceCharacteristics
95
90
85
80
75
70
65
60
55
50
45
95
90
85
80
75
70
65
60
55
50
45
0
200
400
600
0
200
400
600
Load Current (mA)
Load Current (mA)
Efficiency vs. Load Current: VIN = 5.0V, VOUT (from
top to bottom) = 3.3, 2.5, 1.8, 1.2V
Efficiency vs. Load Current: VIN = 3.7V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
95
90
85
80
75
70
65
60
55
50
45
0
200
400
600
Load Current (mA)
Efficiency vs. Load Current: VIN = 3.3V, VOUT (from
top to bottom) = 2.5, 1.8, 1.2V
Start Up Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA (VID MODE)
Start Up Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 500mA (VID MODE)
www.altera.com/enpirion Page 5
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 10mA
Shut-down Waveform: VIN = 5.0V, VOUT = 3.3V;
ILOAD = 500mA
Output Ripple: VIN = 5.0V, VOUT = 1.2V,
Load = 500mA
Output Ripple: VIN = 5.0V, VOUT = 3.3V
Load = 500mA
Output Ripple: VIN = 3.3V, VOUT = 1.8V
Load = 500mA
Output Ripple: VIN = 3.3V, VOUT = 1.2V,
Load = 500mA
www.altera.com/enpirion Page 6
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Load Transient: VIN = 3.3V, VOUT = 1.8V
Load stepped from 10mA to 500mA
Load Transient: VIN = 5.0V, VOUT = 1.2V
Load stepped from 10mA to 500mA
www.altera.com/enpirion Page 7
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Functional Block Diagram
PVIN
EP5358UI
UVLO
Thermal Limit
Current Limit
NC(SW)
ENABLE
Soft Start
P-Drive
Logic
VOUT
(-)
PWM
Comp
N-Drive
(+)
GND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
Error
Amp
VFB
(+)
DAC
Voltage
Select
VREF
Package Boundry
AVIN AGND
VS0 VS1 VS2
Figure 5: Functional Block Diagram
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03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Detailed Description
Functional Overview
Integrated Inductor: Low-Noise Low-EMI
The EP5358xUI requires only 2 small MLCC
capacitors for a complete DC-DC converter
The EP5358xUI utilizes a proprietary low loss
integrated inductor.
The integration of the
solution.
switches,
The device integrates MOSFET
PWM controller, Gate-drive,
inductor greatly simplifies the power supply
design process. The inherent shielding and
compact construction of the integrated inductor
reduces the conducted and radiated noise that
can couple into the traces of the printed circuit
compensation, and inductor into a tiny 2.5mm x
2.25mm 1.1mm micro-QFN package.
x
Advanced package design, along with the high
level of integration, provides very low output
ripple and noise. The EP5358xUI uses voltage
mode control for high noise immunity and load
matching to advanced ≤90nm loads. A 3-pin
VID allows the user to choose from one of 8
board.
Further, the package layout is
optimized to reduce the electrical path length
for the high di/dT input AC ripple currents that
are a major source of radiated emissions from
DC-DC converters. The integrated inductor
provides the optimal solution to the complexity,
output ripple, and noise that plague low power
DCDC converter design.
output voltage settings.
The EP5358xUI
comes with two VID output voltage ranges.
The EP5358HUI provides VOUT settings from
1.8V to 3.3V, the EP5358LUI provides VID
settings from 0.8V to 1.5V, and also has an
external resistor divider option to program
Control Matched to sub 90nm Loads
The EP5358xUI utilizes an integrated type III
compensation network. Voltage mode control
is inherently impedance matched to the sub
90nm process technology that is used in
today’s advanced ICs. Voltage mode control
also provides a high degree of noise immunity
at light load currents so that low ripple and high
accuracy are maintained over the entire load
output setting over the 0.6V to V -0.25V
IN
range. The EP5358xUI provides the industry’s
highest power density of any 600mA DCDC
converter solution.
The key enabler of this revolutionary
integration is Altera’s proprietary power
MOSFET technology. The advanced MOSFET
switches are implemented in deep-submicron
CMOS to supply very low switching loss at high
switching frequencies and to allow a high level
of integration. The semiconductor process
allows seem-less integration of all switching,
control, and compensation circuitry.
range.
The very high switching frequency
allows for a very wide control loop bandwidth
and hence excellent transient performance.
Soft Start
Internal soft start circuits limit in-rush current
when the device starts up from a power down
condition or when the “ENABLE” pin is
asserted “high”. Digital control circuitry limits
the VOUT ramp rate to levels that are safe for
the Power MOSFETS and the integrated
inductor.
The proprietary magnetics design provides
high-density/high-value magnetics in a very
small footprint. Altera Enpirion magnetics are
carefully matched to the control and
compensation circuitry yielding an optimal
solution with assured performance over the
entire operating range.
The EP5358HUI has a soft-start slew rate that
is twice that of the EP5358LUI.
Protection features include under-voltage lock-
out (UVLO), over-current protection (OCP),
short circuit protection, and thermal overload
protection.
When the EP5358LUI is configured in external
resistor divider mode, the device has a fixed
VOUT ramp time. Therefore, the ramp rate will
vary with the output voltage setting. Output
voltage ramp time is given in the Electrical
Characteristics Table.
www.altera.com/enpirion Page 9
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Excess bulk capacitance on the output of the
device can cause an over-current condition at
startup. The maximum total capacitance on
the output, including the output filter capacitor
and bulk and decoupling capacitance, at the
load, is given as:
Under Voltage Lockout
During initial power up an under voltage
lockout circuit will hold-off the switching
circuitry until the input voltage reaches a
sufficient level to insure proper operation. If
the voltage drops below the UVLO threshold
the lockout circuitry will again disable the
switching. Hysteresis is included to prevent
chattering between states.
EP5358LUI:
C
OUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 230uF
EP5358HUI:
OUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 115uF
C
Enable
The ENABLE pin provides a means to shut
down the converter or enable normal
EP5358LUI in external divider mode:
OUT_TOTAL_MAX = 2.086x10-4/VOUT Farads
C
operation.
A logic low will disable the
The above numbers and formula assume a no
load condition.
converter and cause it to shut down. A logic
high will enable the converter into normal
operation.
NOTE: The ENABLE pin must not be left
floating.
Over Current/Short Circuit Protection
The current limit function is achieved by
sensing the current flowing through a sense P-
MOSFET which is compared to a reference
current. When this level is exceeded the P-
FET is turned off and the N-FET is turned on,
pulling VOUT low. This condition is maintained
for approximately 0.5mS and then a normal
Thermal Shutdown
When excessive power is dissipated in the
chip, the junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature the thermal shutdown
circuit turns off the converter output voltage
thus allowing the device to cool. When the
junction temperature decreases by 15C°, the
device will go through the normal startup
process.
soft start is initiated.
If the over current
condition still persists, this cycle will repeat.
www.altera.com/enpirion Page 10
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Application Information
which in turn is connected to the non-inverting
input of the error amplifier. This allows the use
of a single feedback divider with constant loop
gain and optimum compensation, independent
of the output voltage selected.
VOUT
PVIN
VOUT
VIN
AVIN
VSENSE
ENABLE
10µF
4.7µF
VS0
VS1
VS2
NOTE: The VID pins must not be left floating.
AGND
PGND
EP5358L Low VID Range Programming
The EP5358LUI is designed to provide a high
degree of flexibility in powering applications
that require low VOUT settings and dynamic
voltage scaling (DVS). The device employs a
3-pin VID architecture that allows the user to
choose one of seven (7) preset output voltage
settings, or the user can select an external
voltage divider option. The VID pin settings
can be changed on the fly to implement glitch-
free voltage scaling.
Figure 6: Application Circuit, EP5358HUI,.
VOUT
PVIN
VOUT
VIN
AVIN
VSENSE
ENABLE
10µF
4.7µF
VFB
VS0
VS1
VS2
AGND
PGND
Table 1: EP5358LUI VID Voltage Select Settings
VS2
0
0
0
0
1
1
1
VS1
0
0
1
1
0
0
1
VS0
0
1
0
1
0
1
0
VOUT
1.50
1.45
1.20
1.15
1.10
1.05
0.8
Figure 7: Application Circuit, EP5358LUI, showing
the VFB function.
Output Voltage Programming
The EP5358xUI utilizes a 3-pin VID to program
the output voltage value. The VID is available
in two sets of output VID programming ranges.
The VID pins should be connected either to
AVIN or to AGND to avoid noise coupling into
the device.
1
1
1
EXT
Table 1 shows the VS2-VS0 pin logic states for
the EP5358LUI and the associated output
voltage levels.
A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
The “Low” range is optimized for low voltage
applications. It comes with preset VID settings
ranging from 0.80V and 1.5V. This VID set
also has an external divider option.
To specify this VID range, order part number
EP5358LUI.
EP5358LUI External Voltage Divider
The “High” VID set provides output voltage
settings ranging from 1.8V to 3.3V.
This
The external divider option is chosen by
version does not have an external divider
option. To specify this VID range, order part
number EP5358HUI.
connecting VID pins VS2-VS0 to V or a logic
IN
“1” or “high”. The EP5358LUI uses a separate
feedback pin, VFB, when using the external
divider. VSENSE must be connected to VOUT as
indicated in figure 8.
Internally, the output of the VID multiplexer
sets the value for the voltage reference DAC,
www.altera.com/enpirion Page 11
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
PVIN
AVIN
VSENSE
VOUT
VOUT
VIN
10µF
ENABLE
4.7uF
Ra
Rb
Table 2: EP5358HUI VID Voltage Select Settings
VFB
VSO
VS1
VS2
VS2
0
VS1
0
VS0
0
VOUT
3.3
PGND AGND
0
0
1
3.0
0
1
0
2.9
0
1
1
2.6
1
1
0
0
0
1
2.5
2.2
Figure 8: EP5358LUI using external divider
1
1
1
1
0
1
2.1
1.8
The output voltage is selected by the following
formula:
Ra
Rb
VOUT = 0.6V
(
1+
)
Custom VID Setting Adjustment
Ra must be chosen as 237KΩ to maintain loop
gain. Then Rb is given as:
AVIN
Rs
142.2x103
PVIN
VOUT
=
Ω
Rb
4.7uF
EP5358xUI
10uF
VOUT − 0.6
VSENSE
VSO
5.0pF
VS1
VOUT can be programmed over the range of
VS2
ENABLE
AGND
0.6V to (V – 0.25V).
IN
PGND
NOTE: Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
Figure 9: EP5358xUI with RC inserted in VSENSE
path to modify VID output voltages.
EP5358HUI High VID Range Programming
It is possible to adjust VOUT for a given VID
setting by inserting a parallel RC combination
in the VSENSE path as shown in figure 9. The
capacitor value is 5.0pF to ensure stability.
Note that the value of VOUT can only be
increased from its nominal setting
The EP5358HUI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP5358HUI does not have an
(VOUTNEW>VOUTOLD):
external divider option.
EP5358LUI, the VID pin settings can be
changed while the device is enabled.
As with the
For EP5358LUI:
VOUTNEW
VOUTOLD
RsL = 711*
−1 kOhms
Table 2 shows the VS0-VS2 pin logic states for
the EP5358HUI and the associated output
voltage levels.
A logic “1” indicates a
For EP5358HUI:
RsH = 356*
connection to AVIN or to a “high” logic voltage
level. A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
VOUTNEW
VOUTOLD
−1 kOhms
VOUTNEW is the desired “new” VOUT.
www.altera.com/enpirion Page 12
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
VOUTOLD is the VID table output voltage.
Input Filter Capacitor
For ILOAD ≤ 500mA, CIN = 2.2uF
For ILOAD > 500mA CIN = 4.7uF.
For a given Rs Value, the VOUTNEW for VID
settings is determined by the following
equations:
0402 capacitor case size is acceptable.
EP5358LUI:
The input capacitor must use a X5R or X7R or
equivalent dielectric formulation.
equivalent dielectric formulations
capacitance with frequency, bias, and with
temperature, and are not suitable for switch-
mode DC-DC converter input filter applications.
Y5V or
Rs
L
VOUTNEW =VOUTOLD
+1 Volts
lose
711
EP5358HUI:
VOUTNEW =VOUTOLD
Rs
H
+1 Volts
Output Filter Capacitor
356
For VIN ≤ 4.3V, COUT_MIN = 10uF 0603 MLCC.
For VIN > 4.3V, COUT_MIN = 10uF 0805 MLCC.
NOTE: The amount of adjustment is limited to
approximately 15% of the nominal VID setting.
Ripple performance can be improved by using
2x10µF 0603 MLCC capacitors (for any
allowed VIN).
NOTE: Adjusting VOUT using this method will
increase the tolerance of the output voltage.
The larger the adjustment, the greater the
increase in tolerance.
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP5358xUI.
Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance.
Excess total capacitance on the output (Output
Filter + Bulk) can cause an over-current
condition at startup. Refer to the section on
Soft-Start for the maximum total capacitance
on the output.
Pre-Bias Start-up
The output capacitor must use a X5R or X7R
or equivalent dielectric formulation. Y5V or
The EP5358xUI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EP5358xUI is not pre-biased when the
EP5358xUI is first enabled.
equivalent
dielectric
formulations
lose
capacitance with frequency, bias, and
temperature and are not suitable for switch-
mode
DC-DC
converter
output
filter
applications.
www.altera.com/enpirion Page 13
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Layout Recommendation
Figure 10 shows critical components and layer
1 traces of a recommended minimum footprint
EP5358LQI/EP5358HQI layout with ENABLE
tied to V . Alternate ENABLE configurations,
IN
and other small signal pins need to be
connected and routed according to specific
customer application. Please see the Gerber
files
on
the
Altera
website
www.altera.com/enpirion for exact dimensions
and other layers. Please refer to Figure 10
while reading the layout recommendations in
this section.
Figure 10:Top PCB Layer Critical Components
and Copper for Minimum Footprint
Recommendation 1: Input and output filter
capacitors should be placed on the same side
of the PCB, and as close to the EP5358QI
package as possible. They should be
connected to the device with very short and
wide traces. Do not use thermal reliefs or
spokes when connecting the capacitor pads to
the respective nodes. The +V and GND traces
between the capacitors and the EP5358QI
should be as close to each other as possible
so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 4: Multiple small vias
should be used to connect the ground traces
under the device to the system ground plane
on another layer for heat dissipation. The drill
diameter of the vias should be 0.33mm, and
the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole
size around 0.20-0.26mm. Do not use thermal
reliefs or spokes to connect the vias to the
ground plane. It is preferred to put these vias
under the capacitors along the edge of the
GND copper closest to the +V copper. Please
see Figure 10. These vias connect the
input/output filter capacitors to the GND plane
and help reduce parasitic inductances in the
input and output current loops. If the vias
cannot be placed under CIN and COUT, then put
them just outside the capacitors along the
GND. Do not use thermal reliefs or spokes to
connect these vias to the ground plane.
Recommendation 2: Input and output grounds
are separated until they connect at the PGND
pins. The separation shown on Figure 10
between the input and output GND circuits
helps minimize noise coupling between the
converter input and output switching loops.
Recommendation 3: The system ground
plane should be the first layer immediately
below the surface layer. This ground plane
should be continuous and un-interrupted below
the converter and the input/output capacitors.
Please see the Gerber files on the Altera
website www.altera.com/enpirion.
Recommendation 5: AVIN is the power supply
for the internal small-signal control circuits. It
should be connected to the input voltage at a
quiet point. In Figure 10 this connection is
made at the input capacitor close to the V
IN
connection.
www.altera.com/enpirion Page 14
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Recommended PCB Footprint
Figure 11: EP5358xUI Package PCB Footprint
www.altera.com/enpirion Page 15
03541
October 11, 2013
Rev F
EP5358LUI/EP5358HUI
Package and Mechanical
Figure 12: EN5358xUI Package Dimensions
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right tomake changes toany products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advisedto obtainthe latest version of devicespecifications before relying on any publishedinformation and beforeplacing orders for
products or services.
www.altera.com/enpirion Page 16
03541
October 11, 2013
Rev F
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