EVAL-ADAU1979Z [ADI]
Quad Analog-to-Digital Converter (ADC); 四路模拟数字转换器（ ADC ）
| 型号： | EVAL-ADAU1979Z |
| 厂家： | 
ADI |
| 描述： | Quad Analog-to-Digital Converter (ADC) |
| 文件： | 总44页 (文件大小：1698K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Quad Analog-to-Digital Converter (ADC)
Data Sheet
ADAU1979
FEATURES
GENERAL DESCRIPTION
Four 4.5 V rms (typical) differential inputs
On-chip phase-locked loop (PLL) for master clock
Low electromagnetic interference (EMI) design
109 dB (typical) analog-to-digital converter (ADC) dynamic
range
Total harmonic distortion + noise (THD + N): −95 dB (typical)
Selectable digital high-pass filter
24-bit stereo ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I2C/SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S, and TDM modes
Master and slave operation modes
40-lead LFCSP package
The ADAU1979 incorporates four high performance, analog-to-
digital converters (ADCs) with 4.5 V rms capable ac-coupled
inputs. The ADCs use a multibit sigma-delta (Σ-Δ) architecture
with continuous time front end for low EMI. An I2C/serial
peripheral interface (SPI) control port is included that allows a
microcontroller to adjust volume and many other parameters.
The ADAU1979 uses only a single 3.3 V supply. The device
internally generates the required digital DVDD supply. The low
power architecture reduces the power consumption. The on-
chip PLL can derive the master clock from an external clock
input or frame clock (sample rate clock). When fed with the
frame clock, it eliminates the need for a separate high frequency
master clock in the system. The ADAU1979 is available in a
40-lead LFCSP package.
Note that throughout this data sheet, multifunction pins, such
as SCL/CCLK, are referred to either by the entire pin name or
by a single function of the pin, for example, CCLK, when only
that function is relevant.
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Active noise cancellation systems
FUNCTIONAL BLOCK DIAGRAM
3.3V TO 1.8V
REGULATOR
DVDD
ADAU1979
AVDDx
AIN1
AIN1
AIN2
AIN2
AIN3
AIN3
AIN4
AIN4
IOVDD
ADC
ADC
LRCLK
BCLK
ADC
ADC
SDATAOUT1
SDATAOUT2
AGNDx
SCL/CCLK
SDA/COUT
AVDDx
2
ADDR1/CIN
ADDR0/CLATCH
I C/SPI
BG
REF
CONTROL
PLL
PD/RST
AGNDx
AGNDx
Figure 1.
Rev. 0
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ADAU1979
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
SPI Mode ..................................................................................... 24
Register Summary .......................................................................... 26
Register Details ............................................................................... 27
Master Power and Soft Reset Register..................................... 27
PLL Control Register ................................................................. 28
Block Power Control and Serial Port Control Register......... 29
Serial Port Control Register 1................................................... 30
Serial Port Control Register 2................................................... 31
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Performance Specifications ........................................... 3
Digital Input/Output Specifications........................................... 3
Power Supply Specifications........................................................ 4
Digital Filter Specifications......................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 12
Overview...................................................................................... 12
Power Supply and Voltage Reference....................................... 12
Power-On Reset Sequence ........................................................ 12
PLL and Clock............................................................................. 13
Analog Inputs.............................................................................. 14
ADC ............................................................................................. 16
ADC Summing Modes .............................................................. 16
Serial Audio Data Output Ports, Data Format ....................... 17
Control Ports................................................................................... 21
I2C Mode...................................................................................... 21
Channel 1 and Channel 2 Mapping for Output Serial Ports
Register ........................................................................................ 32
Channel 3 and Channel 4 Mapping for Output Serial Ports
Register ........................................................................................ 34
Serial Output Drive Control and Overtemperature Protection
Status Register............................................................................. 35
Post ADC Gain Channel 1 Control Register.......................... 36
Post ADC Gain Channel 2 Control Register.......................... 37
Post ADC Gain Channel 3 Control Register.......................... 37
Post ADC Gain Channel 4 Control Register.......................... 38
High-Pass Filter and DC Offset Control Register and Master
Mute Register.............................................................................. 38
ADC Clipping Status Register .................................................. 39
Digital DC High-Pass Filter and Calibration Register.......... 40
Typical Application Circuit........................................................... 41
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
Automotive Products................................................................. 42
REVISION HISTORY
11/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
Data Sheet
ADAU1979
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; TA = −40°C to +105°C, unless otherwise noted. Master clock = 12.288 MHz
(48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance
(digital output) = 20 pF; load current (digital output) = 1 mA; digital input voltage high = 2.0 V; and digital input voltage low = 0.8 V.
ANALOG PERFORMANCE SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
LINE INPUT
Full Scale AC Differential Input Voltage
Full Scale Single-Ended Input Voltage
Input Common-Mode Voltage
4.18
2.09
4.5
2.25
1.5
4.82
2.41
V rms
V rms
V dc
VIN, cm at AINx/AINx pins
ANALOG-TO-DIGITAL CONVERTERS
Differential Input Resistance
Single-Ended Input Resistance
ADC Resolution
Between AINx and AINx
Between AINx and AINx
64.34
32.17
24
109
−95
kΩ
kΩ
Bits
dB
dB
dB
%
Dynamic Range (A-Weighted) Line Input1
Input = 1 kHz, −60 dBFS (0 dBFS = 4.5 V rms input)
103
Total Harmonic Distortion + Noise (THD + N) Input = 1 kHz, −1 dBFS (0 dBFS = 4.5 V rms input)
Digital Gain Post ADC
Gain Error
Interchannel Gain Mismatch
Gain Drift
Common-Mode Rejection Ratio (CMRR)
−87
60
+10
0
−10
−0.25
+0.25 dB
ppm/°C
100
65
56
70
100
0
400 mV rms, 1 kHz
400 mV rms, 20 kHz
100 mV rms, 1 kHz on AVDD = 3.3 V
50
dB
dB
dB
dB
Power Supply Rejection Ratio (PSRR)
Interchannel Isolation
Interchannel Phase Deviation
REFERENCE
Degrees
Internal Reference Voltage
Output Impedance
VREF pin
1.47
8
1.50
20
1.54
192
V
kΩ
ADC SERIAL PORT
Output Sample Rate
kHz
1 This is for a sampling frequency, fS, ranging from 44.1 kHz to 192 kHz.
DIGITAL INPUT/OUTPUT SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage Current
Input Capacitance
0.7 × IOVDD
−10
V
V
µA
pF
0.3 × IOVDD
+10
5
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
IOH = 1 mA
IOL = 1 mA
IOVDD − 0.60
V
V
0.4
Rev. 0 | Page 3 of 44
ADAU1979
Data Sheet
POWER SUPPLY SPECIFICATIONS
AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, and fS = 48 kHz (master mode), unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SUPPLY
DVDD
AVDDx
IOVDD
On-chip low dropout (LDO) regulator
1.62
3.0
1.62
1.8
3.3
3.3
1.98
3.6
3.6
V
V
V
IOVDD CURRENT
Normal Operation
Master clock = 256 × fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
450
880
1.75
20
µA
µA
mA
µA
Power-Down
AVDDx CURRENT
Normal Operation
4-channel ADC, DVDD internal
4-channel ADC, DVDD external
14
9.5
270
mA
mA
µA
Power-Down
DVDD CURRENT
Normal Operation
Power-Down
DVDD external
5
65
mA
µA
POWER DISSIPATION
Normal Operation
Analog Supply
Master clock = 256 × fS, 48 kHz
DVDD internal
DVDD external
DVDD external
IOVDD = 3.3 V
46.2
31
8.1
1.49
960
mW
mW
mW
mW
µW
Digital Supply
Digital I/O Supply
Power-Down, All Supplies
DIGITAL FILTER SPECIFICATIONS
Table 4.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
Pass Band
All modes, typical at fS = 48 kHz
0.4375 × fS
21
0.015
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
0.5 × fS
0.5625 × fS
24
27
kHz
kHz
dB
µs
µs
79
fS = 8 kHz to 96 kHz
fS = 192 kHz
22.9844/fS
479
35
HIGH-PASS FILTER
Cutoff Frequency
Phase Deviation
Settling Time
All modes, typical at 48 kHz
At −3 dB point
At 20 Hz
0.9375
10
1
Hz
Degrees
sec
ADC DIGITAL GAIN
Gain Step Size
All modes
0
60
dB
dB
0.375
Rev. 0 | Page 4 of 44
Data Sheet
ADAU1979
TIMING SPECIFICATIONS
Table 5.
Limit at
tMIN tMAX
Parameter
Unit
Description
INPUT MASTER CLOCK (MCLK)
Duty Cycle
fMCLKIN
40
60
%
MHz
MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS
MCLKIN frequency, PLL in MCLK mode
See Table 9
RESET
Reset Pulse, tRESET
15
ns
RST low
PLL
Lock Time
10
ms
ADC SERIAL OUTPUT PORT
See Figure 2
tABH
tABL
tALS
10
10
10
5
ns
ns
ns
ns
ns
BCLK high, slave mode
BCLK low, slave mode
LRCLK setup to BCLK rising, slave mode
LRCLK hold from BCLK rising, slave mode
SDATAOUTx delay from BCLK falling
See Figure 3
CCLK frequency
CCLK high
CCLK low
CIN setup to CCLK rising
CIN hold from CCLK rising
CLATCH setup to CCLK rising
CLATCH hold from CCLK rising
CLATCH high
tALH
tABDD
SPI PORT
fCCLK
tCCPH
tCCPL
tCDS
18
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
35
10
10
10
40
10
30
30
30
tCDH
tCLS
tCLH
tCLPH
tCOE
COUT enable from CLATCH falling
COUT delay from CCLK falling
COUT tristate from CLATCH rising
tCOD
tCOTS
I2C PORT
See Figure 4
fSCL
400
kHz
µs
µs
µs
µs
SCL frequency
SCL high
SCL low
tSCLH
tSCLL
tSCS
tSCH
tDS
0.6
1.3
0.6
0.6
100
0
Setup time; relevant for repeated start condition
Hold time; after this period of time, the first clock pulse is generated
Data setup time
Data hold time
ns
tDH
tSCR
tSCF
tSDR
tSDF
tBFT
tSUSTO
300
300
300
300
ns
ns
ns
ns
µs
µs
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Bus-free time; time between stop and start
Setup time for stop condition
1.3
0.6
Rev. 0 | Page 5 of 44
ADAU1979
Data Sheet
Timing Diagrams
tALS
LRCLK
tALH
tABH
BCLK
tABL
tABDD
SDATAOUTx
LEFT JUSTIFIED
MODE
MSB
MSB – 1
tABDD
SDATAOUTx
I S MODE
MSB
2
tABDD
SDATAOUTx
RIGHT JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. ADC Serial Output Port Timing
tCLH
tCLS
tCLPH
tCOE
tCCPL
tCCPH
CLATCH
CCLK
CIN
tCDH
tCDS
tCOTS
COUT
tCOD
Figure 3. SPI Port Timing
tSCH
STOP
START
tDS
tSCH
tSDR
SDA
tSDF
tSCLH
tBFT
tSCR
SCL
tSCS
tSUSTO
tSCLL
tSCF
tDH
Figure 4. I2C Port Timing
Rev. 0 | Page 6 of 44
Data Sheet
ADAU1979
ABSOLUTE MAXIMUM RATINGS
Table 6.
THERMAL RESISTANCE
θJA represents junction-to-ambient thermal resistance, and
θJC represents the junction-to-case thermal resistance. All
characteristics are for a standard JEDEC board per JESD51.
Parameter
Rating
Analog (AVDDx) Supply
Digital Supply
−0.3 V to +3.6 V
DVDD
IOVDD
−0.3 V to +1.98 V
−0.3 V to +3.63 V
20 mA
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−40°C to +105°C
−40°C to +125°C
−65°C to +150°C
Table 7. Thermal Resistance
Package Type
θJA
θJC
Unit
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Ambient)
Junction Temperature Range
Storage Temperature Range
40-Lead LFCSP
32.8
1.93
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 44
ADAU1979
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AGND1
VREF
PLL_FILT
AVDD2
1
2
3
4
5
6
7
8
9
30 NC
29 AGND6
28 AGND5
27 NC
26 NC
25 NC
24 NC
23 NC
22 AGND4
21 AGND3
ADAU1979
TOP VIEW
(Not to Scale)
AGND2
PD/RST
MCLKIN
NC
SA_MODE
DVDD 10
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THESE PINS.
LEAVE THE NC PINS OPEN.
2. THE EXPOSED PAD MUST BE CONNECTED TO THE
GROUND PLANE ON THE PRINTED CIRCUIT BOARD (PCB).
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
AGND1
VREF
Type1 Description
1
2
P
O
Analog Ground.
Voltage Reference. Decouple VREF to AGND with a 10 µF capacitor in parallel with a 100 nF
capacitor.
3
PLL_FILT
O
Phase-Locked Loop Filter. Return PLL_FILT to AVDD using recommended loop filter
components.
4
5
6
7
AVDD2
AGND2
PD/RST
MCLKIN
P
P
I
Analog Power Supply. Connect AVDD2 to an analog 3.3 V supply.
Analog Ground.
Power-Down/Reset (Active Low).
I
Master Clock Input.
8, 23 to 27, 30 NC
No Connect. Do not connect to these pins. Leave the NC pins open.
9
SA_MODE
I
Standalone Mode. Connect SA_MODE to IOVDD using a 10 kΩ pull-up resistor for standalone
mode.
10
DVDD
O
1.8 V Digital Power Supply Output. Decouple DVDD to DGND with 100 nF and 10 µF
capacitors.
11
12
13
14
15
16
17
18
19
20
21
22
28
29
DGND
IOVDD
SDATAOUT1
SDATAOUT2
LRCLK
P
P
Digital Ground.
Digital I/O Power Supply. Connect IOVDD to a supply from 1.8 V to 3.3 V.
ADC Serial Data Output Pair 1 (ADC L1 and ADC R1).
ADC Serial Data Output Pair 2 (ADC L2 and ADC R2).
Frame Clock for ADC Serial Port.
O
O
I/O
I/O
I/O
I
BCLK
Bit Clock for ADC Serial Port.
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
ADDR1/CIN
AGND3
AGND4
AGND5
AGND6
Serial Data Input/Output (I2C)/Control Data Output (SPI).
Serial Clock Input (I2C)/Control Clock Input (SPI).
Chip Address Bit 0 Setting (I2C)/Chip Select Input for Control Data (SPI).
Chip Address Bit 1 Setting (I2C)/Control Data Input (SPI).
Analog Ground.
I
I
P
P
P
Analog Ground.
Analog Ground.
Analog Ground.
P
Rev. 0 | Page 8 of 44
Data Sheet
ADAU1979
Pin No.
31
32
Mnemonic
Type1 Description
AVDD3
AIN1
AIN1
AIN2
AIN2
AIN3
AIN3
AIN4
AIN4
AVDD1
EP
P
I
Analog Power Supply. Connect AVDD3 to an analog 3.3 V supply.
Analog Input Channel 1 Inverting Input.
33
34
I
I
Analog Input Channel 1 Noninverting Input.
Analog Input Channel 2 Inverting Input.
35
36
I
I
Analog Input Channel 2 Noninverting Input.
Analog Input Channel 3 Inverting Input.
37
38
I
I
Analog Input Channel 3 Noninverting Input.
Analog Input Channel 4 Inverting Input.
39
40
I
P
Analog Input Channel 4 Noninverting Input.
Analog Power Supply. Connect AVDD1 to an analog 3.3 V supply.
Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit
board (PCB).
1 P = power, O = output, I = input, I/O = input/output.
Rev. 0 | Page 9 of 44
ADAU1979
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Fast Fourier Transform, 4.5 mV Differential Input at fS = 48 kHz
Figure 9. CMRR Differential Input, Referenced to 450 mV Differential Input
10
0
10
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
20
100
1k
10k 20k
20
100
1k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Fast Fourier Transform, −1 dBFS Differential Input
Figure 10. Fast Fourier Transform, No Input
0
0.10
–10
0.08
0.06
0.04
0.02
0
–20
–30
–40
–50
–60
–70
–0.02
–0.04
–0.06
–0.08
–0.10
–80
–90
–100
–110
–120
5m
10m
100m
1
5
0
2000 4000 6000 8000 10000 12000 14000 16000 18000
FREQUENCY (Hz)
INPUT LEVEL (V rms)
Figure 8. THD + N vs. Input Amplitude
Figure 11. ADC Pass-Band Ripple at fS = 48 kHz
Rev. 0 | Page 10 of 44
Data Sheet
ADAU1979
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5000 10000 15000 20000 25000 30000 35000 40000
FREQUENCY (Hz)
Figure 12. ADC Filter Stop-Band Response at fS = 48 kHz
Rev. 0 | Page 11 of 44
ADAU1979
Data Sheet
THEORY OF OPERATION
The DVDD settling time depends on the charge-up time for the
external capacitors and on the AVDDx ramp-up time.
OVERVIEW
The ADAU1979 incorporates four high performance ADCs and
a phase-locked loop (PLL) circuit for generating the necessary
on-chip clock signals.
The internal POR circuit is provided with hysteresis to ensure that
a reset of the device is not initiated by an instantaneous glitch on
PD RST
DVDD. The typical trip points are 1.2 V with
/
high and
low. This ensures that the core is
not reset until the DVDD level falls below the 0.6 V trip point.
PD RST
pin is pulled high, the internal regulator
POWER SUPPLY AND VOLTAGE REFERENCE
PD RST
0.6 V ( 20%) with
/
The ADAU1979 requires a single 3.3 V power supply. Decouple
all AVDDx pins to the nearest AGNDx pin with 100 nF ceramic
chip capacitors placed as near the AVDDx pins as possible to
minimize noise pickup. A bulk aluminum electrolytic capacitor
of at least 10 μF must be provided on the same PCB as the ADC.
It is important that the analog supply be as clean as possible for
best performance.
As soon as the
/
starts charging up CEXT on the DVDD pin. The DVDD charge-up
time is based on the output resistance of the regulator and the
external decoupling capacitor. The time constant can be calcu-
lated as
tC = ROUT × CEXT
The supply voltage for the digital core (DVDD) is generated
using an internal low dropout regulator. The typical DVDD
output is 1.8 V and must be decoupled using a 100 nF ceramic
capacitor and a 10 µF capacitor. Place the 100 nF ceramic
capacitor as near the DVDD pin as possible.
where ROUT = 20 Ω typical.
For example, if CEXT is 10 µF, tC is 200 µs and is the time that it
takes to reach the DVDD voltage, within 63.6%.
The power-on reset circuit releases an internal reset of the core
when DVDD reaches 1.2 V (see Figure 13). Therefore, it is
recommended to wait for at least the tC period to elapse before
sending I2C or SPI control signals.
The voltage reference for the analog blocks is generated
internally and output at the VREF pin (Pin 2). The typical
voltage at the VREF pin is 1.5 V with an AVDDx of 3.3 V.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the IOVDD supply. The IOVDD
can be in the 1.8 V to 3.3 V range. The IOVDD pin must be
decoupled with a 100 nF capacitor placed as near the IOVDD
pin as possible.
AVDDx
The ADC internal voltage reference is output from the VREF pin
and must be decoupled using a 100 nF ceramic capacitor in
parallel with a 10 µF capacitor. The VREF pin has limited current
capability. The voltage reference is used as a reference to the
ADC; therefore, it is recommended not to draw current from
this pin for external circuits. When using this reference, use a
noninverting amplifier buffer to provide a reference to other
circuits in the application.
PD/RST
1.2V
tRESET
tC
DVDD (1.8V)
tD
0.48V
POR
Figure 13. Power-On Reset Timing
In reset mode, the VREF pin is disabled to save power and is
When applying a hardware reset to the device by pulling the
PD RST
enabled only when the
/
pin is pulled high.
PD RST
/
pin (Pin 6) low and then high, there are certain time
POWER-ON RESET SEQUENCE
PD RST
low pulse period, the DVDD
restrictions. During the
/
starts discharging. The discharge time constant is determined
by the internal resistance of the regulator and CEXT. Use the
following equation to estimate the time required for DVDD to
fall from 1.8 V to 0.48 V (0.6 V − 20%):
The ADAU1979 requires that a single 3.3 V power supply be
provided externally at the AVDDx pin. The device internally
generates DVDD (1.8 V), which is used for the digital core of
the ADC. The DVDD supply output pin (Pin 10) is provided
to connect the decoupling capacitors to DGND. The typical
recommended values for the decoupling capacitors are 100 nF
in parallel with 10 µF. During a reset, the DVDD regulator is
tD = 1.32 × RINT × CEXT
where RINT = 64 kΩ typical. (RINT can vary due to process by 20%.)
For example, if CEXT is 10 µF, tD is 0.845 sec.
PD RST
disabled to reduce power consumption. After the
/
pin
(Pin 6) is pulled high, the device enables the DVDD regulator.
However, the internal ADC and digital core reset are controlled
by the internal power-on reset (POR) signal circuit, which
monitors the DVDD level. Therefore, the device does not exit a
Depending on CEXT, tD may vary and, in turn, affect the mini-
PD RST
PD RST
mum hold period for the
/
pulse. The
/ pulse
must be held low for the entire tD time period to initialize the
core properly.
POR
reset until DVDD reaches 1.2 V and the
signal is released.
Rev. 0 | Page 12 of 44
Data Sheet
ADAU1979
PD RST
low pulse period by adding a
resistor across CEXT. Calculate the new tD value c as
The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock
status of the PLL. It is recommended that the PLL lock status be
read after initial power-up to ensure that the PLL outputs the
correct frequency before unmuting the audio outputs.
Reduce the required
/
tD = 1.32 × REQ × CEXT
where REQ = 64 kΩ || REXT
.
Table 9. Required Master Clock Input Frequency for
Common Sample Rates
The resistor ensures that DVDD not only discharges quickly during
a reset or an AVDDx power loss but also resets the internal blocks
correctly. Note that some power loss in this resistor is to be
expected because the resistor constantly draws current from
MCS
Frequency
MCLKIN
(Bits[2:0]) fS (kHz) Multiplication Ratio Frequency (MHz)
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
000
001
010
011
100
32
32
32
32
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
128 × fS
256 × fS
384 × fS
512 × fS
768 × fS
64 × fS
128 × fS
192 × fS
256 × fS
384 × fS
32 × fS
64 × fS
96 × fS
128 × fS
192 × fS
4.096
8.192
DVDD. The typical value for CEXT is 10 µF and 3 kΩ for REXT
This results in a time constant of
.
12.288
16.384
24.576
5.6448
11.2896
16.9344
22.5792
33.8688
6.144
12.288
18.432
24.576
36.864
6.144
12.288
18.432
24.576
36.864
6.144
12.288
18.432
24.576
36.864
tD = 1.32 × REQ × CEXT = 37.8 ms
32
where REQ = 2.866 kΩ (64 kΩ || 3 kΩ).
44.1
44.1
44.1
44.1
44.1
48
48
48
48
48
Using this equation at a set CEXT value, the REXT can be calculated
PD RST
for a desired
/
pulse period.
There is also a software reset bit (S_RST, Bit 7 of Register 0x00)
available that can be used to reset the part, but note that during an
AVDDx power loss, the software reset may not ensure proper
initialization because DVDD may not be stable.
+3.3V
AVDD1 AVDD3 AVDD2
96
96
96
96
DVDD
3.3V TO 1.8V
REGULATOR
C
0.1µF
C
10µF
R
EXT
EXT
3kΩ
MLCC X7R
96
TO INTERNAL
BLOCKS
192
192
192
192
192
+1.8V OR +3.3V
IOVDD
ADAU1979
C
0.1µF
The PLL can accept the audio frame clock (sample rate clock) as
the input, but the serial port must be configured as a slave, and
the frame clock must be fed to the device from the master. It is
strongly recommended that the PLL be disabled, reprogrammed
with the new setting, and then reenabled. A lock bit is provided
that is polled via I2C to check whether the PLL has acquired
lock.
Figure 14. DVDD Regulator Output Connections
PLL AND CLOCK
The ADAU1979 has a built-in analog PLL to provide a jitter-free
master clock to the internal ADC. The PLL must be programmed
for the appropriate input clock frequency. The PLL_CONTROL
Register 0x01 sets the PLL.
The PLL requires an external filter, which is connected at the
PLL_FILT pin (Pin 3). The recommended PLL filter circuit for
MCLK or LRCLK mode is shown in Figure 15. Using NPO
capacitors is recommended for temperature stability. Place the
filter components near the device for best performance.
The CLK_S bit (Bit 4) of Register 0x01 sets the clock source for
the PLL. The clock source can be either the MCLKIN pin or the
LRCLK pin (slave mode). In LRCLK mode, the PLL supports
sample rates between 32 kHz and 192 kHz.
In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01)
must be set to the desired input clock frequency for the MCLKIN
pin. Table 9 shows the master clock input frequency required
for the most common sample rates and the MCS bit settings.
AVDDx
AVDDx
39nF
5.6nF
2.2nF
390pF
4.87kΩ
1kΩ
PLL_FILT
PLL_FILT
LRCLK MODE
MCLK MODE
Figure 15. PLL Filter
Rev. 0 | Page 13 of 44
ADAU1979
Data Sheet
14.3kΩ
ANALOG INPUTS
32.17kΩ
32.17kΩ
AINxP
AINxN
The ADAU1979 has four differential analog inputs. The ADCs
can accommodate both dc- and ac-coupled input signals.
V
REF
The block diagram shown in Figure 16 represents the typical
input circuit.
In most audio applications, the dc content of the signal is removed
by using a coupling capacitor. However, the ADAU1979 consists
of a unique input structure that allows ac coupling of the input
signals. The typical input resistance is approximately 32 kΩ
from each input to AGNDx.
14.3kΩ
V
V
= V INPUT DIFFERENTIAL
ID
AT AINxP/AINxN = 1.5V
CM
Figure 16. Analog Input Block
The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a
48 kHz sample rate. The cutoff frequency scales directly with
the sample frequency. However, care is required in dc-coupled
applications to ensure that the common-mode dc voltage does
not exceed the specified limit. The input required for the full-
scale ADC output (0 dBFS) is typically 4.5 V rms differential.
Rev. 0 | Page 14 of 44
Data Sheet
ADAU1979
Line Inputs
Refer to Figure 18 for information about connecting the line
level inputs to the ADAU1979.
This section describes some of the possible methods to connect
the line level inputs of the ADAU1979.
Line Input Unbalanced or Single-Ended, Pseudo Differential
AC-Coupled Case
Line Input Balanced or Differential Input DC-Coupled Case
For a single-ended application, reduce the signal swing by half
because only one input is used for the signal and the other is
connected to 0 V. Doing this reduces the input signal capability
to 2.25 V rms in the single-ended application and measures
approximately −6.16 dBFS (ac only with a dc high-pass filter) at
the ADC output.
For an input signal of 4.5 V rms differential with approximately
1.5 V common-mode dc, the signal at each input pin has a 2.25
V rms or 6.36 V p-p signal swing. At a common-mode dc of 1.5 V,
the signal can swing between (1.5 + 3.18) = 4.68 V and (1.5 –
3.18) = −1.68 V at each input. Therefore, this is approximately
AINx
12.72 V p-p differential across AINx and
and measures
near 0 dBFS (ac only with a dc high-pass filter) at the ADC
output (see Figure 17).
See Figure 19 for additional information. The value of C1/C2 is
similar to the balanced ac-coupled case previously mentioned in
the Line Input Balanced or Differential Input AC-Coupled Case
section.
Line Input Balanced or Differential Input AC-Coupled Case
For connecting the ADAU1979 to a head unit amplifier output,
AINx
ac coupling is recommended. In this case, the AINx/
pins
are at a common-mode level of 1.5 V. Use the attenuator to
reduce the input level if it is more than 4.5 V rms.
Use the following equation to identify the C1 and C2 values for
the required low frequency cutoff:
C1 or C2 = 1/(2 × π × fC × Input Resistance)
where the Input Resistance of the ADAU1979 is 32.17 kΩ
typical.
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
AINx
AINx
V
V
= 4.5V rms AC
= 1.5V DC
DIFF
CM
OPTION A: DIFFERENTIAL DC-COUPLED
Figure 17. Connecting the Line Level Inputs—Differential DC-Coupled Case
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
C1
AINx
AINx
ATTENUATOR
C2
V
= 2V rms
DIFF
OPTION B: DIFFERENTIAL AC-COUPLED
Figure 18. Connecting the Line Level Inputs—Differential AC-Coupled Case
TYPICAL AUDIO POWER
AMPLIFIER OUTPUT
C1
AINx
AINx
C2
V
= 2V rms AC
IN
OPTION C: PSEUDO DIFFERENTIAL AC-COUPLED
Figure 19. Connecting the Line Level Inputs—Pseudo Differential AC-Coupled Case
Rev. 0 | Page 15 of 44
ADAU1979
Data Sheet
1-Channel Summing Mode
ADC
When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set
to 10, the Channel 1 through Channel 4 ADC data are combined
and output from the SDATAOUT1 pin. As a result, the SNR
improves by 6 dB. For this mode, all four channels must be
connected to the same input signal source.
The ADAU1979 contains four Σ-Δ ADC channels configured as
two stereo pairs with configurable differential/single-ended
inputs. The ADC can operate at a nominal sample rate of 32 kHz
up to 192 kHz. The ADCs include on-board digital antialiasing
filters with 79 dB stop-band attenuation and linear phase response.
Digital outputs are supplied through two serial data output pins
(one for each stereo pair) and a common frame clock (LRCLK)
and bit clock (BCLK). Alternatively, one of the TDM modes can
be used to support up to 16 channels on a single TDM data line.
OPTION B: DIFFERENTIAL AC-COUPLED
TYPICAL STEREO
OUTPUT
V
= 4.5V rms
C1
DIFF
AIN1
AIN1
C2
With smaller amplitude input signals, a 10-bit programmable
digital gain compensation for an individual channel is provided
to scale up the output word to full scale. Take care to avoid
overcompensation (large gain compensation), which leads to
clipping and THD degradation in the ADC.
AIN2
AIN2
Σ
AIN3
AIN3
The ADCs also have a dc offset calibration algorithm to null the
systematic dc offset of the ADC. This feature is useful for dc
measurement applications.
AIN4
AIN4
ADC SUMMING MODES
The four ADCs can be grouped into either a single stereo ADC
or a single mono ADC to increase the SNR for the application.
Two options are available: one option for summing two channels of
the ADC and another option for summing all four channels of
the ADC. Summing is performed in the digital block.
Figure 21. 1-Channel Summing Mode Connection Diagram
2-Channel Summing Mode
When the SUM_MODE bits (Bits[7:6] of Register 0x0E) are set
to 01, the Channel 1 and Channel 2 ADC data are combined
and output from the SDATAOUT1 pin. Similarly, the Channel 3
and Channel 4 ADC data are combined and output from the
SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For this
mode, both Channel 1 and Channel 2 must be connected to the
same input signal source. Similarly, Channel 3 and Channel 4
must be connected to the same input signal source.
OPTION B: DIFFERENTIAL AC-COUPLED
TYPICAL STEREO
OUTPUT
V
= 4.5V rms
C1
DIFF
AIN1
AIN1
C2
Σ
AIN2
AIN2
C3
C4
AIN3
AIN3
Σ
AIN4
AIN4
Figure 20. 2-Channel Summing Mode Connection Diagram
Rev. 0 | Page 16 of 44
Data Sheet
ADAU1979
Stereo Mode
SERIAL AUDIO DATA OUTPUT PORTS, DATA
FORMAT
In 2-channel or stereo mode, the SDATAOUT1 outputs ADC
data for Channel 1 and Channel 2, and the SDATOUT2 outputs
ADC data for Channel 3 and Channel 4. Figure 22 through
Figure 24 show the supported audio formats.
The serial audio port comprises four pins: BCLK, LRCLK,
SDATAOUT1, and SDATAOUT2. The ADAU1979 ADC outputs
are available on the SDATAOUT1 and SDATAOUT2 pins in
serial format. The BCLK and LRCLK pins serve as the bit clock
and frame clock, respectively. The port can be operated as a
master or slave and can be set either in stereo mode (2-channel
mode) or in TDM multichannel mode. The supported popular
audio formats are I2S, left justified (LJ), and right justified (RJ).
BCLK
LRCLK
SDATAOUT1
(I S MODE)
CHANNEL 1
CHANNEL 2
2
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL 4
SDATAOUT2
CHANNEL 3
2
(I S MODE)
NOTES
1. SAI = 0.
2. SDATA_FMT = 0 (I S).
2
Figure 22. I2S Audio Format
BCLK
LRCLK
SDATAOUT1
(LJ MODE)
CHANNEL 1
CHANNEL 3
CHANNEL 2
CHANNEL 4
SDATAOUT2
(LJ MODE)
NOTES
1. SDATA_FMT = 1 (LJ).
Figure 23. Left Justified Audio Format
BCLK
LRCLK
SDATAOUT1
(RJ MODE)
CHANNEL 1
CHANNEL 2
CHANNEL 4
SDATAOUT2
(RJ MODE)
CHANNEL 3
NOTES
1. SDATA_FMT = 2 (RJ, 24-BIT).
Figure 24. Right Justified Audio Format
Rev. 0 | Page 17 of 44
ADAU1979
Data Sheet
TDM Mode
(Figure 27 shows the TDM mode slot assignments). During the
unused slots, the output pin becomes high-Z so that the same
data line can be shared with other devices on the TDM bus.
Register 0x05 through Register 0x08 provide programmability
for the TDM mode. The TDM slot width, data width, and
channel assignment, as well as the pin used to output the data,
are programmable.
The TDM port can be operated as either a master or a slave.
In master mode, the BCLK and LRCLK pins are output from
the ADAU1979, whereas in slave mode, the BCLK and LRCLK
pins are set to receive the clock from the master in the system.
By default, serial data is output on the SDATAOUT1 pin;
however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be
used to change the setting so that serial data is output from the
SDATAOUT2 pin.
Both the nonpulse and pulse modes are supported. In nonpulse
mode, the LRCLK signal is typically 50% of the duty cycle, whereas
in pulse mode, the LRCLK signal must be at least one BCLK wide
(see Figure 25 and Figure 26).
The TDM mode supports two, four, eight, or 16 channels. The
ADAU1979 outputs four channels of data in the assigned slots
BCLK
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
LRCLK
2
CHANNEL 1
CHANNEL 2
8 TO 32 BCLKs
CHANNEL N
SDATA I
S
8 TO 32 BCLKs
8 TO 32 BCLKs
SDATA LJ
8 TO 32 BCLKs
8 TO 32 BCLKs
8 TO 32 BCLKs
CHANNEL N
2
CHANNEL 1
24 OR 16 BCLKs
CHANNEL 2
24 OR 16 BCLKs
SDATA I
S
24 OR 16 BCLKs
NOTES
1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS).
2
2. SDATA_FMT = 00 (I S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT).
3. BCLK_EDGE = 0.
4. LR_MODE = 0.
5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs).
Figure 25. TDM Nonpulse Mode Audio Format
BCLK
LRCLK
2
32/24/16 BCLKs
32/24/16 BCLKs
32/24/16 BCLKs
CHANNEL 1
CHANNEL 2
CHANNEL N
8 TO 32 BCLKs
SDATA I
S
8 TO 32 BCLKs
8 TO 32 BCLKs
SDATA LJ
8 TO 32 BCLKs
8 TO 32 BCLKs
8 TO 32 BCLKs
2
CHANNEL 1
24 OR 16 BCLKs
CHANNEL 2
CHANNEL N
24 OR 16 BCLKs
SDATA I
S
24 OR 16 BCLKs
NOTES
1. SAI = 001 (2 CHANNELS), 010 (4 CHANNELS), 011 (8 CHANNELS), 100 (16 CHANNELS)
2
2. SDATA_FMT = 00 (I S), 01 (LJ), 10 (RJ, 24-BIT), 11 (RJ, 16-BIT)
3. BCLK_EDGE = 0
4. LR_MODE = 1
5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 (16 BCLKs)
Figure 26. TDM Pulse Mode Audio Format
Rev. 0 | Page 18 of 44
Data Sheet
ADAU1979
LRCLK
NUMBER OF BCLK CYCLES = (NUMBER OF BCLKs/SLOT) × NUMBER OF SLOTS
BCLK
SLOT1
SLOT2
SDATAOUTx—TDM2
SDATAOUTx—TDM4
SDATAOUTx—TDM8
SDATAOUTx—TDM16
SLOT1
SLOT2
SLOT3
SLOT4
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SLOT1
SLOT2
SLOT3
SLOT4
SLOT5
SLOT6
SLOT7
SLOT8
SLOT9
SLOT10
SLOT11
SLOT12
SLOT13
SLOT14
SLOT15
SLOT16
DATA WIDTH
16/24 BITS
HIGH-Z
HIGH-Z
SLOT WIDTH
16/24/32 BITS
Figure 27. TDM Mode Slot Assignment
Table 10. Bit Clock Frequency TDM Mode
BCLK Frequency
24 Bit Clocks Per Slot
48 × fS
96 × fS
192 × fS
Mode
TDM2
TDM4
TDM8
TDM16
16 Bit Clocks Per Slot
32 × fS
64 × fS
128 × fS
256 × fS
32 Bit Clocks Per Slot
64 × fS
128 × fS
256 × fS
512 × fS
384 × fS
The bit clock frequency depends on the sample rate, the slot
width, and the number of bit clocks per slot. Use Table 10 to
calculate the BCLK frequency.
frame. There are two options in this case: either operate with a
32-bit data width in TDM4 or operate with a 16-bit data width
in TDM8. In slave mode, this limitation does not exist because
the bit clock and frame clock are fed to the ADAU1979. Various
combinations of BCLK frequencies and modes are available, but
take care to choose the combination that is most suitable for the
application.
The sample rate (fS) can range from 8 kHz up to 192 kHz.
However, in master mode, the maximum bit clock frequency
(BCLK) is 24.576 MHz. For example, for a sample rate of
192 kHz, 128 × fS is the maximum possible BCLK frequency.
Therefore, only 128-bit clock cycles are available per TDM
Rev. 0 | Page 19 of 44
ADAU1979
Data Sheet
SLAVE
SLAVE
DSP
Connection Options
ADAU1979
Figure 28 through Figure 32 show the available options for
connecting the serial audio port in I2S or TDM mode. In
TDM mode, it is recommended to include a pull-down resistor
on the data signal to prevent the line from floating when the
SDATAOUTx pin of the ADAU1979 becomes high-Z during an
inactive period. Select a resistor value such that no more than
2 mA is drawn from the SDATAOUTx pin. Although the resistor
value is typically in the 10 kΩ to 47 kΩ range, the appropriate
resistor value depends on the devices on the data bus.
BCLK
LRCLK
SDATAOUTx
MASTER
ADAU1979
OR
SIMILAR ADC
MASTER
SLAVE
BCLK
LRCLK
ADAU1979
DSP
SDATAOUTx
BCLK
LRCLK
Figure 31. Serial Port Connection Option 4—TDM Mode, Second ADC Master
SDATAOUT1
SDATAOUT2
SLAVE
MASTER
DSP
ADAU1979
Figure 28. Serial Port Connection Option 1—I2S/Left Justified/Right Justified
Modes, ADAU1979 Master
BCLK
LRCLK
SLAVE
MASTER
DSP
SDATAOUTx
ADAU1979
BCLK
LRCLK
SLAVE
SDATAOUT1
SDATAOUT2
ADAU1979
OR
SIMILAR ADC
BCLK
LRCLK
Figure 29. Serial Port Connection Option 2—I2S/Left Justified/Right Justified
Modes, ADAU1979 Slave
SDATAOUTx
MASTER
SLAVE
DSP
ADAU1979
Figure 32. Serial Port Connection Option 5—TDM Mode, DSP Master
BCLK
LRCLK
SDATAOUTx
SLAVE
ADAU1979
OR
SIMILAR ADC
BCLK
LRCLK
SDATAOUTx
Figure 30. Serial Port Connection Option 3—TDM Mode, ADAU1979 Master
Rev. 0 | Page 20 of 44
Data Sheet
ADAU1979
CONTROL PORTS
The ADAU1979 control port allows two modes of operation,
either 2-wire I2C mode or 4-wire SPI mode, for setting the
internal registers of the device. Both the I2C and SPI modes
allow read and write capability of the registers. All the registers
are eight bits wide. The registers start at Address 0x00 and end
at Address 0x1A.
ADDR1 and ADDR0 pins, which set the chip address to the
desired value.
The 7-bit I2C device address can be set to one of four of the
following possible options using the ADDR1 and ADDR0 pins:
•
•
•
•
I2C Device Address 0010001 (0x11)
I2C Device Address 0110001 (0x31)
I2C Device Address 1010001 (0x51)
I2C Device Address 1110001 (0x71)
The control port in both I2C and SPI modes is slave only and,
therefore, requires the master in the system to operate. The
registers can be accessed with or without the master clock to the
device. However, to operate the PLL, serial audio ports, and
boost converter, the master clock is necessary.
By default, the ADAU1979 operates in I2C mode, but the device
can be put into SPI mode by pulling the
times.
In I2C mode, both the SDA and SCL pins require that an
appropriate pull-up resistor be connected to IOVDD. Ensure
that the voltage on these signal lines does not exceed the voltage
on the IOVDD pin. Figure 44 shows a typical connection
diagram for the I2C mode.
CLATCH
pin low three
Calculate the value of the pull-up resistor for the SDA or SCL
pin as follows.
The control port pins are multifunctional, depending on the
mode in which the device is operating. Table 12 describes the
control port pin functions in both modes.
Minimum RPULL UP = (IOVDD − VIL)/ISINK
I2C MODE
where:
IOVDD is the I/O supply voltage, typically ranging from 1.8 V
up to 3.3 V.
The ADAU1979 supports a 2-wire serial (I2C-compatible) bus
protocol. Two pins, serial data (SDA) and serial clock (SCL), are
used to communicate with the system I2C master controller. In
I2C mode, the ADAU1979 is always a slave on the bus, meaning
that it cannot initiate a data transfer. Each slave device on the
I2C bus is recognized by a unique device address. The device
VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as
per the I2C specifications).
I
SINK is the current sink capability of the I/O pin.
The SDA pin can sink 2 mA of current; therefore, the minimum
value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ.
W
address and R/ byte for the ADAU1979 are shown in Table 11.
The address resides in the first seven bits of the I2C write. Bit 7
and Bit 6 of the I2C address for the ADAU1979 are set by the
levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C
Depending on the capacitance of the printed circuit board, the
speed of the bus can be restricted to meet the rise time and fall
time specifications.
W
byte (the R/ bit) from the master identifies whether it is a read
For fast mode with a bit rate of around 1 Mbps, the rise time
must be less than 550 ns. Use the following equation to
determine whether the rise time specification can be met:
or write operation. Logic Level 1 in the LSB (Bit 0) corresponds
to a read operation, and Logic Level 0 corresponds to a write
operation.
t = 0.8473 × RPULL UP × CBOARD
Table 11. I2C First Byte Format
where CBOARD must be less than 236 pF to meet the 300 ns rise
time requirement.
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADDR1 ADDR0
1
0
0
0
1
R/W
For the SCL pin, the calculations depend on the current sink
capability of the I2C master used in the system.
The first seven bits of the I2C chip address for the ADAU1979
are xx10001. Set Bit 7 and Bit 6 of the address byte using the
Table 12. Control Port Pin Functions
I2C Mode
SPI Mode
Pin No.
17
18
Mnemonic
SDA/COUT
SCL/CCLK
ADDR0/CLATCH
ADDR1/CIN
Pin Function
SDA data
SCL clock
I2C Device Address Bit 0
I2C Device Address Bit 1
Pin Type
Pin Function
COUT data
CCLK clock
CLATCH chip select
CIN data
Pin Type
I/O
O
I
I
I
I
I
19
20
I
Rev. 0 | Page 21 of 44
ADAU1979
Data Sheet
Addressing
W
The R/ bit determines the direction of the data. A Logic 0 on the
LSB of the first byte means that the master is to write information
to the slave, whereas a Logic 1 means that the master is to read
information from the slave after writing the address and repeating
the start address. A data transfer takes place until a master initiates
a stop condition. A stop condition occurs when SDA transitions
from low to high while SCL is held high.
Initially, each device on the I2C bus is in an idle state and monitors
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address/data stream
follows. All devices on the bus respond to the start condition
and acquire the next eight bits from the master (the 7-bit address
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
during normal read and write operations, the ADAU1979
immediately jumps to the idle condition.
W
plus the R/ bit) MSB first. The master sends the 7-bit device
W
address with the R/ bit to all the slaves on the bus. The device
with the matching address responds by pulling the data line
(SDA) low during the ninth clock pulse. This ninth bit is known
as an acknowledge bit. All other devices withdraw from the bus
at this point and return to the idle condition.
Figure 33 and Figure 34 use the following abbreviations:
ACK = acknowledge
No ACK = no acknowledge
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SCL
SDA
FIRST BYTE (DEVICE ADDRESS)
SECOND BYTE (REGISTER ADDRESS)
THIRD BYTE (DATA)
ADDR1 ADDR0
1
0
0
0
1
R/W
ACK
ADAU1979
ACK
ADAU1979
STOP
START
Figure 33. I2C Write to ADAU1979 Single Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SCL
FIRST BYTE (DEVICE ADDRESS)
SECOND BYTE (REGISTER ADDRESS)
ADDR1 ADDR0
1
0
0
0
1
R/W
SDA
ACK
ADAU1979
ACK
ADAU1979
START
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SCL
SDA
THIRD BYTE (DEVICE ADDRESS)
DATA BYTE FROM ADAU1979
ADDR1 ADDR0
1
0
0
0
1
R/W
NO ACK
ACK
ADAU1979
REPEAT START
STOP
Figure 34. I2C Read from ADAU1979 Single Byte
Rev. 0 | Page 22 of 44
Data Sheet
ADAU1979
I2C Read and Write Operations
W
followed by the chip address byte with the R/ bit set to 1
(read). This causes the ADAU1979 SDA to reverse and begin
driving data back to the master. The master then responds every
ninth pulse with an acknowledge pulse to the ADAU1979.
Figure 35 shows the format of a single-word I2C write
operation. Every ninth clock pulse, the ADAU1979 issues an
acknowledge by pulling SDA low.
Figure 38 shows the format of a burst mode I2C read sequence.
This figure shows an example of a read from sequential single-
byte registers. The ADAU1979 increments its address registers
after every byte because the ADAU1979 uses an 8-bit register
address.
Figure 36 shows the format of a burst mode I2C write sequence.
This figure shows an example of a write to sequential single-byte
registers. The ADAU1979 increments its address register after
every byte because the requested address corresponds to a
register or memory area with a 1-byte word length.
Figure 37 shows the format of a single-word I2C read operation.
Figure 35 to Figure 38 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
W
Note that the first R/ bit is 0, indicating a write operation.
This is because the address still needs to be written to set up the
internal address. After the ADAU1979 acknowledges the receipt
of the address, the master must issue a repeated start command
S
CHIP ADDRESS,
R/W = 0
AS
REGISTER ADDRESS
8 BITS
AS
DATA BYTE
P
Figure 35. Single-Word I2C Write Format
S
CHIP
AS REGISTER
CHIP
AS DATA AS DATA AS DATA AS DATA AS ...
P
ADDRESS,
R/W = 0
ADDRESS ADDRESS,
8 BITS R/W = 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 36. Burst Mode I2C Write Format
S
CHIP
ADDRESS,
R/W = 0
AS
REGISTER
ADDRESS
8 BITS
AS
S
CHIP
ADDRESS,
R/W = 1
AS
DATA
BYTE 1
P
Figure 37. Single-Word I2C Read Format
S
CHIP
ADDRESS,
R/W = 0
AS REGISTER AS
ADDRESS
S
CHIP
ADDRESS,
R/W = 1
AS DATA AM DATA AM ...
BYTE 1 BYTE 2
P
8 BITS
Figure 38. Burst Mode I2C Read Format
Rev. 0 | Page 23 of 44
ADAU1979
Data Sheet
Register Address
SPI MODE
By default, the ADAU1979 is in I2C mode. To invoke SPI control
The 8-bit address word is decoded to a location in one of the
registers. This address is the location of the appropriate register.
CLATCH
mode, pull
low three times. This is achieved by perform-
ing three dummy writes to the SPI port (the ADAU1979 does not
acknowledge these three writes, see Figure 39). Beginning with the
fourth SPI write, data can be written to or read from the device.
The ADAU1979 can be taken out of SPI mode only by a full
reset initiated by power cycling the device.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode SPI write, an initial register
address is written followed by a continuous sequence of data for
consecutive register locations.
CLATCH
The SPI port uses a 4-wire interface, consisting of the
CCLK, CIN, and COUT signals, and it is always a slave port.
CLATCH
,
A sample timing diagram for a single-word SPI write operation
to a register is shown in Figure 40. A sample timing diagram of
a single-word SPI read operation is shown in Figure 41. The
COUT pin transitions being high-Z to being driven at the
beginning of Byte 3. In this example, Byte 0 to Byte 1 contain
the device address, the R/ bit, and the register address to be
read. Subsequent bytes carry the data from the device.
The
signal goes low at the beginning of a transaction
and high at the end of a transaction. The CCLK signal latches
COUT on a low-to-high transition. COUT data is shifted out of
the ADAU1979 on the falling edge of CCLK and is clocked into
a receiving device, such as a microcontroller, on the CCLK
rising edge. The CIN signal carries the serial input data, and the
COUT signal carries the serial output data. The COUT signal
remains tristated until a read operation is requested. This allows
direct connection to other SPI-compatible peripheral COUT ports
for sharing the same system controller port. All SPI transactions
have the same basic generic control word format, as shown in
Table 15. A timing diagram is shown in Figure 3. Write all data
MSB first.
W
Standalone Mode
The ADAU1979 can also operate in standalone mode. However,
in standalone mode, the boost converter, microphone bias, and
diagnostics blocks are powered down. To set the device in
standalone mode, pull the SA_MODE pin to IOVDD. In this
mode, some pins change functionality to provide more flexibility
(see Table 14 for more information).
W
Chip Address R/
Table 14. Pin Functionality in Standalone Mode
Pin Function1
Setting
Description
W
The LSB of the first byte of an SPI transaction is a R/ bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in Table 13.
ADDR0
0
1
I2S SAI format
TDM modes, determined by the
SDATAOUT2 pin
W
Table 13. SPI Address and R/ Byte Format
ADDR1
SDA
0
1
0
1
0
1
0
1
Master mode SAI
Slave mode SAI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
R/W
MCLK = 256 × fS, PLL on
MCLK = 384 × fS, PLL on
48 kHz sample rate
96 kHz sample rate
TDM4—LRCLK pulse
TDM8—LRCLK pulse
SCL
SDATAOUT2
1 Pin functionality, not full pin names, is listed. See Table 12 for additional
information.
Table 15. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Data[7:0]
Byte 31
Device Address[6:0], R/W
Register Address[7:0]
Data[7:0]
1 Continues to end of data.
Rev. 0 | Page 24 of 44
Data Sheet
ADAU1979
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLATCH
CCLK
CIN
Figure 39. SPI Mode Initial Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21 22
23
24
25
14
CLATCH
CCLK
DEVICE ADDRESS (7 BITS)
R/W
REGISTER ADDRESS BYTE
DATA BYTE
CIN
Figure 40. SPI Write to ADAU1979 Clocking (Single-Word Write Mode)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21 22
23
24
25
14
CCLK
CLATCH
DEVICE ADDRESS (7 BITS)
REGISTER ADDRESS BYTE
DATA BYTE
CIN
R/W
DATA BYTE FROM ADAU1979
COUT
Figure 41. SPI Read from ADAU1979 Clocking (Single-Word Read Mode)
CLATCH
CCLK
CIN
DATA BYTE1
DEVICE
ADDRESS
BYTE
REGISTER
ADDRESS
BYTE
DATA BYTE2
DATA BYTE n – 1
DATA BYTE n
Figure 42. SPI Write to ADAU1979 (Multiple Bytes)
CLATCH
CCLK
CIN
DEVICE
ADDRESS
BYTE
REGISTER
ADDRESS
BYTE
COUT
DATA BYTE1
DATA BYTE2
DATA BYTE3
DATA BYTE n – 1
DATA BYTE n
Figure 43. SPI Read from ADAU1979 (Multiple Bytes)
Rev. 0 | Page 25 of 44
ADAU1979
Data Sheet
REGISTER SUMMARY
Table 16. REGMAP_ADAU1979 Register Summary
Reg Name
Bits Bit 7
[7:0] S_RST
[7:0] PLL_LOCK
[7:0]
Bit 6
Bit 5
Bit 4
Bit 3
RESERVED
RESERVED
RESERVED
RESERVED
VREF_EN ADC_EN4
SAI
DATA_WIDTH LR_MODE
Bit 2
Bit 1
MCS
Bit 0
Reset
0x00
0x41
RW
RW
RW
0x00 M_POWER
0x01 PLL_CONTROL
0x02 RESERVED
0x03 RESERVED
PWUP
PLL_MUTE
RESERVED
CLK_S
Reserved Reserved
Reserved Reserved
[7:0]
0x04 BLOCK_POWER_SAI [7:0] LR_POL
BCLKEDGE
LDO_EN
ADC_EN3 ADC_EN2
FS
ADC_EN1
0x3F
0x02
0x00
0x10
0x32
0xF0
0xA0
0xA0
0xA0
0xA0
0x02
0xFF
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0x05 SAI_CTRL0
[7:0]
SDATA_FMT
0x06 SAI_CTRL1
[7:0] SDATA_SEL
SLOT_WIDTH
SAI_MSB
BCLKRATE SAI_MS
0x07 SAI_CMAP12
0x08 SAI_CMAP34
0x09 SAI_OVERTEMP
0x0A POSTADC_GAIN1
0x0B POSTADC_GAIN2
0x0C POSTADC_GAIN3
0x0D POSTADC_GAIN4
0x0E MISC_CONTROL
0x0F RESERVED
[7:0]
CMAP_C2
CMAP_C4
CMAP_C1
[7:0]
CMAP_C3
[7:0] SAI_DRV_C4 SAI_DRV_C3
SAI_DRV_C2 SAI_DRV_C1 DRV_HIZ
PADC_GAIN1
RESERVED RESERVED OT
[7:0]
[7:0]
[7:0]
[7:0]
PADC_GAIN2
PADC_GAIN3
PADC_GAIN4
[7:0]
SUM_MODE
RESERVED
RESERVED
MMUTE
RESERVED
RESERVED
DC_CAL
RESERVED
[7:0]
RESERVED
0x10 RESERVED
[7:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED RESERVED RESERVED 0x0F
RESERVED RESERVED RESERVED 0x00
RESERVED RESERVED RESERVED 0x00
RESERVED RESERVED RESERVED 0x00
RESERVED RESERVED RESERVED 0x00
RESERVED RESERVED RESERVED 0x20
RESERVED RESERVED RESERVED 0x00
0x11 RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0] RESERVED
[7:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0x12 RESERVED
0x13 RESERVED
0x14 RESERVED
0x15 RESERVED
0x16 RESERVED
0x17 RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Reserved Reserved
0x18 RESERVED
[7:0]
RESERVED
ADC_CLIP4
DC_HPF_C4
RESERVED RESERVED RESERVED Reserved Reserved
0x19 ASDC_CLIP
0x1A DC_HPF_CAL
[7:0]
RESERVED
DC_SUB_C2 DC_SUB_C1
ADC_CLIP3 ADC_CLIP2 ADC_CLIP1 0x00
DC_HPF_C3 DC_HPF_C2 DC_HPF_C1 0x00
RW
RW
[7:0] DC_SUB_C4 DC_SUB_C3
Rev. 0 | Page 26 of 44
Data Sheet
ADAU1979
REGISTER DETAILS
MASTER POWER AND SOFT RESET REGISTER
Address: 0x00, Reset: 0x00, Name: M_POWER
The power management control register enables the boost regulator, microphone bias, PLL, band gap reference, ADC, and LDO regulator.
Table 17. Bit Descriptions for M_POWER
Bits Bit Name Settings Description
Reset Access
7
S_RST
Software Reset. The software reset resets all internal circuitry and all control registers to
their respective default states. It is not necessary to reset the ADAU1979 during a power-
up or power-down cycle.
0x0
RW
0
1
Normal Operation.
Software Reset.
Reserved.
[6:1] RESERVED
PWUP
0x00
0x0
RW
RW
0
Master Power-Up Control. The master power-up control fully powers up or powers down
the ADAU1979. This must be set to 1 to power up the ADAU1979. Individual blocks can
be powered down via their respective power control registers.
0
1
Full Power-Down.
Master Power-Up.
Rev. 0 | Page 27 of 44
ADAU1979
Data Sheet
PLL CONTROL REGISTER
Address: 0x01, Reset: 0x41, Name: PLL_CONTROL
Table 18. Bit Descriptions for PLL_CONTROL
Bits Bit Name
Settings Description
PLL Lock Status. PLL lock status bit. When set to 1, the PLL is locked.
PLL Not Locked.
Reset Access
7
PLL_LOCK
0x0
R
0
1
PLL Locked.
6
PLL_MUTE
PLL Unlock Automute. When set to 1, it mutes the ADC output if PLL becomes unlocked.
No Automatic Mute on PLL Unlock.
Automatic Mute with PLL Unlock.
0x1
RW
0
1
5
4
RESERVED
CLK_S
Reserved.
0x0
0x0
RW
RW
PLL Clock Source Select. Selecting input clock source for PLL.
MCLK Used for PLL Input.
LRCLK Used for PLL Input; Only Supported for Sample Rates in the Range of 32 kHz to
192 kHz.
0
1
3
RESERVED
Reserved.
0x0
0x1
RW
RW
[2:0] MCS
Master Clock Select. MCS bits determine the frequency multiplication ratio of the PLL. It
must be set based on the input MCLK frequency and sample rate.
001 256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
010 384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
011 512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
100 768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
000 128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).
101 Reserved.
110 Reserved.
111 Reserved.
Rev. 0 | Page 28 of 44
Data Sheet
ADAU1979
BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER
Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI
Table 19. Bit Descriptions for BLOCK_POWER_SAI
Bits Bit Name
Settings
Description
Reset Access
7
6
5
4
3
2
1
0
LR_POL
Sets LRCLK Polarity
LRCLK Low then High
LRCLK High then Low
0x0
0x0
0x1
0x1
0x1
0x1
0x1
0x1
RW
RW
RW
RW
RW
RW
RW
RW
0
1
BCLKEDGE
LDO_EN
Sets the Bit Clock Edge on Which Data Changes
Data Changes on Falling Edge
Data Changes on Rising Edge
LDO Regulator Enable
LDO Powered Down
LDO Enabled
0
1
0
1
VREF_EN
ADC_EN4
ADC_EN3
ADC_EN2
ADC_EN1
Voltage Reference Enable
Voltage Reference Powered Down
Voltage Reference Enabled
ADC Channel 4 Enable
ADC Channel Powered Down
ADC Channel Enabled
0
1
0
1
ADC Channel 3 Enable
ADC Channel Powered Down
ADC Channel Enabled
0
1
ADC Channel 2 Enable
ADC Channel Powered Down
ADC Channel Enabled
0
1
ADC Channel 1 Enable
0
1
ADC Channel Powered Down
ADC Channel Enabled
Rev. 0 | Page 29 of 44
ADAU1979
Data Sheet
SERIAL PORT CONTROL REGISTER 1
Address: 0x05, Reset: 0x02, Name: SAI_CTRL0
Table 20. Bit Descriptions for SAI_CTRL0
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SDATA_FMT
Serial Data Format
00 I2S Data Delayed from Edge of LRCLK by 1 BCLK
0x0
RW
01 Left Justified
10 Right Justified, 24-Bit Data
11 Right Justified, 16-Bit Data
Serial Port Mode
[5:3]
[2:0]
SAI
FS
0x0
RW
RW
000 Stereo (I2S, LJ, RJ)
001 TDM2
010 TDM4
011 TDM8
100 TDM16
Sampling Rate
0x2
000 8 kHz to 12 kHz
001 16 kHz to 24 kHz
010 32 kHz to 48 kHz
011 64 kHz to 96 kHz
100 128 kHz to 192 kHz
Rev. 0 | Page 30 of 44
Data Sheet
ADAU1979
SERIAL PORT CONTROL REGISTER 2
Address: 0x06, Reset: 0x00, Name: SAI_CTRL1
Table 21. Bit Descriptions for SAI_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
7
SDATA_SEL
SDATAOUTx Pin Selection in TDM4 or Greater Modes
SDATAOUT1 used for output
SDATAOUT2 used for output
0x0
RW
0
1
[6:5]
SLOT_WIDTH
Number of BCLKs per Slot in TDM Mode
0x0
RW
00 32 BCLKs per TDM slot
01 24 BCLKs per TDM slot
10 16 BCLKs per TDM slot
11 Reserved
4
3
2
1
DATA_WIDTH
LR_MODE
SAI_MSB
Output Data Bit Width
24-bit data
16-bit data
0x0
0x0
0x0
0x0
RW
RW
RW
RW
0
1
Sets LRCLK Mode
50% duty cycle clock
Pulse—LRCLK is a single BCLK cycle wide pulse
Sets Data to be Input/Output Either MSB or LSB First
MSB first data
0
1
0
1
LSB first data
BCLKRATE
Sets the Number of Bit Clock Cycles per Data Channel Generated When in
Master Mode
0
1
32 BCLKs/channel
16 BCLKs/channel
0
SAI_MS
Sets the Serial Port into Master or Slave Mode
LRCLK/BCLK slave
LRCLK/BCLK master
0x0
RW
0
1
Rev. 0 | Page 31 of 44
ADAU1979
Data Sheet
CHANNEL 1 AND CHANNEL 2 MAPPING FOR OUTPUT SERIAL PORTS REGISTER
Address: 0x07, Reset: 0x10, Name: SAI_CMAP12
Table 22. Bit Descriptions for SAI_CMAP12
Bits
Bit Name
Settings
Description
Reset
Access
[7:4]
CMAP_C2
ADC Channel 2 Output Mapping.
0x1
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. 0 | Page 32 of 44
Data Sheet
ADAU1979
Bits
Bit Name
Settings
Description
Reset
Access
[3:0]
CMAP_C1
ADC Channel 1 Output Mapping. If CMAP is set to a slot that does not
exist for a given serial mode, that channel is not driven. For example, if
CMAP is set to Slot 9 and the serial format is I2S, that channel is not driven.
If more than one channel is set to the same slot, only the lowest channel
number is driven; other channels are not driven.
0x0
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. 0 | Page 33 of 44
ADAU1979
Data Sheet
CHANNEL 3 AND CHANNEL 4 MAPPING FOR OUTPUT SERIAL PORTS REGISTER
Address: 0x08, Reset: 0x32, Name: SAI_CMAP34
Table 23. Bit Descriptions for SAI_CMAP34
Bits Bit Name Settings Description
Reset Access
[7:4] CMAP_C4
ADC Channel 4 Output Mapping
0000 Slot 1 for Channel
0x3
RW
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
Rev. 0 | Page 34 of 44
Data Sheet
ADAU1979
Bits Bit Name Settings Description
Reset Access
[3:0] CMAP_C3
ADC Channel 3 Output Mapping
0x2
RW
0000 Slot 1 for Channel
0001 Slot 2 for Channel
0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)
0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)
0100 Slot 5 for Channel (TDM8+ only)
0101 Slot 6 for Channel (TDM8+ only)
0110 Slot 7 for Channel (TDM8+ only)
0111 Slot 8 for Channel (TDM8+ only)
1000 Slot 9 for Channel (TDM16 only)
1001 Slot 10 for Channel (TDM16 only)
1010 Slot 11 for Channel (TDM16 only)
1011 Slot 12 for Channel (TDM16 only)
1100 Slot 13 for Channel (TDM16 only)
1101 Slot 14 for Channel (TDM16 only)
1110 Slot 15 for Channel (TDM16 only)
1111 Slot 16 for Channel (TDM16 only)
SERIAL OUTPUT DRIVE CONTROL AND OVERTEMPERATURE PROTECTION STATUS REGISTER
Address: 0x09, Reset: 0xF0, Name: SAI_OVERTEMP
Table 24. Bit Descriptions for SAI_OVERTEMP
Bits Bit Name
Settings Description
Reset
Access
7
SAI_DRV_C4
Channel 4 Serial Output Drive Enable.
0x1
RW
0
1
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_C4.
Rev. 0 | Page 35 of 44
ADAU1979
Data Sheet
Bits Bit Name
Settings Description
Channel 3 Serial Output Drive Enable.
Reset
Access
6
5
4
3
SAI_DRV_C3
SAI_DRV_C2
SAI_DRV_C1
DRV_HIZ
0x1
RW
0
1
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_C3.
Channel 2 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_C2.
Channel 1 Serial Output Drive Enable.
Channel Not Driven on Serial Output Port.
Channel Driven on Serial Output Port. Slot determined by CMAP_C1.
Select Whether to Tristate Unused SAI Channels or Actively Drive These Data Slots.
Unused outputs driven low.
0x1
0x1
0x0
RW
RW
RW
0
1
0
1
0
1
Unused outputs high-Z.
[2:1] RESERVED
OT
Reserved
0x0
0x0
R
R
0
Overtemperature Status
0
1
Normal Operation.
Overtemperature Fault.
POST ADC GAIN CHANNEL 1 CONTROL REGISTER
Address: 0x0A, Reset: 0xA0, Name: POSTADC_GAIN1
Table 25. Bit Descriptions for POSTADC_GAIN1
Bits
Bit Name
Settings
Description
Reset
Access
RW
[7:0]
PADC_GAIN1
Channel 1 Post ADC Gain
0xA0
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
Rev. 0 | Page 36 of 44
Data Sheet
ADAU1979
POST ADC GAIN CHANNEL 2 CONTROL REGISTER
Address: 0x0B, Reset: 0xA0, Name: POSTADC_GAIN2
Table 26. Bit Descriptions for POSTADC_GAIN2
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN2
Channel 2 Post ADC Gain
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
POST ADC GAIN CHANNEL 3 CONTROL REGISTER
Address: 0x0C, Reset: 0xA0, Name: POSTADC_GAIN3
Table 27. Bit Descriptions for POSTADC_GAIN3
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN3
Channel 3 Post ADC Gain
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
Rev. 0 | Page 37 of 44
ADAU1979
Data Sheet
POST ADC GAIN CHANNEL 4 CONTROL REGISTER
Address: 0x0D, Reset: 0xA0, Name: POSTADC_GAIN4
Table 28. Bit Descriptions for POSTADC_GAIN4
Bits
Bit Name
Settings
Description
Reset
Access
[7:0]
PADC_GAIN4
Channel 4 Post ADC Gain.
0xA0
RW
00000000 +60 dB Gain
00000001 +59.625 dB Gain
00000010 +59.25 dB Gain
... ...
10011111 +0.375 dB Gain
10100000 0 dB Gain
10100001 −0.375 dB Gain
... ...
11111110 −35.625 dB Gain
11111111 Mute
HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE REGISTER
Address: 0x0E, Reset: 0x02, Name: MISC_CONTROL
Rev. 0 | Page 38 of 44
Data Sheet
ADAU1979
Table 29. Bit Descriptions for MISC_CONTROL
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
SUM_MODE
Channel Summing Mode Control for Higher SNR
0x0
RW
00 Normal 4-Channel Operation
01 2-Channel Summing Operation (See the ADC Summing Modes Section)
10 1-Channel Summing Operation (See the ADC Summing Modes Section)
11 Reserved
Reserved
5
4
RESERVED
MMUTE
0x0
0x0
RW
RW
Master Mute
0
1
Normal Operation
All Channels Muted
Reserved
[3:1]
0
RESERVED
DC_CAL
0x0
0x0
RW
RW
DC Calibration Enable
Normal Operation
Perform DC Calibration
0
1
ADC CLIPPING STATUS REGISTER
Address: 0x19, Reset: 0x00, Name: ASDC_CLIP
Table 30. Bit Descriptions for ASDC_CLIP
Bits
[7:4]
3
Bit Name
RESERVED
ADC_CLIP4
Settings
Description
Reset
0x0
Access
Reserved
RW
R
ADC Channel 4 Clip Status
Normal Operation
ADC Channel Clipping
ADC Channel 3 Clip Status
Normal Operation
ADC Channel Clipping
ADC Channel 2 Clip Status
Normal Operation
ADC Channel Clipping
ADC Channel 1 Clip Status
Normal Operation
0x0
0
1
2
1
0
ADC_CLIP3
ADC_CLIP2
ADC_CLIP1
0x0
0x0
0x0
R
R
R
0
1
0
1
0
1
ADC Channel Clipping
Rev. 0 | Page 39 of 44
ADAU1979
Data Sheet
DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER
Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL
Table 31. Bit Descriptions for DC_HPF_CAL
Bits
Bit Name
Settings
Description
Reset
Access
7
DC_SUB_C4
Channel 4 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 3 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 2 DC Subtraction from Calibration
No DC Subtraction
DC Value from DC Calibration Is Subtracted
Channel 1 DC Subtraction from Calibration
No DC Subtraction
0x0
RW
0
1
6
5
4
3
2
1
0
DC_SUB_C3
DC_SUB_C2
DC_SUB_C1
DC_HPF_C4
DC_HPF_C3
DC_HPF_C2
DC_HPF_C1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
DC Value from DC Calibration Is Subtracted
Channel 4 DC High-Pass Filter Enable
HPF Off
0
1
HPF On
Channel 3 DC High-Pass Filter Enable
HPF Off
HPF On
0
1
Channel 2 DC High-Pass Filter Enable
HPF Off
HPF On
0
1
Channel 1 DC High-Pass Filter Enable
HPF Off
HPF On
0
1
Rev. 0 | Page 40 of 44
Data Sheet
ADAU1979
TYPICAL APPLICATION CIRCUIT
+3.3V
10µF
MLCC X7R
C12
0.1µF
C13
0.1µF
C14
0.1µF
* FOR MORE INFORMATION ABOUT CALCULATING THE VALUE
FOR R
, SEE THE POWER-ON RESET SEQUENCE SECTION.
EXT
DVDD
3.3V TO 1.8V
REGULATOR
REFER TO THE SPECIFICATIONS
SECTION FOR THE TYPICAL
DIFFERENTIAL INPUT VOLTAGE
C15
0.1µF
C16
R
*
EXT
10µF
ADAU1979
MLCC X7R
AIN1
+1.8V OR +3.3V
ADC
ADC
ADC
ADC
LINE1
AIN1
IOVDD
C7
0.1µF
AIN2
LINE2
AIN2
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
AIN3
TO DSP
LINE3
AIN3
AIN4
IOVDD
LINE4
AIN4
SCL/CCLK
SDA/COUT
ADDR1/CIN
AGND1
AVDD2
AGND3
2
BG
REF
I
C/SPI
MICRO-
CONTROLLER
PLL
CONTROL
ADDR0/CLATCH
PD/RST
AGND2
AGND2
R13
R14
NOTES
1. R9, R10 = TYPICAL 2kΩ FOR IOVDD = 3.3V, 1kΩ FOR IOVDD = 1.8V.
2. R11 THROUGH R14 USED FOR SETTING THE DEVICE IN I2C MODE.
3. R16 = TYPICAL 47kΩ FOR IOVDD = 3.3V, 22kΩ FOR IOVDD = 1.8V.
4. PLL LOOP FILTER:
C18
10µF
C19
0.1µF
C21
R17
C20
PLL INPUT OPTION
LRCLK
MCLK
R17
C20
C21
4.87kΩ
2200pF
39nF
1kΩ
+3.3V (AVDD2)
390pF
5600pF
Figure 44. Typical Application Circuit, Four Inputs, I2C and I2S Mode
Rev. 0 | Page 41 of 44
ADAU1979
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
4.05
3.90 SQ
3.75
EXPOSED
PAD
21
20
10
11
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-40-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
–40°C to +105°C
–40°C to +105°C
Package Description
Package Option
ADAU1979WBCPZ
ADAU1979WBCPZ-RL
EVAL-ADAU1979Z
40-Lead LFCSP_WQ
40-Lead LFCSP, 13”Tape and Reel
Evaluation Board
CP-40-14
CP-40-14
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1979WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. 0 | Page 42 of 44
Data Sheet
NOTES
ADAU1979
Rev. 0 | Page 43 of 44
ADAU1979
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11408-0-11/13(0)
Rev. 0 | Page 44 of 44
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