EVAL-ADCMP563BRQ [ADI]
Dual, High Speed ECL Comparators; 双通道，高速ECL比较器
| 型号： | EVAL-ADCMP563BRQ |
| 厂家： | 
ADI |
| 描述： | Dual, High Speed ECL Comparators |
| 文件： | 总16页 (文件大小：280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, High Speed ECL Comparators
ADCMP563/ADCMP564
FUNCTIONAL BLOCK DIAGRAM
FEATURES
HYS*
Differential ECL-compatible outputs
700 ps propagation delay input to output
75 ps propagation delay dispersion
Input common-mode range: –2.0 V to +3.0 V
Robust input protection
NONINVERTING
Q OUTPUT
INPUT
ADCMP563/
ADCMP564
INVERTING
Q OUTPUT
INPUT
Differential latch control
Internal latch pull-up resistors
Power supply rejection greater than 85 dB
700 ps minimum pulse width
LATCH ENABLE
LATCH ENABLE
INPUT
INPUT
*ADCMP564 ONLY
1.5 GHz equivalent input rise time bandwidth
Typical output rise/fall time of 500 ps
ESD protection > 4kV HBM, >200V MM
Programmable hysteresis
Figure 1.
GND
QA
GND
1
2
20
19 QB
1
2
3
4
5
6
7
8
16
QB
QA
QA
QA
QB
3
18
17
16
15
14
13
12
11
15 QB
ADCMP564
BRQ
TOP VIEW
(Not to Scale)
GND
LEA
LEA
GND
LEB
LEB
4
14 GND
13 LEB
12 LEB
APPLICATIONS
GND
LEA
LEA
5
ADCMP563
BRQ
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
6
TOP VIEW
(Not to Scale)
V
V
7
EE
CC
11
V
V
CC
10 –INB
+INB
EE
–INA
+INA
–INB
+INB
HYSB
8
–INA
+INA
9
9
HYSA
10
Peak detection
Figure 2. ADCMP563 16-Lead QSOP
Figure 3. ADCMP564 20-Lead QSOP
High speed triggers
QA QA QB QB
16
15
14
13
Patient diagnostics
PIN1
Hand-held test instruments
Zero crossing detectors
Line receivers and signal restoration
Clock drivers
GND
LEA
LEA
GND
LEB
LEB
1
2
3
4
12
11
10
9
ADCMP563
BCP
TOP VIEW
(Not to Scale)
V
V
EE
CC
5
6
7
8
GENERAL DESCRIPTION
–INA +INA +INB –INB
Figure 4. ADCMP563 16-Lead LFCSP
The ADCMP563/ADCMP564 are high speed comparators
fabricated on Analog Devices’ proprietary XFCB process. The
devices feature a 700 ps propagation delay with less than 75 ps
overdrive dispersion. Dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of high speed comparators.
A separate programmable hysteresis pin is available on the
ADCMP564.
that are fully compatible with ECL 10 K and 10 KH logic
families. The outputs provide sufficient drive current to directly
drive transmission lines terminated in 50 Ω to −2 V. A latch
input, which is included, permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
A differential input stage permits consistent propagation delay
with a wide variety of signals in the common-mode range from
−2.0 V to +3.0 V. Outputs are complementary digital signals
The ADCMP563/ADCMP564 are specified over the industrial
temperature range (−40°C to +85°C).
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
ADCMP563/ADCMP564
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Timing Information ....................................................................... 10
Application Information................................................................ 11
Clock Timing Recovery............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
5/05—Rev. A to Rev. B
Added 16-Lead LFCSP.......................................................Universal
Changes to Applications .................................................................. 1
Changes to Table 1............................................................................ 3
Changes to Optimizing High Speed Performance Section....... 11
Changes to Comparator Hysteresis Section................................ 12
Changes to Minimum Input Slew Rate Requirement Section.. 12
Changes to Ordering Guide .......................................................... 14
7/04—Rev. 0 to Rev. A
Changes to Specification Table ....................................................... 4
Changes to Figure 14........................................................................ 9
Changes to Figure 21...................................................................... 12
Changes to Figure 23...................................................................... 13
4/04—Revision 0: Initial Version
Rev. B | Page 2 of 16
ADCMP563/ADCMP564
SPECIFICATIONS
VCC = +5.0 V, VEE = −5.2 V, TA = −40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Voltage
Input Offset Voltage
Input Offset Voltage Channel Matching
Offset Voltage Temperature Coefficient
Input Bias Current
Input Bias Current Temperature Coefficient
Input Offset Current
−2.0
−5
−10.0
3.0
+5
V
V
VOS
VCM = 0 V
2.0
2.0
2.0
3
0.5
1.0
0.75
750
1800
63
+10.0 mV
mV
μV/°C
+10.0 μA
nA/°C
∆VOS/dT
IBC
@ −IN = −2 V, +IN = +3 V
−10.0
μA
pF
Input Capacitance
CIN
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
Common-Mode Rejection Ratio
Hysteresis
kΩ
kΩ
dB
dB
mV
AV
CMRR
VCM = −2.0 V to +3.0 V
RHYS = ∞
80
1.0
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range
Latch Enable Differential Input Voltage
Latch Enable Input High Current
Latch Enable Input Low Current
LE Voltage, Open
−2.0
0.4
−300
−300
−0.2
−2.8
0
2.0
+300 μA
+300 μA
+0.1
−2.4
V
V
@ 0.0 V
@ −2.0 V
Latch inputs not connected
Latch inputs not connected
VOD = 250 mV
0
V
V
LE Voltage, Open
−2.6
200
200
500
Latch Setup Time
Latch Hold Time
Latch to Output Delay
tS
tH
tPLOH
tPLOL
ps
ps
ps
VOD = 250 mV
VOD = 250 mV
,
Latch Minimum Pulse Width
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level
Output Voltage—Low Level
Rise Time
tPL
VOD = 250 mV
500
ps
VOH
VOL
tR
ECL 50 Ω to −2.0 V
ECL 50 Ω to −2.0 V
10% to 90%
−1.15
−1.95
−0.81
−1.54
V
V
ps
ps
530
450
Fall Time
tF
10% to 90%
AC PERFORMANCE
Propagation Delay
tPD
VOD = 1 V
VOD = 20 mV
VOD = 1 V
700
830
0.25
50
ps
ps
ps/°C
ps
Propagation Delay Temperature Coefficient
Prop Delay Skew—Rising Transition to Falling
Transition
∆tPD /dT
VOD = 1 V
Within Device Propagation Delay Skew—
Channel-to-Channel
VOD = 1 V
50
ps
Overdrive Dispersion
20 mV ≤ VOD ≤ 100 mV
100 mV ≤ VOD ≤ 1.5 V
0.4 V/ns ≤ SR ≤ 1.33 V/ns
750ps ≤ PW ≤ 10ns
33 MHz, 1 V/ns, 0.5 V
1 V swing, −1.5 V ≤ VCM ≤ +2.5 V
75
75
50
25
10
10
ps
ps
ps
ps
ps
ps
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion
Common-Mode Voltage Dispersion
Rev. B | Page 3 of 16
ADCMP563/ADCMP564
Parameter
Symbol
BWEQ
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE (Continued)
Equivalent Input Rise Time Bandwidth1
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
0 V to 1 V swing, 2 V/ns
>50% output swing, 50% duty cycle
ΔtPD < 25 ps
VOD = 400 mV, 1.3 V/ns, 312 MHz,
50% duty cycle
1500
800
700
1.0
MHz
MHz
ps
PWMIN
ps
Unit to Unit Propagation Delay Skew
POWER SUPPLY
100
ps
Positive Supply Current
Negative Supply Current
Positive Supply Voltage
Negative Supply Voltage
Power Dissipation
IVCC
IVEE
VCC
VEE
PD
@ +5.0 V
@ −5.2 V
Dual
Dual
Dual, without load
Dual, with load
2
10
4.75
−4.96 −5.2
90
3.2
19
5.0
5
25
5.25
−5.45
150
230
mA
mA
V
V
120
180
85
mW
mW
dB
dB
150
DC Power Supply Rejection Ratio—VCC
DC Power Supply Rejection Ratio—VEE
HYSTERESIS (ADCMP564 Only)
Hysteresis
PSRRVCC
PSRRVEE
85
RHYS = 23.5 kΩ
RHYS = 9.0 kΩ
Referred to AGND
20
70
−1
3
mV
mV
V
Hysteresis Pin Bias Voltage
Hysteresis Pin Series Resistance
kΩ
1 Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√(trCOMP2 – trIN2), where trIN is the
20/80 input transition time applied to the comparator and trCOMP is the effective transition time, as digitized by the comparator input.
Rev. B | Page 4 of 16
ADCMP563/ADCMP564
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Supply Voltages
Positive Supply Voltage (VCC to GND)
Negative Supply Voltage (VEE to GND)
Ground Voltage Differential
Input Voltages
Input Common-Mode Voltage
Differential Input Voltage
Input Voltage, Latch Controls
Output
−0.5 V to +6.0 V
−6.0 V to +0.5 V
−0.5 V to +0.5 V
−3.0 V to +4.0 V
−7.0 V to +7.0 V
VEE to +0.5 V
THERMAL CONSIDERATIONS
The ADCMP563 QSOP 16-lead package option has a θJA
(junction-to-ambient thermal resistance) of 104°C/W in
still air.
Output Current
30 mA
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +85°C
125°C
−65°C to +150°C
The ADCMP563 LFCSP 16-lead package option has a θJA
(junction-to-ambient thermal resistance) of 70°C/W in
still air.
The ADCMP564 QSOP 20-lead package option has a θJA
(junction-to-ambient thermal resistance) of 80°C/W in
still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 5 of 16
ADCMP563/ADCMP564
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
QA QA QB QB
16
15
14
13
GND
GND
1
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
16 QB
QA
QA
PIN1
QA
QB
2
GND
LEA
LEA
GND
LEB
LEB
1
2
3
4
12
11
10
9
15 QB
QA
QB
3
14 GND
13 LEB
12 LEB
GND
LEA
LEA
ADCMP563
BCP
ADCMP563
BRQ
ADCMP564
BRQ
TOP VIEW
(Not to Scale)
GND
LEA
LEA
GND
LEB
LEB
4
TOP VIEW
(Not to Scale)
5
TOP VIEW
(Not to Scale)
V
V
EE
CC
6
11
V
V
CC
10 –INB
+INB
EE
5
6
7
8
V
V
7
EE
CC
–INA
+INA
–INA +INA +INB –INB
–INA
+INA
–INB
+INB
HYSB
8
9
9
HYSA
10
Figure 6. ADCMP564 20-Lead QSOP
Pin Configuration
Figure 7. ADCMP563 16-Lead LFCSP
Pin Configuration
Figure 5. ADCMP563 16-Lead QSOP
Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP563 ADCMP563 ADCMP564
16-Lead
QSOP
16-Lead
LFCSP
20-Lead
QSOP
Mnemonic Function
1
2
GND
QA
Analog Ground.
1
2
15
16
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEA pin for more information.
One of Two Complementary Outputs for Channel A. QA is logic low if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEA pin for more information.
3
QA
3
4
1
2
4
5
GND
LEA
Analog Ground.
One of Two Complementary Inputs for Channel A Latch Enable. In compare
mode (logic high), the output tracks change at the input of the comparator.
In latch mode (logic low), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEA must be driven in
conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
5
3
6
LEA
One of Two Complementary Inputs for Channel A Latch Enable. In compare
mode (logic low), the output tracks change at the input of the comparator.
In latch mode (logic high), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEA must be driven in
conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
6
7
4
5
7
8
VEE
−INA
Negative Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The
Inverting A input must be driven in conjunction with the Noninverting A input.
8
6
9
+INA
Noninverting Analog Input of the Differential Input Stage for Channel A. The
Noninverting A input must be driven in conjunction with the Inverting A input.
10
11
12
HYSA
HYSB
+INB
Programmable Hysteresis Input.
Programmable Hysteresis Input.
Noninverting Analog Input of the Differential Input Stage for Channel B. The
Noninverting B input must be driven in conjunction with the Inverting B input.
Inverting Analog Input of the Differential Input Stage for Channel B. The
Inverting B input must be driven in conjunction with the Noninverting B input.
Positive Supply Terminal.
9
7
8
9
10
11
13
14
−INB
VCC
Rev. B | Page 6 of 16
ADCMP563/ADCMP564
Pin No.
ADCMP563 ADCMP563 ADCMP564
16-Lead
QSOP
16-Lead
LFCSP
20-Lead
QSOP
Mnemonic Function
12
13
10
11
15
16
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In compare
mode (logic low), the output tracks change at the input of the comparator.
In latch mode (logic high), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEB must be driven in conjunction
with LEB. If left unconnected, the comparator defaults to compare mode.
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In compare
mode (logic high), the output tracks change at the input of the comparator.
In latch mode (logic low), the output reflects the input state just prior to the
comparator being placed in the latch mode. LEB must be driven in conjunction
with LEB. If left unconnected, the comparator defaults to compare mode.
14
15
12
13
17
18
GND
QB
Analog Ground.
One of Two Complementary Outputs for Channel B. QB is logic low if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See
the description of the LEB pin for more information.
16
14
19
20
QB
One of Two Complementary Outputs for Channel B. QB is logic high if the
analog voltage at the noninverting input is greater than the analog voltage
at the inverting input (provided the comparator is in compare mode). See the
description of the LEB pin for more information.
GND
Analog Ground.
Rev. B | Page 7 of 16
ADCMP563/ADCMP564
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
3.0
2.80
2.78
2.76
2.74
2.72
2.70
2.68
2.66
2.64
2.62
2.60
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–2.5
–1.5
–0.5
0.5
1.5
2.5
3.5
–40
–20
0
20
40
60
80
NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V)
TEMPERATURE (°C)
Figure 8. Input Bias Current vs. Input Voltage
Figure 11. Input Bias Current vs. Temperature
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
–0.8
–1.0
–1.2
–1.4
–1.6
–1.8
–2.0
–40
–20
0
20
40
60
80
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
TEMPERATURE (°C)
TIME (ns)
Figure 9. Input Offset Voltage vs. Temperature
Figure 12. Rise and Fall of Outputs vs. Time
550
545
540
535
530
525
520
515
510
505
500
475
470
465
460
455
450
445
440
435
430
425
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Rise Time vs. Temperature
Figure 13. Fall Time vs. Temperature
Rev. B | Page 8 of 16
ADCMP563/ADCMP564
720
715
710
705
700
695
690
685
680
705
704
703
702
701
700
699
698
697
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–2
–1
0
1
2
3
TEMPERATURE (°C)
INPUT COMMON-MODE VOLTAGE (V)
Figure 14. Propagation Delay vs. Temperature
Figure 17. Propagation Delay vs. Common-Mode Voltage
140
120
100
80
25
20
15
10
5
60
40
0
20
0
–5
0.7
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.7
2.7
3.7
4.7
5.7
6.7
7.7
8.7
9.7
OVERDRIVE VOLTAGE (V)
PULSE WIDTH (ns)
Figure 15. Propagation Delay Error vs. Overdrive Voltage
Figure 18. Propagation Delay Error vs. Pulse Width
160
140
120
100
80
160
140
120
100
80
60
60
40
40
20
20
0
0
50
0
50
100
(μA)
150
40
30
20
10
0
I
R
(kΩ)
HYS
HYS
Figure 19. Comparator Hysteresis vs. IHYS
Figure 16. Comparator Hysteresis vs. RHYS
Rev. B | Page 9 of 16
ADCMP563/ADCMP564
TIMING INFORMATION
LATCH ENABLE
50%
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
REF
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 20. System Timing Diagram
Figure 20 shows the compare and latch features of the ADCMP563. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tPLOH
tPLOL
tH
Input-to-Output High Delay
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Input-to-Output Low Delay
Latch Enable to Output High Delay
Latch Enable to Output Low Delay
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPL
tS
Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change.
Minimum Setup Time
Output Rise Time
Output Fall Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
tR
tF
VOD
Voltage Overdrive
Difference between the differential input and reference input voltages.
Rev. B | Page 10 of 16
ADCMP563/ADCMP564
APPLICATION INFORMATION
The ADCMP563/ADCMP564 comparators are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP563/ADCMP564 design is the use of a
low impedance ground plane. A ground plane, as part of a
multilayer board, is recommended for proper high speed
performance. Using a continuous conductive plane over the
surface of the circuit board can create this, allowing breaks in
the plane only for necessary signal paths. The ground plane
provides a low inductance ground, eliminating any potential
differences at different ground points throughout the circuit
board caused by ground bounce. A proper ground plane also
minimizes the effects of stray capacitance on the circuit board.
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design
and layout techniques should be used to ensure optimal
performance from the ADCMP563/ADCMP564. The perfor-
mance limits of high speed circuitry all too often are the result
of stray capacitance, improper ground impedance, or other
layout issues.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 μF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close as possible from the
power supply pins on the ADCMP563/ADCMP564 to ground.
These capacitors act as a charge reservoir for the device during
high frequency switching.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP563/ADCMP564. Source resistance, in combination
with equivalent input capacitance, could cause a lagged
response at the input, thus delaying the output. The input
capacitance of the ADCMP563/ADCMP564, in combination
with stray capacitance from an input pin to ground, could result
in several picofarads of equivalent capacitance. A combination
of 3 kΩ source resistance and 5 pF input capacitance yields a
time constant of 15 ns, which is significantly slower than the
750 ps capability of the ADCMP563/ADCMP564. Source
impedances should be significantly less than 100 Ω for best
performance.
The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input can be
left open or grounded (ground is an ECL logic high). The
complementary input,
, can be left open or
LATCH ENABLE
tied to −2.0 V. Leaving the latch inputs unconnected or
providing the proper voltages disables the latching function.
Occasionally, one of the two comparator stages within the
ADCMP563/ADCMP564 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain can cause the output to oscillate (possibly affecting the
comparator that is being used), unless the output is forced into
a fixed state. This is easily accomplished by ensuring that the
two inputs are at least one diode drop apart, while also
appropriately connecting the LATCH ENABLE and
Sockets should be avoided due to stray capacitance and induc-
tance. If proper high speed techniques are used, the devices
should be free from oscillation when the comparator input
signal passes through the switching threshold.
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP563/ADCMP564 have been specifically designed
to reduce propagation delay dispersion over an input overdrive
range of 100 mV to 1.5 V. Propagation delay overdrive
dispersion is the change in propagation delay that results from a
change in the degree of overdrive (how far the switching point
is exceeded by the input). The overall result is a higher degree of
timing accuracy because the ADCMP563/ADCMP564 are far
less sensitive to input variations than most comparator designs.
inputs as described previously.
LATCH ENABLE
The best performance is achieved with the use of proper ECL
terminations. The open emitter outputs of the ADCMP563/
ADCMP564 are designed to be terminated through 50 Ω
resistors to −2.0 V, or any other equivalent ECL termination. If a
−2.0 V supply is not available, an 82 Ω resistor to ground and a
130 Ω resistor to −5.2 V provide a suitable equivalent. If high
speed ECL signals must be routed more than a centimeter,
microstrip or stripline techniques may be required to ensure
proper transition times and prevent output ringing.
Rev. B | Page 11 of 16
ADCMP563/ADCMP564
Propagation delay dispersion is important in critical timing
applications such as ATE, bench instruments, and nuclear
instrumentation. Overdrive dispersion is defined as the varia-
tion in propagation delay as the input overdrive conditions are
changed (Figure 21). For the ADCMP563/ADCMP564, over-
drive dispersion is typically 75 ps as the overdrive is changed
from 100 mV to 1.5 V. This specification applies for both
positive and negative overdrive because the ADCMP563 and
the ADCMP564 have equal delays for positive and negative
going inputs.
A current may be sourced into the HYS pin. The pin is biased
approximately 1 V below AGND and has a 3 kΩ series
resistance. The relationship between the current applied to the
HYS pin and the resulting hysteresis is shown in Figure 19.
–V
2
+V
2
H
H
0V
INPUT
1
1.5V OVERDRIVE
INPUT VOLTAGE
20mV OVERDRIVE
± V
0
V
REF
OS
OUTPUT
DISPERSION
Figure 22. Comparator Hysteresis Transfer Function
Q OUTPUT
Figure 21. Propagation Delay Dispersion
160
140
120
100
80
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often useful in a
noisy environment, or where it is not desirable for the compar-
ator to toggle between states when the input signal is at the
switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 22. If the input voltage
approaches the threshold from the negative direction, the
comparator switches from 0 to 1 when the input crosses +VH/2.
The new switching threshold becomes −VH/2. The comparator
remains in a 1 state until the threshold −VH/2 is crossed while
coming from the positive direction. In this manner, noise
centered on 0 V input does not cause the comparator to switch
states unless it exceeds the region bounded by VH/2.
60
40
20
0
50
40
30
20
10
0
R
(kΩ)
HYS
Figure 23. Comparator Hysteresis vs. RHYS
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that can be load dependent and is not symmetrical
about the threshold. The external feedback network can also
introduce significant parasitics, which reduce high speed
performance and can induce oscillation in some cases.
MINIMUM INPUT SLEW RATE REQUIREMENT
As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate as the input
crosses the threshold. This oscillation is due in part to the high
input bandwidth of the comparator and the parasitics of the
package. ADI recommends a slew rate of 1 V/μs or faster to
ensure a clean output transition. If slew rates less than 1 V/μs
are used, hysteresis can be added to prevent the oscillation.
In the ADCMP564, hysteresis is generated through the
programmable hysteresis pin. A resistor from the HYS pin to
GND creates a current into the part that is used to generate
hysteresis. Hysteresis generated in this manner is independent
of output swing and is symmetrical around the trip point. The
hysteresis vs. resistance curve is shown in Figure 23.
Rev. B | Page 12 of 16
ADCMP563/ADCMP564
TYPICAL APPLICATION CIRCUITS
V
V
IN
IN
ADCMP563/
ADCMP564
OUTPUTS
ADCMP564
OUTPUTS
V
V
REF
REF
HYS
0Ω TO 80kΩ
LATCH
ENABLE
INPUTS
–2.0V
–2.0V
ALL RESISTORS 50Ω, UNLESS OTHERWISE NOTED
ALL RESISTORS 50Ω
Figure 26. Adding Hysteresis Using the HYS Control Pin
Figure 24. High Speed Sampling Circuits
+V
REF
ADCMP563/
ADCMP564
OUTPUTS
V
IN
–2V
ADCMP563/
ADCMP564
OUTPUTS
–V
REF
30Ω
50Ω
50Ω
ADCMP563/
ADCMP564
V
IN
30Ω
127Ω
127Ω
–2V
LATCH
ENABLE
INPUTS
–5.2V
ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED
Figure 25. High Speed Window Comparator
Figure 27. One Method to Interface an ECL Output to an
Instrument with a 50 Ω to Ground Input
Rev. B | Page 13 of 16
ADCMP563/ADCMP564
OUTLINE DIMENSIONS
0.341
BSC
0.193
BSC
20
1
11
10
16
9
0.154
BSC
0.154
BSC
0.236
BSC
0.236
BSC
1
8
PIN 1
PIN 1
0.069
0.053
0.065
0.049
0.065
0.049
0.069
0.053
8°
0°
8°
0°
0.010
0.004
0.010
0.004
0.025
BSC
0.012
0.008
0.025
BSC
SEATING
PLANE
0.012
0.008
0.050
0.016
0.050
0.016
0.010
0.006
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137-AD
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 29. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Figure 28. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
Dimensions shown in inches
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.65
13
12
16
0.45
1
4
1.50 SQ
1.35
PIN 1
TOP
2.75
BSC SQ
EXPOSED
PAD
INDICATOR
VIEW
(BOTTOM VIEW)
9
8
5
0.50
BSC
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
0.30
PLANE
0.20 REF
0.23
0.18
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADCMP563BRQ
Temperature Range
Package Description
16-Lead QSOP
16-Lead QSOP
16-Lead LFCSP_VQ, 250 Unit Reel
16-Lead LFCSP_VQ, 1,500 Unit Reel
16-Lead LFCSP_VQ, 50 Unit Waffle Pack
Evaluation Board
Package Option
RQ-16
RQ-16
CP-16-3
CP-16-3
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
ADCMP563BRQZ1
ADCMP563BCP-R2
ADCMP563BCP-RL7
ADCMP563BCP-WP
EVAL-ADCMP563BRQ
ADCMP564BRQ
CP-16-3
−40°C to +85°C
−40°C to +85°C
20-Lead QSOP
20-Lead QSOP
RQ-20
RQ-20
ADCMP564BRQZ1
EVAL-ADCMP564BRQ
Evaluation Board
1 Z = Pb-free part.
Rev. B | Page 14 of 16
ADCMP563/ADCMP564
NOTES
Rev. B | Page 15 of 16
ADCMP563/ADCMP564
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04650–0–5/05(B)
Rev. B | Page 16 of 16
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