EVAL-ADCMP552BRQ [ADI]
Single-Supply, High Speed PECL/LVPECL Comparators; 单电源，高速PECL / LVPECL比较
| 型号： | EVAL-ADCMP552BRQ |
| 厂家： | 
ADI |
| 描述： | Single-Supply, High Speed PECL/LVPECL Comparators |
| 文件： | 总16页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single-Supply, High Speed
PECL/LVPECL Comparators
ADCMP551/ADCMP552/ADCMP553
FEATURES
Single power supply
FUNCTIONAL BLOCK DIAGRAM
HYS*
500 ps propagation delay input to output
125 ps overdrive dispersion
Differential PECL/LVPECL compatible outputs
Differential latch control
NONINVERTING
Q OUTPUT
INPUT
ADCMP551/
ADCMP552/
ADCMP553
INVERTING
Q OUTPUT
INPUT
Internal latch pull-up resistors
Power supply rejection greater than 70 dB
700 ps minimum pulse width
Equivalent input rise time bandwidth > 750 MHz
Typical output rise/fall of 500 ps
Programmable hysteresis
LATCH ENABLE
LATCH ENABLE
INPUT
INPUT
*ADCMP552 ONLY
Figure 1.
GENERAL DESCRIPTION
APPLICATIONS
The ADCMP551/ADCMP552/ADCMP553 are single-supply,
high speed comparators fabricated on Analog Devices’
proprietary XFCB process. The devices feature a 500 ps
propagation delay with less than 125 ps overdrive dispersion.
Overdrive dispersion, a measure of the difference in
propagation delay under differing overdrive conditions, is a
particularly important characteristic of high speed comparators.
A separate programmable hysteresis pin is available on the
ADCMP552.
Automatic test equipment
High speed instrumentation
Scope and logic analyzer front ends
Window comparators
High speed line receivers
Threshold detection
Peak detection
High speed triggers
Patient diagnostics
A differential input stage permits consistent propagation delay
with a common-mode range from –0.2 V to VCCI – 2.0 V.
Outputs are complementary digital signals and are fully
compatible with PECL and 3.3V LVPECL logic families. The
outputs provide sufficient drive current to directly drive
transmission lines terminated in 50 Ω to VCCO − 2 V. A latch
input is included and permits tracking, track-and-hold, or
sample-and-hold modes of operation. The latch input pins
contain internal pull-ups that set the latch in tracking mode
when left open.
Disk drive read channel detection
Hand-held test instruments
Zero-crossing detectors
Line receivers and signal restoration
Clock drivers
The ADCMP551/ADCMP552/ADCMP553 are specified over
the –40°C to +85°C industrial temperature range. The
ADCMP551 is available in a 16-lead QSOP package; the
ADCMP552 is available in a 20-lead QSOP package; and the
ADCMP553 is available in an 8-lead MSOP package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADCMP551/ADCMP552/ADCMP553
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Timing Information ....................................................................... 10
Application Information................................................................ 11
Clock Timing Recovery............................................................. 11
Optimizing High Speed Performance ..................................... 11
Comparator Propagation Delay Dispersion ........................... 11
Comparator Hysteresis .............................................................. 12
Minimum Input Slew Rate Requirement................................ 12
Typical Application Circuits ......................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADCMP551/ADCMP552/ADCMP553
SPECIFICATIONS
VCCI = 3.3 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Voltage Range
Input Offset Voltage
Input Offset Voltage Channel Matching
Offset Voltage Tempco
Input Bias Current
−0.2
−3
−10.0
VCCI – 2.0
+3
+10.0
V
V
VOS
−IN = 0 V, +IN = 0 V
2.0
1.0
2.0
-6.0
-5.0
1.0
mV
mV
µV/°C
µA
nA/°C
µA
∆VOS/dT
IIN
−IN = −0.2 V, +IN = +1.3 V
−28.0
−3.0
+5.0
+3.0
Input Bias Current Tempco
Input Offset Current
Input Capacitance
CIN
1.0
pF
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
1800
1000
60
kΩ
kΩ
dB
AV
Common-Mode Rejection Ratio
Hysteresis
CMRR
VCM = −0.2 V to +1.3 V
RHYS = ∞
76
0.5
dB
mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Voltage Range
Latch Enable Differential Voltage Range
Latch Enable Input High Current
Latch Enable Input Low Current
LE Voltage, Open
VCCI – 1.8
0.4
−150
−150
VCCI – 0.15
VCCI/2 – 0.075
VCCI – 0.8
1.0
+150
+150
VCCI
V
V
µA
µA
V
@ VCCI – 0.8 V
@ VCCI – 1.8 V
Latch inputs not connected
Latch inputs not connected
VOD = 250 mV
VOD = 250 mV
VOD = 250 mV
VOD = 250 mV
LE
VCCI/2 + 0.075
V
Voltage, Open
Latch Setup Time
Latch Hold Time
tS
tH
100
100
450
700
ps
ps
ps
ps
Latch to Output Delay
Latch Minimum Pulse Width
DC OUTPUT CHARACTERISTICS
Output Voltage—High Level
Output Voltage—Low Level
AC OUTPUT CHARACTERISTICS
Rise Time
tPLOH, tPLOL
tPL
VOH
VOL
PECL 50 Ω to VDD − 2.0 V
PECL 50 Ω to VDD − 2.0 V
VCCO − 1.15
VCCO − 2.00
VCCO − 0.78
VCCO − 1.54
V
V
tR
tF
10% to 90%
10% to 90%
510
490
ps
ps
Fall Time
AC OUTPUT CHARACTERISTICS (ADCMP553)
Rise Time
Fall Time
tR
tF
10% to 90%
10% to 90%
440
410
ps
ps
AC PERFORMANCE
Propagation Delay
tPD
VOD = 1 V
VOD = 20 mV
VOD = 1 V
500
625
0.25
35
ps
ps
ps/°C
ps
Propagation Delay Tempco
Prop Delay Skew—Rising Transition to
Falling Transition
∆tPD/dT
VOD = 1 V
Within Device Propagation Delay
Skew—Channel-to-Channel
VOD = 1 V
35
ps
Overdrive Dispersion
Overdrive Dispersion
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion
Common-Mode Voltage Dispersion
20 mV ≤ VOD ≤ 100 mV
50 mV ≤ VOD ≤ 1.0 V
0.4 V/ns ≤ SR ≤ 1.33 V/ns
700 ps ≤ PW ≤ 10 ns
33 MHz, 1 V/ns, VCM = 0.5 V
1 V swing, 0.3 V ≤ VCM ≤ 0.8 V
75
75
75
25
10
10
ps
ps
ps
ps
ps
ps
Rev. 0 | Page 3 of 16
ADCMP551/ADCMP552/ADCMP553
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE (continued)
Equivalent Input Rise Time Bandwidth1
Maximum Toggle Rate
Minimum Pulse Width
RMS Random Jitter
BWEQ
0 V to 1 V swing, 2 V/ns
>50% output swing
∆tPD < 25 ps
VOD = 250 mV, 1.3 V/ns,
500 MHz, 50% duty cycle
750
800
700
1.1
MHz
MHz
ps
PWMIN
ps
Unit-to-Unit Propagation Delay Skew
POWER SUPPLY (ADCMP551/ADCMP552)
Input Supply Current
Output Supply Current
Output Supply Current
Input Supply Voltage
Output Supply Voltage
Positive Supply Differential
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio—VCCI
DC Power Supply Rejection Ratio—VCCO
POWER SUPPLY (ADCMP553)
Positive Supply Current
Positive Supply Current
Positive Supply Voltage
Power Dissipation
Power Dissipation
DC Power Supply Rejection Ratio—VCC
HYSTERESIS (ADCMP552 Only)
Programmable Hysteresis
50
ps
IVCCI
IVCCO
@ 3.3 V
8
3
40
3.135
3.135
–0.2
40
12
5
55
3.3
3.3
17
9
70
5.25
5.25
+2.3
75
mA
mA
mA
V
V
V
mW
mW
dB
dB
@ 3.3 V without load
@ 3.3 V with load
Dual
VCCI
VCCO
VCCO − VCCI
PD
Dual
Dual, without load
Dual, with load
55
110
75
90
130
PSRRVCCI
PSRRVCCO
85
IVCC
@ 3.3 V without load
@ 3.3 V with load
Dual
Dual, without load
Dual, with load
9
13
42
5.25
42
75
mA
mA
V
mW
mW
dB
35
3.3
30
60
70
VCC
PD
3.135
PSRRVCC
0
40
mV
1 Equivalent input rise time bandwidth assumes a first order input response and is calculated by the following formula: BWEQ = .22/√ (trCOMP2 - trIN2),
where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input.
Rev. 0 | Page 4 of 16
ADCMP551/ADCMP552/ADCMP553
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Rating
Supply Voltages
Input Supply Voltage (VCCI to GND)
Output Supply Voltage (VCCO to GND)
Ground Voltage Differential
Input Voltages
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−0.5 V to +0.5 V
Input Common-Mode Voltage
Differential Input Voltage
Input Voltage, Latch Controls
Output
−0.5 V to +3.5 V
−4.0 V to +4.0 V
−0.5 V to +5.5 V
THERMAL CONSIDERATIONS
The ADCMP551 16-lead QSOP package has a θJA (junction-to-
ambient thermal resistance) of 104°C/W in still air.
Output Current
30 mA
The ADCMP552 20-lead QSOP package has a θJA (junction-to-
ambient thermal resistance) of 80°C/W in still air.
Temperature
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +85°C
125°C
−65°C to +150°C
The ADCMP553 8-lead MSOP package has a θJA (junction-to-
ambient thermal resistance) of 130°C/W in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
ADCMP551/ADCMP552/ADCMP553
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
V
CCO
1
2
20
19
18
17
16
15
14
13
12
11
CCO
QA
QB
QB
V
1
2
3
4
5
6
7
8
16 QB
15 QB
QA
QA
QA
3
1
2
3
4
8
7
6
5
AGND
LEA
LEA
ADCMP552
TOP VIEW
(Not to Scale)
V
4
CCO
CCO
14
V
CCO
V
ADCMP553
TOP VIEW
(Not to Scale)
CCO
V
CC
LEA
LEA
LEB
5
ADCMP551
TOP VIEW
(Not to Scale)
13 LEB
12 LEB
11 AGND
10 –INB
LEA
LEA
QA
QA
+INA
–INA
LEB
6
V
AGND
–INB
+INB
HYSB
7
CCI
V
CCI
–INA
+INA
8
–INA
+INA
9
+INB
9
HYSA
10
Figure 2. ADCMP551 16-Lead QSOP
Pin Configuration
Figure 3. ADCMP552 20-Lead QSOP
Pin Configuration
Figure 4. ADCMP553 8-Lead MSOP
Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Function
ADCMP551 ADCMP552 ADCMP553
3, 14
1
1, 4, 17, 20
2
VCCO
QA
Logic Supply Terminal.
6
5
2
One of Two Complementary Outputs for Channel A. QA is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
2
4
3
5
QA
QA
One of Two Complementary Outputs for Channel A. is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEA for more information.
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
LEA
LEA
prior to the comparator’s being placed in the latch mode.
conjunction with LEA.
must be driven in
5
6
1
LEA
One of Two Complementary Outputs for Channel A Latch Enable. In the
compare mode (logic high), the output tracks changes at the input of the
comparator. In the latch mode (logic low), the output reflects the input state just
prior to the comparator’s being placed in the latch mode. LEA must be driven in
LEA
conjunction with
.
6
7
7
8
VCCI
−INA
Input Supply Terminal.
Inverting Analog Input of the Differential Input Stage for Channel A. The
inverting A input must be driven in conjunction with the noninverting A input.
Noninverting Analog Input of the Differential Input Stage for Channel A. The
noninverting A input must be driven in conjunction with the inverting A input.
4
3
8
9
+INA
10
11
12
HYSA
HYSB
+INB
Programmable Hysteresis.
Programmable Hysteresis.
Noninverting Analog Input of the Differential Input Stage for Channel B. The
noninverting B input must be driven in conjunction with the inverting B input.
9
10
11
13
14
−INB
Inverting Analog Input of the Differential Input Stage for Channel B. The
inverting B input must be driven in conjunction with the noninverting B input.
Analog Ground.
8
AGND
Rev. 0 | Page 6 of 16
ADCMP551/ADCMP552/ADCMP553
Pin No.
Mnemonic Function
ADCMP551 ADCMP552 ADCMP553
12
15
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In the compare
mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction
LEB
with
.
13
16
LEB
One of Two Complementary Inputs for Channel B Latch Enable. In the compare
mode (logic low), the output tracks changes at the input of the comparator. In
the latch mode (logic high), the output reflects the input state just prior to the
comparator’s being placed in the latch mode. LEB must be driven in conjunction
LEB
with
QB
One of Two Complementary Outputs for Channel B. is logic low if the analog
voltage at the noninverting input is greater than the analog voltage at the
inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.
One of Two Complementary Outputs for Channel B. QB is logic high if the
analog voltage at the noninverting input is greater than the analog voltage at
the inverting input (provided the comparator is in the compare mode). See the
description of Pin LEB for more information.
.
15
16
18
19
QB
QB
VCC
7
Positive Supply Terminal.
Rev. 0 | Page 7 of 16
ADCMP551/ADCMP552/ADCMP553
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = 3.3 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
–5
–6.5
–6.6
–6.7
–6.8
–6.9
–7.0
–7.1
–7.2
–7.3
–7.4
–7.5
–6
–7
–8
–9
–10
–0.2
0.1
0.4
0.7
1.0
1.3
–40
–20
0
20
40
60
80
NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V)
TEMPERATURE (°C)
Figure 5. Input Bias Current vs. Input Voltage
Figure 8. Input Bias Current vs. Temperature
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
RISE
FALL
–40
–20
0
20
40
60
80
0
0.25
0.50
0.75
TIME (ns)
1.00
1.25
1.50
1.75
TEMPERATURE (°C)
Figure 6. Input Offset Voltage vs. Temperature
Figure 9. Rise and Fall of Outputs vs. Time
460
450
440
430
420
410
400
525
515
505
495
485
475
RISE
RISE
FALL
FALL
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 10. ADCMP553 Rise/Fall Time vs. Temperature
Figure 7. ADCMP551/2 Rise/Fall Time vs. Temperature
Rev. 0 | Page 8 of 16
ADCMP551/ADCMP552/ADCMP553
515
510
505
500
495
490
485
480
505
504
503
502
501
500
499
498
497
496
495
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–0.2
0.1
0.4
0.7
1.0
1.3
TEMPERATURE (°C)
INPUT COMMON MODE VOLTAGE (V)
Figure 11. Propagation Delay vs. Temperature
Figure 14. Propagation Delay vs. Common-Mode Voltage
140
120
100
80
25
20
15
10
5
60
40
0
20
0
–5
0.7
0
0.2
0.4
0.6
0.8
1.0
1.7
2.7
3.7
4.7
5.7
6.7
7.7
8.7
9.7
OVERDRIVE VOLTAGE (V)
PULSE WIDTH (ns)
Figure 12. Propagation Delay vs. Overdrive Voltage
Figure 15. Propagation Delay Error vs. Pulse Width
120
100
80
60
40
20
0
140
120
100
80
60
40
20
0
100
10
(k
1
0
50
100
150
200
250
300
R
Ω)
I
(µA)
HYS
HYS
Figure 16. Comparator Hysteresis vs. IHYS
Figure 13. Comparator Hysteresis vs. RHYS
Rev. 0 | Page 9 of 16
ADCMP551/ADCMP552/ADCMP553
TIMING INFORMATION
LATCH ENABLE
50%
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
REF
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 17. System Timing Diagram
Figure 17 shows the compare and latch features of the ADCMP55x family. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tPLOH
tPLOL
tH
Input to Output High Delay
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output low-to-high transition
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50% point of an output high-to-low transition
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition
Input to Output Low Delay
Latch Enable to Output High Delay
Latch Enable to Output Low Delay
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs
tPL
tS
Minimum Latch Enable Pulse Width Minimum time the latch enable signal must be high to acquire an input signal change
Minimum Setup Time
Output Rise Time
Output Fall Time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points
tR
tF
VOD
Voltage Overdrive
Difference between the differential input and reference input voltages
Rev. 0 | Page 10 of 16
ADCMP551/ADCMP552/ADCMP553
APPLICATION INFORMATION
The comparators in the ADCMP55x series are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP55x design is the use of a low impedance
ground plane. A ground plane, as part of a multilayer board, is
recommended for proper high speed performance. Using a
continuous conductive plane over the surface of the circuit
board can create this, allowing breaks in the plane only for
necessary signal paths. The ground plane provides a low
inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused by
ground bounce. A proper ground plane also minimizes the
effects of stray capacitance on the circuit board.
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a
distance, even tens of centimeters, can become distorted due to
stray capacitance and inductance. Poor layout or improper
termination can also cause reflections on the transmission line,
further distorting the signal waveform. A high speed
comparator can be used to recover the distorted waveform
while maintaining a minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design
and layout techniques should be used to ensure optimal
performance from the ADCMP55x. The performance limits of
high speed circuitry can easily be a result of stray capacitance,
improper ground impedance, or other layout issues.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 µF electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF
ceramic capacitor should be placed as close to the power supply
pins as possible on the ADCMP55x to ground. These capacitors
act as a charge reservoir for the device during high frequency
switching.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP55x. Source resistance in combination with equivalent
input capacitance can cause a lagged response at the input, thus
delaying the output. The input capacitance of the ADCMP55x,
in combination with stray capacitance from an input pin to
ground, could result in several picofarads of equivalent
capacitance. A combination of 3 kΩ source resistance and 5 pF
input capacitance yields a time constant of 15 ns, which is
significantly slower than the 500 ps capability of the
The LATCH ENABLE input is active low (latched). If the
latching function is not used, the LATCH ENABLE input pins
may be left open. The internal pull-ups on the latch pins set the
latch to transparent mode. If the latch is to be used, valid PECL
voltages are required on the inputs for proper operation. The
ADCMP55x. Source impedances should be significantly less
than 100 Ω for best performance.
PECL voltages should be referenced to VCCI
.
Sockets should be avoided due to stray capacitance and
inductance. If proper high speed techniques are used, the
ADCMP55x should be free from oscillation when the
comparator input signal passes through the switching threshold.
Occasionally, one of the two comparator stages within the
ADCMP551/ADCMP552 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP55x has been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
20 mV to 1 V. Propagation delay overdrive dispersion is the
change in propagation delay that results from a change in the
degree of overdrive (how far the switching point is exceeded by
the input). The overall result is a higher degree of timing
accuracy since the ADCMP55x is far less sensitive to input
variations than most comparator designs.
LATCH ENABLE
connecting the LATCH ENABLE and
as described previously.
inputs
The best performance is achieved with the use of proper PECL
terminations. The open-emitter outputs of the ADCMP55x are
designed to be terminated through 50 Ω resistors to
VCCO − 2.0 V or any other equivalent PECL termination. If high
speed PECL signals must be routed more than a centimeter,
microstrip or stripline techniques may be required to ensure
proper transition times and prevent output ringing.
Rev. 0 | Page 11 of 16
ADCMP551/ADCMP552/ADCMP553
Propagation delay dispersion is an important specification in
critical timing applications such as ATE, bench instruments,
and nuclear instrumentation. Overdrive dispersion is defined as
the variation in propagation delay as the input overdrive
conditions are changed (Figure 18). For the ADCMP55x,
overdrive dispersion is typically 125 ps as the overdrive is
changed from 20 mV to 1 V. This specification applies for both
positive and negative overdrive since the ADCMP55x has equal
delays for positive- and negative-going inputs.
A current source can also be used with the HYS pin. The
relationship between the current applied to the HYS pin and the
resulting hysteresis is shown in Figure 16.
–V
2
+V
2
H
H
0V
INPUT
1
1.5V OVERDRIVE
INPUT VOLTAGE
20mV OVERDRIVE
± V
0
V
REF
OS
OUTPUT
DISPERSION
Q OUTPUT
Figure 19. Comparator Hysteresis Transfer Function
Figure 18. Propagation Delay Dispersion
120
100
80
60
40
20
0
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often useful in a
noisy environment or where it is not desirable for the
comparator to toggle between states when the input signal is at
the switching threshold. The transfer function for a comparator
with hysteresis is shown in Figure 19. If the input voltage
approaches the threshold from the negative direction, the
comparator switches from a 0 to a 1 when the input crosses
+VH/2. The new switching threshold becomes −VH/2. The
comparator remains in a 1 state until the −VH/2 threshold is
crossed coming from the positive direction. In this manner,
noise centered on 0 V input does not cause the comparator to
switch states unless it exceeds the region bounded by VH/2.
100
10
(k
1
R
Ω)
HYS
Figure 20. Comparator Hysteresis Transfer Function
Positive feedback from the output to the input is often used to
produce hysteresis in a comparator (Figure 23). The major
problem with this approach is that the amount of hysteresis
varies with the output logic levels, resulting in a hysteresis that
is not symmetrical around zero.
MINIMUM INPUT SLEW RATE REQUIREMENT
As for all high speed comparators, a minimum slew rate must
be met to ensure that the device does not oscillate when the
input crosses the threshold. This oscillation is due in part to the
high input bandwidth of the comparator and the parasitics of
the package. Analog Devices recommends a slew rate of 1 V/µs
or faster to ensure a clean output transition. If slew rates less
than 1 V/µs are used, hysteresis should be added to reduce the
oscillation.
In the ADCMP552, hysteresis is generated through the
programmable hysteresis pin. A resistor from the HYS pin to
VCCI creates a current into the part that is used to generate
hysteresis. Hysteresis generated in this manner is independent
of output swing and is symmetrical around the trip point. The
hysteresis versus resistance curve is shown in Figure 20.
Rev. 0 | Page 12 of 16
ADCMP551/ADCMP552/ADCMP553
TYPICAL APPLICATION CIRCUITS
V
+
IN
ADCMP551/
ADCMP552/
ADCMP553
V
IN
ADCMP551/
ADCMP552/
OUTPUTS
OUTPUTS
V
ADCMP553
REF
V
REF
HYS
–
0Ω TO 80kΩ
LATCH
ENABLE
INPUTS
V
– 2V
CCO
V
V
– 2.0V
CCO
CCI
ALL RESISTORS 50Ω, UNLESS OTHERWISE NOTED
ALL RESISTORS 50Ω
Figure 23. Adding Hysteresis Using the HYS Control Pin
Figure 21. High Speed Sampling Circuits
50Ω
50Ω
50Ω
+
+
+V
ADCMP551/
ADCMP552/
REF
ADCMP551/
ADCMP552/
V
IN
OUTPUTS
50Ω
ADCMP553
ADCMP553
V
–
IN
–
100Ω
100Ω
(V
– 2V)
×
2
CCO
V
–2V
CCO
+
Figure 24. How to Interface a PECL Output to an Instrument with a
ADCMP551/
ADCMP552/
OUTPUTS
50 Ω to Ground Input
ADCMP553
–V
REF
–
V
–2V
CCO
LATCH
ENABLE
INPUTS
ALL RESISTORS 50
Ω UNLESS OTHERWISE NOTED
Figure 22. High Speed Window Comparator
Rev. 0 | Page 13 of 16
ADCMP551/ADCMP552/ADCMP553
OUTLINE DIMENSIONS
0.341
BSC
20
11
10
0.154
BSC
0.236
BSC
1
PIN 1
0.065
0.049
0.069
0.053
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
SEATING
PLANE
0.050
0.016
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AD
Figure 25. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in inches
0.193
BSC
3.00
BSC
8
1
5
4
16
1
9
8
0.154
BSC
4.90
BSC
3.00
BSC
0.236
BSC
PIN 1
0.65 BSC
PIN 1
0.069
0.053
0.065
0.049
1.10 MAX
0.15
0.00
0.80
0.60
0.40
8°
0°
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
SEATING
PLANE
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 27. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
COMPLIANT TO JEDEC STANDARDS MO-137AB
Figure 26. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in millimeters
Dimensions shown in inches
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead QSOP
20-Lead QSOP
8-Lead MSOP
EVALUATION BOARD
EVALUATION BOARD
Package Option
RQ-16
RQ-20
Branding
ADCMP551BRQ
ADCMP552BRQ
ADCMP553BRM
EVAL-ADCMP551BRQ
EVAL-ADCMP552BRQ
RM-8
B53
Rev. 0 | Page 14 of 16
ADCMP551/ADCMP552/ADCMP553
NOTES
Rev. 0 | Page 15 of 16
ADCMP551/ADCMP552/ADCMP553
NOTES
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04722–0–10/04(0)
Rev. 0 | Page 16 of 16
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