EVAL-ADAU7002Z [ADI]
Stereo PDM-to-I2S or TDM Conversion IC; 立体声PDM至I2S或TDM转换IC
| 型号： | EVAL-ADAU7002Z |
| 厂家： | 
ADI |
| 描述： | Stereo PDM-to-I2S or TDM Conversion IC |
| 文件： | 总16页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stereo PDM-to-I2S or
TDM Conversion IC
ADAU7002
Data Sheet
FEATURES
GENERAL DESCRIPTION
64× decimation of a stereo pulse density modulation (PDM)
bit stream to pulse code modulation (PCM) audio data
Slave I2S or time division multiplexed (TDM) output interface
Configurable TDM slots
I/O supply operation: 1.62 V to 3.6 V
64× output sample rate PDM clock
The ADAU7002 converts a stereo PDM bit stream into a PCM
output. The source for the PDM data can be two microphones
or other PDM sources. The PCM audio data is output on a
serial audio interface port in either I2S or TDM format.
The ADAU7002 is specified over the commercial temperature
range (−40°C to +85°C). It is available in a halide-free, 8-ball,
1.56 mm × 0.76 mm, wafer level chip scale package (WLCSP).
64×/128×/192×/256×/384×/512× output sample rate BCLK
Automatic BCLK ratio detection
Output sample rate: 4 kHz to 96 kHz
Automatic PDM CLK drive at 64× the sample rate
Automatic power down with BCLK removal
0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply
Shutdown current: <1 µA
8-ball, 1.56 mm × 0.76 mm, 0.4 mm pitch WLCSP
Power-on reset
APPLICATIONS
Mobile computing
Portable electronics
Consumer electronics
FUNCTIONAL BLOCK DIAGRAM
1.62V TO 3.6V
CONFIG
GND
IOVDD
PDM_CLK
PDM_DAT
BCLK
2
PDM
INPUT
PORT
DIGITAL
DECIMATION
FILTERING
I S
OUTPUT
PORT
LRCLK
SDATA
ADAU7002
Figure 1.
Rev. 0
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADAU7002
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Typical Performance Characteristics ..............................................6
Typical Application Circuits ............................................................8
Applications Information .................................................................9
Overview ........................................................................................9
Clocking..........................................................................................9
Serial Audio Output Interface .....................................................9
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
REVISION HISTORY
1/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
Data Sheet
ADAU7002
SPECIFICATIONS
IOVDD = 1.8 V, TA = 25°C, BCLK = 3.072 MHz, output = 48 kHz, I2S format, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DIGITAL INPUT/OUTPUT
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage, High (IIH)
Input Leakage, Low (IIL)
Input Capacitance
SDATA
0.7 × IOVDD
0.3 × IOVDD
V
V
BCLK and LRCLK pins
BCLK and LRCLK pins
1
1
5
µA
µA
pF
mA
mA
4.5
9
PDM_CLK
PERFORMANCE
Dynamic Range
20 Hz to 20 kHz, −60 dB input
A-weighted, fourth-order input
DC to 0.45 output fS
With A-Weighted Filter (RMS)
Signal-to-Noise-Ratio
Decimation Ratio
Frequency Response
Stop Band
110
110
64×
dB
dB
−0.1
60
+0.01
dB
fS
dB
0.566
Stop-Band Attenuation
Group Delay
Gain
0.02 fS input signal
PDM to PCM
3.31
0
LRCLK cycles
dB
Start-Up Time
Bit Width
Interchannel Phase
48
20
0
LRCLK cycles
Bits
Internal and output
Degrees
CLOCKING
Output Sampling Rate
BCLK Frequency
POWER SUPPLIES
Supply Voltage Range
Supply Current
fS LRCLK pulse rate
fBCLK
4
48
3.072
96
24.576
kHz
MHz
0.256
IOVDD
IOVDDSY = 1.8 V
IOVDD = 3.3 V
IOVDD = 1.8 V, 16 kHz output
IOVDD = 3.3 V, 16 kHz output
IOVDDSD, no input clocks
1.62
3.6
V
0.67
1.33
0.21
0.41
1
mA
mA
mA
mA
µA
Shutdown Current
Rev. 0 | Page 3 of 16
ADAU7002
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA (junction to air) is specified for the worst-case conditions,
that is, a device soldered in a circuit board for surface-mount
packages. θJA is determined according to JESD51-9 on a 4-layer
printed circuit board (PCB) with natural convection cooling.
Table 2.
Parameter
Rating
IOVDD Supply Voltage
Input Voltage
3.6 V
3.6 V
ESD Susceptibility
4 kV
Table 3. Thermal Resistance
Package Type
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
θJA
Unit
8-ball, 1.56 mm × 0.76 mm WLCSP
90
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 16
Data Sheet
ADAU7002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
PDM_
DAT
PDM_
CLK
A
SDATA
GND
BCLK
LRCLK
CONFIG
B
C
D
IOVDD
TOP VIEW
(BALL SIDE DOWN)
Figure 2. Pin Configuration (Top Side View)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
PDM_DAT
PDM_CLK
SDATA
BCLK
GND
LRCLK
IOVDD
CONFIG
Type
Description
A1
A2
B1
B2
C1
C2
D1
D2
Input
PDM Data Input
PDM Clock Output
Output
Output
Input
Ground
Input
Serial Data Output for I2S/TDM
Bit Clock for I2S/TDM
Ground
Left/Right Clock for I2S/Frame Sync for TDM
Input/Output and Digital Supply
Configuration Pin
Supply
Input
Rev. 0 | Page 5 of 16
ADAU7002
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
–20
–40
–60
–80
–120
CH1
–130
–140
–150
–160
–170
–180
–190
CH2
–100
–120
–140
0.0001
0.001
0.01
0.1
1
20
100
1k
10k 20k
FREQUENCY (Hz)
NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz)
Figure 3. FFT, fS = 48 kHz, −60 dBFS Input
Figure 6. Total Harmonic Distortion + Noise (THD + N) vs.
Normalized Frequency (Relative to fS)
0.1
0
0
–20
–40
–0.1
–0.2
–0.3
–0.4
–0.5
–60
–80
–100
–120
0.0001
0.001
0.01
0.1
1
–120
–100
–80
–60
–40
–20
0
NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz)
GENERATOR LEVEL (dBFS)
Figure 7. THD + N Level vs. Generator Level
Figure 4. Frequency Response
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
160
140
120
100
80
60
40
20
0
0.0001
0.001
0.01
0.1
1
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
SUPPLY VOLTAGE (V)
NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz)
Figure 8. Supply Current vs. Supply Voltage
Figure 5. Group Delay vs. Normalized Frequency (Relative to fS)
Rev. 0 | Page 6 of 16
Data Sheet
ADAU7002
0
–20
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
1.5
FREQUENCY (MHz)
Figure 9. Out-of-Band Frequency Response (48 kHz Output)
Rev. 0 | Page 7 of 16
ADAU7002
Data Sheet
TYPICAL APPLICATION CIRCUIT
IOVDD
0.1µF
IOVDD
PDM_CLK
PDM_DAT
CONFIG
PDM_CLK
PDM_DAT
CONFIG
LRCLK
BCLK
LRCLK
BCLK
ADAU7002
SDATA
SDATA
GND
OPTIONAL
PULL-DOWN
RESISTOR
Figure 10. Typical Application Circuit
Rev. 0 | Page 8 of 16
Data Sheet
ADAU7002
APPLICATIONS INFORMATION
Table 5. PDM Timing Parameters
Parameter
OVERVIEW
tMIN
10
7
tMAX
Unit
ns
ns
The ADAU7002 provides stereo decimation from a 1-bit PDM
source to a 20-bit PCM audio. The downsampling ratio is fixed
at 64×. The 20-bit downsampled PCM audio is output via
standard I2S or TDM formats.
Data Setup Time, tSETUP
Data Hold Time, tHOLD
PDM data is latched on both edges of the clock.
The input source for the ADAU7002 can be any device that has
a PDM output, such as a digital microphone like the ADMP521.
The output pins of these microphones can connect directly to
the input pins of the ADAU7002.
PDM_CLK
tHOLD
tSETUP
CLOCKING
R
L
R
L
PDM_DAT
The ADAU7002 requires a BCLK rate that is a minimum of 64×
the LRCLK sample rate. BCLK rates of 128×, 192×, 256×, 384×,
and 512× the LRCLK rate are also supported. The ADAU7002
automatically detects the ratio between BCLK and LRCLK and
generates a PDM clock output at 64× the LRCLK rate. The
minimum sample rate is 4 kHz, and the maximum is 96 kHz,
which correspond to a PDM clock range of 256 kHz to 6.144 MHz.
Internally, all processing is done at the PDM_CLK rate.
Figure 11. PDM Timing Diagram
SERIAL AUDIO OUTPUT INTERFACE
The ADAU7002 supports I2S and TDM serial output formats.
Format selection and TDM slot placement is set with the CONFIG
pin. The SDATA pin is in tristate mode, except when the port is
driving serial data based on the CONFIG pin configuration.
When BCLK is removed, the ADAU7002 powers down
automatically. When BCLK is not present, the PDM_CLK
output stops.
Table 6. TDM Slot Selection
Device Setting
I2S Format
CONFIG Pin Configuration
Tie to IOVDD
TDM Slot 1 to Slot 2 Used/Driven, 32-Bit Slots
TDM Slot 3 to Slot 4 Used/Driven, 32-Bit Slots
TDM Slot 5 to Slot 6 Used/Driven, 32-Bit Slots
Tie to GND
Open
Tie to IOVDD through a 47 kΩ resistor
TDM Slot 7 to Slot 8 Used/Driven, 32-Bit Slots
Tie to GND through a 47 kΩ resistor
Rev. 0 | Page 9 of 16
ADAU7002
Data Sheet
Serial Port Timing
tBIH
BCLK
tBIL
tLIS
tLIH
LRCLK
tSODM
SDATA
TDM MODE
MSB
MSB – 1
tSODM
SDATA
2
I S JUSTIFIED
MODE
MSB
Figure 12. Serial Port Timing Diagram
Table 7. I2S/TDM Timing Parameters
Parameter
Symbol
tBIH
tBIL
tLIS
tLIH
tMIN
10
10
10
10
tMAX
Unit
ns
ns
ns
ns
BCLK Pulse Width High
BCLK Pulse Width Low
LRCLK Setup Time
LRCLK Hold Time
Time from BCLK Falling
tSODM
10
ns
LRCLK
BCLK
32
BCLKs
2
2
SDATA
I S LEFT CHANNEL
TRISTATE
TRISTATE
I S RIGHT CHANNEL
20
BCLKs
Figure 13. I2S, CONFIG Pin Tied to IOVDD
LRCLK
BCLK
32
BCLKs
LEFT
RIGHT
TRISTATE
SLOT 3
TRISTATE
SLOT 4
TRISTATE
SLOT 5
TRISTATE
SLOT 6
TRISTATE
SLOT 7
TRISTATE
SDATA
20
BCLKs
SLOT 1
SLOT 2
SLOT 8
Figure 14. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND
Rev. 0 | Page 10 of 16
Data Sheet
ADAU7002
LRCLK
BCLK
32
BCLKs
TRISTATE
SLOT 1
TRISTATE
SLOT 2
LEFT
RIGHT
TRISTATE
SLOT 5
TRISTATE
SLOT 6
TRISTATE
SLOT 7
TRISTATE
SDATA
20
BCLKs
SLOT 3
SLOT 4
SLOT 8
Figure 15. TDM8 Channel 3 and Channel 4, CONFIG Pin Open
LRCLK
BCLK
32
BCLKs
TRISTATE
SLOT 1
TRISTATE
SLOT 2
TRISTATE
SLOT 3
TRISTATE
SLOT 4
LEFT
RIGHT
TRISTATE
SLOT 7
TRISTATE
SLOT 8
SDATA
20
BCLKs
SLOT 5
SLOT 6
Figure 16. TDM8 Channel 5 to Channel 6, CONFIG Pin Tied to IOVDD Through a 47 kΩ Resistor
LRCLK
BCLK
32
BCLKs
TRISTATE
SLOT 1
TRISTATE
SLOT 2
TRISTATE
SLOT 3
TRISTATE
SLOT 4
TRISTATE
SLOT 5
TRISTATE
SLOT 6
LEFT
RIGHT
SDATA
20
BCLKs
SLOT 7
SLOT 8
Figure 17. TDM8 Channel 7 and Channel 8, CONFIG Pin Tied to GND Through a 47 kΩ Resistor
Rev. 0 | Page 11 of 16
ADAU7002
Data Sheet
LRCLK
BCLK
32
BCLKs
LEFT
RIGHT
TRISTATE
SLOT 3
TRISTATE
SLOT 4
SDATA
20
BCLKs
SLOT 1
SLOT 2
Figure 18. TDM4 Channel 1 and Channel 2, CONFIG Pin Tied to IOVDD
LRCLK
BCLK
32
BCLKs
TRISTATE
TRISTATE
SLOT 2
LEFT
RIGHT
SDATA
20
BCLKs
SLOT 1
SLOT 3
SLOT 4
Figure 19. TDM4 Channel 3 and Channel 4, CONFIG Pin Open
LRCLK
BCLK
32
BCLKs
LEFT
RIGHT
SDATA
20
BCLKs
SLOT 1
SLOT 2
Figure 20. TDM2 Channel 1 and Channel 2, CONFIG Pin Tied to IOVDD
Rev. 0 | Page 12 of 16
Data Sheet
ADAU7002
OUTLINE DIMENSIONS
0.800
0.760
0.720
BOTTOM VIEW
(BALL SIDE UP)
ORIENTATION
IDENTIFIER
2
1
A
B
C
D
BALL A1
IDENTIFIER
1.600
1.560
1.520
1.20
REF
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
0.40 BSC
0.330
0.300
0.270
0.560
0.500
0.440
SIDE VIEW
COPLANARITY
0.05
SEATING
PLANE
0.3000
0.260
0.220
0.230
0.200
0.170
Figure 21. 8-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-8-6)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model1
Temperature Range Package Description
Option
CB-8-6
CB-8-6
Branding
ADAU7002ACBZ-R7 −40°C to +85°C
ADAU7002ACBZ-RL −40°C to +85°C
EVAL-ADAU7002Z
8-Ball Wafer Level Chip Scale Package [WLCSP], 7”Tape and Reel
8-Ball Wafer Level Chip Scale Package [WLCSP], 13”Tape and Reel
Evaluation Board
BE
BE
1 Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
ADAU7002
NOTES
Data Sheet
Rev. 0 | Page 14 of 16
Data Sheet
NOTES
ADAU7002
Rev. 0 | Page 15 of 16
ADAU7002
NOTES
Data Sheet
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11265-0-1/13(0)
Rev. 0 | Page 16 of 16
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