EVAL-AD7731EB_技术文档

Low Noise, High Throughput

24-Bit Sigma-Delta ADC

a

AD7731

GENERAL D ESCRIP TIO N

FEATURES

T he AD7731 is a complete analog front-end for process control

applications. T he device has a proprietary programmable gain

front end that allows it to accept a range of input signal ranges,

including low level signals, directly from a transducer. The sigma-

delta architecture of the part consists of an analog modulator

and a low pass programmable digital filter, allowing adjustment

of filter cutoff, output rate and settling time.

24-Bit Sigm a-Delta ADC

16 Bits p-p Resolution at 800 Hz Output Rate

Program m able Output Rates up to 6.4 kHz

Program m able Gain Front End

؎0.0015% Nonlinearity

Buffered Differential Inputs

Program m able Filter Cutoffs

FASTStep™* Mode for Channel Sequencing

Single Supply Operation

T he part features three buffered differential programmable gain

analog inputs (which can be configured as five pseudo-differential

inputs), as well as a differential reference input. T he part oper-

ates from a single +5 V supply and accepts seven unipolar ana-

log input ranges: 0 to +20 mV, +40 mV, +80 mV, +160 mV,

+320 mV, +640 mV and +1.28 V, and seven bipolar ranges:

±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and

±1.28 V. T he peak-to-peak resolution achievable directly from

the part is 16 bits at an 800 Hz output rate. T he part can switch

between channels with 1 ms settling time and maintain a perfor-

mance level of 13 bits of peak-to-peak resolution.

APPLICATIONS

Process Control

PLCs/ DCS

Industrial Instrum entation

T he serial interface on the part can be configured for three-wire

operation and is compatible with microcontrollers and digital

signal processors. T he AD7731 contains self-calibration and

system calibration options and features an offset drift of less

than 5 nV/°C and a gain drift of less than 2 ppm/°C.

T he part is available in a 24-lead plastic DIP, a 24-lead SOIC

and 24-lead T SSOP package.

FUNCTIO NAL BLO CK D IAGRAM

REF IN(–)

DV

DD

REF IN(+)

AV

DD

AD7731

NC

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AV

DD

STANDBY

SYNC

SIGMA-DELTA A/D CONVERTER

100nA

BUFFER

SIGMA-

DELTA

PROGRAMMABLE

DIGITAL

MODULATOR

FILTER

PGA

MUX

100nA

AGND

MCLK IN

CLOCK

GENERATION

SERIAL INTERFACE

MCLK OUT

AND CONTROL LOGIC

REGISTER BANK

SCLK

CS

CALIBRATION

MICROCONTROLLER

DIN

DOUT

AGND

DGND

POL

RDY

RESET

*FASTStep is a trademark of Analog Devices, Inc.

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

(AV = +5 V, DV = +3 V or +5 V; REF IN(+) = +2.5 V; REF IN(–) = AGND; AGND =

DD

DGND = 0 V; f_{CLK IN}= 4.9152 MHz. All specifications T_MINto T_MAXunless otherwise noted.)

AD7731–SPECIFICATIONS

P aram eter

B Version¹

Units

Conditions/Com m ents

ST AT IC PERFORMANCE (CHP = 0)

No Missing Codes²

24

Bits min

SKIP = 0³

Output Noise and Update Rates²

Integral Nonlinearity

See T ables I and II

15

See Note 4

0.5

1/2/5

2.5

See Note 4

0.6

1.5/3/6

3

See Note 4

2

ppm of FSR max

Offset Error²

Offset Error and Offset Drift Refer to Both

Input Range = 20 mV, 40 mV, 80 mV, 160 mV

Input Range = 320 mV/640 mV/1.28 V

Offset Drift vs. T emperature²

µV/°C typ

µV/1000 Hr

Offset Drift vs. T ime⁵

Positive Full-Scale Error^{2, 6}

Positive Full-Scale Drift vs. T emp^{2, 7, 8}

µV/°C typ

µV/1000 Hr

Input Range = 20 mV, 40 mV, 80 mV, 160 mV

Input Range = 320 mV/640 mV/1.28 V

Positive Full-Scale Drift vs. T ime⁵

Gain Error^{2, 9}

Gain Drift vs. T emperature^{2, 7, 10}

Gain Drift vs. T ime⁵

ppm/°C typ

ppm/1000 Hr

10

Bipolar Negative Full-Scale Error²

Negative Full-Scale Drift vs. T emp^{2, 7}

Power Supply Rejection¹¹

Common-Mode Rejection (CMR)¹¹

On AIN

See Note 4

1

90

60

µV/°C typ

dB typ

Input Range = 20 mV

Input Range = 1.28 V

95

85

dB typ

At DC. Input Range = 20 mV

At DC. Input Range = 1.28 V

On AIN

On REF IN

120

60

150

30

dB typ

Analog Input DC Bias Current²

Analog Input DC Bias Current Drift²

Analog Input DC Offset Current²

Analog Input DC Offset Current Drift²

nA max

pA/°C typ

nA max

pA/°C typ

100

ST AT IC PERFORMANCE (CHP = 1)²

No Missing Codes

24

Bits min

Output Noise and Update Rates

Integral Nonlinearity

See T ables III and IV

15

ppm of FSR max

Offset Error

See Note 4

5

25

See Note 4

2

10

See Note 4

2

10

Offset Error and Offset Drift Refer to Both

Unipolar Offset and Bipolar Zero Errors

Offset Drift vs. T emperature

nV/°C typ

nV/1000 Hr typ

Offset Drift vs. T ime⁵

Positive Full-Scale Error⁶

Positive Full-Scale Drift vs. T emp^{7, 8}

Positive Full-Scale Drift vs. T ime⁵

Gain Error⁹

ppm of FS/°C max

ppm of FS/1000 Hr

Gain Drift vs. T emperature^{7, 10}

Gain Drift vs. T ime⁵

ppm/°C max

ppm/1000 Hr

Bipolar Negative Full-Scale Error

Negative Full-Scale Drift vs. T emp

Power Supply Rejection¹¹

Common-Mode Rejection (CMR)¹¹

On AIN

See Note 4

2

110

85

ppm of FS/°C max

dB typ

Input Range = 20 mV

Input Range = 1.28 V

110

85

dB typ

At DC. Input Range = 20 mV

At DC. Input Range = 1.28 V

On AIN

On REF IN

120

50

100

10

dB typ

Analog Input DC Bias Current

Analog Input DC Bias Current Drift

Analog Input DC Offset Current

Analog Input DC Offset Current Drift

nA max

pA/°C typ

nA max

pA/°C typ

50

ANALOG INPUT S/REFERENCE INPUT S

Normal Mode 50 Hz/60 Hz Rejection²

Common-Mode 50 Hz/60 Hz Rejection²

Analog Inputs

88

120

dB min

50 Hz/60 Hz ±1 Hz. SKIP = 0

Differential Input Voltage Ranges¹²

Assuming 2.5 V or 5 V Reference with HIREF

Bit Set Appropriately

0 to +20 or ±20

0 to +40 or ±40

0 to +80 or ±80

0 to +160 or ±160

0 to +320 or ±320

0 to +640 or ±640

0 to +1.28 or ±1.28

mV nom

V nom

RN2, RN1, RN0 of Mode Register = 0, 0, 1

RN2, RN1, RN0 of Mode Register = 0, 1, 0

RN2, RN1, RN0 of Mode Register = 0, 1, 1

RN2, RN1, RN0 of Mode Register = 1, 0, 0

RN2, RN1, RN0 of Mode Register = 1, 0, 1

RN2, RN1, RN0 of Mode Register = 1, 1, 0

RN2, RN1, RN0 of Mode Register = 1, 1, 1

–2–

REV. 0

AD7731

P aram eter

Absolute/Common-Mode Voltage¹³

B Version¹

Units

Conditions/Com m ents

AGND + 1.2 V

AV_DD– 0.95 V

V min

V max

Reference Input

REF IN(+) – REF IN (–) Voltage

Reference DC Input Current

Absolute/Common-Mode Voltage¹⁴

+2.5

+5

5.5

10

AGND – 30 mV

AV_DD+ 30 mV

0.3

V nom

µA max

V min

V max

V min

V max

HIREF Bit of Mode Register = 0

HIREF Bit of Mode Register = 1

HIREF Bit of Mode Register = 0

HIREF Bit of Mode Register = 1

NO REF T rigger Voltage

NO REF Bit Active If VREF Below T his Voltage

NO REF Bit Inactive If VREF Above This Voltage

0.65

LOGIC INPUT S

Input Current

±10

µA max

All Inputs Except SCLK and MCLK IN

V_INL, Input Low Voltage

V_INH, Input High Voltage

SCLK Only (Schmitt T riggered Input)

V_{T +}

V_{T –}

V_{T +}– V_{T –}

0.8

0.4

2.0

V max

V min

DV_DD= +5 V

DV_DD= +3 V

1.4/3

V min/V max

DV_DD= +5 V

DV_DD= +3 V

DV_DD= +5 V

DV_DD= +3 V

DV_DD= +5 V

DV_DD= +3 V

0.95/2.5

0.8/1.4

0.4/1.1

0.4/0.85

0.4/0.8

V_{T +}– V_{T –}

MCLK IN Only

V_INL, Input Low Voltage

V_INH, Input High Voltage

0.8

0.4

3.5

2.5

V max

V min

DV_DD= +5 V

DV_DD= +3 V

DV_DD= +5 V

DV_DD= +3 V

LOGIC OUT PUT S (Including MCLK OUT )

V_OL, Output Low Voltage

0.4

V max

V min

I_SINK= 800 µA Except for MCLK OUT ¹⁵

V_DD¹⁶= +5 V

.

V_OL, Output Low Voltage

V_OH, Output High Voltage

0.4

I_SINK= 100 µA Except for MCLK OUT ¹⁵

16

V_DD= +3 V

4.0

I_SOURCE= 200 µA Except for MCLK OUT ¹⁵

.

16

V_DD= +5 V

DV_DD– 0.6 V

I_SOURCE= 100 µA Except for MCLK OUT ¹⁵

16

V_DD= +3 V

Floating State Leakage Current

±10

6

µA max

pF typ

Floating State Output Capacitance³

T RANSDUCER BURNOUT ¹⁷

AIN1(+) Current

AIN1(–) Current

Initial T olerance @ 25°C

Drift

–100

100

±10

0.1

nA nom

% typ

%/°C typ

SYST EM CALIBRAT ION

Positive Full-Scale Calibration Limit¹⁸

1.05 × FS

V max

FS Is the Nominal Full-Scale Voltage (20 mV,

40 mV, 80 mV, 160 mV, 320 mV, 640 mV, 1.28 V)

Negative Full-Scale Calibration Limit¹⁸

Offset Calibration Limit¹⁹

Input Span¹⁹

–1.05 × FS

0.8 × FS

V max

V min

V max

2.1 × FS

POWER REQUIREMENT S

Power Supply Voltages

AV_DD– AGND Voltage

DV_DDVoltage

+5

V nom

V min to V max

+2.7 to +5.25

With AGND = 0 V

Power Supply Currents

External MCLK. Digital I/Ps = 0 V or DV_DD

AV_DDCurrent (Normal Mode)

DV_DDCurrent (Normal Mode)

AV_DD+ DV_DDCurrent (Standby Mode) 25

Power Dissipation

10.3

1.7

3.2

mA max

µA max

DV_DDof 2.7 V to 3.3 V

DV_DDof 4.75 V to 5.25 V

Typically 10 µA. External MCLK IN = 0 V or DV_DD

AV_DD= DV_DD= +5 V. Digital I/Ps = 0 V or DV_DD

Normal Mode

Standby Mode

67.5

125

mW max

µW max

Typically 50 µW. External MCLK IN = 0 V or DV_DD

REV. 0

–3–

AD7731

NOT ES

¹Temperature Range: –40°C to +85°C.

²Sample tested during initial release.

³No missing codes performance with CHP = 0 and SKIP = 1 is 22 bits.

⁴The offset (or zero) numbers with CHP = 0 can be up to 1 mV precalibration. Internal zero-scale calibration reduces this to 2 µV typical. Offset numbers with CHP = 1 are typically

3 µV precalibration. Internal zero-scale calibration reduces this by about 1 µV. System zero-scale calibration reduces offset numbers with CHP = 0 and CHP = 1 to the order of the

noise. Gain errors can be up to 3000 ppm precalibration with CHP = 0 and CHP = 1. Performing internal full-scale calibrations on all input ranges except the 20 mV and 40 mV input

range reduces the gain error to less than 100 ppm. When operating on the 20 mV or 40 mV range, an internal full-scale calibration should be performed on the 80 mV input range with

a resulting gain error of less than 250 ppm. System full-scale calibration reduces the gain error on all input ranges to the order of the noise. Positive and Negative Full-Scale Errors can

be calculated from the offset and gain errors.

⁵These numbers are generated during life testing of the part.

⁶Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges. See Terminology.

⁷Recalibration at any temperature will remove these errors.

⁸Full-scale drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.

⁹Gain Error is a measure of the difference between the measured and the ideal span between any two points in the transfer function. The two points use to calculate the gain error are

positive full-scale and negative full-scale. See Terminology.

¹⁰Gain Error Drift is a span drift and is effectively the drift of the part if zero-scale calibrations only were performed.

¹¹Power Supply Rejection and Common-Mode Rejection are given here for the upper and lower input voltage ranges. The rejection can be approximated to varying linearly (in dBs)

between these values for the other input ranges.

¹²The analog input voltage range on the AIN(+) inputs is given here with respect to the voltage on the respective AIN(–) input.

¹³The common-mode voltage range on the input pairs applies provided the absolute input voltage specification is obeyed.

¹⁴The common-mode voltage range on the reference input pair (REF IN(+) and REF IN(–)) applies provided the absolute input voltage specification is obeyed.

¹⁵These logic output levels apply to the MCLK OUT output only when it is loaded with a single CMOS load.

16

V

DD

refers to DV_DDfor all logic outputs expect D0 and D1 where it refers to AV_DD. In other words, the output logic high for these two outputs is determined by AV_DD.

¹⁷See Burnout Current section.

¹⁸After calibration, if the input voltage exceeds positive full scale, the converter will output all 1s. If the input is less than negative full scale, then the device outputs all 0s.

¹⁹These calibration and span limits apply provided the absolute input voltage specification is obeyed. The offset calibration limit applies to both the unipolar zero point and the bipolar

zero point.

Specifications subject to change without notice.

(AV = +4.75 V to +5.25 V; DV = +2.7 V to +5.25 V; AGND = DGND = 0 V;

DD

1, 2

f_{CLK IN}= 4.9152 MHz; Input Logic 0 = 0 V, Logic 1 = DV unless otherwise noted)

TIMING CHARACTERISTICS

DD

Lim it at T_MIN, T_MAX

(B Version)

P aram eter

Units

Conditions/Com m ents

Master Clock Range

1

5

50

MHz min

MHz max

ns min

For Specified Performance

t₁

t₂

SYNC Pulse Width

RESET Pulse Width

ns min

Read O per ation

t₃

0

ns min

ns max

ns min

ns max

ns min

ns max

RDY to CS Setup T ime

t₄₄

CS Falling Edge to SCLK Active Edge Setup T ime³

SCLK Active Edge to Data Valid Delay³

DV_DD= +4.75 V to +5.25 V

t₅

60

80

0

60

80

100

0

DV_DD= +2.7 V to +3.3 V

4, 5

t_5A

CS Falling Edge to Data Valid Delay³

DV_DD= +4.75 V to +5.25 V

DV_DD= +2.7 V to +3.3 V

SCLK High Pulse Width

t₆

t₇

SCLK Low Pulse Width

t₈₆

CS Rising Edge to SCLK Inactive Edge Hold T ime³

Bus Relinquish T ime after SCLK Inactive Edge³

t₉

10

80

100

t₁₀

SCLK Active Edge to RDY High^{3, 7}

Wr ite O per ation

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

t₁₆

0

ns min

CS Falling Edge to SCLK Active Edge Setup T ime³

Data Valid to SCLK Edge Setup T ime

Data Valid to SCLK Edge Hold T ime

SCLK High Pulse Width

SCLK Low Pulse Width

CS Rising Edge to SCLK Edge Hold T ime

30

25

100

0

NOTES

¹Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV_DD) and timed from a voltage level of 1.6 V.

²See Figures 15 and 16.

³SCLK active edge is falling edge of SCLK with POL = 1; SCLK active edge is rising edge of SCLK with POL = 0.

⁴T hese numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁵T his specification only comes into play if CS goes low while SCLK is low (POL = 1) or if CS goes low while SCLK is high (POL = 0). It is required primarily for interfacing to

DSP machines.

⁶T hese numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapo-

lated back to remove effects of charging or discharging the 50 pF capacitor. T his means that the times quoted in the timing characteristics are the true bus relinquish times of the

part and as such are independent of external bus loading capacitances.

⁷RDY returns high after the first read from the device after an output update. T he same data can be read again, if required, while RDY is high, although care should be taken that

subsequent reads do not occur close to the next output update.

–4–

REV. 0

AD7731

ABSO LUTE MAXIMUM RATINGS*

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

(T _A= +25°C unless otherwise noted)

θ

_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W

AV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV_DDto DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . –5 V to +0.3 V

AV_DDto DV_DD. . . . . . . . . . . . . . . . . . . . . . . . . . –2 V to +5 V

Analog Input Voltage to AGND . . . . –0.3 V to AV_DD+ 0.3 V

Reference Input Voltage to AGND . . –0.3 V to AV_DD+ 0.3 V

AIN/REF IN Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA

Digital Input Voltage to DGND . . . . –0.3 V to DV_DD+ 0.3 V

Digital Output Voltage to DGND . . . –0.3 V to DV_DD+ 0.3 V

Output Voltage (D0, D1) to DGND . . –0.3 V to AV_DD+ 0.3 V

Operating T emperature Range

Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . +260°C

T SSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW

θ

_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W

Lead T emperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

_JAT hermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W

Lead T emperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. T his is a stress rating only; functional operation of

the device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . . . . . –65°C to +150°C

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

O RD ERING GUID E

Model

Tem perature Range

P ackage D escription

P ackage O ptions

AD7731BN

AD7731BR

AD7731BRU

EVAL-AD7731EB

–40°C to +85°C

Evaluation Board

Plastic DIP

Small Outline

T hin Shrink Small Outline (T SSOP)

N-24

R-24

RU-24

I

(800µA AT DV = +5V

DD

SINK

100µA AT DV = +3V)

DD

TO OUTPUT

+1.6V

50pF

I

(200µA AT DV = +5V

SOURCE

DD

100µA AT DV = +3V)

DD

Figure 1. Load Circuit for Access Tim e and Bus Relinquish Tim e

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7731 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

–5–

AD7731

PROGRAMMABLE

DIGITAL FILTER

DIFFERENTIAL

REFERENCE

PROGRAMMABLE GAIN

AMPLIFIER

SIGMA-DELTA ADC

BUFFER AMPLIFIER

TWO STAGE FILTER THAT

ALLOWS PROGRAMMING OF

OUTPUT UPDATE RATE AND

SETTLING TIME AND THAT

HAS A FASTSTEP^TMMODE

(SEE FIGURE 3)

THE REFERENCE INPUT TO THE

PART IS DIFFERENTIAL AND

FACILITATES RATIOMETRIC

OPERATION. THE REFERENCE

VOLTAGE CAN BE SELECTED TO

BE NOMINALLY +2.5V OR +5V.

REFERENCE DETECT CIRCUITRY

TESTS FOR OPEN OR SHORTED

REFERENCES

THE PROGRAMMABLE

GAIN AMPLIFIER ALLOWS

SEVEN UNIPOLAR AND

SEVEN BIPOLAR INPUT

RANGES FROM +20mV TO

+1.28V

THE SIGMA-DELTA

ARCHITECTURE ENSURES

24 BITS NO MISSING

CODES. THE ENTIRE

SIGMA-DELTA ADC CAN BE

CHOPPED TO REMOVE

DRIFT ERRORS

THE BUFFER AMPLIFIER

PRESENTS A HIGH

IMPEDANCE INPUT STAGE

FOR THE ANALOG INPUTS

ALLOWING SIGNIFICANT

EXTERNAL SOURCE

IMPEDANCES

BURNOUT CURRENTS

TWO 100nA BURNOUT

CURRENTS ALLOW THE

USER TO EASILY DETECT

IF A TRANSDUCER HAS

BURNT OUT OR GONE

OPEN-CIRCUIT

SEE PAGE 24

SEE PAGE 23

SEE PAGE 24

SEE PAGE 23

SEE PAGE 24

STANDBY MODE

REF IN(–)

DV

DD

REF IN(+)

AV

DD

THE STANDBY MODE

REDUCES POWER

SEE PAGE 23

CONSUMPTION TO 50␮W

AV

DD

SEE PAGE 32

STANDBY

AIN1

AIN2

SIGMA-DELTA A/D CONVERTER

SIGMA-

DELTA

MODULATOR

PROGRAMMABLE

DIGITAL

CLOCK OSCILLATOR

CIRCUIT

SYNC

AIN3/D1

AIN4/D0

AIN5

FILTER

MUX

PGA

THE CLOCK SOURCE FOR THE

PART CAN BE PROVIDED BY

AN EXTERNALLY-APPLIED

CLOCK OR BY CONNECTING A

CRYSTAL OR CERAMIC

RESONATOR ACROSS THE

CLOCK PINS

BUFFER

MCLK IN

CLOCK

GENERATION

SERIAL INTERFACE

AND CONTROL LOGIC

MCLK OUT

AGND

AIN6

REGISTER BANK

SCLK

SEE PAGE 31

CS

CALIBRATION

MICROCONTROLLER

DIN

SERIAL INTERFACE

DOUT

AD7731

SPI*-COMPATIBLE OR DSP-

COMPATIBLE SERIAL

INTERFACE THAT CAN BE

OPERATED FROM JUST THREE

WIRES. ALL FUNCTIONS ON THE

PART (APART FROM MASTER

RESET) CAN BE ACCESSED VIA

THE SERIAL INTERFACE

AGND

DGND

POL

RDY

RESET

ANALOG MULTIPLEXER

OUTPUT DRIVERS

A DIFFERENTIAL MULTIPLEXER

ALLOWS SELECTION OF THREE

FULLY DIFFERENTIAL PAIRS OR

FIVE PSEUDO-DIFFERENTIAL INPUT

PAIRS TO BE SWITCHED TO THE

BUFFER AMPLIFIER. THE

REGISTER BANK

CALIBRATION

MICROCONTROLLER

SEE PAGE 33

THE AIN3 AND AIN4 INPUT

CHANNELS CAN BE

RECONFIGURED TO BECOME

TWO OUTPUT DIGITAL PORT

LINES THAT CAN BE

PROGRAMMED OVER THE

SERIAL INTERFACE

TWELVE REGISTERS CONTROL

ALL FUNCTIONS ON THE PART

AND PROVIDE STATUS

INFORMATION AND

CONVERSION RESULTS

THE AD7731 OFFERS A

NUMBER OF DIFFERENT

CALIBRATION OPTIONS

INCLUDING SELF AND

SYSTEM CALIBRATION

MULTIPLEXER IS CONTROLLED

VIA THE SERIAL INTERFACE

SEE PAGE 20

SEE PAGE 23

SEE PAGE 28

SEE PAGE 32

*SPI IS A TRADEMARK OF MOTOROLA, INC.

Figure 2. Detailed Functional Block Diagram

–6–

REV. 0

AD7731

3

SINC FILTER

SKIP MODE

22-TAP FIR FILTER

INPUT CHOPPING

IN SKIP MODE, THERE IS NO

SECOND STAGE OF FILTERING ON

THE PART. THE SINC³FILTER IS

THE ONLY FILTERING PERFORMED

ON THE PART. THIS IS THE

WITH SKIP DISABLED, THE NORMAL

OPERATING MODE OF THE SECOND STAGE

OF THE DIGITAL FILTERING ON THE PART IS

A FIXED 22-TAP FIR FILTER. IN SKIP MODE,

THIS FIR FILTER IS BYPASSED. WHEN

FASTSTEP™MODE IS ENABLED AND A

STEP INPUT IS DETECTED, THE SECOND

STAGE FILTERING IS PERFORMED BY THE

FAST STEP FILTER UNTIL THE OUTPUT OF

THIS FILTER HAS FULLY SETTLED

THE FIRST STAGE OF THE DIGITAL

FILTERING ON THE PART IS THE

SINC³FILTER. THE OUTPUT UPDATE

RATE AND BANDWIDTH OF THIS

FILTER CAN BE PROGRAMMED. IN

SKIP MODE, THE SINC³FILTER IS

THE ONLY FILTERING PERFORMED

ON THE P3T.

THE ANALOG INPUT TO THE PART

CAN BE CHOPPED. IN CHOPPING MODE,

THE INPUT IS CHOPPEDAND THE OUTPUT OF

THE FIRST STAGE FILTER IS CHOPPED

REMOVING ERRORS IN THAT PATH.

THE DEFAULT CONDITION IS

SECOND STAGE FILTER

CHOPPING DISABLED

SEE PAGE 25

SEE PAGE 26

22-TAP

FIR FILTER

PGA &

SIGMA-DELTA

MODULATOR

SKIP

3

SINC

OUTPUT

SCALING

ANALOG

CHOP

DIGITAL

OUTPUT

CHOP

BUFFER

FILTER

INPUT

FASTSTEP™

FILTER

FASTSTEP™ FILTER

YY

OUTPUT CHOPPING

OUTPUT SCALING

BUFFER

PGA & SIGMA-DELTA

MODULATOR

THE OUTPUT WORD FROM THE

DIGITAL FILTER IS SCALED BY THE

CALIBRATION COEFFICIENTS

BEFORE BEING PROVIDED AS THE

CONVERSION RESULT

THE INPUT SIGNAL IS BUFFERED

ON-CHIP BEFORE BEING APPLIED

TO THE SAMPLING CAPACITOR OF

THE SIGMA DELTA MODULATOR.

THIS ISOLATES THE SAMPLING

CAPACITOR CHARGING CURRENTS

FROM THE ANALOG INPUT PINS

THE OUTPUT OF THE FIRST STAGE

OF FILTERING ON THE PART CAN

BE CHOPPED. THE DEFAULT

CONDITION IS CHOPPING

DISABLED

WHEN FASTSTEP™ MODE IS

ENABLED AND A STEP CHANGE ON

THE INPUT HAS BEEN DETECTED,

THE SECOND STAGE FILTERING IS

PERFORMED BY THE FASTSTEP™

FILTER UNTIL THE FIR FILTER HAS

FULLY SETTLED.

THE PROGRAMMABLE GAIN

CAPABILITY OF THE PART IS

INCORPORATED AROUND THE

SIGMA DELTA MODULATOR.THE

MODULATOR PROVIDES A HIGH-

FREQUENCY 1-BIT DATA STREAM

TO THE DIGITAL FILTER.

SEE PAGE 29

SEE PAGE 25

SEE PAGE 23

SEE PAGE 28

SEE PAGE 24

Figure 3. Signal Processing Chain

P IN CO NFIGURATIO N

1

2

24

23

22

21

SCLK

MCLK IN

MCLK OUT

POL

DGND

DV

DD

3

4

DIN

DOUT

5

20 RDY

SYNC

AD7731

TOP VIEW

6

19

RESET

NC

CS

7

18

STANDBY

(Not to Scale)

8

17 AIN6

AGND

9

16 AIN5

AV

DD

10

15 REF IN(–)

AIN1

14 REF IN(+)

AIN2 11

AIN3/D1 12

13

AIN4/D0

NC = NO CONNECT

P IN FUNCTIO N D ESCRIP TIO NS

P in

No.

P in

Mnem onic

Function

1

SCLK

Serial Clock. Schmitt-T riggered Logic Input. An external serial clock is applied to this input to transfer

serial data to or from the AD7731. T his serial clock can be a continuous clock with all data transmitted in a

continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-

mitted to or from the AD7731 in smaller batches of data.

2

MCLK IN

Master Clock signal for the device. T his can be provided in the form of a crystal/resonator or external clock.

A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN

pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. T he part is specified

with a clock input frequency of 4.9152 MHz.

REV. 0

–7–

AD7731

P IN FUNCTIO N D ESCRIP TIO NS (Continued)

P in

No.

P in

Mnem onic

Function

3

4

MCLK OUT

POL

When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between

MCLK IN and MCLK OUT . If an external clock is applied to the MCLK IN, MCLK OUT provides an

inverted clock signal. T his clock can be used to provide a clock source for external circuits and MCLK OUT

is capable of driving one CMOS load.

Clock Polarity. Logic Input. T his determines the polarity of the serial clock. If the active edge for the proces-

sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7731 puts out data on

the DAT A OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the

DAT A IN line in a write operation on a high-to-low transition of SCLK. In applications with a noncontinuous

serial clock (such as most microcontroller applications), this means that the serial clock should idle low

between data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input

should be high. In this mode, the AD7731 puts out data on the DAT A OUT line in a read operation on a

high-to-low transition of SCLK and clocks in data from the DAT A IN line in a write operation on a low-to-

high transition of SCLK. In applications with a noncontinuous serial clock (such as most microcontroller

applications), this means that the serial clock should idle high between data transfers.

5

6

SYNC

Logic Input that allows for synchronization of the digital filters and analog modulators when using a number

of AD7731s. While SYNC is low, the nodes of the digital filter, the filter control logic and the calibration

control logic are reset and the analog modulator is also held in its reset state. SYNC does not affect the

digital interface but does reset RDY to a high state if it is low. While SYNC is asserted, the Mode Bits may

be set up for a subsequent operation that will commence when the SYNC pin is deasserted.

RESET

Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and

all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock

oscillator is reset when the RESET pin is exercised.

7

NC

No Connect. T he user is advised not to connect anything to this pin.

Ground reference point for analog circuitry.

8

AGND

AV_DD

AIN1

9

Analog Positive Supply Voltage. T he AV_DDto AGND differential is 5 V nominal.

10

Analog Input Channel 1. Programmable-gain analog input that can be used as a pseudo-differential input

when used with AIN6 or as the positive input of a differential pair when used with AIN2.

11

12

AIN2

Analog Input Channel 2. Programmable-gain analog input that can be used as a pseudo-differential input

when used with AIN6 or as the negative input of a differential pair when used with AIN1.

AIN3/D1

Analog Input Channel 3 or Digital Output 1. T his pin can be used as either an analog input or a digital

output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain

analog input, it can be used as a pseudo-differential input when used with AIN6 or as the positive input of a

differential pair when used with AIN4. When selected as a digital output, this output can be programmed

over the serial interface using bit D1 of the Mode Register.

13

14

AIN4/D0

Analog Input Channel 4 or Digital Output 0. T his pin can be used as either an analog input or a digital

output bit as determined by the DEN bit of the Mode Register. When selected as a programmable-gain

analog input, it can be used as a pseudo-differential input when used with AIN6 or as the negative input of a

differential pair when used with AIN3. When selected as a digital output, this output can be programmed

over the serial interface using bit D0 of the Mode Register.

REF IN(+)

Reference Input. Positive terminal of the differential reference input to the AD7731. REF IN(+) can lie

anywhere between AV_DDand AGND. T he nominal reference voltage (i.e., the differential voltage between

REF IN(+) and REF IN(–)) should be +2.5 V when the HIREF bit of the Mode Register is 0 and is +5 V

when the HIREF bit of the Mode Register is 1.

15

16

17

18

19

REF IN(–)

AIN5

Reference Input. Negative terminal of the differential reference input to the AD7731. T he REF IN(–) can lie

anywhere between AV_DDand AGND.

Analog Input Channel 5. Programmable-gain analog input which can be used is the positive input of a differ-

ential pair when used with AIN6.

AIN6

Analog Input Channel 6. Reference point for AIN1 through AIN4 in pseudo-differential mode or as the

negative input of a differential input pair when used with AIN5.

STANDBY

CS

Logic Input. T aking this pin low shuts down the analog and digital circuitry, reducing current consumption

to the 10 µA range. T he on-chip registers retain all their values when the part is in standby mode.

Chip Select. Active low Logic Input used to select the AD7731. With this input hardwired low, the

AD7731 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to interface to the

device. CS can be used to select the device in systems with more than one device on the serial bus or as a

frame synchronization signal in communicating with the AD7731.

–8–

REV. 0

AD7731

P IN FUNCTIO N D ESCRIP TIO NS (Continued)

P in

No.

P in

Mnem onic

Function

20

RDY

Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a

logic low on this output indicates that a new output word is available from the AD7731 data register. T he

RDY pin will return high upon completion of a read operation of a full output word. If no data read has

taken place after an output update, the RDY line will return high prior to the next output update, remain

high while the update is taking place and return low again. T his gives an indication of when a read operation

should not be initiated to avoid initiating a read from the data register as it is being updated. In calibration

mode, RDY goes high when calibration is initiated and returns low to indicate that calibration is complete. A

number of different events on the AD7731 set the RDY high and these are outlined in T able XVII.

21

22

DOUT

DIN

Serial Data Output with serial data being read from the output shift register on the part. T his output shift

register can contain information from the calibration registers, mode register, status register, filter register or

data register depending on the register selection bits of the Communications Register.

Serial Data Input with serial data being written to the input shift register on the part. Data from this input

shift register is transferred to the calibration registers, mode register, communications register or filter regis-

ter depending on the register selection bits of the Communications Register.

23

24

DV_DD

Digital Supply Voltage, +3 V or +5 V nominal.

Ground reference point for digital circuitry.

DGND

P O SITIVE FULL-SCALE O VERRANGE

TERMINO LO GY

Positive Full-Scale Overrange is the amount of overhead avail-

able to handle input voltages on AIN(+) input greater than

AIN(–) + V_REF/GAIN (for example, noise peaks or excess volt-

ages due to system gain errors in system calibration routines)

without introducing errors due to overloading the analog modu-

lator or overflowing the digital filter.

INTEGRAL NO NLINEARITY

T his is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. T he end-

points of the transfer function are zero scale (not to be confused

with bipolar zero), a point 0.5 LSB below the first code transi-

tion (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB

above the last code transition (111 . . . 110 to 111 . . . 111). T he

error is expressed as a percentage of full scale.

NEGATIVE FULL-SCALE O VERRANGE

T his is the amount of overhead available to handle voltages on

AIN(+) below AIN(–) – V_REF/GAIN without overloading the

analog modulator or overflowing the digital filter.

P O SITIVE FULL-SCALE ERRO R

Positive Full-Scale Error is the deviation of the last code transi-

tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage

(AIN(–) + V_REF/GAIN – 3/2 LSBs). It applies to both unipolar

and bipolar analog input ranges.

O FFSET CALIBRATIO N RANGE

In the system calibration modes, the AD7731 calibrates its

offset with respect to the analog input. T he Offset Calibration

Range specification defines the range of voltages the AD7731

can accept and still accurately calibrate offset.

UNIP O LAR O FFSET ERRO R

Unipolar Offset Error is the deviation of the first code transition

from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-

ating in the unipolar mode.

FULL-SCALE CALIBRATIO N RANGE

T his is the range of voltages that the AD7731 can accept in the

system calibration mode and still accurately calibrate full scale.

BIP O LAR ZERO ERRO R

T his is the deviation of the midscale transition (0111 . . . 111

to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) –

0.5 LSB) when operating in the bipolar mode.

INP UT SP AN

In system calibration schemes, two voltages applied in sequence

to the AD7731’s analog input define the analog input range.

T he input span specification defines the minimum and maxi-

mum input voltages from zero to full scale that the AD7731 can

accept and still accurately calibrate gain.

GAIN ERRO R

T his is a measure of the span error of the ADC. It is a measure

of the difference between the measured and the ideal span be-

tween any two points in the transfer function. T he two points

used to calculate the gain error are positive full scale and nega-

tive full scale.

BIP O LAR NEGATIVE FULL-SCALE ERRO R

T his is the deviation of the first code transition from the ideal

AIN(+) voltage (AIN(–) – V_REF/GAIN + 0.5 LSB) when operat-

ing in the bipolar mode. Negative full-scale error is a summation

of zero error and gain error.

REV. 0

–9–

AD7731

O UTP UT NO ISE AND RESO LUTIO N SP ECIFICATIO N

T he AD7731 has a number of different modes of operation of the on-chip filter and chopping features. T hese options are discussed

in more detail in later sections. T he part can be programmed either to optimize the throughput rate and settling time or to optimize

noise and drift performance. Noise tables for two of the primary modes of operation of the part are outlined below for a selection of

output rates and settling times. T he first mode, where the AD7731 is configured with CHP = 0 and SKIP mode enabled, provides

fast settling time while still maintaining high resolution. T he second mode, where CHP = 1 and the full second filter is included,

provides very low noise numbers with lower output rates. Settling time refers to the time taken to get an output that is 100% settled

to the new value after a channel change or exercising SYNC.

O utput Noise (CH P = 0, SKIP = 1)

T able I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in

nonchop mode (CHP of Filter Register = 0) and with the second filter bypassed (SKIP of Filter Register = 1). T he table is generated

with a master clock frequency of 4.9152 MHz. T hese numbers are typical and generated at a differential analog input voltage of 0 V.

T he output update rate is selected via the SF0 to SF11 bits of the Filter Register. T able II, meanwhile, shows the output peak-to-

peak resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in

T able II represent the resolution for which there will be no code flicker within a six-sigma limit. T hey are not calculated based on

rms noise but on peak-to-peak noise.

T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the

same as the equivalent bipolar input range. As a result, the numbers in T able I will remain the same for unipolar ranges. T o calculate

the numbers for T able II for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.

Table I. O utput Noise vs. Input Range and Update Rate (CH P = 0, SKIP = 1)

Typical O utput RMS Noise in ␮V

O utput

D ata Rate

–3 dB

Frequency Word

SF

Settling

Tim e

Input Range

؎1.28 V ؎640 m V ؎320 m V ؎160 m V ؎80 m V ؎40 m V ؎20 m V

150 Hz

200 Hz

300 Hz

400 Hz

600 Hz

800 Hz

1200 Hz

1600 Hz

2400 Hz

3200 Hz

4800 Hz

6400 Hz

39.3 Hz

52.4 Hz

78.6 Hz

104.8 Hz

157 Hz

209.6 Hz

314 Hz

419.2 Hz

629 Hz

2048

1536

1024

768

512

384

256

192

128

96

20 ms

15 ms

10 ms

7.5 ms

5 ms

3.75 ms

2.5 ms

1.87 ms

1.25 ms

0.94 ms

2.6

3.0

3.7

4.2

5.2

6

7.8

10.9

27.1

47

1.45

1.66

2

2.3

2.9

3.3

4.3

5.4

13.9

24.4

50.3

97

0.87

1.02

1.26

1.46

1.78

2.1

2.6

3.5

7.3

0.6

0.43

0.48

0.58

0.69

0.85

0.98

1.27

1.51

2.22

3.1

0.28

0.32

0.41

0.46

0.58

0.66

0.82

0.94

1.24

1.9

0.2

0.69

0.84

1.0

1.2

1.4

1.8

2.18

3.5

5.3

12.5

24

0.22

0.28

0.32

0.41

0.47

0.57

0.64

0.83

1.0

838.4 Hz

1260 Hz

1676 Hz

11.4

24.5

48

64

48

0.625 ms 99

0.47 ms 193

6.5

11.8

3.3

6.6

1.7

3.0

Table II. P eak-to-P eak Resolution vs. Input Range and Update Rate (CH P = 0, SKIP = 1)

P eak-to-P eak Resolution in Bits

O utput

D ata Rate

–3 dB

Frequency Word

SF

Settling

Tim e

Input Range

؎1.28 V ؎640 m V ؎320 m V ؎160 m V ؎80 m V ؎40 m V ؎20 m V

150 Hz

200 Hz

300 Hz

400 Hz

600 Hz

800 Hz

1200 Hz

1600 Hz

2400 Hz

3200 Hz

4800 Hz

6400 Hz

39.3 Hz

52.4 Hz

78.6 Hz

104.8 Hz

157 Hz

209.6 Hz

314 Hz

419.2 Hz

629 Hz

2048

1536

1024

768

512

384

256

192

128

96

20 ms

15 ms

10 ms

7.5 ms

5 ms

3.75 ms

2.5 ms

1.87 ms

1.25 ms

0.94 ms

17.5

17

16.5

16

15.5

15

17

16.5

16

17

16.5

16

15.5

15

14.5

14

16

15.5

15

14.5

14

16.5

16

15.5

15

14.5

14

13.5

13

12

15

16

14.5

14

13.5

13

16

15.5

15

14

13

14

15.5

14

13

12

13.5

13

12.5

12

14

13

838.4 Hz

1260 Hz

1676 Hz

13

12

11

64

48

0.625 ms 12

0.47 ms 11

12

11

11.5

11

–10–

REV. 0

AD7731

O utput Noise (CH P = 1, SKIP = 0)

T able III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in

chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. T he numbers are generated with a mas-

ter clock frequency of 4.9152 MHz. T hese numbers are typical and generated at a differential analog input voltage of 0 V. T he out-

put update rate is selected via the SF0 to SF11 bits of the Filter Register. T able IV, meanwhile, shows the output peak-to-peak

resolution in bits (rounded to the nearest 0.5 LSB) for the same output update rates. It is important to note that the numbers in

T able IV represent the resolution for which there will be no code flicker within a six-sigma limit. T hey are not calculated based on

rms noise but on peak-to-peak noise.

T he numbers are generated for the bipolar input ranges. When the part is operated in unipolar mode, the output noise will be the

same as the equivalent bipolar input range. As a result, the numbers in T able III will remain the same for unipolar ranges. T o calcu-

late the number for T able IV for unipolar input ranges simply subtract one from the peak-to-peak resolution number in bits.

Table III. O utput Noise vs. Input Range and Update Rate (CH P = 1, SKIP = 0)

Typical O utput RMS Noise in nV

O utput

–3 dB

SF

Settling Tim e

Input Range

D ata Rate Frequency Word Norm al Fast Step ؎1.28 V ؎640 m V ؎320 m V ؎160 m V ؎80 m V ؎40 m V ؎20 m V

50 Hz

1.97 Hz

3.95 Hz

5.92 Hz

7.9 Hz

15.8 Hz

31.6 Hz

2048

1024

683

512

256

440 ms

220 ms

147 ms

110 ms

55 ms

40 ms

20 ms

13.3 ms

10 ms

5 ms

700

980

1230

1260

2000

3800

425

550

700

840

1230

2100

265

330

445

500

690

1400

170

230

270

340

430

760

120

190

210

245

335

590

85

55

90

100

105

160

220

100 Hz

150 Hz

200 Hz

400 Hz

800 Hz

115

140

170

215

345

128

27.5 ms 2.5 ms

Table IV. P eak-to-P eak Resolution vs. Input Range and Update Rate (CH P = 1, SKIP = 0)

P eak-to-P eak Resolution in Bits

O utput

–3 dB

SF

Settling Tim e

Input Range

D ata Rate Frequency Word Norm al Fast Step ؎1.28 V ؎640 m V ؎320 m V ؎160 m V ؎80 m V ؎40 m V ؎20 m V

50 Hz

1.97 Hz

3.95 Hz

5.92 Hz

7.9 Hz

15.8 Hz

31.6 Hz

2048

1024

683

512

256

440 ms

230 ms

147 ms

110 ms

55 ms

40 ms

30 ms

13.3 ms

10 ms

5 ms

19

18.5

17.5

17

19

18.5

18

17.5

16.5

18.5

18

17.5

17

18.5

18

17.5

17

18

17

16.5

15.5

17.5

17

16.5

16

17

16

15.5

15

100 Hz

150 Hz

200 Hz

400 Hz

800 Hz

128

27.5 ms 2.5 ms

16

15

COMMUNICATIONS REGISTER

RS2 RS1 RS0

DIN

O N-CH IP REGISTERS

T he AD7731 contains 12 on-chip registers that can be accessed

via the serial port of the part. T hese registers are summarized in

Figure 4 and in T able V, and described in detail in the following

sections.

DOUT

STATUS REGISTER

DATA REGISTER

REGISTER

SELECT

DECODER

DIN

DOUT

MODE REGISTER

DIN

FILTER REGISTER

OFFSET REGISTER (x3)

GAIN REGISTER (x3)

TEST REGISTER

Figure 4. Register Overview

REV. 0

–11–

AD7731

Table V. Sum m ary of O n-Chip Registers

P ower-O n/Reset

Register Nam e

Type

Size

D efault Value

Function

Communications

Register

Write Only 8 Bits

Not Applicable

All operations to other registers are initiated through

the Communications Register. T his controls whether

subsequent operations are read or write operations

and also selects the register for that subsequent opera-

tion. Most subsequent operations return control to

the Communications Register except for the continu-

ous read mode of operation.

WEN

ZERO RW1

RW0 ZERO

RS2

RS1

RS0

Status Register

Read Only 8 Bits

CX Hex

MS1 MS0

Provides status information on conversions, calibra-

tions, settling to step inputs, standby operation and

the validity of the reference voltage.

RDY

STDY

STBY NOREF

MS3

MS2

Data Register

Read Only 16 Bits or 24 Bits 000000 Hex

Provides the most up-to-date conversion result from

the part. Register length can be programmed to be

16 bit or 24 bit.

Mode Register

Read/Write 16 Bits

0174 Hex

Controls functions such as mode of operation, uni-

polar/bipolar operation, controlling the function of

AIN3/D1 and AIN4/D0, burnout current and Data

Register word length. It also contains the reference

selection bit, the range selection bits and the channel

selection bits.

B/U

MD2

MD1

RN2

MD0

RN1

DEN

BO

D1

D0

WL

CH0

HIREF

RN0

CH2

CH1

Filter Register

SF11 SF10

Read/Write 16 Bits

2002 Hex

Controls the amount of averaging in the first stage

filter, selects the fast step and skip modes and con-

trols the chopping modes on the part.

SF9

SF1

SF8

SF0

SF7

SF6

SF5

SF4

SF3

SF2

ZERO CHP

SKIP

FAST

Offset Register

Gain Register

T est Register

Read/Write 24 Bits

Contains a 24-bit word which is the offset calibration

coefficient for the part. T he contents of this register

are used to provide offset correction on the output

from the digital filter. T here are three Offset Regis-

ters on the part and these are associated with input

channel pairs as outlined in T able XIII.

Contains a 24-bit word which is the gain calibration

coefficient for the part. T he contents of this register

are used to provide gain correction on the output

from the digital filter. T here are three Gain Registers

on the part and these are associated with input chan-

nel pairs as outlined in T able XIII.

000000 Hex

Controls the test modes of the part which are used

when testing the part. The user is advised not to

change the contents of this r egister .

–12–

REV. 0

AD7731

Com m unications Register (RS2-RS0 = 0, 0, 0)

T he Communications Register is an 8-bit write-only register. All communications to the part must start with a write operation to the

Communications Register. T he data written to the Communications Register determines whether the next operation is a read or

write operation, the type of read operation and to which register this operation takes place. For single-shot read or write operations,

once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write op-

eration to the Communications Register. T his is the default state of the interface, and on power-up or after a RESET, the AD7731 is

in this default state waiting for a write operation to the Communications Register. In situations where the interface sequence is lost, a

write operation of at least 32 serial clock cycles with DIN high, returns the AD7731 to this default state by resetting the part. T able

VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits

are in the Communications Register. CR7 denotes the first bit of the data stream.

Table VI. Com m unications Register

CR6

CR5

CR4

CR3

CR2

RS2

CR1

RS1

CR0

RS0

CR7

WEN

ZERO

RW1

RW0

ZERO

Bit

Location

Mnem onic

D escription

CR7

WEN

Write Enable Bit. A 0 must be written to this bit so the write operation to the Communica-

tions Register actually takes place. If a 1 is written to this bit, the part will not clock on to

subsequent bits in the register. It will stay at this bit location until a 0 is written to this bit.

Once a 0 is written to the WEN bit, the next seven bits will be loaded to the Communica-

tions Register.

CR6

ZERO

A zero m ust be written to this bit to ensure correct operation of the AD7731.

CR5, CR4

RW1, RW0

Read Write Mode Bits. T hese two bits determine the nature of the subsequent read/write

operation. T able VII outlines the four options.

Table VII. Read/Write Mode

RW1

RW0

Read/Wr ite Mode

0

1

0

1

0

1

Single Write to Specified Register

Single Read of Specified Register

Start Continuous Read of Specified Register

Stop Continuous Read Mode

With 0, 0 written to these two bits, the next operation is a write operation to the register

specified by bits RS2, RS1, RS0. Once the subsequent write operation to the specified regis-

ter has been completed, the part returns to where it is expecting a write operation to the

Communications Register.

With 0, 1 written to these two bits, the next operation is a read operation of the register specified

by bits RS2, RS1, RS0. Once the subsequent read operation to the specified register has been

completed, the part returns to where it is expecting a write operation to the Communications

Register.

Writing 1, 0 to these bits, sets the part into a mode of continuous reads from the register

specified by bits RS2, RS1, RS0. T he most likely registers which the user will want to use this

function with are the Data Register and the Status Register. Subsequent operations to the

part will consist of read operations to the specified register without any intermediate writes to

the Communications Register. T his means that once the next read operation to the specified

register has taken place, the part will be in a mode where it is expecting another read from

that specified register. T he part will remain in this continuous read mode until 30 Hex has

been written to bits RW1 and RW0.

When 1, 1 is written to these bits (and 0 written to bits CR3 through CR0), the continuous

read mode is stopped and the part returns to where it is expecting a write operation to the

Communications Register. Note, the part continues to look at the DIN line on each SCLK

edge during the continuous read mode so that it can determine when to stop the continuous

read mode. T herefore, the user must be careful not to inadvertently exit the continuous read

mode or reset the part by writing a series of 1s to the part. T he easiest way to avoid this is to

place a logic 0 on the DIN line while the part is in continuous read mode.

REV. 0

–13–

AD7731

Bit

Location

Mnem onic

D escription

CR3

ZERO

A zero m ust be written to this bit to ensure correct operation of the AD7731.

CR2-CR0

RS2-RS0

Register Selection Bits. RS2 is the MSB of the three selection bits. The three bits select to which

one of eight on-chip registers the next read or write operation takes place as shown in Table VIII.

Table VIII. Register Selection

RS2

RS1

RS0

Register

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Communications Register (Write Operation)

Status Register (Read Operation)

Data Register

Mode Register

Filter Register

No Register Access

Offset Register

Gain Register

T est Register

Status Register (RS2-RS0 = 0, 0, 0); P ower -O n/Reset Status: CX H ex

T he Status Register is an 8-bit read-only register. T o access the Status Register, the user must write to the Communications Register

selecting either a single-shot read or continuous read mode and load bits RS2, RS1, RS0 with 0, 0, 0. Table IX outlines the bit desig-

nations for the Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 de-

notes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. The number in brackets

indicates the power-on/reset default status of that bit.

Table IX. Status Register

SR7

SR6

SR5

SR4

SR3

SR2

SR1

SR0

RDY (1)

STDY (1)

STBY (0) NOREF (0) MS3 (X)

MS2 (X)

MS1 (X)

MS0 (X)

Bit

Location

Mnem onic

D escription

SR7

SR6

RDY

Ready Bit. T his bit provides the status of the RDY flag from the part. T he status and func-

tion of this bit is the same as the RDY output pin. A number of events set the RDY bit high

as indicated in T able XVII.

STDY

Steady Bit. T his bit is updated when the filter writes a result to the Data Register. If the filter

is in FASTStep™ mode (see Filter Register section), and responding to a step input, the

STDY bit remains high as the initial conversion results become available. T he RDY output

and bit are set low on these initial conversions to indicate that a result is available. However,

if the STDY is high, it indicates that the result being provided is not from a fully settled

second-stage FIR filter. When the FIR filter has fully settled, the STDY bit will go low coin-

cident with RDY. If the part is never placed into its FASTStep™ mode, the STDY bit will go

low at the first Data Register read and it is not cleared by subsequent Data Register reads.

A number of events set the STDY bit high as indicated in T able XVII. STDY is set high

along with RDY by all events in the table except a Data Register read.

SR5

ST BY

Standby Bit. T his bit indicates whether the AD7731 is in its Standby Mode or normal mode

of operation. T he part can be placed in its standby mode using the STANDBY input pin or

by writing 011 to the MD2 to MD0 bits of the Mode Register. T he power-on/reset status of

this bit is 0 assuming the STANDBY pin is high.

SR4

NOREF

MS3-MS0

No Reference Bit. If the voltage between the REF IN(+) and REF IN(–) pins is below 0.5 V

or either of these inputs is open-circuit, the NOREF bit goes to 1. If NOREF is active on

completion of a conversion, the Data Register is loaded with all 1s. If NOREF is active on

completion of a calibration, updating of the calibration registers is inhibited.

SR3-SR0

T hese bits are for factory use. T he power-on/reset status of these bits varies depending on the

factory-assigned number.

–14–

REV. 0

AD7731

D ata Register (RS2-RS0 = 0, 0, 1); P ower O n/Reset Status: 000000 H ex

T he Data Register on the part is a read-only register that contains the most up-to-date conversion result from the AD7731. Figure 5

shows a flowchart for reading from the registers on the AD7731. T he register can be programmed to be either 16 or 24 bits wide,

determined by the status of the WL bit of the Mode Register. T he RDY output and RDY bit of the Status Register are set low when

the Data Register is updated. T he RDY pin and RDY bit will return high once the full contents of the register (either 16 or 24 bits)

have been read. If the Data Register has not been read by the time the next output update occurs, the RDY pin and RDY bit will go

high for at least 158.5 × t_{CLK IN}indicating when a read from the Data Register should not be initiated to avoid a transfer from the

Data Register as it is being updated. Once the updating of the Data Register has taken place, RDY returns low.

If the Communications Register data sets up the part for a write operation to this register, a write operation must actually take place

in order to return the part to where it is expecting a write operation to the Communications Register (the default state of the inter-

face). However, the 16 or 24 bits of data written to the part will be ignored by the AD7731.

Mode Register (RS2-RS0 = 0, 1, 0); P ower -O n/Reset Status: 0174 H ex

T he Mode Register is a 16-bit register from which data can either be read or to which data can be written. T his register configures

the operating modes of the AD7731, the input range selection, the channel selection and the word length of the Data Register. Table X

outlines the bit designations for the Mode Register. MR0 through MR15 indicate the bit location, MR denoting the bits are in the

Mode Register. MR15 denotes the first bit of the data stream. T he number in brackets indicates the power-on/reset default status of

that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the

registers on the part.

Table X. Mode Register

MR15

MR14

MR13

MR12

MR11

MR10

D1 (0)

MR9

MR8

B/U (0)

MD2 (0)

MD1 (0)

MD0 (0)

DEN (0)

D0 (0)

WL (1)

MR7

MR6

MR5

MR4

MR3

MR2

MR1

MR0

HIREF (0)

RN2 (1)

RN1 (1)

RN0 (1)

BO (0)

CH2 (1)

CH1 (0)

CH0 (0)

Bit

Location

Mnem onic

D escription

MR15–MR13

MD2–MD0

Mode Bits. T hese three bits determine the mode of operation of the AD7731 as outlined in

T able XI. T he modes are independent, such that writing new mode bits to the Mode Regis-

ter will exit the part from the mode in which it is operating and place it in the new requested

mode immediately after the Mode Register write. T he function of the mode bits is described

in more detail below.

Table XI. O perating Modes

MD 2

MD 1

MD 0

Mode of O per ation

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Sync (Idle) Mode

Continuous Conversion Mode

Single Conversion Mode

Power-Down (Standby) Mode

Internal Zero-Scale Calibration

Internal Full-Scale Calibration

System Zero-Scale Calibration

System Full-Scale Calibration

Power-On/Reset Default

REV. 0

–15–

AD7731

MD 2

MD 1

MD 0

O perating Mode

0

Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7731 is not

processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC

input pin. However, exerting the SYNC does not actually force these mode bits to 0, 0, 0. T he part re-

turns to this mode after a calibration or after a conversion in Single Conversion Mode. T his is the default

condition of these bits after Power-On/Reset.

0

1

0

1

0

1

0

1

0

Continuous Conversion Mode. In this mode, the AD7731 is continuously processing data and providing

conversion results to the Data Register at the programmed output update rate (as determined by the

Filter Register). For most applications, this would be the normal operating mode of the AD7731.

Single Conversion Mode. In this mode, the AD7731 performs a single conversion, updates the Data

Register, returns to the Sync Mode and resets the mode bits to 0, 0, 0. T he result of the single conversion

on the AD7731 in this mode will not be provided until the full settling-time of the filter has elapsed.

Power-Down (Standby) Mode. In this mode, the AD7731 goes into its power-down or standby state. Placing

the part in this mode is equivalent to exerting the STANDBY input pin. However, exerting STANDBY does

not actually force these mode bits to 0, 1, 1.

Zero-Scale Self-Calibration Mode. T his activates zero-scale self-calibration on the channel selected by the

CH2, CH1 and CH0 bits of the Mode Register. T his zero-scale self-calibration is performed at the se-

lected gain on internally shorted (zeroed) inputs. When this zero-scale self-calibration is complete, the

part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1

and MD0 returning to 0, 0, 0. T he RDY output and bit go high when calibration is initiated and return

low when this zero-scale self-calibration is complete to indicate that the part is back in Sync Mode and

ready for further operations.

1

0

1

0

Full-Scale Self-Calibration Mode. T his activates full-scale self-calibration on the channel selected by the

CH2, CH1 and CH0 bits of the Mode Register. T his full-scale self-calibration is performed at the se-

lected gain on an internally-generated full-scale signal. When this full-scale self-calibration is complete,

the part updates the contents of the Gain Calibration Register and returns to Sync Mode with MD2,

MD1 and MD0 returning to 0, 0, 0. T he RDY output and bit go high when calibration is initiated and

return low when this full-scale self-calibration is complete to indicate that the part is back in Sync Mode

and ready for further operations.

Zero-Scale System Calibration Mode. T his activates zero scale system calibration on the channel selected

by the CH2, CH1 and CH0 bits of the Mode Register. Calibration is performed at the selected gain on

the input voltage provided at the analog input during this calibration sequence. T his input voltage should

remain stable for the duration of the calibration. When this zero-scale system calibration is complete, the

part updates the contents of the Offset Calibration Register and returns to Sync Mode with MD2, MD1

and MD0 returning to 0, 0, 0. T he RDY output and bit go high when calibration is initiated and return

low when this zero-scale calibration is complete to indicate that the part is back in Sync Mode and ready

for further operations.

1

Full-Scale System Calibration Mode. T his activates full-scale system calibration on the selected input

channel. Calibration is performed at the selected gain on the input voltage provided at the analog input

during this calibration sequence. T his input voltage should remain stable for the duration of the calibra-

tion. When this full-scale system calibration is complete, the part updates the contents of the Gain Cali-

bration Register and returns to Sync Mode with MD2, MD1 and MD0 returning to 0, 0, 0. T he RDY

output and bit go high when calibration is initiated and return low when this full-scale calibration is com-

plete to indicate that the part is back in Sync Mode and ready for further operations.

–16–

REV. 0

AD7731

Bit

Location

Mnem onic

D escription

MR12

B/U

Bipolar/Unipolar Bit. A 0 in this bit selects bipolar operation and the output coding is

00...000 for negative full-scale input, 10...000 for zero input and 11...111 for positive full-

scale input. A 1 in this bit selects unipolar operation and the output coding is 00...000 for

zero input and 11...111 for positive full-scale input.

MR11

DEN

Digital Output Enable Bit. With this bit at 1, the AIN3/D1 and AIN4/D0 pins assume their

digital output functions and the output drivers connected to these pins are enabled. In this

mode, the user effectively has two port bits which can be programmed over the serial interface.

MR10–MR9

D1–D0

Digital Output Bits. T hese bits determine the digital outputs on the AIN3/D1 and AIN4/D0

pins respectively when the DEN bit is a 1. For example, a 1 written to the D1 bit of the

Mode Register (with the DEN bit also a 1) will put a logic 1 on the AIN3/D1 pin. T his logic

1 will remain on this pin until a 0 is written to the D1 bit (in which case, the AIN3/D1 pin

goes to a logic 0) or the digital output function is disabled by writing a 0 to the DEN bit.

MR8

MR7

WL

Data Word Length Bit. T his bit determines the word length of the Data Register. A 0 in this

bit selects 16-bit word length when reading from the data register (i.e., RDY returns high

after 16 serial clock cycles in the read operation). A 1 in this bit selects 24-bit word length for

the Data Register.

HIREF

High Reference Bit. T his bit should be set in accordance with the reference voltage which is

being used on the part. If the reference voltage is 2.5 V, the HIREF bit should be set to 0. If

the reference voltage is 5 V, the H IREF bit should be set to a 1. With the H IREF bit set

correctly for the appropriate applied reference voltage, the input ranges are 0 mV to +20 mV,

+40 mV, +80 mV, +160 mV, +320 mV, +640 mV and +1.28 V for unipolar operation and

±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV and ±1.28 V for bipolar operation.

It is possible for a user with a 2.5 V reference to set the HIREF bit to a 1. In this case, the

part is operating with a 2.5 V reference but assumes it has a 5 V reference. As a result, the

input ranges on the part become 0 mV to +10 mV through 0 mV to +640 mV for unipolar

operation and ±10 mV through ±640 mV for bipolar operation. However, the output noise

from the part (in nV) will remain unchanged so the resolution of the part (in LSBs) will re-

duce by 1.

MR6–MR4

RN2–RN0

Input Range Bits. T hese bits determine the analog input range for the selected analog input.

T he different input ranges are outlined in T able XII. T he table is valid for a reference voltage

of 2.5 V with the HIREF bit at 0 or for a reference voltage of 5 V with the HIREF bit at a

logic 1.

Table XII. Input Range Selection

Input Range

RN2 RN1 RN0

B/U Bit = 0

B/U Bit = 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

–20 mV to +20 mV

–40 mV to +40 mV

–80 mV to +80 mV

–160 mV to +160 mV 0 mV to +160 mV

–320 mV to +320 mV 0 mV to +320 mV

–640 mV to +640 mV 0 mV to +640 mV

0 mV to +20 mV

0 mV to +40 mV

0 mV to +80 mV

–1.28 V to +1.28 V

0 mV to +1.28 V Power-On/Reset Default

REV. 0

–17–

AD7731

Bit

Location

Mnem onic

D escription

MR3

BO

Burnout Current Bit. A 1 in this bit activates the burnout currents. When active, the burnout

currents connect to the selected analog input pair, one source current to the AIN(+) input

and one sink current to the AIN(–) input. A 0 in this bit turns off the on-chip burnout

currents.

MR2–MR0

CH2–CH0

Channel Select. T hese three bits select a channel either for conversion or for access to cali-

bration coefficients as outlined in T able XIII. T here are three pairs of calibration registers on

the part. In fully differential mode, the part has three input channels so each channel has its

own pair of calibration registers. In pseudo-differential mode, the AD7731 has five input

channels with some of the input channel combinations sharing calibration registers. With

CH2, CH1 and CH0 at a logic 1, the part looks at the AIN6 input internally shorted to itself.

T his can be used as a test method to evaluate the noise performance of the part with no ex-

ternal noise sources. In this mode, the AIN6 input should be connected to an external volt-

age within the allowable common-mode range for the part. T he power-on/default status of

these bits is 1, 0, 0.

Table XIII. Channel Selection

CH 2 CH 1 CH 0 AIN(+) AIN(–) Type

Calibration Register P air

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AIN1

AIN2

AIN3

AIN4

AIN1

AIN3

AIN5

AIN6

AIN2

AIN4

AIN6

Pseudo Differential

Fully Differential

T est Mode

Register Pair 0

Register Pair 1

Register Pair 2

Register Pair 0

Register Pair 1

Register Pair 2

Filter Register (RS2-RS0 = 0, 1, 1); P ower -O n/Reset Status: 2002 H ex

T he Filter Register is a 16-bit register from which data can either be read or to which data can be written. T his register determines

the amount of averaging performed by the filter and the mode of operation of the filter. It also sets the chopping mode. T able XIV

outlines the bit designations for the Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter

Register. FR15 denotes the first bit of the data stream. T he number in brackets indicates the power-on/reset default status of that bit.

Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers

on the part.

Table XIV. Filter Register

FR15

FR14

FR13

FR12

FR11

FR10

FR9

FR8

SF11 (0)

SF10 (0)

SF9 (1)

SF8 (0)

SF7 (0)

SF6 (0)

SF5 (0)

SF4 (0)

FR7

FR6

FR5

FR4

FR3

FR2

FR1

FR0

SF3 (0)

SF2 (0)

SF1 (0)

SF0 (0)

ZERO (0)

CHP (0)

SKIP (1)

FAST (0)

Bit

Location

Mnem onic

D escription

FR15–FR4

SF11–SF0

Sinc³Filter Selection Bits. T he AD7731 contains two filters, a Sinc³filter and an FIR filter.

T he 12 bits programmed to SF11 through SF0 sets the amount of averaging which the Sinc³

filter performs. As a result, the number programmed to these 12 bits affects the –3 dB fre-

quency and output update rate from the part (see Filter Architecture section). T he allowable

range for SF words depends on whether the part is operated with CHP on or off and SKIP

on or off. T able XV outlines the SF ranges for different setups.

–18–

REV. 0

AD7731

Table XV. SF Ranges

CH O P

SKIP

SF Range

O utput Update Rate Range (Assum ing 4.9152 MH z Clock)

0

1

0

1

0

1

2048 to 150

2048 to 75

2048 to 40

2048 to 20

150 Hz to 2.048 kHz

50 Hz to 1.365 kHz

150 Hz to 7.6 kHz

50 Hz to 5.12 kHz

Bit

Location

Mnem onic

D escription

FR3

FR2

ZERO

CHP

A zero m ust be written to this bit to ensure correct operation of the AD7731.

Chop Enable Bit. T his bit determines if the chopping mode on the part is enabled. A 1 in this

bit location enables chopping on the part. When the chop mode is enabled, the part is effec-

tively chopped at its input and output to remove all offset and offset drift errors on the part.

If offset performance with time and temperature are important parameters in the design, it is

recommended that the user enable chopping on the part.

FR1

FR0

SKIP

FIR Filter Skip Bit. With a 0 in this bit, the AD7731 performs two stages of filtering before

shipping a result out of the filter. T he first is a Sinc³filter followed by a 22-tap FIR filter.

With a 1 in this bit, the FIR filter on the part is bypassed and the output of the Sinc³is fed

directly as the output result of the AD7731’s filter (see Filter Architecture for more details on

the filter implementation).

FAST

FASTStep™ Mode Enable Bit. A 1 in this bit enables the FASTStep™ mode on the AD7731. In

this mode, if a step change on the input is detected, the FIR calculation portion of the filter is

suspended and replaced by a simple moving average on the output of the Sinc³filter. Ini-

tially, two outputs from the sinc³filter are used to calculate an AD7731 output. T he number

of sinc³outputs used to calculate the moving average output is increased (from 2 to 4 to 8 to

16) until the STDY bit goes low. When the FIR filter has fully settled after a step, the STDY

bit will become active and the FIR filter is switched back into the processing loop (see Filter

Architecture section for more details on the FASTStep™ mode).

O ffset Calibr ation Register (RS2–RS0 = 1, 0, 1)

T he AD7731 contains three 24-bit Offset Calibration Registers, labeled Offset Calibration Register 0 to Offset Calibration Register

2, to which data can be written and from which data can be read. T he three registers are totally independent of each other such that

in fully-differential mode there is an offset register for each of the input channels. T his register is used in conjunction with the associ-

ated Gain Calibration Register to form a register pair. T he calibration register pair used to scale the output of the filter is as outlined

in T able XIII. T o access the appropriate Offset Calibration Register the user should write first to the Mode Register setting up the

appropriate address in the CH2 to CH0 bits.

T he Offset Calibration Register is updated after an offset calibration routine (1, 0, 0 or 1, 1, 0 loaded to the MD2, MD1, MD0 bits

of the Mode Register). During subsequent conversions, the contents of this register are subtracted from the filter output prior to gain

scaling being performed on the word. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a

flowchart for writing to the registers on the part.

Gain Calibr ation Register (RS2–RS0 = 1, 1, 0)

T he AD7731 contains three 24-bit Gain Calibration Registers to which data can be written and from which data can be read. T he

three registers are totally independent of each other such that in fully-differential mode there is a gain register for each of the input

channels. T his register is used in conjunction with the associated Offset Calibration Register to form a register pair which scale the

output of the filter before it is loaded to the Data Register. T hese register pairs are associated with input channel pairs as outlined in

T able XIII. T o access the appropriate Gain Calibration Register the user should write first to the Mode Register setting up the ap-

propriate address in the CH2 to CH0 bits.

T he Gain Calibration Register is updated after a gain calibration routine (1, 0, 1 or 1, 1, 1 loaded to the MD2, MD1, MD0 bits of

the Mode Register). During subsequent conversions, the contents of this register are used to scale the number which has already

been offset corrected with the Offset Calibration Register contents. Figure 5 shows a flowchart for reading from the registers on the

AD7731 and Figure 6 shows a flowchart for writing to the registers on the part.

Test Register (RS2–RS0 = 1, 1, 1); P ower O n/Reset Status: 000000H ex

T he AD7731 contains a 24-bit T est Register to which data can be written and from which data can be read. T he contents of this

register are used in testing the device. T he user is advised not to change the status of any of the bits in this register from the default

(Power-On or RESET) status of all 0s as the part will be placed in one of its test modes and will not operate correctly. If the part

enters one of its test modes, exercising RESET or writing 32 successive 1s to the part will exit the part from the mode and return all

register contents to their power-on/reset status. Note, if the part is placed in one of its test modes, it may not be possible to read back

the contents of the T est Register depending on the test mode which the part has been placed.

REV. 0

–19–

AD7731

READ ING FRO M AND WRITING TO TH E O N-CH IP REGISTERS

T he AD7731 contains a total of twelve on-chip registers. T hese registers are all accessed over a three-wire interface. As a result,

addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a

flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of

the registers. Figure 6 gives a flowchart for writing to the different registers on the part, again summarizing the sequence and words

to be written to the AD7731.

START

CONTINUOUS

YES

READS OF

REGISTER

REQUIRED?

Byte W

(H ex)

Byte Y

(H ex)

Byte Z

(H ex)

Register

NO

Status Register

Data Register

Mode Register

Filter Register

Offset Register

Gain Register

10

11

12

13

15

16

20

21

22

N/A*

30

N/A*

WRITE BYTE W TO

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

WRITE BYTE Y TO

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

READ REGISTER

*N/A = Not Applicable. Continuous reads of these registers does

not make sense as the register contents would remain the same

since they are only changed by a write operation.

READ REGISTER

STOP

CONTINUOUS

NO

READ

OPERATION?

YES

WRITE BYTE Z TO

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

Figure 5. Flowchart for Reading from the AD7731 Registers

START

Register

Byte Y (H ex)

Communications Register

Data Register

00

WRITE BYTE Y TO

COMMUNICATIONS REGISTER

(SEE ACCOMPANYING TABLE)

Read Only Register.

Mode Register

Filter Register

Offset Register

Gain Register

02

03

05

06

WRITE TO REGISTER

T est Register

User is advised not

to change contents of

T est Register

END

Figure 6. Flowchart for Writing to the AD7731 Registers

–20–

REV. 0

AD7731

CALIBRATIO N O P ERATIO N SUMMARY

T he AD7731 contains a number of calibration options as outlined previously. T able XVI summarizes the calibration types, the op-

erations involved and the duration of the operations. T here are two methods of determining the end of calibration. T he first is to

monitor the hardware RDY pin using either interrupt-driven or polling routines. T he second method is to do a software poll of the

RDY bit in the Status Register. T his can be achieved by setting up the part for continuous reads of the Status Register once a calibra-

tion has been initiated. T he RDY pin and RDY bit go high on initiating a calibration and return low at the end of the calibration

routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. T he FAST and SKIP bits are treated

as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full details.

Table XVI. Calibration O perations

MD 2, MD 1, D uration to RDY D uration to RDY

Calibration Type

MD 0

Low (CH P = 1)

Low (CH P = 0)

Calibration Sequence

Internal Zero-Scale

1, 0, 0

22 × 1/Output Rate 24 × 1/Output Rate Calibration on internal shorted input with PGA set

for selected input range. T he Offset Calibration

Register for the selected channel is updated at the

end of this calibration sequence. For full self-cali-

bration, this calibration should be preceded by an

Internal Full-Scale calibration. For applications

which require an Internal Zero-Scale and System

Full Scale calibration, this Internal Zero-Scale

calibration should be performed first.

Internal Full-Scale

1, 0, 1

44 × 1/Output Rate 48 × 1/Output Rate Calibration on internally-generated input full-scale

with PGA set for selected input range. T he Gain

Calibration Register for the selected channel is

updated at the end of this calibration sequence. It is

recommended that internal full-scale calibrations

are performed on the operating input range except

for the 20 mV and 40 mV input ranges where opti-

mum results are achieved by calibrating on the

80 mV range. T his calibration should be followed

by either an Internal Zero-Scale or System Zero-

Scale calibration. T his calibration should be fol-

lowed by either an Internal Zero-Scale or System

Zero-Scale calibration. T his zero-scale calibration

should be performed at the operating input range.

System Zero-Scale

1, 1, 0

22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with

PGA set for selected input range. T he input applied

is assumed to be the zero-scale of the system. For

full system calibration, this System Zero-Scale

calibration should be performed first. For applica-

tions which require a System Zero-Scale and Inter-

nal Full Scale calibration, this calibration should be

preceded by the Internal Full-Scale calibration. T he

Offset Calibration Register for the selected channel

is updated at the end of this calibration sequence.

System Full-Scale

1, 1, 1

22 × 1/Output Rate 24 × 1/Output Rate Calibration on externally-applied input voltage with

PGA set for selected input range. T he input applied

is assumed to be the full-scale of the system. T his

calibration should be preceded by a System Zero-

Scale or Internal Zero-Scale calibration. T he Gain

Calibration Register for the selected channel is

updated at the end of this calibration sequence.

REV. 0

–21–

AD7731

CIRCUIT D ESCRIP TIO N

sigma-delta modulator converts the sampled input signal into a

digital pulse train whose duty cycle contains the digital informa-

tion. A digital low-pass filter processes the output of the sigma-

delta modulator and updates the data register at a rate that can

be programmed over the serial interface. T he output data from

the part is accessed over this serial interface. T he cutoff fre-

quency and output rate of this filter can be programmed via on-

chip registers. T he output noise performance and peak-to-peak

resolution of the part varies with gain and with the output rate

as shown in T ables I to IV.

T he AD7731 is a sigma-delta A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low-frequency signals such as those in strain-gage, pressure

transducer, temperature measurement, industrial control or pro-

cess control applications. It contains a sigma-delta (or charge-

balancing) ADC, a calibration microcontroller with on-chip

static RAM, a clock oscillator, a digital filter and a bidirectional

serial communications port. T he part consumes 13.5 mA of

power supply current with a standby mode which consumes

only 20 µA. T he part operates from a single +5 V supply. T he

clock source for the part can be provided via an external clock

or by connecting a crystal oscillator or ceramic resonator across

the MCLK IN or MCLK OUT pins.

T he analog inputs are buffered on-chip, allowing the part to

handle significant source impedances on the analog input. T his

means that external R, C filtering (for noise rejection or RFI

interference reduction) can be placed on the analog inputs if

required. T he common-mode voltage range for the analog in-

puts comes within 1.2 V of AGND and 0.95 V of AV_DD. T he

reference input is also differential and the common-mode range

T he part contains three programmable-gain fully differential

analog input channels which can be reconfigured as five pseudo-

differential inputs. T he part handles a total of seven different

input ranges on all channels which are programmed via the on-

chip registers. T he differential unipolar ranges are: 0 mV to

+20 mV through 0 V to +1.28 V and the differential bipolar

ranges are: ±20 mV through ±1.28 V.

here is from AGND to AV_DD

.

T he AD7731 contains a number of hardware and software

events that set or reset status flags and bits in registers. T able

XVII summarizes which blocks and flags are affected by the

different events.

T he AD7731 employs a sigma-delta conversion technique to

realize up to 24 bits of no missing codes performance. T he

Table XVII. Reset Events

Filter Analog

Set Registers

to D efault

Mode

Bits

Reset Serial

Interface

Set RDY

P in/Bit

Set STDY

Bit

Event

Reset

P ower-D own

Power-On Reset

RESET Pin

STANDBY Pin

Mode 011 Write

SYNC Pin

Mode 000 Write

Conversion or

Cal Mode Write

Clock 32 1s

Yes

No

000

As Is

011

As Is

000

New

Value

As Is

Yes

Initial

Reset

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Data Register Read

No

–22–

REV. 0

AD7731

ANALO G INP UT

Analog Input Channels

0 mV to +80 mV, 0 mV to +160 mV, 0 mV to +320 mV, 0 mV

to +640 mV and 0 V to +1.28 V while the bipolar ranges are

±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV,

±1.28 V. T hese are the nominal ranges which should appear at

the input to the on-chip PGA.

T he AD7731 has six analog input pins (labelled AIN1 to AIN6)

which can be configured as either three fully differential input

channels or five pseudo-differential input channels. Bits CH0,

CH1 and CH2 of the Mode Register configure the input chan-

nel arrangement and the channel selection is as outlined

previously in T able XIII. T he input pairs (either differential

or pseudo-differential) provide programmable-gain, input chan-

nels which can handle either unipolar or bipolar input signals. It

should be noted that the bipolar input signals are referenced to

the respective AIN(–) input of the input pair. T he AIN3 and

AIN4 pins can also be reconfigured as two digital output port

bits, also controlled by the Mode Register.

Bipolar /Unipolar Inputs

T he analog inputs on the AD7731 can accept either unipolar or

bipolar input voltage ranges. Bipolar input ranges do not imply

that the part can handle negative voltages with respect to system

ground on its analog inputs unless the AGND of the part is also

biased below system ground. Unipolar and bipolar signals on

the AIN(+) input are referenced to the voltage on the respec-

tive AIN(–) input. For example, if AIN(–) is +2.5 V and the

AD7731 is configured for an analog input range of 0 mV to

+20 mV, the input voltage range on the AIN(+) input is +2.5 V

to +2.52 V. If AIN(–) is +2.5 V and the AD7731 is configured

for an analog input range of ±1.28 V, the analog input range on

the AIN(+) input is +1.22 V to +3.78 V (i.e., 2.5 V ± 1.28 V).

A differential multiplexer switches one of the two input channels

to the on-chip buffer amplifier. When the analog input channel

is switched, the RDY output goes high and the settling time of

the part must elapse before a valid word from the new channel is

available in the Data Register (indicated by RDY going low).

Bipolar or unipolar options are chosen by programming the B/U

bit of the Mode Register. T his programs the selected channel

for either unipolar or bipolar operation. Programming the chan-

nel for either unipolar or bipolar operation does not change any

of the input signal conditioning; it simply changes the data

output coding and the points on the transfer function where

calibrations occur. When the AD7731 is configured for unipolar

operation, the output coding is natural (straight) binary with a

zero differential voltage resulting in a code of 000...000, a mid-

scale voltage resulting in a code of 100...000 and a full-scale

input voltage resulting in a code of 111...111. When the AD7731 is

configured for bipolar operation, the coding is offset binary with

a negative full-scale voltage resulting in a code of 000...000, a

zero differential voltage resulting in a code of 100...000 and a

positive full-scale voltage resulting in a code of 111...111.

Buffer ed Inputs

T he output of the multiplexer feeds into a high impedance input

stage of the buffer amplifier. As a result, the analog inputs can

handle significant source impedances. T his buffer amplifier has

an input bias current of 50 nA (CHP = 1) and 60 nA (CHP = 0).

T his current flows in each leg of the analog input pair. T he

offset current on the part is the difference between the input

bias on the legs of the input pair. T his offset current is less than

10 nA (CHP = 1) and 25 nA (CHP = 0). Large source resis-

tances result in a dc offset voltage developed across the source

resistance on each leg but matched impedances on the analog

input legs will reduce the offset voltage to that generated by the

input offset current.

Analog Input Ranges

T he absolute input voltage range is restricted to between

AGND + 1.2 V to AV_DD– 0.95 V which also places restrictions

on the common-mode range. Care must be taken in setting up

the common-mode voltage and input voltage range so that these

limits are not exceeded, otherwise there will be a degradation in

linearity performance.

Bur nout Cur r ents

T he AD7731 contains two 100 nA constant current generators,

one source current from AV_DDto AIN(+) and one sink from

AIN1(–) to AGND. T he currents are switched to the selected

analog input pair. Both currents are either on or off depending

on the BO bit of the Mode Register. T hese currents can be used

in checking that a transducer is still operational before attempt-

ing to take measurements on that channel. If the currents are

turned on, allowed flow in the transducer, a measurement of the

input voltage on the analog input taken and the voltage mea-

sured is full scale then it indicates that the transducer has gone

open-circuit. If the voltage measured is 0 V, it indicates that the

transducer has gone open-circuit. For normal operation, these

burnout currents are turned off by writing a 0 to the BO bit.

T he current sources work over the normal absolute input volt-

age range specifications.

In some applications, the analog input range may be biased

either around system ground or slightly below system ground. In

such cases, the AGND of the AD7731 must be biased negative

with respect to system ground such that the analog input voltage

does not go within 1.2 V of AGND. Care should taken to en-

sure that the differential between either AV_DDor DV_DDand this

biased AGND does not exceed 5.5 V. T his is discussed in more

detail in the Applications section.

Pr ogr a m m a ble Ga in Am plifier

T he output from the buffer amplifier is applied to the input of

the on-chip programmable gain amplifier (PGA). T he PGA can

handle seven different unipolar input ranges and seven bipolar

ranges. With the HIREF bit of the Mode Register at 0 and a

+2.5 V reference (or the HIREF bit at 1 and a +5 V reference),

the unipolar ranges are 0 mV to +20 mV, 0 mV to +40 mV,

REV. 0

–23–

AD7731

REFERENCE INP UT

SIGMA-D ELTA MO D ULATO R

T he AD7731’s reference inputs, REF IN(+) and REF IN(–),

provide a differential reference input capability. T he common-

mode range for these differential inputs is from AGND to AV_DD

T he nominal reference voltage, V_REF(REF IN(+) – REF IN(–)),

for specified operation is +2.5 V with the HIREF bit at 0 and

+5 V with the HIREF bit at 1. T he part is also functional with

V_REFof +2.5 V with the HIREF bit at 1. T his results in a halv-

ing of all input ranges. T he resolution in nV will be unaltered,

but will be reduced by 1 bit in terms of peak-to-peak resolution.

A sigma-delta ADC generally consists of two main blocks, an

analog modulator and a digital filter. In the case of the AD7731,

the analog modulator consists of a difference amplifier, an inte-

grator block, a comparator and a feedback DAC as illustrated in

Figure 7. In operation, the analog signal sample is fed to the

difference amplifier along with the output of the feedback DAC.

T he difference between these two signals is integrated and fed to

the comparator. T he output of the comparator provides the

input to the feedback DAC so the system functions as a negative

feedback loop that tries to minimize the difference signal. T he

digital data that represents the analog input voltage is contained

in the duty cycle of the pulse train appearing at the output of the

comparator. T his duty cycle data can be recovered as a data

word using the digital filter. T he sampling frequency of the

modulator loop is many times higher than the bandwidth of the

input signal. T he integrator in the modulator shapes the quanti-

zation noise (which results from the analog to digital conversion) so

that the noise is pushed towards one half of the modulator fre-

quency. The digital filter then bandlimits the response to a fre-

quency significantly lower than one half of the modulator

frequency. In this manner, the 1-bit output of the comparator

is translated into a bandlimited, low noise output from the

AD7731.

.

Both reference inputs provide a high impedance, dynamic load.

T he typical average dc input leakage current is over temperature

is 4.5 µA with HIREF = 0 and 8 µA with HIREF = 1. Because

the input impedance on each reference input is dynamic, exter-

nal resistance/capacitance combinations may result in gain er-

rors on the part.

T he output noise performance outlined in T ables I through IV

is for an analog input of 0 V and is unaffected by noise on the

reference. T o obtain the same noise performance as shown in

the noise tables over the full input range requires a low noise

reference source for the AD7731. If the reference noise in the

bandwidth of interest is excessive, it will degrade the perfor-

mance of the AD7731. In applications where the excitation

voltage for the transducer on the analog input also drives the

reference voltage for the part, the effect of the low-frequency

noise in the excitation voltage will be removed as the application

is ratiometric. In this case, the reference voltage for the AD7731

and the excitation voltage for the transducer are the same. T he

HIREF bit of the Mode Register should be set to 1.

ANALOG DIFFERENCE

INPUT

AMP

COMPARATOR

DIGITAL

FILTER

INTEGRATOR

DAC

DIGITAL DATA

If the AD7731 is not used in a ratiometric application, a low

noise reference should be used. Recommended reference voltage

sources for the AD7731 include the AD780, REF43 and REF192.

If any of these references are used as the reference source for the

AD7731, the HIREF bit should be set to 0. It is generally rec-

ommended to decouple the output of these references to further

reduce the noise level.

Figure 7. Sigm a-Delta Modulator Block Diagram

D IGITAL FILTERING

Filter Ar chitectur e

T he output of the modulator feeds directly into the digital filter.

T his digital filter consists of two portions, a first stage filter and

a second stage filter. T he cutoff frequency and output rate of

the filter are programmable. T he first stage filter is a low-pass,

sinc³or (sinx/x)³filter whose primary function is to remove the

quantization noise introduced at the modulator. T he second

stage filter has three distinct modes of operation. T he first op-

tion is where it is bypassed completely such that the only filter-

ing provided on the AD7731 is performed by the first stage sinc³

filter. T he second is where it provides a low-pass 22-tap FIR

filter which processes the output of the first stage filter. T he

third option is to enable FASTStep™ mode. In this mode, when

a step change is detected on the analog input or the analog input

channel switched, the second stage filter enters a mode where it

performs a variable number of averages for some time after the

step change and then the second stage filter switches back to the

FIR filter.

Refer ence D etect

T he AD7731 includes on-chip circuitry to detect if the part has

a valid reference for conversions or calibrations. If the voltage

between the REF IN(+) and REF IN(–) pins goes below 0.3 V

or either the REF IN(+) or REF IN(–) inputs is open circuit,

the AD7731 detects that it no longer has a valid reference. In

this case, the NOREF bit of the Status Register is set to a 1.

If the AD7731 is performing normal conversions and the NOREF

bit becomes active, the part places all 1s in the Data Register.

T herefore, it is not necessary to continuously monitor the status

of the NOREF bit when performing conversions. It is only nec-

essary to verify its status if the conversion result read from the

Data Register is all 1s.

If the AD7731 is performing either an offset or gain calibration

and the NOREF bit becomes active, the updating of the respec-

tive calibration register is inhibited to avoid loading incorrect

coefficients to this register. If the user is concerned about verify-

ing that a valid reference is in place every time a calibration is

performed, then the status of the NOREF bit should be checked

at the end of the calibration cycle.

T he AD7731 has two primary modes of operation, chop mode

(CHP = 1) and nonchop mode (CHP = 0). T he AD7731 alter-

natively reverses its inputs with CHP = 1, and alternate outputs

from the first stage filter have a positive offset and negative

offset term included. With CHP = 0, the input is never reversed

and the output of the first stage filter includes an offset which is

always of the same polarity.

–24–

REV. 0

AD7731

0

T he operation mode can be changed to achieve optimum per-

formance in various applications. T he CHP bit should generally

be set to 0 when using the AD7731 in applications where higher

throughput rates are a concern or in applications where the

reduced rejection at the chopping frequency in chop mode is an

issue. T he part should be operated with CHP = 1 when drift,

noise rejection and optimum EMI rejection are important crite-

ria in the application.

–10

–20

–30

–40

–50

–60

–70

–80

T he output update rate of the AD7731 is programmed using the

SF bits of the Filter Register. With CHP = 0, the output update

is determined by the relationship:

–90

–100

–110

–120

1

Output Rate = f _MOD

×

CHP = 0

0

200

400

600

800 1000 1200 1400 1600 1800

(

)

SF

FREQUENCY – Hz

where SF is the decimal equivalent of the data loaded to the SF

bits of the Filter Register and f_MODis the modulator frequency

and is 1/16th of the master clock frequency.

Figure 8. SKIP Mode Frequency Response (SKIP = 1,

SF = 512)

Chop Mode (SKIP = 1, CH P = 1)

With CHP = 1, the output update is determined by the relation-

ship:

With CHP = 1, the AD7731 alternatively reverses the ADC

inputs, producing an output which contains the channel offset

when not reversed and the negative of the offset when reversed.

As a result, when operating in SKIP mode, the user has to take

two subsequent outputs from the AD7731 and average them to

produce a valid output from the first stage filter. While operat-

ing in this mode gives the benefits of chopping without the

longer settling time associated with the 22-tap FIR filter, care

should be taken with input signals near positive full-scale or

negative full-scale (zero-scale in unipolar mode). Since the

calibration coefficients are generated for the averaged offset, and

not for the individual offsets represented in each sample, one of

the two samples in the pair may record an all 1s or all 0s read-

ing. If this happens it will result in an error in the averaged

reading. T ime to first output for the part is 1/Output Rate in

this mode. However, since the user really needs two outputs to

derive a correct chopped result, the time to get two outputs for

averaging is 2 × 1/Output Rate. T able XVIII summarizes the

settling time and subsequent throughput rate for the various

different modes. If the user wants the benefits of chopping with-

out the longer settling time associated with the 22-tap FIR filter,

it is recommended that the part be used in FASTStep™ mode.

1

Output Rate = f _MOD

×

CHP = 1

(

)

3 × SF

where SF is the decimal equivalent of the data loaded to the SF

bits of the Filter Register and f_MODis the modulator frequency

and is 1/16th of the master clock frequency.

T hus for a given SF word the output rate from the AD7731 is

three times faster with CHP = 0 than CHP = 1.

T he various filter stages and options are discussed in the follow-

ing sections.

Fir st Stage Filter /SKIP Mode Enabled (SKIP = 1)

With SKIP mode enabled, the only filtering on the part is the

first stage filter. T he frequency response for this first stage filter

is shown in Figure 8. T he response of this first stage filter is

similar to that of an averaging filter but with a sharper roll-off.

With CHP = 0, the output rate for the filter corresponds with

the positioning of the first notch of the filter’s frequency re-

sponse. T hus, for the plot of Figure 8 where the output rate is

600 Hz (f_{CLK IN}= 4.9152 MHz and SF = 512), the first notch of

the filter is at 600 Hz. With CHP = 1, the magnitude response

is the same as in Figure 8 but in this case, the output rate is

1/3rd the output rate so for the example shown in Figure 8 the

output data rate is 200 Hz. T he notches of this sinc³filter fre-

quency response are repeated at multiples of the first notch. T he

filter provides attenuation of better than 100 dB around these

notches. Programming a different cutoff frequency via SF0 –

SF11 does not alter the profile of the filter response; it simply

changes the location of the notches. The –3 dB frequency for both

Chop and Nonchop modes is defined as:

Second Stage Filter

With SKIP mode disabled, the second stage filter is included in

the signal processing. T his second stage filter produces a differ-

ent response depending on the CHP and FAST bits.

Nor m al FIR O per ation (SKIP = 0)

T he normal mode of operation of the second stage filter is as a

22-tap low-pass FIR filter. T his second stage filter processes the

output of the first stage filter and the net frequency response of

the filter is simply a product of the filter response of both filters.

T he overall filter response of the AD7731 is guaranteed to have

no overshoot.

1

f_{3 dB}= 0.262 × f _MOD

×

SF

Nonchop Mode (SKIP = 1, CH P = 0)

With CHP = 0, the input chopping on the AD7731 is disabled

and any offset content in the samples to the first stage filter are

all of the same polarity. When using the part in SKIP mode, the

user can take the output from the AD7731 directly. T ime to the

first output for the part is 3 × 1/Output Rate in this mode. Table

XVIII summarizes the settling time and subsequent throughput

rate for the various different modes.

REV. 0

–25–

AD7731

Chop Mode (SKIP = 0, CH P = 1)

Figure 10 shows the frequency response for the same set of

conditions as for Figure 9 but in this case the response in shown

out to 600 Hz. T his response shows that the attenuation of

input frequencies close to 200 Hz and 400 Hz is significantly

less than at other input frequencies. T hese “peaks” in the fre-

quency response are a by-product of the chopping of the input.

T he plot of Figure 10 is the amplitude for different input fre-

quencies. Note that because the output rate is 200 Hz for the

conditions under which Figure 10 is plotted, if something ex-

isted in the input frequency domain at 200 Hz, it would be

aliased and appear in the output frequency domain at dc.

With CHOP mode enabled and SKIP mode disabled, the sec-

ond stage filter is presented with alternating first stage filter

outputs and processes data accordingly. It has two primary

functions. One is to set the overall frequency response and the

second is to eliminate the modulated offset effect which appears

on the output of the first stage filter. T ime to first output is

22 × 1/Output Rate in this mode. T able XVIII summarizes the

settling time and subsequent throughput rate for the various

different modes.

Figure 9 shows the full frequency response of the AD7731 when

the second stage filter is set for normal FIR operation. T his

response is for chop mode enabled with the decimal equivalent

of the word in the SF bits set to 512 and a master clock fre-

quency of 4.9152 MHz. T he response will scale proportionately

with master clock frequency. T he response is shown from dc to

100 Hz. T he rejection at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz is

better than 88 dB.

Because of this effect, care should be taken in choosing an out-

put rate which is close to the line frequency in the application.

For example, if the line frequency is 50 Hz, an output update

rate of 50 Hz should not be chosen as it will significantly reduce

the AD7731’s line frequency rejection (the 50 Hz will appear as

a dc component with only 6 dB attenuation). However, choos-

ing 60 Hz as the output rate (SF = 1707) will give better than

90 dB attenuation of the aliased line frequency. In a similar

fashion, if the line frequency is 60 Hz, it is recommended that

the user choose an output update rate of 50 Hz (SF = 2048).

T he –3 dB frequency for the frequency response of the AD7731

with the second stage filter set for normal FIR operation and

chop mode enabled is determined by the following relationship:

0

1

–10

f_{3 dB}= 0.0395 × f _MOD

×

CHP = 1

(

)

3 × SF

–20

–30

–40

In this case, f_{3 dB}= 7.9 Hz and the stop-band, where the attenua-

tion is greater than 64.5 dB, is determined by:

–50

–60

1

f_STOP= 0.14 × f _MOD

×

CHP = 1

(

)

3 × SF

–70

–80

In this case, f_STOP= 28 Hz.

–90

0

–100

–110

–120

–10

–20

–30

–40

0

50 100 150 200 250 300 350 400 450 500 550 600

FREQUENCY – Hz

–50

–60

Figure 10. Expanded Full Frequency Response of AD7731

(SKIP = 0, CHP = 1, SF = 512)

–70

Similarly, multiples of the line frequency should be avoided as

the output rate because harmonics of the line frequency will not

be fully attenuated. T he programmability of the AD7731’s

output rate should allow the user to readily choose an output

rate which overcomes this issue. An alternative is to use the part

in nonchop mode.

–80

–90

–100

–110

–120

0

10

20

30

40

50

60

70

80

90 100

FREQUENCY – Hz

Figure 9. Detailed Full Frequency Response of AD7731

(SKIP = 0, CHP = 1, SF = 512)

–26–

REV. 0

AD7731

Nonchop Mode (SKIP = 0, CHP = 0)

Figure 12 shows the frequency response for the same set of

conditions as for Figure 11 but in this case the response in shown

out to 600 Hz. T his plot is comparable to that of Figure 10. T he

most notable difference is absence of the peaks in the response

at 200 Hz and 400 Hz. As a result, interference at these fre-

quencies will be effectively eliminated before being aliased back

to dc.

With CHOP mode disabled and SKIP mode disabled, the only

function of the second stage filter is to give the overall frequency

response. Figure 11 shows the frequency response for the AD7731

with the second stage filter is set for normal FIR operation, chop

mode disabled, the decimal equivalent of the word in the SF bits

set to 1536 and a master clock frequency of 4.9152 MHz. T he

response is analogous to that of Figure 9 with the three-times

larger SF word producing the same 200 Hz output rate. Once

again, the response will scale proportionally with master clock

frequency. T he response is shown from dc to 100 Hz. T he re-

jection at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz is better than 88 dB.

Table XVIII summarizes the settling time and subsequent through-

put rate for the various different modes.

0

–10

–20

–30

–40

T he –3 dB frequency for the frequency response of the AD7731

with the second stage filter set for normal FIR operation and

chop mode enabled is determined by the following relationship:

–50

–60

1

f_{3 dB}= 0.039 × f _MOD

×

CHP = 0

(

)

SF

–70

–80

In this case, f_{3 dB}= 7.8 Hz and the stop-band, where the attenu-

ation is greater than 64.5 dB, is determined by:

–90

–100

–110

–120

1

f_STOP= 0.14 × f _MOD

In this case, f_STOP= 28 Hz.

×

CHP = 0

(

)

SF

0

50 100 150 200 250 300 350 400 450 500 550 600

FREQUENCY – Hz

Figure 12. Expanded Full Frequency Response of AD7731

(SKIP = 0, CHP = 0, SF = 1536)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

10

20

30

40

50

60

70

80

90

100

FREQUENCY – Hz

Figure 11. Detailed Full Frequency Response of AD7731

(SKIP = 0, CHP = 0, SF = 1536)

REV. 0

–27–

AD7731

FAST Step™ Mode (SKIP = 0, FAST = 1)

In FASTStep™ mode, the part has settled to the new value

much faster. For example, with CHP = 1, the FASTStep™

mode settles to its value in two outputs while the normal mode

settling takes 23 outputs. Between the second and 23rd output,

the FASTStep™ mode produces a settled result but with addi-

tional noise compared to the specified noise level for its operat-

ing conditions. T his noise level starts at approximately 3 times

the final noise converging to FIR mode performance. T he com-

plete settling time to where the part is back within the specified

noise number, is the same for FASTStep™ mode and for normal

mode. When switching channels, the profile of Figure 13 will

not be seen. Since the part is synchronized when a channel

change takes place, it will not produce an output until the filter

(either FASTStep™ or FIR) is settled. T able XVIII gives an

indication of the faster settling time benefits of FASTStep™

mode.

T he second mode of operation of the second stage filter is in

FASTStep™ mode which enables it to respond rapidly to step

inputs even when the second stage filter is in the loop. T he

FASTStep™ mode is not relevant with SKIP mode enabled.

T he FASTStep™ mode is enabled by placing a 1 in the FAST

bit of the Filter Register. If the FAST bit is 0, the part continues

to process step inputs with the normal FIR filter as the second

stage filter. With FASTStep™ mode enabled, the second stage

filter will continue to process steady state inputs with the filter

in its normal FIR mode of operation. However, the part is con-

tinuously monitoring the output of the first stage filter and com-

paring it with the second-previous output. If the difference

between these two outputs is greater than a predetermined

threshold (1% of full scale), the second stage filter switches to a

simple moving average computation. T his also happens when a

change in channels takes place regardless of how close the volt-

ages on the two channels are. When the change is detected, the

STDY bit of the Status Register goes to 1.

As can be seen from T able XVIII, the FASTStep™ mode gives

a much earlier indication of where the output channel is going

and what its new value is. T his feature is very useful in scanning

multiple channels where the user does not have to wait for the

FIR settling time to see if a channel has changed value. In this

case, the part can be set up with CHP = 1, SKIP = 0 and FAST

= 1. T his takes advantage of the low drift, better noise immunity

benefits of the CHOP mode. When a change in channels takes

place, the part enters FASTStep™ mode and provides an output

result in 2 × 1/Output Rate.

T he initial number of averages in the moving average computa-

tion is either 2 (chop enabled) or 1 (chop disabled). T he num-

ber of averages will be held at this value as long as the threshold

is exceeded. Once the threshold is no longer exceeded (the step

on the analog input has settled), the number of outputs used to

compute the moving average output is increased. T he first and

second outputs from the first stage filter where the threshold is

no longer exceeded is computed as an average by 2, then 4

outputs with an average of 4, 8 outputs with an average of 8 and

6 outputs with an average of 16. At this time, the second stage

filter reverts back to its normal FIR mode of operation. When

the second stage filter reverts back to the normal FIR, the STDY

bit of the Status Register goes to 0.

Note, if the FAST bit is set and the part operated in single con-

version mode, the AD7731 will continue to output results until

the STDY bit goes to 0.

Table XVIII. Tim e to First and Subsequent O utputs Follow-

ing Channel Change

Figure 13 gives an indication of the different responses to a step

input with FASTStep™ mode enabled and disabled. T he verti-

cal axis indicates the settling of the output to the input step

change while the horizontal axis shows how many outputs it

takes for that settling to occur. T he positive input step change

occurs at a time coincident with the fifth output.

Tim e

Tim e to

Subsequent O /P s

SKIP

CH P FAST

to First O /P ¹

0

1

0

1

0

1

0

1

0

24 × SF/f_MOD

66 × SF/f_MOD

3 × SF/f_MOD

6 × SF/f_MOD

SF/f_MOD

3 × SF/f_MOD

SF/f_MOD

3 × SF/f_MOD

SF/f_MOD

3 × SF/f_MOD

X²

X

1

20000000

15000000

10000000

5000000

0

1

¹T his O/P is fully settled.

²X = Don’t Care.

0

5

10

15

20

25

NUMBER OF OUTPUTS

Figure 13. Step Response for FASTStep™ and Norm al

Operation

–28–

REV. 0

AD7731

CALIBRATIO N

conversion on the input voltage provided, the accuracy of the

calibration can only be as good as the noise level which the part

provides in normal mode. T o optimize the calibration accuracy,

it is recommended to calibrate the part at its lowest output rate

where the noise level is lowest. T he coefficients generated at any

output update rate will be valid for all selected output update

rates. T his scheme of calibrating at the lowest output update

rate does mean that the duration of calibration is longer.

T he AD7731 provides a number of calibration options that can

be programmed via the MD2, MD1 and MD0 bits of the Mode

Register. T he different calibration options are outlined in the

Mode Register and Calibration Operations sections. A calibra-

tion cycle may be initiated at any time by writing to these bits of

the Mode Register. Calibration on the AD7731 removes offset

and gain errors from the device.

T he AD7731 gives the user access to the on-chip calibration

registers allowing the microprocessor to read the device’s cali-

bration coefficients and also to write its own calibration coeffi-

cients to the part from prestored values in E²PROM. T his gives

the microprocessor much greater control over the AD7731’s

calibration procedure. It also means that by comparing the

coefficients after calibration with prestored values in E²PROM,

the user can verify that the device has correctly performed its

calibration. T he values in these calibration registers are 24 bits

wide. In addition, the span and offset for the part can be ad-

justed by the user.

Inter nal Zer o-Scale Calibr ation

An internal zero-scale calibration is initiated on the AD7731 by

writing the appropriate values (1, 0, 0) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode with a

unipolar input range, the zero-scale point used in determining

the calibration coefficients is with the inputs of the differential

pair internally shorted on the part (i.e., AIN[+] = AIN[–] =

Externally-Applied AIN[–] voltage). T he PGA is set for the

selected gain (as per the RN2, RN1, RN0 bits in the Mode

Register) for this internal zero-scale calibration conversion.

T he duration time of the calibration depends upon the CHP bit

of the Filter Register. With CHP = 1, the duration is 22 × 1/

Output Rate; with CHP = 0, the duration is 24 × 1/Output

Rate. At this time the MD2, MD1 and MD0 bits in the Mode

Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731).

T he RDY line goes high when calibration is initiated and re-

turns low when calibration is complete. Note, the part has not

performed a conversion at this time; it has simply performed a

zero-scale calibration and updated the Offset Calibration

Register for the selected channel. T he user must write either

0, 0, 1 or 0, 1 ,0 to the MD2, MD1, MD0 bits of the Mode

Register to initiate a conversion. If RDY is low before (or goes

low during) the calibration command write to the Mode Regis-

ter, it may take up to one modulator cycle (MCLK IN/16) be-

fore RDY goes high to indicate that calibration is in progress.

T herefore, RDY should be ignored for up to one modulator

cycle after the last bit of the calibration command is written to

the Mode Register.

Internally in the AD7731, the coefficients are normalized before

being used to scale the words coming out of the digital filter.

T he offset calibration register contains a value which, when

normalized, is subtracted from all conversion results. T he gain

calibration register contains a value which, when normalized, is

multiplied by all conversion results. T he offset calibration coeffi-

cient is subtracted from the result prior to the multiplication by

the gain coefficient.

T he AD7731 offers self-calibration or system calibration facili-

ties. For full calibration to occur on the selected channel, the

on-chip microcontroller must record the modulator output for

two different input conditions. T hese are “zero-scale” and “full-

scale” points. T hese points are derived by performing a conver-

sion on the different input voltages provided to the input of the

modulator during calibration. T he result of the “zero-scale”

calibration conversion is stored in the Offset Calibration Regis-

ter for the appropriate channel. T he result of the “full-scale”

calibration conversion is stored in the Gain Calibration Register

for the appropriate channel. With these readings, the micro-

controller can calculate the offset and the gain slope for the

input-to-output transfer function of the converter. Internally,

the part works with 33 bits of resolution to determine its conver-

sion result of either 16 bits or 24 bits.

For bipolar input ranges in the internal zero-scale calibrating

mode, the sequence is very similar to that just outlined. In this

case, the zero-scale point is exactly the same as above but since

the part is configured for bipolar operation, the output code for

zero differential input is 800000 Hex in 24-bit mode.

T he internal zero-scale calibration needs to be performed as one

part of a two-step full calibration. H owever, once a full cali-

bration has been performed, additional internal zero-scale

calibrations can be performed by themselves to adjust the

part’s zero-scale point only. When performing a two-step full

calibration, care should be taken as to the sequence in which the

two steps are performed. If the internal zero-scale calibration is

one part of a full self-calibration, then it should take place after

an internal full-scale calibration. If it takes place in association

with a system full-scale calibration, then this internal zero-scale

calibration should be performed first.

T he sequence in which the zero-scale and full-scale calibration

occurs depends upon the type of full-scale calibration being

performed. T he internal full-scale calibration is a two-step cali-

bration that alters the value of the Offset Calibration Register.

T hus, the user must perform a zero-scale calibration (either

internal or system) after an internal full-scale calibration to

correct the Offset Calibration Register contents. When using

system full-scale calibration, it is recommended that the zero-

scale calibration (either internal or system) is performed first.

Calibration time is the same regardless of whether the SKIP

mode is enabled or not. T his is because the SKIP bit is ignored

and the second stage filter is included in the calibration cycle.

T his is done to derive more accurate calibration coefficients. If

the subsequent operating mode is with CHP = 0, the calibration

should be performed with CHP = 0 so the offset calibration

coefficient and the subsequent conversion offsets are consistent.

Since the calibration coefficients are derived by performing a

REV. 0

–29–

AD7731

Inter nal Full-Scale Calibr ation

T he duration time of the calibration depends upon the CHP bit

of the Filter Register. With CHP = 1, the duration is 22 × 1/

Output Rate; with CHP = 0, the duration is 24 × 1/Output

Rate. At this time the MD2, MD1 and MD0 bits in the Mode

Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731).

T he RDY line goes high when calibration is initiated and re-

turns low when calibration is complete. Note, the part has not

performed a conversion at this time; it has simply performed a

zero-scale calibration and updated the Offset Calibration Regis-

ter for the selected channel. T he user must write either 0, 0, 1

or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode Register to

initiate a conversion. If RDY is low before (or goes low during)

the calibration command write to the Mode Register, it may

take up to one modulator cycle (MCLK IN/16) before RDY

goes high to indicate that calibration is in progress. T herefore,

RDY should be ignored for up to one modulator cycle after the

last bit of the calibration command is written to the Mode Register.

An internal full-scale calibration is initiated on the AD7731 by

writing the appropriate values (1, 0, 1) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode, the

full-scale point used in determining the calibration coefficients is

with an internally-generated full-scale voltage. T his full-scale

voltage is derived from the reference voltage for the AD7731

and the PGA is set for the selected gain (as per the RN2, RN1,

RN0 bits in the Mode Register) for this internal full-scale cali-

bration conversion.

Normally, the internal full-scale calibration is performed at the

required operating output range. When operating with a 20 mV

or 40 mV input range, it is recommended that internal full-scale

calibrations are performed on the 80 mV input range.

T he internal full-scale calibration is a two-step sequence which

runs when an internal full-scale calibration command is written

to the AD7731. One part of the calibration is a zero-scale cali-

bration and as a result, the contents of the Offset Calibration

Register are altered during this Internal Full-Scale Calibration.

T he user must, therefore, perform a zero-scale calibration

(either internal or system) AFT ER the internal full-scale cali-

bration. T his means that internal full-scale calibrations cannot

be performed in isolation.

For bipolar input ranges in the system zero-scale calibrating

mode, the sequence is very similar to that just outlined. In this

case, the zero-scale point is the mid-point of the AD7731’s

transfer function.

T he system zero-scale calibration needs to be performed as one

part of a two part full calibration. H owever, once a full cali-

bration has been performed, additional system zero-scale

calibrations can be performed by themselves to adjust the

part’s zero-scale point only. When performing a two-step full

calibration, care should be taken as to the sequence in which the

two steps are performed. If the system zero-scale calibration is

one part of a full system calibration, it should take place before a

system full-scale calibration. If it takes place in association with

an internal full-scale calibration, this system zero-scale calibra-

tion should be performed after the full-scale calibration.

T he duration time of the calibration depends upon the CHP bit

of the Filter Register. With CHP = 1, the duration is 44 × 1/

Output Rate; with CHP = 0, the duration is 48 × 1/Output

Rate. At this time the MD2, MD1 and MD0 bits in the Mode

Register return to 0, 0, 0 (Sync or Idle Mode for the AD7731).

T he RDY line goes high when calibration is initiated and re-

turns low when calibration is complete. Note, the part has not

performed a conversion at this time. T he user must write either

0, 0, 1 or 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode

Register to initiate a conversion. If RDY is low before (or goes

low during) the calibration command write to the Mode Regis-

ter, it may take up to one modulator cycle (MCLK IN/16) be-

fore RDY goes high to indicate that calibration is in progress.

T herefore, RDY should be ignored for up to one modulator

cycle after the last bit of the calibration command is written to

the Mode Register.

System Full-Scale Calibr ation

A system full-scale calibration is initiated on the AD7731 by

writing the appropriate values (1, 1, 1) to the MD2, MD1 and

MD0 bits of the Mode Register. System full-scale calibration is

performed using the system’s positive full-scale voltage. T his

full-scale voltage must be set up before the calibration is initi-

ated, and it must remain stable throughout the calibration step.

T he system full-scale calibration is performed at the selected

gain (as per the RN2, RN1, RN0 bits in the Mode Register).

System Zer o-Scale Calibr ation

System calibration allows the AD7731 to compensate for system

gain and offset errors as well as its own internal errors. System

calibration performs the same slope factor calculations as self-

calibration but uses voltage values presented by the system to

the AIN inputs for the zero- and full-scale points.

T he duration time of the calibration depends upon the CHP bit

of the Filter Register. With CHP = 1, the duration is 22 × 1/

Output Rate; with CHP = 0, the duration is 24 × 1/Output Rate.

At this time the MD2, MD1 and MD0 bits in the Mode Regis-

ter return to 0, 0, 0 (Sync or Idle Mode for the AD7731). T he

RDY line goes high when calibration is initiated and returns low

when calibration is complete. Note, the part has not performed

a conversion at this time; it has simply performed a full-scale

calibration and updated the Gain Calibration Register for the

selected channel. T he user must write either 0, 0, 1 or 0, 1, 0 to

the MD2, MD1, MD0 bits of the Mode Register to initiate a

conversion. If RDY is low before (or goes low during) the cali-

bration command write to the Mode Register, it may take up to

one modulator cycle (MCLK IN/16) before RDY goes high to

indicate that calibration is in progress. T herefore, RDY should

be ignored for up to one modulator cycle after the last bit of the

calibration command is written to the Mode Register.

A system zero-scale calibration is initiated on the AD7731 by

writing the appropriate values (1, 1, 0) to the MD2, MD1 and

MD0 bits of the Mode Register. In this calibration mode with a

unipolar input range, the zero-scale point used in determining

the calibration coefficients is the bottom end of the transfer

function. The system’s zero-scale point is applied to the AD7731’s

AIN input before the calibration step and this voltage must

remain stable for the duration of the system zero-scale calibra-

tion. T he PGA is set for the selected gain (as per the RN2,

RN1, RN0 bits in the Mode Register) for this system zero-scale

calibration conversion. T he allowable range for the system zero-

scale voltage is discussed in the Span and Offsets Section.

–30–

REV. 0

AD7731

1.05 FS.

T he system full-scale calibration needs to be performed as one

part of a two part full calibration. However, once a full calibra-

tion has been performed, additional system full-scale calibra-

tions can be performed by themselves to adjust the part’s gain

calibration point only. When performing a two-step full calibra-

tion, care should be taken as to the sequence in which the two

steps are performed. A system full-scale calibration should not

be carried out unless the part contains valid zero-scale coeffi-

cients. T herefore, an internal zero-scale calibration or a system

zero-scale calibration must be performed before the system full-

scale calibration when a full two-step calibration operation is

being performed.

UPPER LIMIT. AD7731’s INPUT

VOLTAGE CANNOT EXCEED THIS

GAIN CALIBRATIONS EXPAND OR

CONTRACT THE AD7731’s INPUT

RANGE

AD7731

INPUT RANGE

(0.8 FS TO

2.1 FS)

0V DIFFERENTIAL

NOMINAL ZERO-SCALE POINT

ZERO-SCALE CALIBRATIONS

MOVE INPUT RANGE UP OR DOWN

LOWER LIMIT. AD7731’s INPUT

VOLTAGE CANNOT EXCEED THIS

–1.05 FS.

Span and O ffset Lim its

Figure 14. Span and Offset Lim its

Whenever a system calibration mode is used, there are limits on

the amount of offset and span that can be accommodated. T he

overriding requirement in determining the amount of offset and

gain that can be accommodated by the part is the requirement

that the positive full-scale calibration limit is ≤ 1.05 × FS, where

FS is 20 mV through 1.28 V depending on the RN2, RN1, RN0

bits in the Mode Register. T his allows the input range to go 5%

above the nominal range. The built-in headroom in the AD7731’s

analog modulator ensures that the part will still operate correctly

with a positive full-scale voltage that is 5% beyond the nominal.

P ower -Up and Calibr ation

On power-up, the AD7731 performs an internal reset that sets

the contents of the internal registers to a known state. T here are

default values loaded to all registers after a power-on or reset.

T he default values contain nominal calibration coefficients for

the calibration registers. However, to ensure correct calibration

for the device, a calibration routine should be performed after

power-up.

T he range of input span in both the unipolar and bipolar modes

has a minimum value of 0.8 × FS and a maximum value of

2.1 × FS. However, the span (which is the difference between

the bottom of the AD7731’s input range and the top of its input

range) has to take into account the limitation on the positive

full-scale voltage. T he amount of offset which can be accommo-

dated depends on whether the unipolar or bipolar mode is being

used. Once again, the offset has to take into account the limita-

tion on the positive full-scale voltage. In unipolar mode, there is

considerable flexibility in handling negative (with respect to

AIN[–]) offsets. In both unipolar and bipolar modes, the range

of positive offsets that can be handled by the part depends on

the selected span. T herefore, in determining the limits for sys-

tem zero-scale and full-scale calibrations, the user has to ensure

that the offset range plus the span range does not exceed

1.05 × FS. T his is best illustrated by looking at a few examples.

T he power dissipation and temperature drift of the AD7731 are

low and no warm-up time is required before the initial calibra-

tion is performed. However, if an external reference is being

used, this reference must have stabilized before calibration is

initiated. Similarly, if the clock source for the part is generated

from a crystal or resonator across the MCLK pins, the start-up

time for the oscillator circuit should elapse before a calibration

is initiated on the part (see below).

D r ift Consider ations

T he AD7731 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog multiplexer and

dc leakage currents at the analog input are the primary sources

of offset voltage drift in the part. T he dc input leakage current is

essentially independent of the selected gain. Gain drift within

the converter depends primarily upon the temperature tracking

of the internal capacitors. It is not affected by leakage currents.

If the part is used in unipolar mode with a required span of

0.8 × FS, the offset range the system calibration can handle is

from –1.05 × FS to +0.25 × FS. If the part is used in unipolar

mode with a required span of FS, the offset range the system

calibration can handle is from –1.05 × FS to +0.05 × FS. Simi-

larly, if the part is used in unipolar mode and required to remove

an offset of 0.2 × FS, the span range the system calibration can

handle is 0.85 × FS.

When operating the part in CHOP mode (CHP = 1), the signal

chain including the first-stage filter is chopped. T his chopping

reduces the overall offset drift to 5 nV/°C. When operating in

CHOP mode, it is recommended to calibrate the AD7731 only

after power-up or reset to achieve the optimum drift perfor-

mance from the part. Integral and differential linearity errors are

not significantly affected by temperature changes.

Care must also be taken with external drift effects in order to

achieve optimum drift performance. T he user has to be espe-

cially careful to avoid, as much as possible, thermocouple effects

from junctions of different materials. Devices should not be

placed in sockets when evaluating temperature drift, there should

be no links in series with the analog inputs and care must be

taken as to how the input voltage is applied to the input pins.

T he true offset drift of the AD7731 itself can be evaluated by

performing temperature drift testing of the part with the

AIN(–)/AIN(–) input channel arrangement (i.e., internal

shorted input, test mode).

If the part is used in bipolar mode with a required span of

±0.4 × FS, the offset range the system calibration can handle is

from –0.65 × FS to +0.65 × FS. If the part is used in bipolar

mode with a required span of ±FS, the offset range the system

calibration can handle is from –0.05 × FS to +0.05 × FS. Simi-

larly, if the part is used in bipolar mode and required to remove

an offset of ±0.2 × FS, the span range the system calibration can

handle is ±0.85 × FS. Figure 14 summarizes the span and offset

ranges.

REV. 0

–31–

AD7731

USING TH E AD 7731

Clocking and O scillator Cir cuit

output updates will then be synchronized with the maximum

possible difference between the output updates of the individual

AD7731s being one MCLK IN cycle.

T he AD7731 requires a master clock input, which may be an

external CMOS compatible clock signal applied to the MCLK IN

pin with the MCLK OUT pin left unconnected. Alternatively, a

crystal or ceramic resonator of the correct frequency can be

connected between MCLK IN and MCLK OUT in which case

the clock circuit will function as an oscillator, providing the

clock source for the part. T he input sampling frequency, the

modulator sampling frequency, the –3 dB frequency, output

update rate and calibration time are all directly related to the

master clock frequency, f_{CLK IN}. Reducing the master clock

frequency by a factor of 2 will halve the above frequencies and

update rate and double the calibration time.

Single-Shot Conver sions

T he SYNC input can also be used as a start convert command

allowing the AD7731 to be operated in a conventional converter

fashion. In this mode, the rising edge of SYNC starts conversion

and the falling edge of RDY indicates when conversion is com-

plete. T he disadvantage of this scheme is that the settling time

of the filter has to be taken into account for every data register

update.

Writing 0, 1, 0 to the MD2, MD1, MD0 bits of the Mode regis-

ter has the same effect. T his initiates a single conversion on the

AD7731 with the part returning to idle mode at the end of

conversion. Once again, the full settling time of the filter has to

elapse before the Data Register is updated.

T he crystal or ceramic resonator is connected across the MCLK

IN and MCLK OUT pins, as per Figure 15*. When using a

master clock frequency of 4.9152 MHz, C1 and C2 should both

have a value equal to 33 pF.

Note, if the FAST bit is set and the part operated in single con-

version mode, the AD7731 will continue to output results until

the STDY bit goes to 0.

MCLK IN

Reset Input

CRYSTAL OR

CERAMIC

RESONATOR

C1

C2

T he RESET input on the AD7731 resets all the logic, the digital

filter and the analog modulator while all on-chip registers are

reset to their default state. RDY is driven high and the AD7731

ignores all communications to any of its registers while the

RESET input is low. When the RESET input returns high, the

AD7731 starts to process data and RDY will return low after

the filter has settled indicating a valid new word in the data

register. However, the AD7731 operates with its default setup

conditions after a RESET and it is generally necessary to set up

all registers and carry out a calibration after a RESET command.

AD7731

MCLK OUT

Figure 15. Crystal/Resonator Connections

T he on-chip oscillator circuit also has a start-up time associated

with it before it has attained its correct frequency and correct

voltage levels. T he typical start-up time for the circuit is 6 ms

with a DV_DDof +5 V and 8 ms with a DV_DDof +3 V.

T he AD7731’s on-chip oscillator circuit continues to function

even when the RESET input is low. T he master clock signal

continues to be available on the MCLK OUT pin. T herefore, in

applications where the system clock is provided by the AD7731’s

clock, the AD7731 produces an uninterrupted master clock

during RESET commands.

T he AD7731’s master clock appears on the MCLK OUT pin of

the device. T he maximum recommended load on this pin is one

CMOS load. When using a crystal or ceramic resonator to gen-

erate the AD7731’s clock, it may be desirable to then use this

clock as the clock source for the system. In this case, it is recom-

mended that the MCLK OUT signal is buffered with a CMOS

buffer before being applied to the rest of the circuit.

Standby Mode

T he STANDBY input on the AD7731 allows the user to place

the part in a power-down mode when it is not required to

provide conversion results. T he part can also be placed in its

standby mode by writing 0, 1, 1 to the MD2, MD1, MD0 bits

of the Mode Register. T he AD7731 retains the contents of all its

on-chip registers (including the Data Register) while in standby

mode. Data can still be read from the part in Standby Mode.

T he ST BY bit of the Status Register indicates whether the part

is in standby or normal operating mode. When the STANDBY

pin is taken high, the part returns to operating as it had been

prior to the STANDBY pin going low.

System Synchr onization

T he SYNC input allows the user to reset the modulator and

digital filter without affecting any of the setup conditions on the

part. T his allows the user to start gathering samples of the ana-

log input from a known point in time, i.e., the rising edge of

SYNC.

If multiple AD7731s are operated from a common master clock,

they can be synchronized to update their output registers simul-

taneously. A falling edge on the SYNC input resets the digital

filter and analog modulator and places the AD7731 into a con-

sistent, known state. While the SYNC input is low, the AD7731

will be maintained in this state. On the rising edge of SYNC,

the modulator and filter are taken out of this reset state and on

the next clock edge the part again starts to gather input samples.

In a system using multiple AD7731s, a common signal to their

SYNC inputs will synchronize their operation. T his would nor-

mally be done after each AD7731 has performed its own cali-

bration or has had calibration coefficients loaded to it. T he

T he STANDBY input (or 0, 1, 1 in the MD2, MD1, MD0 bits)

does not affect the digital interface. It does, however, set the

RDY bit and pin high and also sets the STDY bit high. When

STANDBY goes high again, RDY and STDY remain high until

set low by a conversion or calibration.

*T he AD7731 has a capacitance of 5 pF on MCLK IN and 13 pF on MCLK

OUT .

–32–

REV. 0

AD7731

Placing the part in standby mode reduces the total current to

10 µA typical when the part is operated from an external master

clock, provided this master clock is stopped. If the external

clock continues to run in standby mode, the standby current

increases to 400 µA typical. If a crystal or ceramic resonator is

used as the clock source, then the total current in standby mode

is 400 µA typical. T his is because the on-chip oscillator circuit

continues to run when the part is in its standby mode. T his is

important in applications where the system clock is provided by

the AD7731’s clock, so that the AD7731 produces an uninter-

rupted master clock even when it is in its standby mode.

an AGND to DGND connection, the ground planes should be

connected at the AGND and DGND pins of the AD7731. If the

AD7731 is in a system where multiple devices require AGND to

DGND connections, the connection should still be made at one

point only, a star ground point, which should be established as

close as possible to the AD7731.

Avoid running digital lines under the device as these will couple

noise onto the die. T he analog ground plane should be allowed

to run under the AD7731 to avoid noise coupling. T he power

supply lines to the AD7731 should use as large a trace as pos-

sible to provide low impedance paths and reduce the effects of

glitches on the power supply line. Fast switching signals like

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board and clock signals should

never be run near the analog inputs. Avoid crossover of digital

and analog signals. T races on opposite sides of the board should

run at right angles to each other. T his will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the solder side.

D igital O utputs

T he AD7731 has two digital output pins, D0 and D1. When

the DEN bit of the Mode Register is set to 1, these digital

outputs assume the logic status of bits D0 and D1 of the

Mode Register. It gives the user access to two digital port

pins which can be programmed over the normal serial inter-

face of the AD7731. T he two outputs obtain their supply

voltage from AV_DD, thus the outputs operate to 5 V levels

even in cases where DV_DD= +3 V.

P O WER SUP P LIES

Good decoupling is important when using high resolution ADCs.

All analog supplies should be decoupled with 10 µF tantalum in

parallel with 0.1 µF capacitors to AGND. T o achieve the best

from these decoupling components, they have to be placed as

close as possible to the device, ideally right up against the device.

All logic chips should be decoupled with 0.1 µF disc ceramic

capacitors to DGND. In systems where a common supply volt-

age is used to drive both the AV_DDand DV_DDof the AD7731, it

is recommended that the system’s AV_DDsupply is used. T his

supply should have the recommended analog supply decoupling

capacitors between the AV_DDpin of the AD7731 and AGND

and the recommended digital supply decoupling capacitor

between the DV_DDpin of the AD7731 and DGND.

T here is no specific power sequence required for the AD7731,

either the AV_DDor the DV_DDsupply can come up first. While

the latch-up performance of the AD7731 is very good, it is

important that power is applied to the AD7731 before signals at

REF IN, AIN or the logic input pins in order to avoid latch-up

caused by excessive current. If this is not possible, then the

current which flows in any of these pins should be limited to less

than 30 mA per pin and less than 100 mA cumulative. If sepa-

rate supplies are used for the AD7731 and the system digital

circuitry, then the AD7731 should be powered up first. If it is

not possible to guarantee this, then current limiting resistors

should be placed in series with the logic inputs to again limit the

current to less than 30 mA per pin and less than 100 mA total.

Evaluating the AD 7731 P er for m ance

Gr ounding and Layout

A recommended layout for the AD7731 is outlined in the evalu-

ation board for the AD7731. T he evaluation board package

includes a fully assembled and tested evaluation board, docu-

mentation, software for controlling the board over the printer

port of a PC and software for analyzing the AD7731’s perfor-

mance on the PC. T he evaluation board order number is

EVAL-AD7731EB.

Since the analog inputs and reference input are differential,

most of the voltages in the analog modulator are common-mode

voltages. T he excellent Common-Mode Rejection of the part

will remove common-mode noise on these inputs. T he analog

and digital supplies to the AD7731 are independent and sepa-

rately pinned out to minimize coupling between the analog and

digital sections of the device. T he digital filter will provide rejec-

tion of broadband noise on the power supplies, except at integer

multiples of the modulator sampling frequency. T he digital filter

also removes noise from the analog and reference inputs pro-

vided those noise sources do not saturate the analog modulator.

As a result, the AD7731 is more immune to noise interference

that a conventional high resolution converter. However, because

the resolution of the AD7731 is so high and the noise levels

from the AD7731 so low, care must be taken with regard to

grounding and layout.

Noise levels in the signals applied to the AD7731 may also

affect performance of the part. T he AD7731 allows a technique

for evaluating the true performance of the part, independent of

the analog input signal. T his scheme should be used after a

calibration has been performed on the part.

T he first method is to select the AIN6/AIN6 input channel

arrangement. In this case, the differential inputs to the AD7731

are internally shorted together to provide a zero differential

voltage for the analog modulator. External to the device, the

AIN6 input should be connected to a voltage which is within the

allowable common-mode range of the part.

T he printed circuit board that houses the AD7731 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. T his facilitates the

use of ground planes which can be separated easily. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD7731 is the only device requiring

T he software in the evaluation board package allows the user to

look at the noise performance in terms of bits and nV. Once the

user has established that the noise performance of the part is

satisfactory in this mode, then an external input voltage can be

applied to the device incorporating more of the signal chain.

REV. 0

–33–

AD7731

SERIAL INTERFACE

data from the input shift register takes place after eight serial

clock cycles for a DAC Register write while the transfer of data

from the input shift register takes place after 24 serial clock

cycles when writing to the Filter Register. Figure 16 shows a

timing diagram for a write operation to the input shift register of

the AD7731. With the POL input at a logic high, the data is

latched into the input shift register on the rising edge of SCLK.

With the POL input at a logic low, the data is latched into the

input shift register on the falling edge of SCLK.

T he AD7731’s programmable functions are controlled via a set

of on-chip registers. Access to these registers is via the part’s

serial interface. After power-on or RESET , the device expects a

write to its Communications Register. T he data written to this

register determines whether the next operation to the part is a

read or a write operation and also determines to which register

this read or write operation occurs. T herefore, write access to

one of the control registers on the part starts with a write opera-

tion to the Communications Register followed by a write to the

selected register. Reading from the part’s on-chip registers can

either take the form of a single read or continuous read. A single

read from a register consists of a write to the Communications

Register (with RW1 = 0 and RW0 = 1) followed by the read

from the specified register. T o perform continuous reads from a

register, write to the Communications Register (with RW1 = 1

and RW0 = 0) to place the part in continuous read mode. T he

specified register can then be read from continuously until a

write operation to the Communications Register (with RW1 = 1

and RW0 = 1) which takes the part out of continuous read

mode. When operating in continuous read mode, the part is

continuously monitoring its DIN line. T herefore, the DIN line

should be permanently low to allow the part to stay in continu-

ous read mode. Figure 5 and Figure 6, shown previously, indi-

cate the correct flow diagrams when reading and writing from

the AD7731’s registers.

Figure 16 also shows the CS input being used to decode the

write operation to the AD7731. However, this CS input can be

used in a number of different ways. It is possible to operate the

part in three-wire mode where the CS input is permanently tied

low. In this case, the SCLK line should idle high between data

transfer when the POL input is high and should idle low be-

tween data transfers when the POL input is low. For POL = 1,

the first falling edge of SCLK clocks data from the microcontroller

onto the DIN line of the AD7731. It is then clocked into the

input shift register on the next rising edge of SCLK. For POL = 0,

the first clock edge which clocks data from the microcontroller

onto the DIN line of the AD7731 is a rising edge. It is then

clocked into the input shift register on the next falling edge of

SCLK.

In other microcontroller applications, which require a decoding

of the AD7731, CS can be generated from a port line. In this

case, CS would go low well in advance of the first falling edge of

SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).

Clocking of each bit of data is as just described.

The AD7731’s serial interface consists of five signals, CS, SCLK,

DIN, DOUT and RDY. T he DIN line is used for transferring

data into the on-chip registers while the DOUT line is used for

accessing data from the on-chip registers. SCLK is the serial

clock input for the device and all data transfers (either on DIN

or DOUT ) take place with respect to this SCLK signal.

In DSP applications, the SCLK is generally a continuous clock.

In these applications, the CS input for the AD7731 is generated

from a frame synchronization signal from the DSP. For proces-

sors with the rising edge of SCLK as the active edge, the POL

input should be tied high. For processors with the falling edge of

SCLK as the active edge, the POL input should be tied low. In

these applications, the first edge after CS goes low is the active

edge. T he MSB of the data to be shifted into the AD7731 must

be set up prior to this first active edge.

Wr ite O per ation

T he transfer of data into the part is to an input shift register. On

completion of a write operation, data is transferred to the speci-

fied register. T his internal transfer will not take place until the

correct number of bits for the specified register have been

loaded to the input shift register. For example, the transfer of

CS

t₁₆

t₁₁

t₁₄

SCLK

(POL = 1)

t₁₅

t₁₄

SCLK

(POL = 0)

t₁₅

t₁₂

t₁₃

MSB

LSB

DIN

Figure 16. Write Cycle Tim ing Diagram

–34–

REV. 0

AD7731

be set up prior to this first active edge. Unlike microcontroller

applications, the DSP does not provide a clock edge to clock the

MSB from the AD7731. In this case, the CS of the AD7731

places the MSB on the DOUT line. For processors with the

rising edge of SCLK as the active edge, the POL input should

be tied high. In this case, the microcontroller takes data on the

rising edge. If CS goes low while SCLK is low, the MSB is

clocked out on the DOUT line from the CS. Subsequent data

bits are clocked from the falling edge of SCLK. For processors

with the falling edge of SCLK as the active edge, the POL input

should be tied low. In this case, the microcontroller takes data

on the falling edge. If CS goes low while SCLK is high, then the

MSB is clocked out on the DOUT line from the CS. Subse-

quent data bits are clocked from the rising edge of SCLK.

Read O per ation

T he reading of data from the part is from an output shift regis-

ter. On initiation of a read operation, data is transferred from

the specified register to the output shift register. T his is a paral-

lel shift and is transparent to the user. Figure 16 shows a timing

diagram for a read operation from the output shift register of the

AD7731. With the POL input at a logic high, the data is clocked

out of the output shift register on the falling edge of SCLK.

With the POL input at a logic low, the data is clocked out of the

output shift register on the rising edge of SCLK.

Figure 16 also shows the CS input being used to decode the

read operation to the AD7731. However, this CS input can be

used in a number of different ways. It is possible to operate the

part in three-wire mode where the CS input is tied low perma-

nently. In this case, the SCLK line should idle high between

data transfer when the POL input is high and should idle low

between data transfers when the POL input is low. For POL = 1,

the first falling edge of SCLK clocks data from the output shift

register onto the DOUT line of the AD7731. It is then clocked

into the microcontroller on the next rising edge of SCLK. For

POL = 0, the first clock edge which clocks data from the AD7731

onto the DOUT line is a rising edge. It is then clocked into the

microcontroller on the next falling edge of SCLK.

T he RDY line is used as a status signal to indicate when data is

ready to be read from the AD7731’s data register. RDY goes

low when a new data word is available in the data register. It is

reset high when a read operation from the data register is com-

plete. It also goes high prior to the updating of the data register

to indicate when a read from the data register should not be

initiated. T his is to ensure that the transfer of data from the data

register to the output shift register does not occur while the data

register is being updated. It is possible to read the same data

twice from the output register even though the RDY line returns

high after the first read operation. Care must be taken, however,

to ensure that the read operations are not initiated as the next

output update is about to take place.

In other microcontroller applications, which require a decoding

of the AD7731, CS can be generated from a port line. In this

case, CS would go low well in advance of the first falling edge of

SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).

Clocking of each bit of data is as just described.

For systems with a single data line, the DIN and DOUT lines

on the AD7731 can be connected together but care must be

taken in this case not to place the part in continuous read mode

as the part monitors DIN while supplying data on DOUT and

as a result, it may not be possible to take the part out of its

continuous read mode.

In DSP applications, the SCLK is generally a continuous clock.

In these applications, the CS input for the AD7731 is generated

from a frame synchronization signal from the DSP. In these

applications, the first edge after CS goes low is the active edge.

T he MSB of the data to be shifted into the microcontroller must

RDY

t₁₀

t₃

CS

t₈

t₄

t₆

SCLK

(POL = 1)

t₇

t₆

SCLK

(POL = 0)

t₇

t₅

t₉

t_5A

DOUT

MSB

LSB

Figure 17. Read Cycle Tim ing Diagram

REV. 0

–35–

AD7731

CO NFIGURING TH E AD 7731

T he AD7731 contains twelve on-chip registers which can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a

flowchart for the reading and writing of these registers. T able XIX and T able XX outline sample pseudo-code for some commonly

used routines. T he required operating conditions will dictate the values loaded to the Mode and Filter Registers. T he values given

here are for example purposes only.

Table XIX. P seudo-Code for Initiating a Self-Calibration after P ower-O n/Reset

Write 03 Hex to Serial Port¹

Write 1332 Hex to Serial Port¹

Write 02 Hex to Serial Port

Write B174 Hex to Serial Port

/* Writes to Communications Register Setting Next Operation as Write to

Filter Register*/

/* Writes to Filter Register Setting a 1 kHz Output Rate in nonCHOP

Mode*/

/* Writes to Communications Register Setting Next Operation as Write to

Mode Register*/

/* Writes to Mode Register Initiating Internal Full-Scale Calibration for

0 V to +1.28 V Input Range on Channel Pair AIN1/AIN2*/

Wait for RDY Low

/* Wait for RDY pin to go low to indicate end of calibration cycle*/

Write 02 Hex to Serial Port

/* Writes to Communications Register Setting Next Operation as Write to

Mode Register*/

Write 9174 Hex to Serial Port

/* Writes to Mode Register Initiating Internal Zero-Scale Calibration for

0 V to +1.28 V Input Range*/

Wait for RDY Low

/* Wait for RDY pin to go low to indicate end of calibration cycle*/

/* T he part has now completed self-calibration and is in idle mode*/

¹T his operation is not necessary if the default values of the Filter Register are the values used in the application.

Table XX. P seudo-Code for Looping AD 7731 Through Three Fully-D ifferential Channels

CHANNEL = 4 Hex

/* Sets a Variable Called CHANNEL*/

/* Sets a Variable Called MODE */

/* Logical AND of Both Variables */

CH_LOOP: MODE = 2177 Hex

MODE = MODE AND CHANNEL

Write 02 Hex to Serial Port

/* Writes to Communications Register Setting Next Operation as Write to

Mode Register*/

Write MODE to Serial Port

/* Writes to Mode Register Setting Continuous Conversion Mode for 0 V

to +1.28 V Input Range on Channel Determined by CHANNEL Variable*/

Wait for RDY Low

/* Wait for RDY pin to go low to Indicate Output Update*/

Write 11 Hex to Serial Port

/* Writes to Communications Register Setting Next Operation as Read

From Data Register*/

Read 24-Bit Data From Serial Port

Increment CHANNEL

/* Read Conversion Result from AD7731’s Data Register*/

/* Increments Channel Address*/

If CHANNEL = 7Hex T hen Set CHANNEL = 4 Hex /* Resets Channel Address*/

Loop to CH_LOOP

–36–

REV. 0

AD7731

MICRO CO MP UTER/MICRO P RO CESSO R INTERFACING

T he AD7731’s flexible serial interface allows for easy interface

to most microcomputers and microprocessors. T he pseudo-code

of T able XVIII and T able XIX outline typical sequences for

interfacing a microcontroller or microprocessor to the AD7731.

Figures 18, 19 and 20 show some typical interface circuits.

that the SCLK idle high, the CPOL bit of the 68HC11 should

be set to a logic 1 and the POL input of the AD7731 should be

hard-wired to a logic high.

T he AD7731 is not capable of full duplex operation. If the

AD7731 is configured for a write operation, no data appears on

the DAT A OUT lines even when the SCLK input is active.

However, when the AD7731 is configured for continuous read

operation, data presented to the part on the DAT A IN line is

monitored to determine when to exit the continuous read mode.

T he serial interface on the AD7731 has the capability of operat-

ing from just three wires and is compatible with SPI interface

protocols. T he three-wire operation makes the part ideal for

isolated systems where minimizing the number of interface lines

minimizes the number of opto-isolators required in the system.

DV

DD

DV

DD

Register lengths on the AD7731 vary from 8 to 16 to 24 bits.

T he 8-bit serial serial ports of most microcontrollers can handle

communication with these registers as either one, two or three

8-bit transfers. DSP processors and microprocessors generally

transfer 16 bits of data in a serial data operation. Some of these

processors, such as the ADSP-2105, have the facility to program

the amount of cycles in a serial transfer. T his allows the user to

tailor the number of bits in any transfer to match the register

length of the required register in the AD7731. In any case,

writing 32 bits of data to a 24-bit register is not an issue pro-

vided the final 8 bits of the word are all 1s. T his is because the

part returns to the Communications Register following a write

operation.

SS

SYNC

RESET

68HC11

AD7731

SCLK

SCK

MISO

MOSI

DATA OUT

DATA IN

CS

POL

Figure 18. AD7731 to 68HC11 Interface

AD 7731 to 8051 Inter face

AD 7731 to 68H C11 Inter face

Figure 18 shows an interface between the AD7731 and the

68HC11 microcontroller. T he diagram shows the minimum

(three-wire) interface with CS on the AD7731 hard-wired low.

In this scheme, the RDY bit of the Status Register is monitored

to determine when the Data Register is updated. An alternative

scheme, which increases the number of interface lines to four, is

to monitor the RDY output line from the AD7731. T he moni-

toring of the RDY line can be done in two ways. First, RDY can

be connected to one of the 68HC11’s port bits (such as PC0)

which is configured as an input. T his port bit is then polled to

determine the status of RDY. T he second scheme is to use an

interrupt driven system in which case, the RDY output is con-

nected to the IRQ input of the 68HC11. For interfaces which

require control of the CS input on the AD7731, one of the port

bits of the 68HC11 (such as PC1), which is configured as an

output, can be used to drive the CS input.

An interface circuit between the AD7731 and the 8XC51 micro-

controller is shown in Figure 19. T he diagram shows the mini-

mum number of interface connections with CS on the AD7731

hard-wired low. In the case of the 8XC51 interface the mini-

mum number of interconnects is just two. In this scheme, the

RDY bit of the Status Register is monitored to determine when

the Data Register is updated. T he alternative scheme, which

increases the number of interface lines to three, is to monitor

the RDY output line from the AD7731. T he monitoring of the

RDY line can be done in two ways. First, RDY can be con-

nected to one of the 8XC51’s port bits (such as P1.0) which is

configured as an input. T his port bit is then polled to determine

the status of RDY. T he second scheme is to use an interrupt

driven system in which case, the RDY output is connected to

the INT 1 input of the 8XC51. For interfaces which require

control of the CS input on the AD7731, one of the port bits of

the 8XC51 (such as P1.1), which is configured as an output,

can be used to drive the CS input.

T he 68HC11 is configured in the master mode with its CPOL

bit set to a logic zero and its CPHA bit set to a logic one. When

the 68HC11 is configured like this, its SCLK line idles low

between data transfers. Therefore, the POL input of the AD7731

should be hard-wired low. For systems where it is preferable

REV. 0

–37–

AD7731

T he 8XC51 is configured in its Mode 0 serial interface mode.

Its serial interface contains a single data line. As a result, the

DAT A OUT and DAT A IN pins of the AD7731 should be

connected together. T his means that the AD7731 must not be

configured for continuous read operation when interfacing to

the 8XC51. T he serial clock on the 8XC51 idles high between

data transfers and, therefore, the POL input of the AD7731

should be hard-wired to a logic high. T he 8XC51 outputs the

LSB first in a write operation while the AD7731 expects the

MSB first so the data to be transmitted has to be rearranged

before being written to the output serial register. Similarly, the

AD7731 outputs the MSB first during a read operation while

the 8XC51 expects the LSB first. T herefore, the data read into

the serial buffer needs to be rearranged before the correct data

word from the AD7731 is available in the accumulator.

AD 7731 to AD SP -2103/AD SP -2105 Inter face

Figure 20 shows an interface between the AD7731 and the

ADSP-2105 DSP processor. In the interface shown, the RDY

bit of the Status Register is again monitored to determine when

the Data Register is updated. T he alternative scheme is to use

an interrupt driven system, in which case the RDY output is

connected to the IRQ2 input of the ADSP-2105. T he RFS and

TFS pins of the ADSP-2105 are configured as active low out-

puts and the ADSP-2105 serial clock line, SCLK, is also config-

ured as an output. T he POL pin of the AD7731 is hard-wired

low. Because the SCLK from the ADSP-2105 is a continuous

clock, the CS of the AD7731 must be used to gate off the clock

once the transfer is complete. T he CS for the AD7731 is active

when either the RFS or TFS outputs from the ADSP-2105 are

active. T he serial clock rate on the ADSP-2105 should be lim-

ited to 3 MHz to ensure correct operation with the AD7731.

DV

DD

DV

DD

SYNC

ADSP-2105

RESET

8XC51

AD7731

RFS

POL

CS

TFS

P3.0

P3.1

DATA OUT

DATA IN

DR

DT

DATA OUT

DATA IN

SCLK

POL

CS

Figure 20. AD7731 to ADSP-2105 Interface

Figure 19. AD7731 to 8XC51 Interface

–38–

REV. 0

AD7731

AP P LICATIO NS

D ata Acquisition

T he on-chip PGA allows the AD7731 to handle analog input

voltage ranges from 20 mV to 1.28 V. T his makes the AD7731

suitable for a range of application areas from handling signals

directly from a transducer to processing fully-conditioned full-

scale inputs. Some of these applications are discussed in the

following sections.

T he AD7731 with its three differential channels (or five pseudo-

differential channels) is suited to low bandwidth, high resolution

data acquisition systems. In addition, the three-wire digital

interface allows this data acquisition front end to be isolated

with just three optoisolators. T he entire system can be operated

from a single +5 V supply provided that the input signals to the

AD7731’s analog inputs are all of positive polarity. Figure 21

shows the AD7731 in an isolated three-channel data acquisition

system.

T he AD7731 offers both unipolar and bipolar input ranges. In

many cases, the application is single supply with the bipolar

input voltages referenced to a biased-up differential voltage.

Some applications will, however, require the flexibility of han-

dling true bipolar inputs. Figure 25 shows how to configure the

AD7731 to handle this type of signal.

P r ogr am m able Logic Contr oller s

T he AD7731 is also suited to programmable logic controller

applications. In such applications, the ADC is required to

handle signals from a variety of different transducers. T he

AD7731’s programmable gain front end allows the part to either

handle low level signals directly from a transducer or full-scale

signals which have already been conditioned. T he fast through-

put rate and settling-time of the part is also an important feature

in these applications where loop response time is often critical.

T he configuration of the AD7731 in PLC applications is similar

to that outlined in Figure 21 for the data acquisition system.

It should be noted in multiplexed applications that an input

overvoltage (either >AVDD + 0.3 V or <AGND – 0.3 V) on an

unselected channel can affect the conversion result on the se-

lected channel. T he system design should ensure that the input

voltage on channels where input leads may be unconnected or

broken be kept within the above limits.

T he AD7731 has a variety of different modes aimed at optimiz-

ing the AD7731’s performance across differing application require-

ments. The issue of filtering and settling time and throughput rates

in multichannel applications has previously been discussed in the

Filter Architecture section.

+5V

AV

DD

DV

DD

AV

DD

AD7731

100nA

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

SIGMA-DELTA A/D

CONVERTER

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

STANDBY

BUFFER

SIGMA-

DELTA

MODULATOR

DIGITAL

FILTER

SYNC

PGA

MCLK IN

CLOCK

GENERATION

SERIAL INTERFACE

AND CONTROL LOGIC

+5V

100nA

MCLK OUT

+V

IN

REGISTER BANK

AGND

REF IN (+)

RESET

RDY

V

OUT

AD780

GND

REF IN (–)

AGND

POL

DGND

DOUT

DIN

CS

SCLK

MICROCONTROLLER

OPTO-ISOLATORS

Figure 21. Data Acquisition Using the AD7731

REV. 0

–39–

AD7731

P r essur e Measur em ent

Figure 24 shows another temperature measurement application

for the AD7731. In this case, the temperature transducer is an

RT D (Resistive T emperature Device), a PT 100. T he arrange-

ment is a four-lead RT D configuration. T here are voltage drops

across lead resistances RL1 and RL4 and across resistor R2 but

these simply shift the common-mode voltage. Resistor R2 is

required to set the common-mode voltage within the allowable

range for the AD7731. T he voltage differential caused by RL2

and RL3 and the AD7731’s offset current is negligible.

One typical application of the AD7731 where it is connected

directly to a transducer is in pressure measurement. Figure 22

shows the AD7731 with a pressure transducer in a bridge

arrangement. T he differential output from the transducer is

connected directly to the AIN1/AIN2 input channel. T he entire

circuit is powered from a single +5 V supply that generates the

excitation voltage for the transducer and the power supply, and

reference voltage for the AD7731. T he application is ratiometric

and variations in the excitation voltage do not introduce errors

in the measurement.

In the application shown, the external 400 µA current source

provides the excitation current for the PT 100 and it also gener-

ates the reference voltage for the AD7731 via resistor R1. Varia-

tions in the excitation current do not affect the circuit as the

input voltage and the reference voltage vary ratiometrically with

the excitation current. Resistor R1, however, must have a low

temperature coefficient to avoid errors in the reference voltage

over temperature.

Tem per atur e Measur em ent

Another application area where the transducer can be connected

directly to the AD7731 is in temperature measurement. Figure

23 outlines a connection between a thermocouple and the

AD7731. In order to place the differential voltage from the

AD7731 on a suitable common-mode voltage, the AIN2 input

of the AD7731 is biased up at the reference voltage, +2.5 V.

EXCITATION VOLTAGE = +5V

AV

DD

DV

DD

AV

DD

AD7731

IN+

100nA

OUT+

AIN1

SIGMA-DELTA A/D

CONVERTER

OUT–

AIN2

STANDBY

BUFFER

SIGMA-

DELTA

MODULATOR

AIN3

IN–

DIGITAL

FILTER

SYNC

PGA

AIN4

AIN5

AIN6

MCLK IN

CLOCK

GENERATION

SERIAL INTERFACE

AND CONTROL LOGIC

100nA

MCLK OUT

REGISTER BANK

AGND

REF IN (+)

RESET

RDY

POL

REF IN (–)

AGND

DGND

DOUT

DIN

CS

SCLK

Figure 22. Pressure Measurem ent Using the AD7731

–40–

REV. 0

AD7731

+5V

AV

DV

DD

AV

DD

AD7731

100nA

THERMOCOUPLE

JUNCTION

R

AIN1

AIN2

SIGMA-DELTA A/D

CONVERTER

STANDBY

SYNC

BUFFER

C

SIGMA-

DELTA

AIN3

AIN4

AIN5

AIN6

DIGITAL

FILTER

PGA

MODULATOR

MCLK IN

CLOCK

GENERATION

SERIAL INTERFACE

AND CONTROL LOGIC

+5V

100nA

MCLK OUT

+V

IN

REGISTER BANK

AGND

SCLK

CS

REF IN (+)

V

OUT

AD780

GND

REF IN (–)

AGND

DIN

DOUT

DGND

POL

RDY

RESET

Figure 23. Tem perature Measurem ent Using the AD7731

+5V

AV

DD

DV

400␮A

DD

REF IN (+)

AD7731

AV

DD

R1

6.25kΩ

100nA

R

L1

REF IN (–)

AIN1

SIGMA-DELTA A/D

CONVERTER

STANDBY

R

L2

BUFFER

SIGMA-

DELTA

MODULATOR

DIGITAL

FILTER

SYNC

PGA

RTD

R

MCLK IN

L3

AIN2

CLOCK

GENERATION

SERIAL INTERFACE

AND CONTROL LOGIC

MCLK OUT

100nA

R2

3kΩ

REGISTER BANK

AGND

R

L4

AGND

DGND

RESET

RDY

POL

DOUT

DIN

CS

SCLK

Figure 24. RTD Measurem ent Using the AD7731

REV. 0

–41–

AD7731

Bipolar Input Signals

A1 and A2 buffer the resistor string voltages and provide the

AV_DDand AGND voltages as well as the REF IN(+) and REF

IN(–) voltages for the AD7731. T he differential reference volt-

age for the part is +5 V. If the input voltage is from a transducer

excited by the ±5 V, the AD7731 retains its ratiometric opera-

tion with this reference voltage varying in sympathy with the

analog input voltage.

As mentioned previously, some applications will require that the

AD7731 handle input signals that are negative with respect to

system ground. T he number of applications requiring this are

limited but with the addition of some external components the

AD7731 is capable of handling such signals. Figure 25 outlines

one approach to the problem.

T he example shown is a system that is driven from ±5 V sup-

plies. In such a circuit, two issues must be addressed. T he first

is how to get the AD7731 to handle input voltages below ground

and the second is how to generate a suitable reference voltage

for the AD7731. T he circuit of Figure 25 attempts to address

these two issues simultaneously.

T he values of the resistors in the resistor string are chosen as-

suming the maximum input voltage range of ±1.28 V is applied

to the AD7731. The minimum input voltage must be 1.2 V above

the AD7731’s AGND, while the maximum input voltage must be

0.95 V below the AD7731’s AV_DD. For smaller input voltage

ranges, the resistor ratios in the resistor string can be changed

to allow a larger DV_DDvoltage. For example, if R1 = 3 kΩ,

R2 = 10 kΩ and R3 = 6.8 kΩ, the AV_DDand AGND voltages

become +3.49 V and –1.56 V respectively. T his allows the

AD7731 to be used with a +3.6 V DV_DDvoltage while allowing

analog input ranges of ±320 mV and below.

T he AD7731’s analog and digital supplies can be split such that

AV_DDand DV_DDcan be at separate potentials and AGND and

DGND can also be at separate potentials. T he only stipulation

is that AV_DDor DV_DDmust not exceed the AGND by 5.5 V. In

Figure 25, the DV_DDis operated at +3 V which allows the AGND

to go down to –2.5 V with respect to system ground. T his

means that all logic signals to the part must not exceed 3 V with

respect to system ground. T he AV_DDis operated at +2.5 V with

respect to system ground.

An alternate scheme is to generate the AV_DDand AGND volt-

ages from regulators or Zener diodes driven from the +5 V and

–5 V supplies respectively. T he reference voltage for the part

can be generated from an AD780 whose GND pin is connected

to the AD7731’s AGND pin.

T he resistor string R1, R2 and R3 takes the ±5 V supply voltage

and generates a differential voltage of nominally 5 V. Amplifiers

+3V

DV

DD

1/2 OP284

OR 1/2 OP213

AV

DD

+5V

AD7731

+5V

AV

DD

R1

5kΩ

REF IN(+)

A1

100nA

SIGMA-DELTA A/D CONVERTER

–5V

STANDBY

AIN1(+)

AIN1(–)

BUFFER

SIGMA-

DELTA

MODULATOR

PROGRAMMABLE

DIGITAL

R2

10kΩ

SYNC

FILTER

PGA

+5V

–5V

MCLK IN

REF IN(–)

AGND

CLOCK

GENERATION

A2

R3

5kΩ

SERIAL INTERFACE

AND CONTROL LOGIC

MCLK OUT

100nA

REGISTER BANK

1/2 OP284

OR 1/2 OP213

–5V

SCLK

CS

AGND

CALIBRATION

MICROCONTROLLER

DIN

DOUT

DGND

POL

RDY

RESET

ALL VOLTAGE VALUES ARE WITH

RESPECT TO SYSTEM GROUND.

SYSTEM

GROUND

Figure 25. Bipolar Input Signals on the AD7731

–42–

REV. 0

AD7731

P AGE IND EX

Topic

P age

SERIAL INT ERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

CONFIGURING T HE AD7731 . . . . . . . . . . . . . . . . . . . . . 36

MICROCOMPUT ER/MICROPROCESSOR

INT ERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

AD7731 to 68HC11 Interface . . . . . . . . . . . . . . . . . . . . . 37

AD7731 to 8051 Interface . . . . . . . . . . . . . . . . . . . . . . . 37

AD7731 to ADSP-2103/ADSP-2105 Interface . . . . . . . . 38

APPLICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Data Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Programmable Logic Controllers . . . . . . . . . . . . . . . . . . 39

Pressure Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 40

T emperature Measurement . . . . . . . . . . . . . . . . . . . . . . . 40

Bipolar Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 44

FEAT URES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

T IMING CHARACT ERIST ICS . . . . . . . . . . . . . . . . . . . . . 4

ABSOLUT E MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . 5

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

DET AILED FUNCT IONAL BLOCK DIAGRAM . . . . . . . 6

SIGNAL PROCESSING CHAIN . . . . . . . . . . . . . . . . . . . . . 7

PIN CONFIGURAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PIN FUNCT ION DESCRIPT IONS . . . . . . . . . . . . . . . . . . 7

T ERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

OUT PUT NOISE AND RESOLUT ION

SPECIFICAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ON-CHIP REGIST ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Summary Of On-Chip Registers . . . . . . . . . . . . . . . . . . . 12

Communications Register . . . . . . . . . . . . . . . . . . . . . . . . 13

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Offset Calibration Register . . . . . . . . . . . . . . . . . . . . . . . 19

Gain Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . 19

T est Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

READING FROM AND WRIT ING T O T HE

ON-CHIP REGIST ERS . . . . . . . . . . . . . . . . . . . . . . . . . 20

CALIBRAT ION OPERAT ION SUMMARY . . . . . . . . . . . 21

CIRCUIT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . 22

ANALOG INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Analog Input Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Analog Input Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Bipolar/Unipolar Inputs . . . . . . . . . . . . . . . . . . . . . . . . . 23

Burnout Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

REFERENCE INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reference Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SIGMA-DELT A MODULAT OR . . . . . . . . . . . . . . . . . . . . 24

DIGIT AL FILT ERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Filter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

First Stage Filter/SKIP Mode Enabled . . . . . . . . . . . . . . 25

Second Stage Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Normal FIR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 25

FASTStep™ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

CALIBRAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Internal Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . 29

Internal Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . 30

System Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . 30

System Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 30

Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . 31

Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

USING T HE AD7731 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 32

System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 32

Single-Shot Conversions . . . . . . . . . . . . . . . . . . . . . . . . . 32

Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Evaluating the AD7731 Performance . . . . . . . . . . . . . . . 33

TABLE IND EX

Table

Title

P age

T able I.

Output Noise vs. Input Range and

Update Rate (CHP = 0, SKIP = 1) . . . . . . . 10

T able II.

T able III.

T able IV.

Peak-to-Peak Resolution vs. Input Range

and Update Rate (CHP = 0, SKIP = 1) . . . . 10

Output Noise vs. Input Range and

Update Rate (CHP = 1, SKIP = 0) . . . . . . . 11

Peak-to-Peak Resolution vs. Input Range

and Update Rate (CHP = 1, SKIP = 0) . . . . 11

T able V.

Summary of On-Chip Registers . . . . . . . . . . 12

Communications Register . . . . . . . . . . . . . . 13

Read/Write Mode . . . . . . . . . . . . . . . . . . . . 13

Register Selection . . . . . . . . . . . . . . . . . . . . 14

Status Register . . . . . . . . . . . . . . . . . . . . . . . 14

Mode Register . . . . . . . . . . . . . . . . . . . . . . . 15

Operating Modes . . . . . . . . . . . . . . . . . . . . . 15

Input Range Selection . . . . . . . . . . . . . . . . . 17

Channel Selection . . . . . . . . . . . . . . . . . . . . 18

Filter Register . . . . . . . . . . . . . . . . . . . . . . . 18

SF Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Calibration Operations . . . . . . . . . . . . . . . . 21

T able VI.

T able VII.

T able VIII.

T able IX.

T able X.

T able XI.

T able XII.

T able XIII.

T able XIV.

T able XV.

T able XVI.

T able XVII. Reset Events . . . . . . . . . . . . . . . . . . . . . . . . 22

T able XVIII. T ime to First and Subsequent Outputs

Following Channel Change . . . . . . . . . . . . . 28

T able XIX.

Pseudo-Code for Initiating a

Self-Calibration After Power-On/Reset . . . . 36

T able XX.

Pseudo-Code for Looping T hrough T hree

Fully-Differential Channels . . . . . . . . . . . . . 36

REV. 0

–43–

AD7731

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

24-Lead P lastic D IP

(N-24)

1.275 (32.30)

1.125 (28.60)

24

1

13

0.280 (7.11)

0.240 (6.10)

12

0.325 (8.25)

0.300 (7.62)

0.195 (4.95)

0.115 (2.93)

PIN 1

0.060 (1.52)

0.015 (0.38)

0.210

(5.33)

MAX

0.150

(3.81)

MIN

0.200 (5.05)

0.125 (3.18)

0.015 (0.381)

0.008 (0.204)

0.100 (2.54)

BSC

0.022 (0.558)

0.014 (0.356)

0.070 (1.77) SEATING

PLANE

0.045 (1.15)

24-Lead Wide Body (SO IC)

(R-24)

0.6141 (15.60)

0.5985 (15.20)

24

13

12

1

PIN 1

0.1043 (2.65)

0.0926 (2.35)

0.0291 (0.74)

x 45°

0.0098 (0.25)

0.0500 (1.27)

0.0157 (0.40)

8°

0°

0.0500

(1.27)

BSC

0.0192 (0.49)

0.0138 (0.35)

0.0118 (0.30)

0.0040 (0.10)

SEATING

PLANE

0.0125 (0.32)

0.0091 (0.23)

24-Lead Thin Shrink Sm all O utline (TSSO P )

(RU-24)

0.311 (7.90)

0.303 (7.70)

24

13

12

1

0.006 (0.15)

0.002 (0.05)

PIN 1

0.0433

(1.10)

MAX

0.028 (0.70)

0.020 (0.50)

8°

0°

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

SEATING

PLANE

0.0079 (0.20)

0.0035 (0.090)

–44–

REV. 0


型号：	EVAL-AD7731EB
厂家：	ADI
描述：	Low Noise, High Throughput 24-Bit Sigma-Delta ADC 低噪声，高吞吐量的24位Σ-Δ型ADC
文件：	总44页 (文件大小：412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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