EVAL-AD7761FMCZ [ADI]
8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW;
| 型号： | EVAL-AD7761FMCZ |
| 厂家： | 
ADI |
| 描述： | 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW |
| 文件： | 总76页 (文件大小：1516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Channel, 16-Bit, Simultaneous Sampling
ADC with Power Scaling, 110.8 kHz BW
AD7761
Data Sheet
Linear phase digital filter
FEATURES
Low latency sinc5 filter
Precision ac and dc performance
8-channel simultaneous sampling
256 kSPS ADC ODR per channel
97.7 dB dynamic range
110.8 kHz input bandwidth (−3 dB BW)
−120 dB THD, typical
Wideband brick wall filter: 0.005 dB ripple to 102.4 kHz
Analog input precharge buffers
Power supply
AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V
IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V
64-lead LQFP package, no exposed pad
1 LSB INL, 1 LSB offset error, 5 LSB gain error
Optimized power dissipation vs. noise vs. input bandwidth
Selectable power, speed, and input bandwidth
Fast (highest speed): 110.8 kHz BW, 51.5 mW per channel
Median (half speed): 55.4 kHz BW, 27.5 mW per channel
Low power (lowest power): 13.8 kHz BW, 9.375 mW per
channel
Temperature range: −40°C to +105°C
APPLICATIONS
Data acquisition systems: USB/PXI/Ethernet
Instrumentation and industrial control loops
Audio testing and measurement
Vibration and asset condition monitoring
3-phase power quality analysis
Input BW range: dc to 110.8 kHz
Programmable input bandwidth/sampling rates
CRC error checking on data interface
Sonar
High precision medical electroencephalogram (EEG)/
electromyography (EMG)/electrocardiogram (ECG)
Daisy-chaining
FUNCTIONAL BLOCK DIAGRAM
AVDD1A,
AVDD1B
AVDD2A, REGCAPA,
REFx+ REFx–
AVDD2B REGCAPB DGND
IOVDD
DREGCAP
BUFFERED
VCM
1.8V
LDO
1.8V
LDO
PRECHARGE
REFERENCE
BUFFERS
VCM
×8
VCM
SYNC_IN
SYNC_OUT
START
AIN0+
AIN0–
AIN1+
AIN1–
P
P
P
P
P
P
OFFSET,
Σ-Δ
RESET
DIGITAL
FILTER
ENGINE
CH 0
GAIN PHASE
CORRECTION
ADC
FORMAT1
FORMAT0
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
CH 1
ADC
OUTPUT
DATA
DRDY
SINC5
LOW LATENCY
FILTER
AIN2+
AIN2–
DCLK
SERIAL
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
CH 2
INTERFACE
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
AIN3+
AIN3–
AIN4+
AIN4–
P
P
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
CH 3
CH 4
CH 5
WIDEBAND
LOW RIPPLE
FILTER
P
P
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
AIN5+
AIN5–
P
P
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
ST0/CS
SPI
ST1/SCLK
DEC0/SDO
DEC1/SDI
CONTROL
INTERFACE
P
P
AIN6+
AIN6–
OFFSET,
Σ-Δ
CH 6
CH 7
GAIN PHASE
CORRECTION
ADC
AIN7+
AIN7–
P
P
OFFSET,
GAIN PHASE
CORRECTION
Σ-Δ
ADC
PIN/SPI
×16 ANALOG INPUT
PRECHARGE BUFFERS (P)
AD7761
AVSS
XTAL2/MCLK XTAL1
MODE3/GPIO3 FILTER/GPIO4
TO
MODE0/GPIO0
Figure 1.
Rev. A
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DESIGN RESOURCES
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EVALUATION KITS
• AD7761 Evaluation Board
DOCUMENTATION
Data Sheet
DISCUSSIONS
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• AD7761: 8-Channel, 16-Bit, Simultaneous Sampling ADC
with Power Scaling, 110.8 kHz BW Data Sheet
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• UG-949: Evaluation Board for the AD7761 16-Bit, 8-
Channel, Simultaneous Sampling, 256 kSPS, Sigma-Delta
ADC with Power Scaling
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AD7761
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Setting the Format of Data Output .......................................... 49
ADC Conversion Output: Header and Data .......................... 50
Functionality ................................................................................... 59
GPIO Functionality.................................................................... 59
Register Map Details (SPI Control) ............................................. 60
Register Map ............................................................................... 60
Channel Standby Register ......................................................... 62
Channel Mode A Register......................................................... 63
Channel Mode B Register ......................................................... 63
Channel Mode Select Register.................................................. 64
Power Mode Select Register...................................................... 64
General Device Configuration Register.................................. 65
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Specifications..................................................................................... 5
Timing Specifications ................................................................ 10
1.8 V IOVDD Timing Specifications....................................... 11
Absolute Maximum Ratings.......................................................... 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 20
Terminology .................................................................................... 26
Theory of Operation ...................................................................... 27
Clocking, Sampling Tree, and Power Scaling ............................. 27
Noise Performance and Resolution.......................................... 28
Applications Information .............................................................. 30
Power Supplies ............................................................................ 31
Device Configuration ................................................................ 32
Pin Control Mode....................................................................... 32
SPI Control.................................................................................. 35
SPI Control Functionality ......................................................... 36
SPI Control Mode Extra Diagnostic Features ........................ 38
Circuit Information........................................................................ 39
Core Signal Chain....................................................................... 39
Analog Inputs.............................................................................. 40
VCM............................................................................................. 41
Reference Input........................................................................... 42
Clock Selection ........................................................................... 42
Digital Filtering........................................................................... 42
Decimation Rate Control .......................................................... 46
Antialiasing ................................................................................. 46
Calibration................................................................................... 48
Data Interface.................................................................................. 49
Data Control: Soft Reset, Sync, and Single-Shot Control
Register ........................................................................................ 66
Interface Configuration Register.............................................. 66
Digital Filter RAM Built in Self Test (BIST) Register............ 67
Status Register............................................................................. 67
Revision Identification Register ............................................... 68
GPIO Control Register .............................................................. 68
GPIO Write Data Register......................................................... 69
GPIO Read Data Register.......................................................... 69
Analog Input Precharge Buffer Enable Register Channel 0 to
Channel 3 .................................................................................... 69
Analog Input Precharge Buffer Enable Register Channel 4 to
Channel 7 .................................................................................... 70
Positive Reference Precharge Buffer Enable Register............ 70
Negative Reference Precharge Buffer Enable Register .......... 71
Offset Registers........................................................................... 71
Gain Registers............................................................................. 72
Sync Phase Offset Registers ...................................................... 72
ADC Diagnostic Receive Select Register ................................ 72
ADC Diagnostic Control Register ........................................... 73
Modulator Delay Control Register........................................... 74
Chopping Control Register....................................................... 74
Outline Dimensions....................................................................... 75
Ordering Guide .......................................................................... 75
Rev. A | Page 2 of 75
Data Sheet
AD7761
REVISION HISTORY
9/2017—Rev. 0 to Rev. A
Moved Table 26................................................................................45
Changes to Modulator Saturation Point Section ........................47
Added Figure 68..............................................................................47
Changes to Bit 7 Bit Name, Table 31, and ERROR_FLAGGED
Section ..............................................................................................50
Changes to Data Interface: One-Shot Conversion Operation
Section ..............................................................................................53
Changes to CRC Check on Data Interface Section ....................55
Added CRC Code Example Section .............................................56
Change to Register 0x05, Bit 6, Table 33......................................60
Changes to Table 39 ........................................................................65
Changes to Analog Input Precharge Buffer Enable Register
Channel 0 to Channel 3 Section....................................................69
Changes to Analog Input Precharge Buffer Enable Register
Channel 4 to Channel 7 Section....................................................70
Changed Focus Mode to Low Power Mode............... Throughout
Changes to Table 1 ............................................................................5
Changes to Figure 2.........................................................................13
Changes to Thermal Resistance Section and Table 7 .................15
Changes to Table 8 ..........................................................................16
Changes to Figure 47 ......................................................................27
Changes to Figure 48 ......................................................................30
Changes to MCLK Source Selection Section...............................37
Changes to Analog Input Precharge Buffers Section .................38
Changes to Analog Inputs Section................................................40
Added Figure 61; Renumbered Sequentially...............................41
Changes to Table 24 ........................................................................41
Changes to Reference Input Section.............................................42
Added Figure 62 ..............................................................................42
Added Filter Settling Time Section...............................................43
Changes to Wideband Low Ripple Filter Section .......................43
Moved Table 25................................................................................44
4/2016—Revision 0: Initial Version
Rev. A | Page 3 of 75
AD7761
Data Sheet
GENERAL DESCRIPTION
The AD7761 is an 8-channel, simultaneous sampling sigma-delta
(Σ-Δ) analog-to-digital converter (ADC) with a Σ-Δ modulator
and digital filter per channel, enabling synchronized sampling of ac
and dc signals.
The wideband and sinc5 filters can be selected and run on a per
channel basis.
Within these filter options, the user can improve the dynamic
range by selecting from decimation rates of ×32, ×64, ×128,
×256, ×512, and ×1024. The ability to vary the decimation
filtering optimizes noise performance to the required input
bandwidth.
The AD7761 achieves 97.7 dB dynamic range at a maximum
input bandwidth of 110.8 kHz, combined with typical performance
of 1 LSB integral nonlinearity (INL), 1 LSB offset error, and
5 LSB gain error.
Embedded analog functionality on each ADC channel makes
design easier, such as a precharge buffer on each analog input
that reduces analog input current and a precharge reference
buffer per channel reduces input current and glitches on the
reference input terminals.
The AD7761 user can trade off input bandwidth, output data rate,
and power dissipation. Select one of three power modes to optimize
the device for noise targets and power consumption. The
flexibility of the AD7761 allows it to become a reusable platform
for low power dc and high performance ac measurement
modules.
The device operates with a 5 V AVDD1A and AVDD1B supply,
a 2.25 V to 5.0 V AVDD2A and AVDD2B supply, and a 2.5 V to
3.3 V or 1.8 V IOVDD supply (see the 1.8 V IOVDD Operation
section for specific requirements for operating at 1.8 V IOVDD).
The AD7761 has three modes: fast mode (256 kSPS maximum,
110.8 kHz input bandwidth, 51.5 mW per channel), median
mode (128 kSPS maximum, 55.4 kHz input bandwidth, 27.5 mW
per channel) and low power mode (32 kSPS maximum, 13.8 kHz
input bandwidth, 9.375 mW per channel).
The device requires an external reference; the absolute input
reference voltage range is 1 V to AVDD1 − AVSS.
For the purposes of clarity within this data sheet, the AVDD1A
and AVDD1B supplies are referred to as AVDD1 and the AVDD2A
and AVDD2B supplies are referred to as AVDD2. For the
negative supplies, AVSS refers to the AVSS1A, AVSS1B,
AVSS2A, AVSS2B, and AVSS pins.
The AD7761 offers extensive digital filtering capabilities, such as
a wideband, low 0.005 dB pass-band ripple, antialiasing low-
pass filter with sharp roll-off, and 105 dB attenuation at the
Nyquist frequency.
Frequency domain measurements can use the wideband linear
phase filter. This filter has a flat pass band ( 0.005 dB ripple)
from dc to 102.4 kHz at 256 kSPS, from dc to 51.2 kHz at
128 kSPS, or from dc to 12.8 kHz at 32 kSPS.
The specified operating temperature range is −40°C to +105°C.
The device is housed in a 10 mm × 10 mm 64-lead LQFP package
with a 12 mm × 12 mm printed circuit board (PCB) footprint.
Throughout this data sheet, multifunction pins, such as
XTAL2/MCLK, are referred to either by the entire pin name or
by a single function of the pin, for example MCLK, when only
that function is relevant.
The AD7761 also offers sinc response via a sinc5 filter, a low
latency path for low bandwidth, and low noise measurements.
Rev. A | Page 4 of 75
Data Sheet
AD7761
SPECIFICATIONS
AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V and 2.25 V to 3.6 V, AVSS =
DGND = 0 V, REFx+ = 4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers
off, wideband filter, fCHOP = fMOD/32, TA = −40°C to +105°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR), per
Channel1
Fast
8
256
kSPS
Median
Low power
Fast, wideband filter
Median, wideband filter
Low power, wideband filter
4
1
128
32
110.8
55.4
13.8
kSPS
kSPS
kHz
kHz
kHz
−3 dB Bandwidth (BW)
Data Output Coding
No Missing Codes2
Twos complement, MSB first
16
Bits
dB
DYNAMIC PERFORMANCE
Decimation by 32, 256 kSPS ODR
Shorted input, wideband filter
1 kHz, −0.5 dBFS, sine wave input
Sinc5 filter
Wideband filter
1 kHz, −0.5 dBFS, sine wave input
Dynamic Range
Signal-to-Noise Ratio (SNR)
97.3
97.7
97.3
97.3
97.3
97.9
97.7
97.7
dB
dB
dB
Signal-to-Noise-and-Distortion
Ratio (SINAD)
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
1 kHz, −0.5 dBFS, sine wave input
−120
126
−107
dB
dBc
INTERMODULATON DISTORTION (IMD) fINA = 9.7 kHz, fINB = 10.3 kHz
Second order
Third order
−125
−124
dB
dB
ACCURACY
INL3
Offset Error4
Gain Error4
Endpoint method
TA = 25°C
1
1
5
0.01
1.5
2
40
LSB
LSB
LSB
LSB/°C
Gain Drift vs. Temperature2
0.02
VCM PIN
Output
With respect to AVSS
∆VOUT/∆IL
Applies to the following VCM output
options only: VCM = ∆VOUT/∆(AVDD1 −
AVSS)/2, VCM = 1.65 V, and VCM = 2.5 V
(AVDD1 −
AVSS)/2
400
5
V
Load Regulation
Voltage Regulation
µV/mA
µV/V
Short-Circuit Current
ANALOG INPUTS
Differential Input Voltage Range
Input Common-Mode Range2
Absolute Analog Input Voltage Limits2
Analog Input Current
30
mA
See the Analog Inputs section
VREF = (REFx+) − (REFx−)
−VREF
AVSS
AVSS
+VREF
AVDD1
AVDD1
V
V
V
Unbuffered
Differential component
Common-mode component
48
17
−20
µA/V
µA/V
µA
Precharge Buffer On5
Input Current Drift
Unbuffered
5
31
nA/V/°C
nA/°C
Precharge Buffer On
Rev. A | Page 5 of 75
AD7761
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
EXTERNAL REFERENCE
Reference Voltage
Absolute Reference Voltage Limits2
VREF = (REFx+) − (REFx−)
Precharge reference buffers off
1
AVDD1 − AVSS
AVDD1 + 0.05
V
V
AVSS −
0.05
Precharge reference buffers on
Fast mode
AVSS
AVDD1
V
Average Reference Current
Precharge reference buffers off
Precharge reference buffers on
Fast mode
72
16
µA/V/channel
µA/V/channel
Average Reference Current Drift
Precharge reference buffers off
Precharge reference buffers on
1.7
49
95
nA/V/°C
nA/V/°C
dB
Common-Mode Rejection
DIGITAL FILTER RESPONSE
Low Ripple Wideband Filter
Decimation Rate
FILTER = 0
Up to six selectable decimation rates
Latency
32
1024
Group Delay
Settling Time
Pass-Band Ripple2
34/ODR
68/ODR
sec
sec
dB
Hz
Hz
Hz
Hz
dB
Complete settling
0.005
Pass Band
0.005 dB bandwidth
−0.1 dB bandwidth
−3 dB bandwidth
0.4 × ODR
0.409 × ODR
0.433 × ODR
0.499 × ODR
105
Stop Band Frequency
Stop Band Attenuation
Sinc5 Filter
Attenuation > 105 dB
FILTER = 1
Decimation Rate
Group Delay
Settling Time
Up to six selectable decimation rates
Latency
Complete settling
−3 dB bandwidth
32
1024
3/ODR
7/ODR
0.204 × ODR
sec
sec
Hz
Pass Band
REJECTION
AC Power Supply Rejection Ratio
(PSRR)
VIN = 0.1 V, AVDD1 = 5 V, AVDD2 =
5 V, IOVDD = 2.5 V
AVDD1
AVDD2
IOVDD
90
100
75
dB
dB
dB
DC PSRR
AVDD1
AVDD2
IOVDD
VIN = 1 V
100
118
90
dB
dB
dB
Analog Input Common-Mode
Rejection Ratio (CMRR)
DC
AC
Crosstalk
CLOCK
VIN = 0.1 V
Up to 10 kHz
−0.5 dBFS input on adjacent channels
95
95
−120
dB
dB
dB
See the Clock Selection section for
data sheet performance functionality
Crystal Frequency
External Clock (MCLK)
Duty Cycle
8
32.768
32.768
50:50
34
MHz
MHz
%
MCLK Pulse Width2
Logic Low
Logic High
12.2
12.2
ns
ns
CMOS Clock Input Voltage
High, VINH
See the Logic Inputs parameter
Low, VINL
Rev. A | Page 6 of 75
Data Sheet
AD7761
Parameter
LVDS Clock2
Test Conditions/Comments
Min
Typ
Max
Unit
RL = 100 Ω
Differential Input Voltage
Common-Mode Input Voltage
Absolute Input Voltage
100
800
650
1575
1.88
mV
mV
V
ADC RESET2
ADC Start-Up Time After Reset6
Time to first DRDY, fast mode,
decimation by 32
1.58
1.66
ms
Minimum RESET Low Pulse Width
tMCLK = 1/MCLK
2 × tMCLK
LOGIC INPUTS
Input Voltage2
High, VINH
0.65 ×
V
IOVDD
Low, VINL
2.25 V < IOVDD < 3.6 V
1.72 V < IOVDD < 1.88 V
2.25 V < IOVDD < 3.6 V
1.72 V < IOVDD < 1.88 V
0.7
0.4
0.09
0.2
+10
+10
V
V
V
V
µA
µA
Hysteresis2
0.04
0.04
−10
−10
Leakage Current
+0.03
RESET pin7
LOGIC OUTPUTS
Output Voltage2
High, VOH
ISOURCE = 200 μA
0.8 ×
V
IOVDD
Low, VOL
Leakage Current
Output Capacitance
SYSTEM CALIBRATION2
Full-Scale Calibration Limit
Zero-Scale Calibration Limit
ISINK = 400 µA
Floating state
Floating state
0.4
+10
V
µA
pF
−10
10
1.05 × VREF
2.1 × VREF
V
V
−1.05 ×
VREF
0.4 × VREF
Input Span
V
POWER REQUIREMENTS
Power Supply Voltage
AVDD1 − AVSS
4.5
2.0
−2.75
1.72
5.0
2.25 to 5.0
5.5
5.5
0
V
V
V
V
AVDD2 − AVSS
AVSS − DGND
IOVDD − DGND
2.5 to 3.3
or 1.8
3.6
POWER SUPPLY CURRENTS
Maximum output data rate, CMOS
MCLK, eight DOUTx signals, all
supplies at maximum voltages, all
channels in Channel Mode A
Eight Channels Active
Fast Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
36
40
64
40
69
29
mA
mA
mA
mA
mA
57.5
37.5
63
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter2
27
Median Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
18.5
29
21.3
34
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
16
Rev. A | Page 7 of 75
AD7761
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Low Power Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
5.1
8
9.3
12.5
8
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
Four Channels Active2
Fast Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
18.2
28.8
18.8
43.5
17
20.3
32.5
20.3
47.7
18.6
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
Median Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
9.3
mA
mA
mA
mA
mA
14.7
10.7
24.5
11
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
Low Power Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
2.7
4.1
4.7
10
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
6.5
Two Channels Active2
Fast Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
9.3
14.7
9.5
34
10.5
16.6
10.5
36.7
13.5
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
12
Median Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
4.8
7.5
5.5
19.5
8.5
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
Low Power Mode
AVDD1 Current
Precharge reference buffers off
Precharge reference buffers on
1.52
2.2
2.4
8.6
5.8
6.5
mA
mA
mA
mA
mA
mA
AVDD2 Current
IOVDD Current
Wideband filter
Sinc5 filter
All channels disabled (sinc5 filter
enabled)
Standby Mode
8
Sleep Mode
Full power-down (serial peripheral
interface (SPI) mode only)
Extra current in IOVDD when using
an external crystal compared to
using the CMOS MCLK
0.73
540
1.2
mA
µA
Crystal Excitation Current
Rev. A | Page 8 of 75
Data Sheet
AD7761
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER DISSIPATION
External CMOS MCLK, all channels
active, MCLK = 32.768 MHz, all
channels in Channel Mode A
Full Operating Mode
Wideband Filter
Fast
Analog precharge buffers on
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off2
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on2
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 3.6 V, precharge reference
buffers off
412
600
631
446
645
681
mW
mW
mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V, precharge
reference buffers off2
524
571
mW
Median
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 3.6 V, precharge reference
buffers off
220
320
341
mW
mW
mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V, precharge
reference buffers off
284
mW
Low Power
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 3.6 V, precharge reference
buffers off
75
mW
mW
mW
107
124
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V, precharge
reference buffers off
99
mW
Sinc5 Filter2
Fast
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 3.6 V, precharge reference
buffers off
325
475
501
355
525
545
mW
mW
mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V, precharge
reference buffers off
455
495
mW
Median
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 3.6 V, precharge reference
buffers off
175
260
277
mW
mW
mW
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V, precharge
reference buffers off
248
mW
Rev. A | Page 9 of 75
AD7761
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Low Power
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V,
precharge reference buffers off
65
mW
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V,
precharge reference buffers on
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 3.6 V, precharge reference
buffers off
95
mW
mW
108
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V, precharge
reference buffers off
All channels disabled; AVDD1 = 5 V,
AVDD2 = IOVDD = 2.5 V
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V
AVDD1 = AVDD2 = 5.5 V, IOVDD =
3.6 V
94
mW
mW
Standby Mode
14.5
21
23.5
mW
mW
29
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V
Full power-down (SPI mode only);
AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V
AVDD1 = 5 V, AVDD2 = IOVDD = 3.3 V
AVDD1 = AVDD2 = 5.5 V, IOVDD =
3.6 V
12.5
mW
mW
Sleep Mode
1.8
2.5
2.7
mW
mW
6.5
AVDD1 = 5.5 V, AVDD2 = 5.5 V,
IOVDD = 1.88 V
1.5
mW
1 The output data rate ranges refer to the programmable decimation rates available on the AD7761 for a fixed MCLK rate of 32.768 MHz. Varying MCLK rates allow users
a wider variation of ODR.
2 These specifications are not production tested but are supported by characterization data at initial product release.
3 The maximum INL specification is guaranteed by design and characterization testing prior to release. This specification is not production tested.
4 Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale calibration
reduces the gain error to the order of the noise for the programmed output data rate.
5 −25 μA is measured when the analog input is close to either the AVDD1 or AVSS rail. The input current reduces as the common-mode voltage approaches (AVDD1 −
AVSS)/2. The analog input current scales with the MCLK frequency and device power mode.
For lower MCLK rates or higher decimation rates, use Table 25 and Table 26 to calculate any additional delay before the first
6
DRDY
pulse.
7
RESET
The
pin has an internal pull-up device to IOVDD.
TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 2.25 V to 3.6 V, Input Logic 0 = DGND, Input Logic 1 = IOVDD;
CLOAD = 10 pF on the DCLK pin, CLOAD = 20 pF on the other digital outputs; REFx+ = 4.096 V, TA = −40°C to +105°C. See Table 4 and
Table 5 for timing specifications at 1.8 V IOVDD.
Table 2. Data Interface Timing1
Parameter Description
Test Conditions/Comments
Min
Typ
Max
Unit
MHz
Hz
Hz
Hz
ns
MCLK
fMOD
Master clock
Modulator frequency
1.15
34
Fast mode
Median mode
Low power mode
MCLK/4
MCLK/8
MCLK/32
28
t1
t2
t3
t4
t5
t6
t7
t8
DRDY high time
tDCLK = t8 + t9
tDCLK − 10%
−3.5
DCLK rising edge to DRDY rising edge
DCLK rising to DRDY falling
DCLK rise to DOUTx valid
DCLK rise to DOUTx invalid
DOUTx valid to DCLK falling
DCLK falling edge to DOUTx invalid
DCLK high time, DCLK = MCLK/1
t8a = DCLK = MCLK/2
2
ns
0
ns
1.5
ns
ns
ns
ns
ns
ns
−3
9.5
9.5
tDCLK/2
tDCLK/2
tDCLK/2
tDCLK/2
tMCLK
50:50 CMOS clock
tMCLK = 1/MCLK
(tDCLK/2) + 5
t8b = DCLK = MCLK/4
t8c = DCLK = MCLK/8
2 × tMCLK
4 × tMCLK
ns
ns
Rev. A | Page 10 of 75
Data Sheet
AD7761
Parameter Description
Test Conditions/Comments
Min
Typ
Max
Unit
ns
ns
t9
DCLK low time DCLK = MCLK/1
50:50 CMOS clock
(tDCLK/2) − 5
tMCLK/2
tMCLK
tDCLK/2
t9a = DCLK = MCLK/2
t9b = DCLK = MCLK/4
t9c = DCLK = MCLK/8
2 × tMCLK
4 × tMCLK
ns
ns
t10
t11
t12
t13
t14
MCLK rising to DCLK rising
Setup time of DOUT6 and DOUT7
Hold time of DOUT6 and DOUT7
START low time
CMOS clock
CMOS clock
30
ns
ns
ns
ns
14
0
1 × tMCLK
MCLK to SYNC_OUT valid
SYNC_OUT RETIME_EN bit
disabled; measured from
falling edge of MCLK
SYNC_OUT RETIME_EN bit
enabled; measured from
rising edge of MCLK
4.5
9.5
22
ns
ns
27.5
t15
t16
SYNC_IN setup time
SYNC_IN hold time
CMOS clock
CMOS clock
0
ns
ns
10
1 These specifications are not production tested but are supported by characterization data at initial product release.
Table 3. SPI Control Interface Timing1
Parameter
Description
Test Conditions/Comments
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
SCLK period
100
26.5
27
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
CS falling edge to data output enable
SCLK high time
22.5
20
20
40.5
15
50
50
SCLK low time
SCLK falling edge to SDO valid
SDO hold time after SCLK falling
SDI setup time
SDI hold time
SCLK enable time
7
0
6
0
0
10
SCLK disable time
CS high time
CS low time
f
MOD = MCLK/4
1.1 × tMCLK
2.2 × tMCLK
8.8 × tMCLK
fMOD = MCLK/8
fMOD = MCLK/32
1 These specifications are not production tested but are supported by characterization data at initial product release.
1.8 V IOVDD TIMING SPECIFICATIONS
AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 =
DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C.
Table 4. Data Interface Timing1
Parameter Description
Test Conditions/Comments
Min
Typ
Max
Unit
MHz
Hz
Hz
Hz
MCLK
fMOD
Master clock
Modulator frequency
1.15
34
Fast mode
Median mode
Low power mode
MCLK/4
MCLK/8
MCLK/32
28
t1
t2
t3
DRDY high time
t
DCLK − 10%
ns
DCLK rising edge to DRDY rising edge
DCLK rising to DRDY falling
2
0
ns
−4.5
ns
Rev. A | Page 11 of 75
AD7761
Data Sheet
Parameter Description
Test Conditions/Comments
Min
Typ
Max
Unit
ns
ns
ns
ns
t4
t5
t6
t7
t8
DCLK rise to DOUTx valid
2.0
DCLK rise to DOUTx invalid
DOUTx valid to DCLK falling
DCLK falling edge to DOUTx invalid
DCLK high time, DCLK = MCLK/1
t8a = DCLK = MCLK/2
−4
8.5
8.5
tDCLK/2
tDCLK/2
tDCLK/2
tDCLK/2
tMCLK
2 × tMCLK
4 × tMCLK
50:50 CMOS clock
50:50 CMOS clock
CMOS clock
(tDCLK/2) + 5 ns
ns
ns
ns
t8b = DCLK = MCLK/4
t8c = DCLK = MCLK/8
t9
DCLK low time DCLK = MCLK/1
t9a = DCLK = MCLK/2
(tDCLK/2) − 5 tMCLK/2
tMCLK
tDCLK/2
ns
ns
ns
ns
ns
ns
ns
ns
t9b = DCLK = MCLK/4
t9c = DCLK = MCLK/8
2 × tMCLK
4 × tMCLK
t10
t11
t12
t13
t14
MCLK rising to DCLK rising
Setup time DOUT6 and DOUT7
Hold time DOUT6 and DOUT7
START low time
37
14
0
1 × tMCLK
MCLK to SYNC_OUT valid
CMOS clock
SYNC_OUT RETIME_EN bit
disabled; measured from
falling edge of MCLK
SYNC_OUT RETIME_EN bit
enabled; measured from
rising edge of MCLK
10
15
31
37
ns
ns
t15
t16
SYNC_IN setup time
SYNC_IN hold time
CMOS clock
CMOS clock
0
ns
ns
11
1 These specifications are not production tested but are supported by characterization data at initial product release.
Table 5. SPI Control Interface Timing1
Parameter
Description
Test Conditions/Comments
Min
100
31.5
30
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
SCLK period
CS falling edge to SCLK rising edge
SCLK falling edge to CS rising edge
CS falling edge to data output enable
SCLK high time
29
54
16
20
20
50
50
SCLK low time
SCLK falling edge to SDO valid
SDO hold time after SCLK falling
SDI setup time
SDI hold time
SCLK enable time
7
0
10
0
0
10
SCLK disable time
CS high time
CS low time
f
MOD = MCLK/4
1.1 × tMCLK
2.2 × tMCLK
8.8 × tMCLK
fMOD = MCLK/8
fMOD = MCLK/32
1 These specifications are not production tested but are supported by characterization data at initial product release.
Rev. A | Page 12 of 75
Data Sheet
AD7761
Timing Diagrams
t1
DRDY
tODR = 1/ODR
t2
t8
DCLK
t9
t5
t3
t4
t6
DOUTx
D23
t7
Figure 2. Data Interface Timing Diagram
MCLK
t10
t8a
DCLK = MCLK/2
DCLK = MCLK/4
DCLK = MCLK/8
t9a
t8b
t9b
t8c
t9c
Figure 3. MCLK to DCLK Divider Timing Diagram
tODR
DRDY
DCLK
t11
DOUT6
AND
DOUT7
t12
Figure 4. Daisy-Chain Setup and Hold Timing Diagram
MCLK
START
t14
t13
SYNC_OUT
START
SYNC_OUT
Timing Diagram
Figure 5. Asynchronous
and
Rev. A | Page 13 of 75
AD7761
Data Sheet
MCLK
SYNC_IN
t15
t16
t15
SYNC_IN
Figure 6. Synchronous
Pulse Timing Diagram
t30
CS
t18
t19
t17
t21
SCLK
SDO
t22
MSB
t20
t23
t24
Figure 7. SPI Serial Read Timing Diagram
t30
CS
t18
SCLK
t25
t26
SDI
MSB
LSB
Figure 8. SPI Serial Write Timing Diagram
t29
CS
SCLK
t28
t27
Figure 9. SCLK Enable and Disable Timing Diagram
Rev. A | Page 14 of 75
Data Sheet
AD7761
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Table 6.
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
AVDD1, AVDD2 to AVSS1
AVDD1 to DGND
IOVDD to DGND
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
IOVDD, DREGCAP to DGND (IOVDD Tied −0.3 V to +2.25 V
to DREGCAP for 1.8 V Operation)
IOVDD to AVSS
AVSS to DGND
−0.3 V to +7.5 V
THERMAL RESISTANCE
−3.25 V to +0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Analog Input Voltage to AVSS
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Storage Temperature Range
Table 7. Thermal Resistance
Package Type
θJA θJC
Unit
JEDEC Board Layers
ST-64-2
38 9.2 °C/W
2P2S1
Pb-Free Temperature, Soldering
Reflow (10 sec to 30 sec)
260°C
1 2P2S is a JEDEC standard PCB configuration per JEDEC Standard JESD51-7.
Maximum Junction Temperature
Maximum Package Classification
Temperature
150°C
260°C
ESD CAUTION
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) latch-up.
Rev. A | Page 15 of 75
AD7761
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AIN1–
AIN5–
2
3
AIN1+
AVSS1A
AIN5+
AVSS1B
AVDD1B
REF2–
4
AVDD1A
5
REF1–
6
REF1+
REF2+
7
AIN2–
AIN6–
AD7761
TOP VIEW
(Not to Scale)
8
AIN6+
AIN2+
9
AIN3–
AIN7–
10
11
12
13
14
15
16
AIN3+
AIN7+
FILTER/GPIO4
MODE0/GPIO0
MODE1/GPIO1
MODE2/GPIO2
MODE3/GPIO3
ST0/CS
SYNC_OUT
START
SYNC_IN
IOVDD
DREGCAP
DGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 10. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic
Type1
Description
1
2
3
4
5
AIN1−
AIN1+
AVSS1A
AVDD1A
REF1−
AI
AI
P
P
AI
Negative Analog Input to ADC Channel 1.
Positive Analog Input to ADC Channel 1.
Negative Analog Supply. This pin is nominally 0 V.
Analog Supply Voltage, 5 V 10% with Respect to AVSS.
Reference Input Negative. REF1− is the negative reference terminal for Channel 0 to Channel 3. The
REF1− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality
capacitor, and maintain a low impedance between this capacitor and Pin 3.
6
REF1+
AI
Reference Input Positive. REF1+ is the positive reference terminal for Channel 0 to Channel 3.
The REF1+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external reference differential
between REF1+ and REF1− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to AVSS
with a high quality capacitor, and maintain a low impedance between this capacitor and Pin 3.
7
AIN2−
AI
Negative Analog Input to ADC Channel 2.
8
AIN2+
AI
Positive Analog Input to ADC Channel 2.
9
AIN3−
AI
Negative Analog Input to ADC Channel 3.
10
11
AIN3+
FILTER/GPIO4
AI
DI/O
Positive Analog Input to ADC Channel 3.
Filter Select/General-Purpose Input/Output 4. In pin control mode, this pin selects the filter type.
Set this pin to Logic 1 for the sinc5 filter. This sinc5 filter is a low latency filter, and is best for dc
applications or when a user has specialized postfiltering implemented off chip.
Set this pin to Logic 0 for the wideband low ripple filter response. This filter has a steep
transition band and 105 dB stop band attenuation. Full attenuation at Nyquist (ODR/2) means
that no aliasing occurs at ODR/2 out to the first chopping zone.
In SPI control mode, this pin can be used as a general-purpose input/output (GPIO4). For further
information on GPIO configuration, see the GPIO Functionality section.
In SPI control mode, when not used as a GPIO pin, and when using a crystal as the clock source,
this pin must be set to 1.
Rev. A | Page 16 of 75
Data Sheet
AD7761
Pin No. Mnemonic
Type1
DI/DI/O Mode Selection/General-Purpose Input/Output Pin 0 to Pin 3.
Description
12, 13,
14, 15
MODE0/GPIO0,
MODE1/GPIO1,
MODE2/GPIO2,
MODE3/GPIO3
In pin control mode, the MODEx pins set the mode of operation for all ADC channels, controlling
power consumption, DCLK frequency, and the ADC conversion type, allowing one-shot
conversion operation.
In SPI control mode, the GPIOx pins, in addition to the FILTER/GPIO4 pin, form five general-
purpose input/output pins (GPIO4 to GPIO0).
16
17
ST0/CS
DI
DI
Standby 0/Chip Select Input.
In pin control mode, a Logic 1 places Channel 0 to Channel 3 into standby mode.
In SPI control mode, this pin is the active low chip select input to the SPI control interface.
Standby 1/Serial Clock Input.
ST1/SCLK
In pin control mode, a Logic 1 places Channel 4 to Channel 7 into standby mode.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into
standby mode, the crystal circuitry is also disabled for maximum power saving. Channel 4 must
be enabled while the external crystal is used on the AD7761.
In SPI control mode, this pin is the serial clock input pin for the SPI control interface.
Decimation Rate Control Input 1/Serial Data Input.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.
In SPI control mode, this pin is the serial data input pin used to write data to the AD7761
register bank.
Decimation Rate Control Input 0/Serial Data Output.
In pin control mode, the DEC0 and DEC1 pins configure the decimation rate for all ADC channels.
In SPI control mode, this pin is the serial data output pin, allowing readback from the AD7761
registers.
Conversion Data Output 7. This pin is synchronous to DCLK and framed by DRDY. This pin acts as
a digital input from a separate AD7761 device if configured in a synchronized multidevice daisy
chain when the FORMATx pins are configured as 01. To use the AD7761 in a daisy chain, hardwire the
FORMATx pins as either 01, 10, or 11, depending on the best interfacing format for the application.
When FORMATx is set to 10 or 11, connect this pin to ground through a pull-down resistor.
18
19
20
DEC1/SDI
DEC0/SDO
DOUT7
DI
DI/O
DI/O
21
DOUT6
DI/O
Conversion Data Output 6. This pin is synchronous to DCLK and framed by DRDY. This pin acts as
a digital input from a separate AD7761 device if configured in a synchronized multidevice daisy
chain. To use this pin in a daisy chain, hardwire the FORMATx pins as either 01, 10, or 11,
depending on the best interfacing format for the application.
22
23
24
25
26
27
28
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
DCLK
DO
DO
DO
DO
DO
DO
DO
Conversion Data Output 5. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 4. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 3. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 2. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 1. This pin is synchronous to DCLK and framed by DRDY.
Conversion Data Output 0. This pin is synchronous to DCLK and framed by DRDY
ADC Conversion Data Clock. This pin clocks conversion data out to the digital host, either digital
signal processing (DSP) or field programmable gate array (FPGA). This pin is synchronous
with DRDY and any conversion data output on DOUT0 to DOUT7 and is derived from the MCLK
signal. This pin is unrelated to the control SPI interface.
29
30
31
DRDY
RESET
XTAL1
DO
DI
Data Ready. Periodic signal output framing the conversion results from the eight ADCs. This pin
is synchronous to DCLK and DOUT0 to DOUT7.
Hardware Asynchronous Reset Input. After the device is fully powered up, it is recommended to
perform a hard or soft reset.
DI
Input 1 for Crystal or Connection to an LVDS Clock. When CLK_SEL is 0, connect XTAL1 to DGND.
In SPI control mode, when using a crystal source, the FILTER pin must be set to Logic 1 for
correct operation.
Rev. A | Page 17 of 75
AD7761
Data Sheet
Pin No. Mnemonic
Type1
Description
32
XTAL2/MCLK
DI
Input 2 for CMOS or Crystal/LVDS Sampling Clock. See the CLK_SEL pin for the details of this
configuration.
External crystal. XTAL2 is connected to the external crystal. In SPI control mode, when using a
crystal source, the FILTER pin must be set to Logic 1 for correct operation.
LVDS. A second LVDS input is connected to this pin.
CMOS clock. This pin operates as an MCLK input. CMOS input with logic level of IOVDD/DGND.
Set FILTER pin to Logic 1 for crystal clock source.
33
34
DGND
DREGCAP
P
AO
Digital Ground. This pin is nominally 0 V.
Digital Low Dropout (LDO) Regulator Output. Decouple this pin to DGND with a high quality,
low equivalent series resistance (ESR), 10 µF capacitor. For optimum performance, use a
decoupling capacitor with an ESR specification between 50 mΩ and 400 mΩ. This pin is not for
use in circuits external to the AD7761. For 1.8 V IOVDD operation, connect this pin to IOVDD via
an external trace to provide power to the digital processing core.
35
36
IOVDD
P
Digital Supply. This pin sets the logic levels for all interface pins. IOVDD also powers the digital
processing core via the digital LDO when IOVDD is at least 2.25 V. For 1.8 V IOVDD operation,
connect this pin to DREGCAP via an external trace to provide power to the digital processing core.
Synchronization Input. SYNC_IN receives the synchronous signal from SYNC_OUT. It is used in
the synchronization of any AD7761 that requires simultaneous sampling or is in a daisy chain.
Ignore the START and SYNC_OUT functions if the SYNC_IN pin is connected to the system
synchronization pulse. This signal pulse must be synchronous to the MCLK clock domain.
SYNC_IN
DI
37
38
START
DI
Start Signal. The START pulse synchronizes the AD7761 to other devices. The signal can be
asynchronous. The AD7761 samples the input and then outputs a SYNC_OUT pulse.
This SYNC_OUT pulse must be routed to the SYNC_IN pin of this device and any other AD7761
devices that must be synchronized together. This means that the user does not need to run the
ADCs and their digital host from the same clock domain, which is useful when there are long
traces or back planes between the ADC and the controller. If this pin is not used, it must be tied
to a Logic 1 through a pull-up resistor.
Synchronization Output. This pin operates only when using the START input. When using
the START input feature, the SYNC_OUT pin must be connected to SYNC_IN via an external
trace. SYNC_OUT is a digital output that is synchronous to the MCLK signal; the synchronization
signal driven in on START is internally synchronized to the MCLK signal and is driven out
on SYNC_OUT. SYNC_OUT can also be routed to other AD7761 devices requiring simultaneous
sampling and/or daisy-chaining, ensuring synchronization of devices related to the MCLK clock
domain. It must then be wired to drive the SYNC_IN pin on the same AD7761 and on the other
AD7761 devices.
SYNC_OUT
DO
39
40
41
42
43
AIN7+
AIN7−
AIN6+
AIN6−
REF2+
AI
AI
AI
AI
AI
Positive Analog Input to ADC Channel 7.
Negative Analog Input to ADC Channel 7.
Positive Analog Input to ADC Channel 6.
Negative Analog Input to ADC Channel 6.
Reference Input Positive. REF2+ is the positive reference terminal for Channel 4 to Channel 7.
The REF2+ voltage range is from (AVSS + 1 V) to AVDD1. Apply an external reference differential
between REF2+ and REF2− in the range from 1 V to |AVDD1 − AVSS|. Decouple this pin to AVSS
with a high quality capacitor, and maintain a low impedance between this capacitor and Pin 46.
44
REF2−
AI
Reference Input Negative. REF2− is the negative reference terminal for Channel 4 to Channel 7. The
REF2− voltage range is from AVSS to (AVDD1 − 1 V). Decouple this pin to AVSS with a high quality
capacitor, and maintain a low impedance between this capacitor and Pin 46.
45
46
47
48
49
50
51
52
53
54
AVDD1B
AVSS1B
AIN5+
AIN5−
AIN4+
P
P
Analog Supply Voltage. This pin is 5 V 10% with respect to AVSS.
Negative Analog Supply. This pin is nominally 0 V.
Positive Analog Input to ADC Channel 5.
Negative Analog Input to ADC Channel 5.
Positive Analog Input to ADC Channel 4.
AI
AI
AI
AI
P
AO
P
P
AIN4−
Negative Analog Input to ADC Channel 4.
AVSS2B
REGCAPB
AVDD2B
AVSS
Negative Analog Supply. This pin is nominally 0 V.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
Negative Analog Supply. This pin is nominally 0 V.
Rev. A | Page 18 of 75
Data Sheet
AD7761
Pin No. Mnemonic
Type1
Description
55, 56
FORMAT1,
FORMAT0
DI
Format Selection Pins. Hardwire the FORMATx pins to the required values in pin control and SPI
control mode. These pins set the number of DOUTx pins used to output ADC conversion data. The
FORMATx pins are checked by the AD7761 on power-up; the AD7761 then remains in this data
output configuration.
57
PIN/SPI
DI
Pin Control/SPI Control. This pin sets the control method.
Logic 0 = pin control mode for the AD7761. Pin control mode allows pin strapped configuration
of the AD7761 by tying logic input pins to the required logic levels. Tie the logic pins (MODE0 to
MODE4, DEC0 and DEC1, and FILTER) as required for the configuration.
Logic 1 = SPI control mode for the AD7761. Use the SPI control interface signals (CS, SCLK, SDI,
and SDO) for reading and writing to the AD7761 memory map.
Clock Select.
0 = pull this pin low for the CMOS clock option. The clock is applied to Pin 32 (connect Pin 31 to
DGND).
1 = pull this pin high for the crystal or LVDS clock option. The crystal or LVDS clock is applied to
Pin 31 and Pin 32. The LVDS option is available only in SPI control mode. A write is required to
enable the LVDS clock option.
Common-Mode Voltage Output. This pin outputs (AVDD1 − AVSS)/2, which is 2.5 V by default in
pin control mode. Configure this pin to (AVDD1 − AVSS)/2, 2.5 V, 2.14 V, or 1.65 V in SPI control
mode. When driving capacitive loads larger than 0.1 µF, it is recommended to place a 50 Ω series
resistor between this pin and the capacitive load for stability.
58
59
CLK_SEL
VCM
DI
AO
60
61
62
63
64
AVDD2A
REGCAPA
AVSS2A
AIN0−
P
AO
P
AI
AI
Analog Supply Voltage. This pin is 2 V to 5.5 V with respect to AVSS.
Analog LDO Regulator Output. Decouple this pin to AVSS with a 1 µF capacitor.
Negative Analog Supply. This pin is nominally 0 V.
Negative Analog Input to ADC Channel 0.
Positive Analog Input to ADC Channel 0.
AIN0+
1 AI is analog input, P is power, DI/O is digital input/output, DI is digital input, DO is digital output, and AO is analog output.
Rev. A | Page 19 of 75
AD7761
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 5 V, AVDD2 = 2.5 V, AVSS = 0 V, IOVDD = 2.5 V, VREF = 4.096 V, TA = 25°C, wideband filter, decimation = ×32, MCLK =
32.768 MHz, analog input precharge buffers on, precharge reference buffers off, unless otherwise noted.
0
0
SNR = 97.8dB
THD = –124.2dB
SNR = 97.7dB
THD = –123.8dB
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Fast Fourier Transform (FFT), Fast Mode, Wideband Filter,
−0.5 dBFS
Figure 14. FFT, Fast Mode, Sinc5 Filter, −0.5 dBFS
0
0
–20
SNR = 97.7dB
THD = –125.1dB
SNR = 97.9dB
THD = –125.1dB
–20
–40
–60
–40
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
10
100
1k
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. FFT, Median Mode, Wideband Filter, −0.5 dBFS
Figure 15. FFT, Median Mode, Sinc5 Filter, −0.5 dBFS
0
0
–20
SNR = 97.7dB
THD = –128.3dB
SNR = 97.9dB
THD = –128.3dB
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–200
–100
–120
–140
–160
–180
–200
1
10
100
1k
10k
1
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 13. FFT, Low Power Mode, Wideband Filter, −0.5 dBFS
Figure 16. FFT, Low Power Mode, Sinc5 Filter, −0.5 dBFS
Rev. A | Page 20 of 75
Data Sheet
AD7761
0
0
99
98
97
96
95
94
93
92
91
90
SNR = 97.9dB
THD = –119.9dB
–20
–40
SNR, FAST
–20
–40
–60
–80
–100
–120
–140
–60
–80
–100
–120
–140
–160
–180
–200
THD + N, FAST
THD, FAST
fIN = 1kHz
–160
40
0
5
10
15
20
25
30
35
5
50
500
FREQUENCY (Hz)
5000
MCLK FREQUENCY (MHz)
Figure 17. FFT One-Shot Mode, Sinc5 Filter, Median Mode,
Figure 20. SNR, THD, and THD + N vs. MCLK Frequency
SYNC_IN
Decimation = ×64, −0.5 dBFS,
Frequency = MCLK/4000
0
0
SECOND-ORDER IMD = –125.2dB
THIRD-ORDER IMD = –120.8 dB
–20
–40
–20
–40
–60
–80
–60
–100
–120
–140
–160
–180
–200
FAST
MEDIAN
FOCUS
–80
–100
–120
–140
10
100
1k
10k
100k
100
1k
10k
FREQUENCY (Hz)
100k
INPUT FREQUENCY (Hz)
Figure 21. THD vs. Input Frequency, Three Power Modes, Wideband Filter
Figure 18. IMD with Input Signals at 9.7 kHz and 10.3 kHz
0
–20
–40
–60
–80
0
fIN = 3.15kHz
INTERFERER (1kHz) ON ALL OTHER CHANNELS
–20
–40
–60
–80
–100
–120
–140
–160
–180
THD + N
–100
–120
THD
–140
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
0
1
2
3
4
5
6
7
CHANNEL
Figure 22. THD and THD + N vs. Input Amplitude, Wideband Filter, Fast Mode
Figure 19. Crosstalk
Rev. A | Page 21 of 75
AD7761
Data Sheet
1.0
35
30
25
20
15
10
5
+105°C
+25°C
–40°C
0.8
FAST
MEDIAN
FOCUS
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
–V
0V
+V
REF
REF
INPUT VOLTAGE (V)
GAIN ERROR ( LSB)
Figure 23. INL Error vs. Input Voltage
Figure 26. Gain Error Distribution (100 Devices Sampled)
1.0
25
20
15
10
5
–40°C
0°C
+25°C
+85°C
+105°C
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
–V
0V
+V
REF
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30
GAIN ERROR (LSB)
REF
INPUT VOLTAGE (V)
Figure 24. INL Error vs. Input Voltage for Various Temperatures,
Fast Mode
Figure 27. Channel to Channel Gain Error Matching (100 Devices Sampled)
18000
16000
14000
12000
10000
8000
6000
4000
2000
0
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
10
100
1k
10k
100k
1M
10M
INPUT FREQUENCY (Hz)
OFFSET ERROR (LSB)
Figure 28. AC CMRR vs. Input Frequency
Figure 25. Offset Error Distribution (Approximately 2500 Devices Sampled)
Rev. A | Page 22 of 75
Data Sheet
AD7761
20
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
DCLK = 32.768MHz
AVDD1 = 5V + 100mV p-p
–20
–40
FOCUS
MEDIAN
FAST
–60
–80
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
–100
–120
–140
–160
–180
–100
100
1k
10k
100k
1M
10M
–0.1
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
FREQUENCY (Hz)
NORMALIZED INPUT FREQUENCY (fIN
/
fODR
)
Figure 29. AC PSRR vs. Frequency, AVDD1
Figure 32. Wideband Filter Profile, Amplitude vs. fIN/fODR
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
5
4
70000
60000
50000
40000
30000
20000
10000
0
DCLK = 32.768MHz
AVDD2 = 5V + 100mV p-p
3
AINx
DOUTx
2
1
0
CH0
CH4
CH1
CH5
CH2
CH6
CH3
CH7
–1
–2
–3
–4
100
1k
10k
100k
1M
10M
0
10
20
30
40
50
60
70
80
FREQUENCY (Hz)
SAMPLES
Figure 33. Step Response, Wideband Filter
Figure 30. AC PSRR vs. Frequency, AVDD2
0.005
0.004
0.003
0.002
0.001
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
FOCUS
MEDIAN
FAST
IOVDD = 1.8V, DCLK = 32.768MHz, CH7
IOVDD = 2.5V, DCLK = 32.768MHz, CH7
IOVDD = 1.8V, DCLK = 8.192MHz, CH7
IOVDD = 2.5V, DCLK = 8.192MHz, CH7
–0.001
–0.002
–0.003
–0.004
–0.005
100
1k
10k
100k
1M
10M
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
NORMALIZED INPUT FREQUENCY (fIN
FREQUENCY (Hz)
/
fODR)
Figure 34. Wideband Filter Ripple
Figure 31. AC PSRR vs. Frequency, IOVDD
Rev. A | Page 23 of 75
AD7761
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–20
–40
–60
–80
FAST WITH PRECHARGE
FAST, NO PRECHARGE
MEDIAN WITH PRECHARGE
MEDIAN, NO PRECHARGE
FOCUS WITH PRECHARGE
FOCUS, NO PRECHARGE
–100
–120
–140
RESOLUTION LIMIT = –110dB
–160
0
–40
25
TEMPERATURE (°C)
105
1
2
3
4
5
6
NORMALIZED INPUT FREQUENCY (fIN
/
fODR)
Figure 35. Sinc5 Filter Profile, Amplitude vs. fIN/fODR
Figure 38. Reference Input Current vs. Temperature, Reference Precharge
Buffers On/Off
5
4
70000
60000
50000
40000
30000
20000
10000
0
AVDD1 = 5V, AVSS = 0V
VCM_VSEL = 10
PART TO PART DISTRIBUTION
120
3
100
80
60
40
20
0
AINx
DOUTx
2
1
0
–1
–2
–3
–4
2.42
2.43
2.44
2.45
(V)
2.46
2.47
0
5
10
15
20
25
30
V
SAMPLES
CM
Figure 36. Step Response, Sinc5 Filter
Figure 39. VCM Output Voltage Distribution
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
DIFFERENTIAL COMPONENT, NO PRECHARGE (µA/V)
COMMON-MODE COMPONENT, NO PRECHARGE (µA/V)
FAST
MEDIAN
FOCUS
–10
–20
–30
–40
TOTAL CURRENT, PRECHARGE ON (µA)
0
–40
25
105
–40 –25 –10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 37. Analog Input Current vs. Temperature, Analog Input Precharge
Buffers On/Off
Figure 40. Supply Current vs. Temperature, AVDD1
Rev. A | Page 24 of 75
Data Sheet
AD7761
40
500
450
400
350
300
250
200
150
100
50
FAST, WIDEBAND FILTER
FAST
35
30
25
20
15
10
5
FAST, SINC5 FILTER
MEDIAN
FOCUS
MEDIAN, WIDEBAND FILTER
MEDIAN, SINC5 FILTER
FOCUS, WIDEBAND FILTER
FOCUS, SINC5 FILTER
0
0
–40
25
105
–40 –25 –10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 41. Supply Current vs. Temperature, AVDD2
Figure 43. Total Power vs. Temperature
70
60
50
40
30
20
10
0
FAST, SINC5
FAST, WIDEBAND
MEDIAN, SINC5
MEDIAN, WIDEBAND
FOCUS, SINC5
FOCUS, WIDEBAND
–40 –25 –10
5
20
35
50
65
80
95
110
TEMPERATURE (°C)
Figure 42. Supply Current vs. Temperature, IOVDD
Rev. A | Page 25 of 75
AD7761
Data Sheet
TERMINOLOGY
As a result, the second-order and third-order terms are
AC Common-Mode Rejection Ratio (AC CMRR)
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals, expressed in
decibels.
AC CMRR is defined as the ratio of the power in the ADC output
at frequency, f, to the power of a sine wave applied to the common-
mode voltage of AINx+ and AINx− at frequency, fS.
AC CMRR (dB) = 10log(Pf/PfS)
where:
Least Significant Bit (LSB)
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
The least significant bit, or LSB, is the smallest increment that
can be represented by a converter. For a fully differential input
ADC with N bits of resolution, the LSB expressed in volts is as
follows:
Gain Error
The first transition (from 100 … 000 to 100 … 001) occurs at a
level ½ LSB above nominal negative full scale (−4.0959375 V for
the 4.096 V range). The last transition (from 011 … 110 to
011 … 111) occurs for an analog voltage 1½ LSB below the
nominal full scale (+4.0959375 V for the 4.096 V range). The
gain error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition from
the difference between the ideal levels.
LSB (V) = (2 × VREF)/2N
where:
VREF is the difference voltage between the REFx+ and REFx− pins.
N = 16.
Offset Error
Offset error is the difference between the ideal midscale input
voltage (0 V) and the actual voltage producing the midscale
output code.
Gain Error Drift
Gain error drift is defined as the gain error change due to a
temperature change of 1°C. It is expressed in parts per million
per degree Celsius.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the full-scale transition point due to a change in the power
supply voltage from the nominal value.
Integral Nonlinearity (INL) Error
INL error refers to the deviation of each individual code from a
line drawn from negative full scale through positive full scale.
The point used as negative full scale occurs ½ LSB before the
first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is measured
from the middle of each code to the true straight line.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at the sum and difference frequencies of mfa and nfb,
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m or n are equal to 0. For
example, the second-order terms include (fa + fb) and (fa − fb),
and the third-order terms include (2fa + fb), (2fa − fb), (fa +
2fb), and (fa − 2fb).
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal (excluding the
first five harmonics).
The AD7761 is tested using the CCIF standard, in which two
input frequencies near to each other are used. In this case, the
second-order terms are usually distanced in frequency from the
original sine waves, and the third-order terms are usually at a
frequency close to the input frequencies.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and
is expressed in decibels.
Rev. A | Page 26 of 75
Data Sheet
AD7761
THEORY OF OPERATION
The AD7761 is an 8-channel, simultaneously sampled, low
noise, Σ-∆ ADC.
CLOCKING, SAMPLING TREE, AND POWER SCALING
The AD7761 includes multiple ADC cores. Each of these ADCs
receives the same master clock signal, MCLK. The MCLK signal
can be sourced from one of three options: a CMOS clock, a crystal
connected between the XTAL1 and XTAL2 pins, or in the form
of an LVDS signal. The MCLK signal received by the AD7761 is
used to define the modulator clock rate, fMOD, and in turn the
sampling frequency of the modulator of 2 × fMOD. The same
MCLK signal is also used to define the digital output clock,
DCLK. The fMOD and DCLK internal signals are synchronous
with MCLK.
Each ADC within the AD7761 employs a Σ-Δ modulator whose
clock runs at a frequency of fMOD. The modulator samples the
inputs at a rate of 2 × fMOD, to convert the analog input into an
equivalent 16-bit digital representation, and these samples there-
fore represent a quantized version of the analog input signal.
The Σ-Δ conversion technique is an oversampled architecture.
This oversampled approach spreads the quantization noise over
a wide frequency band (see Figure 44). To reduce the quantization
noise in the signal band, the high order modulator shapes the noise
spectrum so that most of the noise energy is shifted out of the
band of interest (see Figure 45). The digital filter that follows the
modulator removes the large out of band quantization noise
(see Figure 46).
Figure 47 shows the clock tree from the MCLK input to the
modulator, the digital filter, and the DCLK output. There are
divider settings for MCLK and DCLK. These dividers, in
conjunction with the power mode and digital filter decimation
settings, are key to the operation of the AD7761.
For further information on the basics as well as more advanced
concepts of Σ-Δ ADCs, see the MT-022 Tutorial and the
MT-023 Tutorial.
The AD7761 has the ability to scale power consumption vs. the
input bandwidth or desired noise. The user controls two para-
meters to achieve this: MCLK division and power mode. When
combined, these two settings determine the clock frequency of the
modulator (fMOD) and the bias current supplied to each modulator.
The power mode (fast, median, or low power) sets the noise, speed
capability, and current consumption of the modulator. The
power mode is the dominant control for scaling the power
consumption of the ADC. All settings of MCLK division and
power mode apply to all ADC channels.
Digital filtering has certain advantages over analog filtering. First, it
is insensitive to component tolerances and the variation of
component parameters over time and temperature. And because
digital filtering on the AD7761 occurs after the analog-to-digital
conversion, it can remove some of the noise injected during the
conversion process; analog filtering cannot remove noise
injected during conversion. Second, the digital filter combines
low pass-band ripple with a steep roll-off and high stop-band
attenuation, while also maintaining a linear phase response,
which is difficult to achieve in an analog filter implementation.
DCLK_DIV
00: DCLK = MCLK/8
01: DCLK = MCLK/4
10: DCLK = MCLK/2
11: DCLK = MCLK/1
MCLK_DIV
MCLK/4
MCLK/8
MCLK/32
QUANTIZATION NOISE
fMOD/2
DCLK
BAND OF INTEREST
DIGITAL
FILTER
DATA
INTERFACE
CONTROL
ADC
MODULATOR
DRDY
Figure 44. Σ-Δ ADC Quantization Noise (Linear Scale X-Axis)
DOUTx
POWER MODES:
FAST
DECIMATION RATES = ×32, ×64,
×128, ×256, ×512, ×1024
MEDIAN
LOW POWER
NOISE SHAPING
Figure 47. Sampling Structure, Defined by the MCLK, DCLK_DIV, and
MCLK_DIV Settings
fMOD/2
BAND OF INTEREST
The modulator clock frequency (fMOD) is determined by selecting
one of three clock divider settings: MCLK/4, MCLK/8, or
MCLK/32.
Figure 45. Σ-Δ ADC Noise Shaping (Linear Scale X-Axis)
Although the MCLK division and power modes are independent
settings, there are restrictions that must be adhered to. A valid
range of modulator frequencies exists for each power mode.
Table 9 describes this recommended range, which allows the
device to achieve the best performance while minimizing power
consumption. The AD7761 specifications do not cover the
performance and function beyond the maximum fMOD for a given
power mode.
DIGITAL FILTER CUTOFF FREQUENCY
fMOD/2
BAND OF INTEREST
Figure 46. Σ-Δ ADC Digital Filter Cutoff Frequency (Linear Scale X-Axis)
Rev. A | Page 27 of 75
AD7761
Data Sheet
For example, to maximize the speed of conversion or input
bandwidth in fast mode, an MCLK of 32.768 MHz is required
and MCLK_DIV = 4 must be selected for a modulator
frequency of 8.192 MHz.
Configuration A
To maximize the dynamic range, use the following settings:
•
•
•
•
•
MCLK = 16 MHz
Median power
Table 9. Recommended fMOD Range for Each Power Mode
Power Mode Recommended fMOD (MHz), MCLK = 32.768 MHz
f
MOD = MCLK/4
Decimation = ×64 (digital filter setting)
ODR = 62.5 kHz
Low Power
Median
Fast
0.036 to 1.024
1.024 to 4.096
4.096 to 8.192
This configuration maximizes the available decimation rate (or
oversampling ratio) for the bandwidth required and MCLK rate
available. The decimation averages the noise from the modulator,
maximizing the dynamic range.
Control of the settings for the power mode, the modulator
frequency, and the data clock frequency differs in pin control
mode vs. SPI control mode.
Configuration B
In SPI control mode, the user can program the power mode, the
MCLK divider (MCLK_DIV), and the DCLK frequency using
Register 0x04 and Register 0x07 (see Table 38 and Table 41 for
register information). Independent selection of the power mode
and MCLK_DIV allows full freedom in the MCLK speed selection
to achieve a target modulator frequency.
To minimize power, use the following settings:
•
•
•
•
•
MCLK = 16 MHz
Median power
f
MOD = MCLK/8
Decimation = ×32 (digital filter setting)
ODR = 62.5 kHz
In pin control mode, the MODEx pins determine the power
mode, the modulator frequency, and the DCLK frequency. The
modulator frequency tracks the power mode. This means that
This configuration reduces the clocking speed of the modulator
and the digital filter.
f
MOD is fixed at MCLK/32 for low power mode, MCLK/8 for
When compared to Configuration A, Configuration B saves
48 mW of power. The trade-off in the case of Configuration B is
that the digital filter must run at a 2× lower decimation rate.
This 2× reduction in decimation rate (or oversampling ratio)
results in a 3 dB reduction in the dynamic range vs. Config-
uration A.
median mode, and MCLK/4 for fast mode (see Table 18).
Example of Power vs. Noise Performance Optimization
Depending on the bandwidth of interest for the measurement,
the user can choose a strategy of either lowest current consumption
or highest resolution. This choice is due to an overlap in the
coverage of each power mode. The AD7761 offers the ability to
balance the MCLK division ratio with the rate of decimation
(averaging) set in the digital filter. Lower power can be achieved
by using lower modulator clock frequencies. Conversely, the
highest resolution can be achieved by using higher modulator
clock frequencies and maximizing the amount of oversampling.
Clocking Out the ADC Conversion Results (DCLK)
The AD7761 DCLK is a divided version of the master clock
input. As shown in Figure 47, the DCLK_DIV setting determines
the speed of the DCLK. DCLK is a continuous clock.
The user can set the DCLK frequency rate to one of four divisions
of MCLK: MCLK/1, MCLK/2, MCLK/4, and MCLK/8. Because
there are eight channels and 24 bits of data per conversion, the
conversion time and the setting of DCLK directly determine the
number of data output lines that are required via the FORMATx
pin settings. Thus, the intended minimum decimation and desired
DCLK_DIV setting must be understood prior to choosing the
setting of the FORMATx pins.
As an example, consider a system constraint with a maximum
available MCLK of 16 MHz. The system is targeting a measure-
ment bandwidth of approximately 25 kHz with the wideband
filter, setting the output data rate of the AD7761 to 62.5 kHz.
Because of the low MCLK frequency available and the system
power budget, median power mode is used.
In median power mode, this 25 kHz input bandwidth can be
achieved by setting the MCLK division and decimation ratio to
balance, using two configurations (Configuration A and
Configuration B). This flexibility is possible in SPI control
mode only.
NOISE PERFORMANCE AND RESOLUTION
Table 10 and Table 11 show the noise performance for the
wideband and sinc5 digital filters of the AD7761 for various
output data rates and power modes. The noise values specified
are typical for the bipolar input range with an external 4.096 V
reference (VREF).
The LSB size with 4.096 V reference is 125 µV, and is calculated
as follows:
LSB (V) = (2 × VREF)/216
Rev. A | Page 28 of 75
Data Sheet
AD7761
Table 10. Wideband Filter Noise: Performance vs. Output Data Rate
Output Data Rate (kSPS)
−3 dB Bandwidth (kHz)
RMS Noise (µV)
Fast Mode
256
128
64
32
16
8
110.8
55.4
27.7
13.9
6.9
11.58
7.77
5.42
3.82
2.72
1.94
3.5
Median Mode
128
64
32
16
8
4
55.4
27.7
13.9
6.9
3.5
1.7
11.36
7.6
5.3
3.74
2.64
1.87
Low Power Mode
32
16
8
4
2
13.9
6.9
3.5
1.7
0.87
0.43
11.28
7.54
5.25
3.71
2.62
1.85
1
Table 11. Sinc5 Filter Noise: Performance vs. Output Data Rate
Output Data Rate (kSPS)
−3 dB Bandwidth (kHz)
RMS Noise (µV)
Fast Mode
256
128
64
32
16
8
52.224
26.112
13.056
6.528
3.264
1.632
7.83
5.43
3.82
2.71
1.93
1.39
Median Mode
128
64
32
16
8
4
26.112
13.056
6.528
3.264
1.632
0.816
7.68
5.3
3.72
2.64
1.87
1.33
Low Power Mode
32
16
8
4
2
6.528
3.264
1.632
0.816
0.408
0.204
7.65
5.26
3.7
2.61
1.85
1.31
1
Rev. A | Page 29 of 75
AD7761
Data Sheet
APPLICATIONS INFORMATION
The AD7761 offers users a multichannel platform measurement
solution for ac and dc signal processing.
•
Control of reference and analog input precharge buffers on
a per channel basis.
•
•
•
Wideband, low ripple, digital filter for ac measurement.
Fast sinc5 filter for precision low frequency measurement.
Two channel modes, defined by the user selected filter choice,
and decimation ratios, can be defined for use on different
ADC channels. This enables optimization of the input
bandwidth versus the signal of interest.
Option of SPI or pin strapped control and configuration.
Offset, gain, and phase calibration registers per channel.
Common-mode voltage output buffer for use by a driver
amplifier.
Flexible filtering allows the AD7761 to be configured to
simultaneously sample ac and dc signals on a per channel basis.
Power scaling allows users to trade off the input bandwidth of
the measurement vs. the current consumption. This ability,
coupled with the flexibility of the digital filtering, allows the
user to optimize the energy efficiency of the measurement,
while still meeting power, bandwidth, and performance targets.
•
•
•
Key capabilities that allow users to choose the AD7761 as their
platform high resolution ADC are highlighted as follows:
•
•
Eight fully differential or pseudo differential analog inputs.
Fast throughput simultaneous sampling ADCs catering for
input signals up to 110.8 kHz.
•
On-board AVDD2 and IOVDD LDOs for the low power,
1.8 V, internal circuitry.
Refer to Figure 48 and Table 12 for the typical connections
and minimum requirements to get started using the AD7761.
•
Three selectable power modes (fast, median, and low
power) for scaling the current consumption and input
bandwidth of the ADC for optimal measurement
efficiency.
Analog input precharge and reference precharge buffers
reduce the drive requirements of external amplifiers.
Table 13 shows the typical power and performance of the
AD7761 for the available power modes, for each filter type.
•
AVDD1A,
AVDD1B
AVDD2A,
AVDD2B
IOVDD
SUGGESTED OP AMPS:
FAST MODE: ADA4896-2 OR ADA4807-2
MEDIAN MODE: ADA4940-2 OR ADA4807-2
LOW POWER MODE: ADA4805-2
REGCAPA,
REGCAPB
DREGCAP
SYNC_IN
SYNC_OUT
START
VCM
AD7761
RESET
FORMATx
DRDY
DCLK
AIN0+
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
5V
ADC
DATA
AIN0–
SINC5
LOW LATENCY FILTER
SERIAL
INTERFACE
AIN7+
ADA4940-1/
ADA4940-2
Σ-Δ
ADC
SPI
CONTROL
INTERFACE
AIN7–
DOUT6
DOUT7
WIDEBAND
LOW RIPPLE FILTER
PRECHARGE
BUFFERS
ST0/CS
ST1/SCLK
DEC0/SDO
DEC1/SDI
FILTER/GPIO4
AVSS
REFx+
REFx–
XTAL1
XTAL2/MCLK
PIN/SPI
MODE3/GPIO3
TO
V
IN
MODE0/GPIO0
–
+
V
V
IN
OUT
ADR4540
ADA4841-1
Figure 48. Typical Connection Diagram
Rev. A | Page 30 of 75
Data Sheet
AD7761
Table 12. Requirements to Operate the AD7761
Requirement
Description
Power Supplies
External Reference
External Driver Amplifiers
External Clock
5 V AVDD1 supply, 2.25 V to 5 V AVDD2 supply, 1.8 V or 2.5 V to 3.3 V IOVDD supply (ADP7104/ADP7118)
2.5 V, 4.096 V, or 5 V (ADR4525, ADR4540, or ADR4550)
The ADA4896-2, the ADA4940-1/ADA4940-2, the ADA4805-2, and the ADA4807-2
Crystal or a CMOS/LVDS clock for the ADC modulator sampling
FPGA or DSP
Input/output voltage of 2.5 V to 3.6 V, or 1.8 V (see the 1.8 V IOVDD Operation section)
Table 13. Speed, Dynamic Range, THD, and Power Overview; Eight Channels Active, Decimate by 321
Sinc5 Filter
Wideband Filter
Output
Power
Mode
Data Rate THD
Dynamic
Range (dB)
Bandwidth
Power Dissipation Dynamic
Bandwidth
(kHz)
Power Dissipation
(mW per channel)
(kSPS)
(dB)
(kHz)
52.224
26.112
6.528
(mW per channel)
Range (dB)
Fast
Median
Low Power 32
256
128
−115
−120
−120
97.7
97.7
97.7
41
22
8.5
97.7
97.7
97.7
110.8
55.4
13.9
52
28
9.5
1 Analog precharge buffers on, precharge reference buffers and VCM disabled, typical values, AVDD1 = 5 V, AVDD2 = IOVDD = 2.5 V, VREF = 4.096 V, MCLK = 32.768 MHz,
DCLK = MCLK/4, TA = 25°C.
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD also sets
the voltage levels for the SPI interface of the ADC. IOVDD is
referenced to DGND, and the voltage on IOVDD can vary from
2.25 V (minimum) to 3.6 V (maximum), with respect to DGND.
IOVDD can also be configured to run at 1.8 V. In this case, IOVDD
and DREGCAP must be tied together and must be within the
range of 1.72 V (minimum) to 1.88 V (maximum), with respect
to DGND. See the 1.8 V IOVDD Operation section for more
information on operating the AD7761 at 1.8 V IOVDD.
POWER SUPPLIES
The AD7761 has three independent power supplies: AVDD1
(given by the AVDD1A pin and the AVDD2A pin), AVDD2
(given by the AVDD2A pin and the AVDD2B pin), and IOVDD.
The reference potentials for these supplies are AVSS and DGND.
Tie all the AVSS supply pins (AVSS1A, AVSS1B, AVSS2A, AVSS2B,
and AVSS) to the same potential with respect to DGND. AVDD1A,
AVDD1B, AVDD2A, and AVDD2B are referenced to this AVSS
rail. IOVDD is referenced to DGND.
The supplies can be powered within the following ranges:
Recommended Power Supply Configuration
•
•
•
AVDD1 = 5 V 10%, relative to AVSS
AVDD2 = 2 V to 5.5 V, relative to AVSS
IOVDD (with internal regulator) = 2.25 V to 3.6 V, relative
to DGND
IOVDD (bypassing regulator) = 1.72 V to 1.88 V, relative to
DGND
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a power solution that uses the ADP7118 is shown
in Figure 49. The ADP7118 provides positive supply rails for
optimal converter performance, creating either a single 5 V,
3.3 V, or dual AVDD1 and AVDD2/IOVDD, depending on the
required supply configuration. The ADP7118 can operate from
input voltages of up to 20 V.
•
•
AVSS = −2.75 V to 0 V, relative to DGND
The AVDD1A and AVDD1B (AVDD1) supplies power the analog
front end, reference input, and common-mode output circuitry.
AVDD1 is referenced to AVSS, and all AVDD1 supplies must be
tied to the same potential with respect to AVSS. If AVDD1 supplies
are used in a 2.5 V split supply configuration, the ADC inputs are
truly bipolar. When using split supplies, reference the absolute
maximum ratings, which apply to the voltage allowed between
the AVSS and IOVDD supplies.
ADP7118
LDO
12V
INPUT
5V: AVDD1x
ADP7118
LDO
3.3V: AVDD2x/IOVDD
Figure 49. Power Supply Configuration
Alternatively, the ADP7112 or ADP7104 can be selected for
powering the AD7761. Refer to the AN-1120 Application Note
for more information regarding low noise LDO performance
and power supply filtering.
The AVDD2A and AVDD2B (AVDD2) supplies connect to
internal 1.8 V analog LDO regulators. The regulators power the
ADC core. AVDD2 is referenced to AVSS, and all AVDD2 supplies
must be tied to the same potential with respect to AVSS. The
voltage on AVDD2 can range from 2 V (minimum) to 5.5 V
(maximum), with respect to AVSS.
Rev. A | Page 31 of 75
AD7761
Data Sheet
1.8 V IOVDD Operation
DEVICE CONFIGURATION
The AD7761 contains an internal 1.8 V LDO on the IOVDD
supply to regulate the IOVDD down to the operating voltage of the
digital core. This internal LDO allows the internal logic to operate
efficiently at 1.8 V and the input/output logic to operate at the
level set by IOVDD. The IOVDD supply is rated from 2.25 V to
3.6 V for normal operation, and 1.8 V for LDO bypass setup.
The AD7761 has independent paths for reading data from the
ADC conversions and for controlling the device functionality.
For control, the device can be configured in either of two
modes. The two modes of configuration are as follows:
•
Pin control mode: pin strapped digital logic inputs (which
allows a subset of the configurability options)
SPI control mode: over a 3-wire or 4-wire SPI interface
(complete configurability)
38
SYNC_OUT
•
37
START
1.8V IOVDD
SUPPLY
36
SYNC_IN
35
IOVDD
PIN
On power-up, the state of the
/SPI pin determines the mode
34
DREGCAP
used. Immediately after power-up, the user must apply a soft or
hard reset to the device when using either control mode.
33
DGND
28 29 30 31 32
Interface Data Format
When operating the device, the data format of the serial interface is
determined by the FORMATx pins. Table 30 shows that each ADC
can be assigned a DOUTx pin, or, alternatively, the data can be
arranged to share the DOUTx pins in a time division multiplexed
manner. For more details, see the Data Interface section.
Figure 50. DREGCAP and IOVDD Connection Diagram for 1.8 V IOVDD
Operation
Users can bypass the LDO by shorting the DREGCAP pin to
IOVDD (see Figure 50), which pulls the internal LDO out of
regulation and sets the internal core voltage and input/output
logic levels to the IOVDD level. When bypassing the internal
LDO, the maximum operating voltage of the IOVDD supply is
equal to the maximum operating voltage of the internal digital core,
which is 1.72 V to 1.88 V.
PIN CONTROL MODE
Pin control mode eliminates the need for an SPI communication
interface. When a single known configuration is required by the
user, or when only limited reconfiguration is required, the number
of signals that require routing to the digital host can be reduced
using this mode. Pin control mode is useful in digitally isolated
applications where minimal adjustment of the configuration is
needed. Pin control offers a subset of the core functionality and
ensures a known state of operation after power-up, reset, or a
fault condition on the power supply. In pin control mode, the
analog input precharge buffers are enabled by default for best
performance. The reference input precharge buffers are disabled
in pin control mode.
Analog Supply Internal Connectivity
The AD7761 has two analog supply rails, AVDD1 and AVDD2,
which are both referred to AVSS. These supplies are completely
separate from the digital pins, IOVDD, DREGCAP, and DGND. To
achieve optimal performance and isolation of the ADCs, more than
one device pin supplies these analog rails to the internal ADCs.
•
•
•
AVSS1A (Pin 3) and AVSS2A (Pin 62) are internally
connected.
After any change to the configuration in pin control mode, the
user must provide a sync signal to the AD7761 by applying the
AVSS (Pin 54) is connected to the substrate, and is connected
internally to AVSS1B (Pin 46) and AVSS2B (Pin 51).
The following supply and reference input pins are separate
on chip: AVDD1A, AVDD1B, AVDD2A, AVDD2B,
REF1+, REF1−, REF2+, and REF2−.
START
SYNC_IN
appropriate pulse to the
pin or the
pin to
ensure that the configuration changes are applied correctly to
the ADC and the digital filters.
Setting the Filter
The filter function chooses between the two filter settings. In
pin control mode, all ADC channels use the same filter type,
which is selected by the FILTER pin, as shown in Table 14.
The details of which individual supplies are shorted internally are
given in this section for informational purposes. In general,
connect the supplies as described in the Power Supplies section.
Table 14. FILTER Control Pin
Logic Level
Function
1
0
Sinc5 filter selected
Wideband filter selected
Rev. A | Page 32 of 75
Data Sheet
AD7761
The MODEx pins map to 16 distinct settings. The settings are
Setting the Decimation Rate
selected to optimize the use cases of the AD7761, allowing the
user to reduce the DCLK frequency for lower, less demanding
power modes and selecting either the one-shot or standard
conversion modes.
Pin control mode allows selection from four possible decimation
rates. The decimation rate is selected via the DEC1 and DEC0 pins.
The chosen decimation rate is used on all ADC channels. Table 15
shows the truth table for the DECx pins.
See Table 18 for the complete selection of operating modes that
are available via the MODEx pins in pin control mode.
Table 15. Decimation Rate Control Pins Truth Table
DEC1
DEC0
Decimation Rate
The power mode setting automatically scales the bias currents
of the ADC and divides the applied MCLK signal to the correct
setting for that mode. Note that this is not the same as using SPI
control mode, where separate bit fields exist to control the bias
currents of the ADC and MCLK division.
0
0
1
1
0
1
0
1
×32
×64
×128
×1024
Operating Mode
In pin control mode, the modulator rate is fixed for each power
mode to achieve the best performance. Table 17 shows the
modulator division for each power mode.
The MODE3 to MODE0 pins determine the configuration of all
channels when using pin control mode. The variables controlled by
the MODEx pins are shown in Table 16. The user selects how
much current the device consumes, the sampling speed of the
ADC (power mode), how fast the ADC result is received by the
digital host (DCLK_DIV), and how the ADC conversion is
initiated (conversion operation). Figure 51 illustrates the inputs
used to configure the device in pin control mode.
Table 17. Modulator Rate, Pin Control Mode
Power Mode
Modulator Rate, fMOD
Fast
MCLK/4
Median
MCLK/8
Low power
MCLK/32
Diagnostics
Table 16. MODEx Pins: Variables for Control
Pin control mode offers a subset of diagnostics features. Internal
errors are reported in the status header output with the data
conversion results for each channel.
Control Variable
Possible Settings
Sampling Speed/Power Consumption
Power Mode
Fast
Median
Low power
Internal cyclic redundancy check (CRC) errors, memory map
flipped bits, and external clocks not detected are reported by Bit
7 of the status header and indicate that a reset is required. The
status header also reports filter not settled, filter type, and filter
saturated signals. Users can determine when to ignore data by
monitoring these error flags. For more information on the status
header, see the ADC Conversion Output: Header and Data section.
Data Clock Output Frequency (DCLK_DIV) DCLK = MCLK/1
DCLK = MCLK/2
DCLK = MCLK/4
DCLK = MCLK/8
Conversion Operation
Standard conversion
One-shot conversion
PIN CONTROL MODE
PIN/SPI = LOW
CHANNEL STANDBY
CH 0 TO CH 3 STANDBY
CH 4 TO CH 7 STANDBY
OUTPUT DATA FORMAT
1 CHANNEL PER PIN
4 CHANNELS PER PIN
8 CHANNELS PER PIN
PIN/SPI
ST0
ST1
FORMAT0
FORMAT1
DOUT0
DOUT1
TO DSP/
FPGA
AD7761
OPTION TO
SELECT
BETWEEN FILTERS
FILTER
DOUT7
MODE0
MODE1
MODE2
MODE3
DEC0/
DEC1
DECIMATION RATES
MODE CONFIGURATION
MODE 0x0 TO MODE 0xF
SET UP VIA 4 PINS
/32
/64
/128
/1024
Figure 51. Pin Configurable Functions
Rev. A | Page 33 of 75
AD7761
Data Sheet
Table 18. MODEx Selection Details: Pin Control Mode
Mode Hex. MODE3
MODE2
MODE1
MODE0
Power Mode
Low power
Low power
Low power
Low power
Median
Median
Median
Median
Fast
DCLK Frequency
MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/1
MCLK/2
MCLK/4
MCLK/8
MCLK/1
MCLK/1
MCLK/2
MCLK/1
Data Conversion
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
One-shot
One-shot
One-shot
One-shot
Fast
Fast
Fast
Low power
Median
Fast
Fast
Table 19. MODEx Example Selection
Mode Hex
MODE3
MODE2
MODE1 MODE0
Power Mode
DCLK Frequency
MCLK/8
Data Conversion
0x3
0
0
1
1
Low Power
Standard
Configuration Example
In the example shown in Table 19, the lowest current
Channel Standby
Table 20 shows how the user can put channels into standby mode.
Set either ST0 or ST1 to Logic 1 to place banks of four channels
into standby mode. When in standby mode, the disabled channels
hold their position in the output data stream. The 8-bit header
and 16-bit conversion results are set to all zeros when the ADC
channels are set to standby.
consumption is used, and the AD7761 is connected to an FPGA.
The FORMATx pins are set such that all eight data outputs,
DOUT0 to DOUT7, connect to the FPGA. For the lowest
power, the lowest DCLK frequency is used. The input bandwidth
is set through the combination of selecting decimation by 64
and selecting the wideband filter.
The VCM voltage output is associated with the Channel 0
circuitry. If Channel 0 is put into standby mode, the VCM
voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally
to the AD7761.
ODR = fMOD ÷ Decimation Ratio
where:
f
MOD is MCLK/32 for low power mode (see Table 17).
Decimation Ratio = 64.
The crystal excitation circuitry is associated with the Channel 4
circuitry. If Channel 4 is put into standby mode, the crystal
circuitry is also disabled for maximum power savings. Channel 4
must be enabled while the external crystal is used on the AD7761.
Thus, for this example, where MCLK = 32.768 MHz,
ODR = (32.768 MHz/32) ÷ 64 = 16 kHz
Minimizing the DCLK frequency means selecting DCLK =
MCLK/8, which results in a 4 MHz DCLK signal. The period of
DCLK in this case is 1/4 MHz = 250 ns. The data conversion on
each DOUTx pin is 24 bits long. The conversion data takes 24 ×
250 ns = 6 μs to be output. All 24 bits must be output within the
ODR period of 1/16 kHz, which is approximately 64 μs. In this
case, the 6 μs required to read out the conversion data is well
within the 64 μs between conversion outputs. Therefore, this
combination, which is summarized in Table 19, is viable for use.
Table 20. Truth Table for the AD7761 ST0 and ST1 Pins
ST1
ST0
Function
0
0
All channels operational.
0
1
Channel 0 to Channel 3 in
standby. Channel 4 to
Channel 7 operational.
1
1
0
1
Channel 4 to Channel 7 in
standby. Channel 0 to
Channel 3 operational.
All channels in standby.
Rev. A | Page 34 of 75
Data Sheet
AD7761
SPI Interface Details
Each SPI access frame is 16 bits long. The MSB (Bit 15) of the
SPI CONTROL
The AD7761 has a 4-wire SPI interface that is compatible with
QSPI™, MICROWIRE®, and DSPs. The interface operates in SPI
W
SDI command is the R/ bit; 1 = read and 0 = write. Bits[14:8]
of the SDI command are the address bits.
CS
Mode 0. In SPI Mode 0, SCLK idles low, the falling edge of
clocks out the MSB, the falling edge of SCLK is the drive edge,
and the rising edge of SCLK is the sample edge. This means that
data is clocked out on the falling/drive edge and data is clocked
in on the rising/sample edge.
The SPI control interface uses an off frame protocol. This means
that the master (FPGA/DSP) communicates with the AD7761 in
W
two frames. The first frame sends a 16-bit instruction (R/
,
address, and data) and the second frame is the response where
the AD7761 sends 16 bits back to the master.
During the master write command, the SDO output contains
eight leading zeros, followed by eight bits of data, as shown in
Figure 54.
DRIVE EDGE
SAMPLE EDGE
Figure 53 shows the off frame protocol. Register access responses
Figure 52. SPI Mode 0 SCLK Edges
CS
are always offset by one
(read RESP 1) to the first command (CMD 1) is output by the
CS
frame. In Figure 53, the response
Accessing the ADC Register Map
PIN
AD7761 during the following
frame at the same time as the
To use SPI control mode, set the
/SPI pin to logic high. The
second command (CMD 2) is being sent.
SPI control operates as a 16-bit, 4-wire interface, allowing read
and write access. Figure 54 shows the interface format between
the AD7761 and the digital host.
SCLK
CS
The SPI serial control interface of the AD7761 is an independent
path for controlling and monitoring the device. There is no direct
link to the data interface. The timing of MCLK and DCLK is
not directly related to the timing of the SPI control interface.
However, the user must ensure that the SPI reads and writes
satisfy the minimum t30 specification (see Table 3 and Table 5)
so that the AD7761 can detect changes to the register map.
CMD 1
CMD 2
SDI
READ RESP 1
SDO
Figure 53. Off Frame Protocol
SPI Control Interface Error Handling
The AD7761 SPI control interface detects whether it has
received an illegal command. An illegal command is a write to a
read only register, a write to a register address that does not
exist, or a read from a register address that does not exist. If any of
these illegal commands are received by the AD7761, the device
responds with an error output of 0x0E00.
SPI access is ignored during the period immediately after a
reset. Allow the full ADC start-up time after reset (see Table 1)
to elapse before accessing the AD7761 over the SPI interface.
SCLK
CS
SDI
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDO
0
0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. Write/Read Command
Rev. A | Page 35 of 75
AD7761
Data Sheet
SPI Reset Configuration
When different decimation rates are selected on different channels,
the AD7761 outputs a data ready signal at the fastest selected
decimation rate. Any channel that runs at a lower output data rate
is updated only at that slower rate. In between valid result data, the
data for that channel is set to zero and the repeated data bit is set in
the header status bits to distinguish it from a real conversion result
(see the ADC Conversion Output: Header and Data section for
more information).
After a power-on or reset, the AD7761 default configuration is set
to the following low current consumption settings:
•
•
Low power mode with MCLK/32.
Interface configuration of DCLK = MCLK/8, header
output enabled, and CRC disabled.
•
•
•
Filter configuration of Channel Mode A and Channel Mode B
is set to sinc5 and decimation = ×1024. Channel mode
select is set to 0x00, and all channels are assigned to
Channel Mode A.
Channel configuration of Channel 0 to Channel 7 is enabled,
with the analog input buffers enabled. The reference precharge
buffers are disabled. The offset, gain, and phase calibration
are set to the zero position.
On the AD7761, consider Channel Mode A as the primary group.
In this respect, it is recommended that there always be at least one
channel assigned to Channel Mode A. If all eight channels of the
AD7761 are assigned to Channel Mode B, conversion data is not
output on the data interface for any of the channels.
Table 21. Channel Mode A/Channel Mode B, Register 0x01
and Register 0x02
Continuous conversion mode is enabled.
Bits Bit Name
Setting Description
Reset Access
SPI CONTROL FUNCTIONALITY
3
FILTER_TYPE_x
Filter output
0x1
RW
SPI control offers the superset of flexibility and diagnostics to
the user. The following sections highlight the functionality and
diagnostics offered when SPI control is used.
0
1
Wideband filter
Sinc5 filter
[2:0] DEC_RATE_x
Decimation rate 0x5
×32 to ×1024
RW
000 to
101
After any change to these configuration register settings, the
user must provide a sync signal to the AD7761 through either
the SPI_SYNC command, or by applying the appropriate pulse
Table 22. Channel Mode Selection, Register 0x03
START
SYNC_IN
to the
pin or
pin to ensure that the configuration
Bits Bit Name
Setting
Description
Channel x
Mode A
Reset Access
changes are applied correctly to the ADC and digital filters.
[7:0] CH_x_MODE
0x0 RW
0
1
Channel Configuration
Mode B
The AD7761 has eight fully differential analog input channels.
The channel configuration registers allow the channels to be
individually configured to adapt to the measurement required
on that channel. Channels can be enabled or disabled using the
channel standby register, Register 0x00. Analog input and
reference precharge buffers can be assigned per input terminal.
Gain, offset, and phase calibration can be controlled on a per
channel basis using the calibration registers. See the Per
Channel Calibration Gain, Offset, and Sync Phase section for
more information.
Reset over SPI Control Interface
Two successive commands must be written to the AD7761 data
control register to initiate a full reset of the device over the SPI
interface. This action fully resets all registers to the default
conditions. Details of the commands and their sequence are
shown in Table 40.
After a reset over the SPI control interface, the AD7761 responds
to the first command sent to the device with 0x0E00. This
response, in addition to the fact that all registers have assumed
their default values, indicates that the software reset succeeded.
Channel Modes
In SPI control mode, the user can set up two channel modes,
Channel Mode A (Register 0x01), and Channel Mode B
(Register 0x02). Each channel mode register can have a specific
filter type and decimation ratio. Using the channel mode select
register (Register 0x03), the user can assign each channel to either
Channel Mode A or Channel Mode B, which maps that mode to
the required ADC channels. These modes allow different filter
types and decimation rates to be selected and mapped to any of the
ADC channels.
Sleep Mode
Sleep mode puts the AD7761 into its lowest power mode. In
sleep mode, all ADCs are disabled and a large portion of the digital
core is inactive.
The AD7761 SPI remains active and is available to the user when in
sleep mode. Write to Register 0x04, Bit 7 to exit sleep mode. For
the lowest power consumption, select the sinc5 filter before
entering sleep mode.
Rev. A | Page 36 of 75
Data Sheet
AD7761
Channel Standby Mode
Interface Configuration
For efficient power usage, place selected channels into standby
mode when not in use. Setting the bits in Register 0x00 disables
the corresponding channel (see Table 34). For maximum power
savings, switch disabled channels to the sinc5 filter using the
channel mode configurations, which disables some clocks
associated with the wideband filters of those channels.
The data interface is a master output interface, where ADC
conversion results are output by the AD7761 at a rate based on
the mode selected. The interface consists of a data clock (DCLK),
DRDY
the data ready (
) framing output, and the data output
pins (DOUT0 to DOUT7).
The interface can be configured to output conversion data on
one, two, or eight of the DOUTx pins. The DOUTx configuration
for the AD7761 is selected using the FORMATx pins (see Table 30).
The VCM voltage output is associated with the Channel 0 circuitry.
If Channel 0 is put into standby mode, the VCM voltage output is
also disabled for maximum power savings. Channel 0 must be
enabled while VCM is being used externally to the AD7761.
The DCLK rate is a direct division of the MCLK input and can
be controlled using Bits[1:0] of Register 0x07. The minimum
DCLK rate can be calculated as
The crystal excitation circuitry is associated with the Channel 4
circuitry. If Channel 4 is put into standby mode, the crystal
circuitry is also disabled for maximum power savings. Channel 4
must be enabled while the external crystal is used on the AD7761.
DCLK (minimum) = Output Data Rate × Channels per
DOUTx × 24 bits
where MCLK ≥ DCLK.
Clocking Selections
With eight ADCs enabled, an MCLK rate of 32.768 MHz, an ODR
of 256 kSPS, and two DOUTx channels, DCLK (minimum) is
The internal modulator frequency (fMOD) used by each of the ADCs
in the AD7761 is derived from the externally applied MCLK
signal. The MCLK division bits allow the user to control the
ratio between the MCLK frequency and the internal modulator
clock frequency. This control allows the user to select the division
ratio that is best for their configuration.
256 kSPS × 4 channels per DOUTx × 24 bits = 24.576 MHz
where DCLK = MCLK/1.
For more information on the status header, CRC, and interface
configuration, see the Data Interface section.
The appropriate clock configuration depends on the power mode,
the decimation rate, and the base MCLK frequency available in
the system. See the Clocking, Sampling Tree section for further
information on setting MCLK_DIV correctly.
CRC Protection
The AD7761 can be configured to output a CRC message per
channel every 4 or 16 samples. This function is available only
with SPI control. CRC is enabled in the interface control register,
Register 0x07 (see the CRC Check on Data Interface section).
MCLK Source Selection
The following clocking options are available as the MCLK input
source in SPI control mode:
ADC Synchronization over SPI
The ADC synchronization over SPI allows the user to request a
synchronization pulse to the ADCs over the SPI interface. To
initiate the synchronization in this manner, write to Bit 7 in
Register 0x06 twice.
•
•
•
LVDS
External crystal
CMOS input MCLK
Setting CLK_SEL to logic low configures the AD7761 for correct
operation using a CMOS clock. Setting CLK_SEL to logic high
enables the use of an external crystal. In SPI control mode, the
FILTER pin must be set to Logic 1 for operation of the external
crystal.
SYNC_OUT
logic high again.
First, the user must write a 0, which sets
low, and
SYNC_OUT
then write a 1 to set the
The SPI_SYNC command is recognized after the last rising
edge of SCLK in the SPI instruction, where the SPI_SYNC bit is
changed from low to high. The SPI_SYNC command is then
output synchronously to the AD7761 MCLK signal on
If CLK_SEL is set to logic high and Bit 3 of Register 0x04 is also
set, the application of an LVDS clock signal to the MCLK pin is
enabled. LVDS clocking is exclusive to SPI control mode and
requires the register selection for operation (see Table 38).
SYNC_OUT
SYNC_OUT
the
signal to the
pin. The user must connect the
SYNC_IN
pin on the PCB.
The DCLK rate is derived from MCLK. DCLK division (the
ratio between MCLK and DCLK) is controlled in the interface
configuration selection register, Register 0x07 (see Table 41).
Rev. A | Page 37 of 75
AD7761
Data Sheet
IOVDD
Per Channel Calibration Gain, Offset, and Sync Phase
The user can adjust the gain, offset, and sync phase of the
AD7761. These options are available only in SPI control mode.
Further register information and calibration instructions are
available in the Offset Registers section, the Gain Registers section,
and the Sync Phase Offset Registers section. See the Calibration
section for information on calibration equations.
AD7761
START
SYNC_OUT
MCLK
SYNCHRONIZATION
LOGIC
MASTER
CLOCK
DIGITAL FILTER
DRDY
DOUT0
DOUT1
SPI INTERFACE
SYNC_IN
GPIOs
DSP/
FPGA
The AD7761 has five GPIO pins available when operating in SPI
control mode. For further information on GPIO configuration,
see the GPIO Functionality section.
Figure 55. Connection Diagram for Synchronization Using SPI_SYNC
SYNC_OUT
SYNC_IN
pins of
The
pin can also be routed to the
SPI CONTROL MODE EXTRA DIAGNOSTIC
FEATURES
RAM Built In Self Test
other AD7761 devices, allowing simultaneous sampling to occur
across larger channel count systems. Any daisy-chained system of
AD7761 devices requires that all ADCs be synchronized.
The read only memory (RAM) built in self test (BIST) is a
coefficient check for the digital filters. The AD7761 DSP path uses
some internal memories for storing data associated with filtering
and calibration. A user may, if desired, initiate a built in self test
(BIST) of these memories. Normal conversions are not possible
while BIST is running. The test is started by writing to the BIST
control register, Register 0x08. The results and status of the test are
available in the status register, Register 0x09 (see Table 43).
In a daisy-chained system of AD7761 devices, two successive
synchronization pulses must be applied to guarantee that all
ADCs are synchronized. Two synchronization pulses are also
required in a system of more than one AD7761 device sharing a
DRDY
single MCLK signal, where the
used to detect new data.
pin of only one device is
SYNC_IN
As per any synchronization pulse present on the
the digital filters of the AD7761 are reset by the SPI_SYNC
pin,
Normal ADC conversion is disrupted when this test is run. A
synchronization pulse is required after this test is complete to
resume normal ADC operation.
command. The full settling time of the filters must then elapse
before valid data is output on the data interface.
Analog Input Precharge Buffers
Revision Identification Number
The AD7761 contains precharge buffers on each analog input to
ease the drive requirements on the external amplifier. Each analog
input precharge buffer can be enabled or disabled using the analog
input precharge buffer registers (see Table 48 and Table 49).
When writing to these registers, the user must write the inverse
of the required bit settings. For example, to clear Bit 1 of this
register, the user must write 0x01 to the register. This clears
Bit 1 and sets all other bits. If the user reads the register again
after writing 0x01, the data read is 0xFE, as required.
The AD7761 contains an identification register that is accessible
in SPI control mode, the revision identification register. This
register is an excellent way to verify the correct operation of the
serial control interface. Register information is available in the
Revision Identification Register section.
Diagnostic Meter Mode
The diagnostic metering mode can be used to verify the
functionality of each ADC by internally passing a positive full-
scale, midscale, or negative full-scale voltage to the ADC. The
user can then read the resulting ADC conversion result to
determine that the ADC is operating correctly. To configure
ADC conversion diagnostics, see the ADC Diagnostic Receive
Select Register section and the ADC Diagnostic Control
Register section.
Reference Precharge Buffers
The AD7761 contains reference precharge buffers on each
reference input to ease the drive requirements on the external
reference and help to settle any nonlinearity on the reference
inputs. Each reference precharge buffer can be enabled or
disabled using the reference precharge buffer registers (see
Table 50 and Table 51).
Rev. A | Page 38 of 75
Data Sheet
AD7761
CIRCUIT INFORMATION
of power modes gives more flexibility to control the bandwidth
and power dissipation for the AD7761. Table 9 shows the
recommended fMOD frequencies for each power mode, and
Table 38 shows the register information for the AD7761.
CORE SIGNAL CHAIN
Each ADC channel on the AD7761 has an identical signal path
from the analog input pins to the data interface. Figure 57 shows
a top level implementation of the core signal chain. Each ADC
channel has its own Σ-Δ modulator that oversamples the analog
input and passes the digital representation to the digital filter block.
The modulator sampling frequency (fMOD) ranges are explained
in the Clocking, Sampling Tree, and Power Scaling section. The
data is filtered, scaled for gain and offset (depending on user
settings), and then output on the data interface. Control of the
flexible settings for the signal chain is provided by either using the
pin control or the SPI control mode, set at power-up by the state of
011 ... 111
011 ... 110
011 ... 101
PIN
the
/SPI input pin.
100 ... 010
100 ... 001
100 ... 000
The AD7761 can use up to a 5 V reference and converts the
differential voltage between the analog inputs (AINx+ and AINx−)
into a digital output. The analog inputs can be configured as either
differential or pseudo differential inputs. As a pseudo differential
input, either AINx+ or AINx− can be connected to a constant
input voltage (such as 0 V, AVSS, or some other reference voltage).
The ADC converts the voltage difference between the analog
input pins into a digital code on the output. Using a common-
mode voltage of AVDD1/2 for the analog inputs, AINx+ and
AINx−, maximizes the ADC input range. The 16-bit conversion
result is in twos complement, MSB first, format. Figure 56
shows the ideal transfer functions for the AD7761.
–FS
–FS + 1LSB
+FS – 1LSB
+FS – 1.5LSB
–FS + 0.5LSB
ANALOG INPUT
Figure 56. ADC Ideal Transfer Functions (FS is Full Scale)
Table 23. Output Codes and Ideal Input Voltages
Analog Input
(AINx+ − (AINx−)) Digital Output Code,
VREF = 4.096 V
Description
Twos Complement (Hex.)
FS − 1 LSB
+4.095875 V
0x7FFF
0x0001
0x0000
0xFFFF
0x8001
0x8000
Midscale + 1 LSB +125 µV
Midscale 0 V
Midscale − 1 LSB −125 µV
−FS + 1 LSB
−FS
ADC Power Modes
The AD7761 has three selectable power modes. In pin control
mode, the modulator rate and power mode are tied together for
best performance. In SPI control mode, the user can select the
power mode and modulator MCLK divider settings. The choice
−4.095875 V
−4.096 V
MCLK
START
SYNC_OUT
SYNC_IN
RESET
SIGNAL CHAIN
FOR SINGLE CHANNEL
PRECHARGE
BUFFER
DRDY
DOUTx
DCLK
AINx+
AINx–
DATA
INTERFACE
CONTROL
Σ-Δ
DIGITAL
FILTER
MODULATOR
ESD
PROTECTION
CONTROL BLOCK
PIN/SPI
CONTROL
OPTION
PIN OR SPI
PIN CONTROL
SPI CONTROL
FILTER/GPIO4 MODE3/GPIO3
CS SCLK SDO SDI
TO
MODE0/GPIO0
Figure 57. Top Level Core Signal Chain and Control
Rev. A | Page 39 of 75
AD7761
Data Sheet
0
–5
ANALOG INPUTS
PRECHARGE BUFFERED AINx+
PRECHARGE BUFFERED AINx–
Figure 58 shows the AD7761 analog front end. The electrostatic
discharge (ESD) protection diodes that are designed to protect
the ADC from some short duration overvoltage and ESD events
are shown on the signal path. The analog input is sampled at
twice the modulator sampling frequency, fMOD, which is derived
from MCLK. By default, the ADC internal sampling capacitors,
CS1 and CS2, are driven by a per channel analog input precharge
buffer to ease the driving requirement of the external network.
–10
–15
–20
–25
–30
BPS 0+
AVDD1
PHI 0
AIN0+
CS1
CS2
0
1
2
3
4
PHI 1
INPUT VOLTAGE (V
)
DIFF
AVSS
Figure 60. Analog Input Current (AIN) vs. Input Voltage, Analog Input
Precharge Buffer On, VCM = 2.5 V, fMOD = 8.192 MHz
PHI 1
PHI 0
BPS 0–
AVDD1
The analog input precharge buffers can be turned on/off by
means of a register write to Register 0x11 and Register 0x12
(Precharge Buffer Register 1 and Precharge Buffer Register 2,
respectively). When writing to these registers, the user must
write the inverse of the required bit settings. For example, to
clear Bit 1 of this register, the user must write 0x01 to the
register. This clears Bit 1 and sets all other bits. If the user reads
the register again after writing 0x01, the data read is 0xFE, as
required.
AIN0–
AVSS
Figure 58. Analog Front End
The analog input precharge buffers, if enabled, are enabled for a set
period of time for each fMOD cycle. The period of time is dependent
on the power mode of the AD7761. The precharge buffer is on for
approximately 15 ns in fast mode, 29 ns in median mode, and
116 ns in low power mode. For the initial rough charging of the
switched capacitor network, the bypass switches, BPS 0+ and
BPS 0−, remain open during this first phase. For the remaining
phase, the bypass switches are closed, and the fine accuracy
settling charge is provided by the external source. PHI 0 and PHI 1
represent the modulator clock sampling phases that switch the
input signals onto the sampling capacitors, CS1 and CS2.
Each analog input precharge buffer is selectable per channel. In
pin control mode, the analog input precharge buffers are always
enabled for optimum performance.
When the analog input precharge buffers are disabled, the
analog input current is sourced completely from the analog
input source. The unbuffered analog input current is calculated
from two components: the differential input voltage on the
analog input pair, and the analog input voltage with respect to
AVSS. With the precharge buffers disabled, for 32.768 MHz
MCLK in fast mode with fMOD = MCLK/4, the differential input
current is approximately 48 µA/V and the current with respect
to ground is approximately 17 µA/V.
The analog input precharge buffers reduce the switching kickback
from the sampling stage to the external circuitry. The precharge
buffer reduces the average input current by a factor of eight, and
makes the input current more signal independent, to reduce the
effects of sampling distortion. This reduction in drive requirements
allows pairing of the AD7761 with lower power, lower bandwidth
front-end driver amplifiers such as the ADA4940-1/ADA4940-2.
400
For example, if the precharge buffers are off, with AIN1+ = 5 V,
and AIN1− = 0 V, estimate the current in each input pin as
follows:
300
200
100
0
AIN1+ = 5 V × 48 µA/V + 5 V × 17 µA/V = 325 µA
AIN1− = −5 V × 48 µA/V + 0 V × 17 µA/V = −240 µA
When the precharge buffers are enabled, the absolute voltage with
respect to AVSS determines the majority of the current. The
maximum input current of approximately −25 µA is measured
when the analog input is close to either the AVDD1 or AVSS rails.
–100
–200
With either precharge buffers enabled or disabled, the analog
input current scales linearly with the modulator clock rate. The
analog input current vs. input voltage is shown in Figure 59.
–300
UNBUFFERED AINx+
UNBUFFERED AINx–
–400
0
1
2
3
4
5
6
INPUT VOLTAGE (V
)
DIFF
Figure 59. Analog Input Current (AIN) vs. Input Voltage, Analog Input
Precharge Buffer Off, VCM = 2.5 V, fMOD = 8.192 MHz
Rev. A | Page 40 of 75
Data Sheet
AD7761
Full settling of the analog inputs to the ADC requires the use of an
external amplifier. Pair amplifiers such as the ADA4805-2 for low
power mode, or the ADA4805-2 or ADA4940-1/ADA4940-2 for
median and fast modes, with the AD7761 (see Table 24 for details
on some of these pairings). Running the AD7761 in median and
low power modes or reducing the MCLK rate reduces the load
and speed requirements of the amplifier; therefore, lower power
amplifiers can be paired with the analog inputs to achieve the
optimum signal chain efficiency.
VCM
AD7761
ADA4805-2
+INx
–INx
RIN
RIN
AINx+
AINx–
C1
C2
24-BIT
Σ-Δ
ADC
C3
PRECHARGE
BUFFERS
There is a resistor/capacitor (RC) network between the
amplifier output and the ADC input. Figure 61 shows a typical
RC network used for the AD7761 for most amplifier pairings.
The RC network performs a variety of tasks. C1 and C2 are
charge reservoirs to the ADC, providing the ADC with fast
charge current to the sampling capacitors.
Figure 61. Typical Input Structure for an RC Network
VCM
The AD7761 provides a buffered common-mode voltage output
on Pin 59. This output can bias up analog input signals. By
incorporating the VCM buffer into the ADC, the AD7761
reduces component count and board space. In pin control
mode, the VCM potential is fixed to (AVDD1 − AVSS)/2, and
is enabled by default.
Capacitor C3 removes common-mode errors between the
AINx+ and AINx− inputs. These capacitors, in combination
with RIN, form a low-pass filter to filter out glitches related to
the input switching. The input resistance also stabilizes the
amplifier when driving large capacitor loads and prevents the
amplifier from oscillating.
In SPI control mode, configure the VCM potential using the
general configuration register (Register 0x05). The output can
be enabled or disabled, and set to (AVDD1 − AVSS)/2, 1.65 V,
2.14 V, or 2.5 V, with respect to AVSS.
The optimum driver amplifiers for each of these requirements
of power, performance, and supply are as follows:
The VCM voltage output is associated with the Channel 0
circuitry. If Channel 0 is put into standby mode, the VCM
voltage output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used externally
to the AD7761.
•
The ADA4805-2 is suited for low power, particularly in low
power mode.
•
The ADA4940-1 is suited for single-supply operation,
which is also the recommended fully differential amplifier
to drive the AD7761.
For more details, see the AN-1384.
Table 24. Amplifier Pairing Options
Amplifier Power
Analog Input Precharge
Buffer
Total Power (Amplifier + AD7761)
(mW/channel)1
Power Mode Amplifier
(mW/channel)1
Fast
Median
Low Power
ADA4940-2
ADA4805-2
ADA4805-2
13.4
6.9
6.5
On
On
On
64.9
34.4
15.9
1 Typical power at 25°C.
Rev. A | Page 41 of 75
AD7761
Data Sheet
Three clock source input options are available to the AD7761:
external CMOS, crystal oscillator, or LVDS. The clock is selected on
power-up and is determined by the state of the CLK_SEL pin.
REFERENCE INPUT
The AD7761 has two differential reference input pairs. REF1+
and REF1− are the reference inputs for Channel 0 to Channel 3,
and REF2+ and REF2− are for Channel 4 to Channel 7. The
absolute input reference voltage range is 1 V to AVDD1 − AVSS.
If CLK_SEL = 0, the CMOS clock option is selected and the
clock is applied to Pin 32 (Pin 31 is tied to DGND).
If CLK_SEL = 1, the crystal or LVDS option is selected and the
crystal or LVDS is applied to Pin 31 and Pin 32. The LVDS
option is available only in SPI control mode. An SPI write to
Bit 3 of Register 0x04 enables the LVDS clock option.
Like the analog inputs, the reference inputs have a precharge buffer
option. Each ADC has an individual buffer for each REFx+ and
REFx−. The precharge buffers help reduce the burden on the
external reference circuitry.
In pin control mode, the reference precharge buffers are off by
default. In SPI control mode, the user can enable or disable the
reference precharge buffers. In the case of unipolar analog supplies,
in SPI control mode, the user can achieve the best performance and
power efficiency by enabling only the REFx+ buffers. The reference
input current scales linearly with the modulator clock rate.
DIGITAL FILTERING
The AD7761 offers two types of digital filters. In SPI control
mode, these filters can be chosen on a per channel basis. In pin
control mode, only one filter can be selected for all channels. The
digital filters available on the AD7761 are
•
•
Sinc5 low latency filter, −3 dB at 0.204 × ODR
Wideband low ripple filter, −3 dB at 0.433 × ODR
For 32 MHz MCLK and MCLK/4 fast mode, the differential
input current is ~72 µA/V per channel, unbuffered, and
~16 µA/V per channel with the precharge buffers enabled.
Both filters can be operated in one of six different decimation rates,
allowing the user to choose the optimal input bandwidth and speed
of the conversion vs. the desired power mode or resolution.
With the precharge buffers off, REFx+ = 5 V, and REFx− = 0 V,
REFx = 5 V × 72 µA/V = 360 µA
Sinc5 Filter
With the precharge buffers on, REFx+ = 5 V, and REFx− = 0 V,
REFx = 5 V × 16 µA/V = 80 µA
Most precision Σ-Δ ADCs use a sinc filter. The sinc5 filter offered
in the AD7761 enables a low latency signal path useful for dc
inputs, for control loops, or where other specific postprocessing
is required. The sinc5 filter path offers the lowest noise and power
consumption. The sinc5 filter has a −3 dB BW of 0.204 × ODR.
Table 11 contains the noise performance for the sinc5 filter across
power modes and decimation ratios.
For the best performance and headroom, it is recommended to
use a 4.096 V reference such as the ADR444 or the ADR4540.
For the best performance at high sampling rates, it is recommended
to use an external reference drive amplifier such as the ADA4841-1
or the AD8031. Figure 62 shows a configuration diagram of the
reference connection.
0
–20
–40
V
IN
REFx+
V
V
OUT
IN
–60
ADA4841-1
ADR4540
AD7761
–80
REFx–
–100
–120
–140
–160
–180
–200
Figure 62. Typical Reference Input Configuration Diagram
CLOCK SELECTION
The AD7761 has an internal oscillator used for initial power-up
of the device. After the AD7761 completes the start-up routine,
the device normally transfer control of the internal clocking to
the externally applied MCLK. The AD7761 counts the falling
edges of the external MCLK over a given number of internal clock
cycles to determine if the clock is valid and at least a frequency of
1.15 MHz. If there is a fault with the external MCLK, the transfer of
control does not occur, the AD7761 outputs an error in the
status header, and the clock error bit is set in the device status
register. No conversion data is output and a reset is required to
exit this error state.
0
2
4
6
8
10
12
14
16
NORMALIZED INPUT FREQUENCY (fIN
/
fODR)
Figure 63. Sinc5 Filter Frequency Response (Decimation = ×32)
The settling times for the AD7761 when using the sinc5 filter are
shown in Table 26.
Rev. A | Page 42 of 75
Data Sheet
AD7761
0
–10
Wideband Low Ripple Filter
The wideband filter, referred to as a brick wall filter, has a low ripple
pass band, within 0.005 dB of ripple, of 0.4 × ODR. The wideband
filter has full attenuation at 0.499 × ODR (Nyquist), maximizing
antialias protection. The wideband filter has a pass-band ripple of
0.005 dB and a stop band attenuation of 105 dB from Nyquist
out to fCHOP. For more information on antialiasing and fCHOP
aliasing, see the Antialiasing section.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
The wideband filter is a very high order digital filter with a group
delay of approximately 34/ODR. After a synchronization pulse,
SYNC_IN
there is an additional delay from the
rising edge to
fully settled data. The settling times for the AD7761 when using
the wideband filter are shown in Table 25. See Table 10 for the
noise performance of the wideband filter across power modes
and decimation rates.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED INPUT FREQUENCY (fIN
/
fODR)
Figure 64. Wideband Filter Frequency Response
0.010
0.008
0.006
0.004
0.002
0
Filter Settling Time
The AD7761 digital filters are resynchronized on the rising edge
of the SYNC_IN signal. This resynchronization should be
provided after power-up in pin control mode or SPI control
mode, and after any reconfiguration of the device in SPI control
mode, prior to capturing ADC samples. Once the SYNC_IN
rising edge is provided, there is a deterministic delay until the
first new conversion result is available, and until the first settled
data is available.
–0.002
–0.004
–0.006
–0.008
–0.010
Table 25 and Table 26 provide these delays, measured in MCLK
cycles, for wideband and sinc5 filters, respectively, for each
possible setting of MCLK_DIV. Each table provides the delays
for configurations in which all channels are using the exact
same configuration (Group B unused), and for configurations
in which one or more channels have a different decimation rate
applied (Group B is used).
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
NORMALIZED INPUT FREQUENCY (fIN
/
fODR
)
Figure 65. Wideband Filter Pass-Band Ripple
1.2
1.0
0.8
0.6
0.4
0.2
0
For example, if a user configures channels with the wideband
filter and MCLK_DIV = MCLK/4, and assigns some channels
to Group A with decimate x32 and others to Group B with
DRDY
decimate x64, then the delay until the first
after the
SYNC_IN is 758 MCLK periods. All active channels then output
the first data after 758 MCLK periods. However, due to differing
decimation rates across channels, in this case the first settled
data becomes available for the Group A channels 8,822 MCLK
periods after SYNC_IN, and after 17,014 MCLK periods for
Group B channels.
–0.2
0
10
20
30
40
50
60
70
80
OUTPUT DATA RATE SAMPLES
Figure 66. Wideband Filter Step Response
Rev. A | Page 43 of 75
AD7761
Data Sheet
SYNC_IN
Table 25. Wideband Filter
to Settled Data
Delay from First MCLK Rise After SYNC_IN
Rise to Earliest Settled Data, DRDY Rise
Delay from First MCLK
Rise After SYNC_IN Rise to
First DRDY Rise
Filter Type
Group A Group B
Decimation Factor
Group A Group B
Group A
MCLK Periods
8400
Group B
MCLK_DIV
Setting
MCLK Periods
336
620
1187
2325
4601
9153
758
MCLK Periods
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
8822
MCLK/4
MCLK/8
MCLK/32
Wideband Wideband 32
Wideband Wideband 64
Wideband Wideband 128
Wideband Wideband 256
Wideband Wideband 512
Wideband Wideband 1024
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 64
Wideband Wideband 128
Wideband Wideband 256
Wideband Wideband 512
Wideband Wideband 1024
Wideband Wideband 32
Wideband Wideband 64
Wideband Wideband 128
Wideband Wideband 256
Wideband Wideband 512
Wideband Wideband 1024
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 64
Wideband Wideband 128
Wideband Wideband 256
Wideband Wideband 512
Wideband Wideband 1024
Wideband Wideband 32
Wideband Wideband 64
Wideband Wideband 128
Wideband Wideband 256
Wideband Wideband 512
Wideband Wideband 1024
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 32
Wideband Wideband 64
Wideband Wideband 128
Wideband Wideband 256
Wideband Wideband 512
Wideband Wideband 1024
Unused
Unused
Unused
Unused
Unused
Unused
32
64
128
256
512
1024
32
32
32
32
16,748
33,443
66,837
133,625
267,201
8822
758
758
758
758
758
759
760
762
8822
8822
8822
8822
17,014
33,526
66,934
133,622
267,253
8823
8824
8826
8822
17,015
33,528
66,938
133,646
267,302
16,784
33,481
66,871
133,659
267,235
534,387
16,948
16,948
16,948
16,948
16,948
16,948
33,590
66,872
133,708
267,332
534,612
67,099
133,879
267,439
534,591
1,068,895
2,137,503
67,099
67,099
67,099
67,099
67,099
67,099
134,683
267,803
535,067
1,069,595
2,137,627
782
806
8846
8870
32
Unused
Unused
Unused
Unused
Unused
Unused
32
64
128
256
512
1024
32
32
32
32
656
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
16,948
33,588
66,868
133,684
267,316
534,580
16,950
16,952
16,972
16,964
16,980
1225
2359
4635
9187
18,291
820
820
820
820
820
820
822
824
844
836
852
32
Unused
Unused
Unused
Unused
Unused
Unused
32
64
128
256
512
1024
32
32
32
32
2587
4855
9391
18,495
36,703
73,119
2587
2587
2587
2587
2587
2587
2587
2587
2587
2587
2587
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
67,099
134,683
267,803
535,067
1,069,595
2,137,627
67,099
67,099
67,099
67,099
67,099
32
Rev. A | Page 44 of 75
Data Sheet
AD7761
SYNC_IN
Table 26. Sinc5 Filter
to Settled Data
Delay from First MCLK Rise After SYNC_IN
Rise to Earliest Settled Data, DRDY Rise
Delay from First MCLK
Rise After SYNC_IN Rise
to First DRDY Rise
Filter Type
Decimation Factor
Group A
MCLK Periods
839
Group B
MCLK Periods
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
839
Power
Mode
Group A
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Group B
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Sinc5
Group A
32
Group B
Unused
Unused
Unused
Unused
Unused
Unused
32
MCLK Periods
199
327
MCLK/4
MCLK/8
MCLK/32
64
1607
3143
6215
128
256
512
1024
32
32
32
32
32
32
64
1024
32
64
128
256
512
1024
32
32
32
32
32
32
64
1024
32
64
128
256
512
1024
32
32
32
32
32
583
1095
2119
4167
199
12359
24,647
839
64
128
256
512
1024
32
32
199
839
1607
199
839
3143
199
839
6215
199
839
12,359
199
839
24,647
199
1607
839
199
24,647
1663
839
Unused
Unused
Unused
Unused
Unused
Unused
32
64
128
256
512
383
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
1663
639
3199
6271
12,415
24,703
49,279
1663
1151
2175
4223
8319
383
383
1663
3199
383
1663
6271
398
1663
12,415
398
1663
24,703
1024
32
32
398
1663
49,279
383
3199
1663
398
49,279
6607
1663
Unused
Unused
Unused
Unused
Unused
Unused
32
64
128
256
512
1487
2511
4559
8655
16,847
33,231
1487
1487
1487
1487
1487
1487
1487
1487
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
6607
12,751
25,039
49,615
98,767
12,751
25,039
49,615
98,767
197,071
6607
6607
6607
6607
6607
32
64
1024
1024
32
32
6607
12,751
197,071
197,071
6607
6607
Rev. A | Page 45 of 75
AD7761
Data Sheet
The modulator has no rejection to signals that are at frequencies in
zones around 2 × fMOD and all even multiples of fMOD. Signals at
these frequencies are aliased by the AD7761. For the AD7761,
DECIMATION RATE CONTROL
The AD7761 has programmable decimation rates for the digital
filters. The decimation rates allow the user to reduce the measure-
ment bandwidth, reducing the speed but increasing the resolution.
When using the SPI control, control the decimation rate on the
AD7761 through the channel mode registers. These registers set
two separate channel modes with a given decimation rate and
filter type. Each ADC is mapped to one of these modes via the
channel mode select register. Table 27 details both the decimation
rates available, and the filter types for selection, within Channel
Mode A and Channel Mode B.
the first of these zones that requires protection is at 2 × fMOD
.
Because typical switch capacitor, discrete time Σ-Δ modulators
provide no protection to aliasing at the frequency, fMOD, the
AD7761 provides a distinct advantage in this regard.
Figure 67 shows the frequency response of the modulator and
wideband digital filter to out of band tones at the analog input.
Figure 67 shows the magnitude of an alias that is seen in band
vs. the frequency of the signal sampled at the analog input. The
relationship between the input signal and the modulator frequency
is expressed in a normalized manner as a ratio of the input signal
frequency (fIN) to the modulator frequency (fMOD). This data
demonstrates the ADC frequency response relative to out of band
tones when using the wideband filter. The fIN is swept from dc to
20 MHz. In fast mode, using an 8.192 MHz fMOD frequency, the
x-axis spans ratios of fIN/fMOD from 0 to 2.44 (equivalent to fIN of
0 Hz to 20 MHz). A similar characteristic occurs in median and
low power modes.
In pin control mode, the decimation ratio is controlled by the
DEC0 and DEC1 pins; see Table 15 for the decimation
configuration in pin control mode.
Table 27. Channel Mode x Registers, Register 0x01 and
Register 0x02
Bits
Name
Logic Value
Decimation Rate
3
FILTER_TYPE_x
0
Wideband filter
Sinc5 filter
32
64
128
256
512
1024
1024
1024
1
[2:0]
DEC_RATE_x
000
001
010
011
100
101
110
111
The notch appears in Figure 67 with fIN at fMOD (designated at
fIN/fMOD = 1.00 on the x-axis). An input at this frequency is
attenuated by 35 dB, which adds to the attenuation of any external
antialiasing filter, thus reducing the frequency roll-off require-
ment of the external filter. If the plot is swept further in frequency,
the notch is seen to recur at fIN/fMOD = 3.00.
The point where fIN = 2 × fMOD (designated on the x-axis at 2.00)
offers 0 dB attenuation, indicating that all signals falling at this
frequency alias directly back into the ADC conversion results, in
accordance with the sampling theory.
ANTIALIASING
Because the AD7761 is a switched capacitor, discrete time ADC,
the user may want to employ external analog antialiasing filters to
protect against foldback of out of band tones.
The AD7761 wideband digital filter also offers an added
protection against aliasing. Because the wideband filter has full
attenuation at the Nyquist frequency (fODR/2, where fODR = fMOD
/
Within this section, an out of band tone refers to an input fre-
quency greater than the pass band frequency specification of
the digital filter that is applied at the analog input.
Decimation Rate), input frequencies, and in particular harmonics
of input frequencies, that may fall close to fODR/2, do not fold back
into the pass band of the AD7761.
When designing an antialiasing filter for the AD7761, three main
aliasing regions must be taken into account. After the alias
requirements of each zone are understood, the user can design
an antialiasing filter to meet the needs of the specific application.
The three zones for consideration are related to the modulator
sampling frequency, the modulator chopping frequency, and the
modulator saturation point.
0
–10
–20
fCHOP
fCHOP
=
=
fMOD/32
fMOD/8
–30
–40
–50
–60
–70
–80
Modulator Sampling Frequency
–90
The AD7761 modulator signal transfer function includes a notch,
at odd multiples of fMOD, to reject tones or harmonics related to
the modulator clock. The modulator itself attenuates signals at
frequencies of fMOD, 3 × fMOD, 5 × fMOD, and so on. For an MCLK
frequency of 32.768 MHz, the attenuation is approximately
35 dB in fast mode, 41 dB in median mode, and 53 dB in low
power mode. Attenuation is increased by 6 dB across each power
mode, with every halving of the MCLK frequency, for example,
when reducing the clock from 32.768 MHz to 16.384 MHz.
–100
–110
–120
–130
–140
fIN/fMOD
Figure 67. Rejection of Out of Band Input Tones, Wideband Filter,
Decimation = ×32, fMOD = 8.192 MHz, Analog Input Sweep from DC to 20 MHz
Rev. A | Page 46 of 75
Data Sheet
AD7761
Modulator Chopping Frequency
Modulator Saturation Point
Figure 67 plots two scenarios that relate to the chopping frequency
of the AD7761 modulator.
A Σ-Δ modulator can be considered a standard control loop,
employing negative feedback. The control loop works to ensure
that the average processed error signal is very small over time. It
uses an integrator to remember preceding errors and force the
mean error to be zero. As the input signal rate of change increases
with respect to the modulator clock, fMOD, a larger voltage feedback
error is processed. Above a certain frequency, the error begins
to saturate the modulator.
The AD7761 uses a chopping technique in the modulator similar
to that of a chopped amplifier to remove offset, offset drift, and
1/f noise. The AD7761 default chopping rate is fMOD/32. In pin
control mode, the chop frequency is hardwired to fMOD/32. In
SPI control mode, the user can select the chop frequency to be
either fMOD/32 or fMOD/8.
For the AD7761, the modulator may saturate for full-scale input
frequencies greater than fMOD/16 (as shown in Figure 68),
depending on the rate of change of input signal, input signal
amplitude, and reference input level. A half power input tone at
As shown in Figure 67, the stop band rejection of the digital
filter is reduced at frequencies that relate to even multiples of
the chopping frequency (fCHOP). All other out of band frequencies
(excluding those already discussed relating to the modulator
clock frequency, fMOD) are rejected by the stop band attenuation
of the digital filter. An out of band tone with a frequency in the
f
MOD/8 can also cause the modulator to saturate. In applications
where there may be high amplitude and frequency out of band
tones, a first-order antialiasing filter is required with a −3 dB
corner frequency set at fMOD/16 to protect against modulator
saturation. For example, if operating the AD7761 at full speed
and using a decimation rate of ×32 to achieve an output data
rate of 256 kSPS, the modulator rate is equal to 8.192 MHz. In
this instance, to protect against saturation, set the antialiasing
filter −3 dB corner frequency to 512 kHz.
range of (2 × fCHOP
)
f3dB, where f3dB is the filter bandwidth
employed, is attenuated to the envelope determined by the chop
frequency setting (see Figure 67), and aliased into the pass
band. Out of band tones near additional even multiples of fCHOP
(that is, N × fCHOP, where N is an even integer), are attenuated
and aliased in the same way.
Chopping at fMOD/32 offers the best performance for noise,
offset, and offset drift for the AD7761.
3
0
–3
For ac performance it may be useful to select chopping at fMOD/8
as this moves the first chopping tone to a higher frequency.
However, chopping at fMOD/8 may lead to slightly degraded
noise (approximately 1 dB loss in dynamic range) and offset
performance compared to the default chop rate of fMOD/32.
–6
–9
–12
–15
–18
–21
Table 28 shows the aliasing achieved by different order anti-
aliasing filter options at the critical frequencies of fMOD/32 and
f
MOD/8 for chop aliasing, fMOD/16 for modulator saturation, and
2 × fMOD for the first zone with 0 dB attenuation. It assumes the
corner frequency of the antialiasing filter is at fMOD/64, which is
just above the maximum input bandwidth that the AD7761
digital filter can pass when using a decimate by 32 filter setting.
–24
–27
MAX SIGNAL
FIRST ORDER (fMOD/64)
0.0004
0.004
0.04
0.4
fIN/fMOD
Figure 68. Maximum Input Signal vs. Frequency
Table 28. External Antialiasing Filter Attenuation
f
MOD/32
fMOD/16
(dB)
fMOD/8
(dB)
2 × fMOD
(dB)
RC Filter
(dB)
First Order
Second Order −12
Third Order −18
−6
−12
−24
−36
−18
−36
−54
−42
−84
−126
Rev. A | Page 47 of 75
AD7761
Data Sheet
the ADC input channels, relative to one another. The range of
CALIBRATION
phase compensation is limited to a maximum of one conversion
cycle, and the resolution of the correction depends on the
decimation rate in use.
In SPI control mode, the AD7761 offers users the ability to adjust
offset, gain, and phase delay on a per channel basis.
Offset Adjustment
Table 29 displays the resolution and register bits used for phase
offset for each decimation ratio.
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_
OFFSET_LSB registers are 24-bit, signed twos complement
registers for channel offset adjustment. If the channel gain setting is
at its ideal nominal value of 0x555555, an LSB of offset register
adjustment changes the digital output by −1/192 LSBs. For
example, changing the offset register from 0 to 4800 changes the
digital output by −25 LSBs. Because offset calibration occurs
before gain calibration, the ratio of −1/192 changes linearly with
gain adjustment via the Channel x gain registers (see Table 53).
After a reset or power cycle, the offset register values revert to the
default factory setting.
Table 29. Phase Delay Resolution
Decimation
Ratio
Sync Phase Offset
Register Bits
Resolution Steps
×32
×64
×128
×256
×512
×1024
1/fMOD
1/fMOD
1/fMOD
1/fMOD
2/fMOD
4/fMOD
32
64
128
256
256
256
[7:3]
[7:2]
[7:1]
[7:0]
[7:0]
[7:0]
Gain Adjustment
Adjusting the sync phase of channels can affect the time to the
DRDY
of the header status (filter not settled data bit) being cleared,
that is, the time to settled data.
first
pulse after the sync pulse, as well as the time to Bit 6
Each ADC channel has an associated gain coefficient. The
coefficient is stored in three single-byte registers split up as
MSB, MID, and LSB. Each of the gain registers are factory
programmed. Nominally, this gain is around the value 0x555555
(for an ADC channel). The user can overwrite the gain register
setting. However, after a reset or power cycle, the gain register
values revert to the hard coded programmed factory setting.
If all channels are using the sinc5 filter, the time to the
DRDY
first
pulse is not affected by the adjustment of the sync
phase offset, assuming that at least one channel has zero sync
phase offset adjustment. If all channels have a nonzero sync phase
DRDY
offset setting, the time to the first
pulse is delayed
Calculate the approximate result that is output using the
following formula:
according to the channel that has the least offset applied.
Channels with a sync offset adjustment setting that delays the
internal sync signal, relative to other channels, may not output
3×VIN
VREF
Gain 4,194,300
1024
Data =
×221 −(Offset) ×
×
242
DRDY
settled data until after the next
pulse. In other words,
where:
there may be a delay of one ODR period between the settled
data being output by the AD7761 for the channels with added
phase delay.
Offset is the offset register setting.
Gain is the gain register setting.
Sync Phase Offset Adjustment
If all channels are using the wideband filter, the time to the
DRDY
first
pulse and the time to settled data is delayed
The AD7761 has one synchronization signal for all channels.
The sync phase offset register allows the user to vary the phase
delay on each channel relative to the synchronization edge
according to the channel with the maximum phase delay
setting. In this case, the interface waits for the latest channel and
outputs data for all channels when that channel is ready.
SYNC_IN
received on the
By default, all ADC channels react simultaneously to
SYNC_IN
pin.
the
pulse. The sync phase registers can be
programmed to equalize known external phase differences on
Rev. A | Page 48 of 75
Data Sheet
AD7761
DATA INTERFACE
Higher DCLK rates make it easier to receive the conversion data
from the AD7761 with a lower number of DOUTx lines;
however, there is a trade-off against ADC offset performance
with higher DCLK frequencies. For the best offset and offset
drift performance, use the lowest DCLK frequency possible.
The user can choose to reduce the DCLK frequency by an
appropriate selection of MCLK frequency, DCLK divider,
and/or the number of DOUTx lines used.
SETTING THE FORMAT OF DATA OUTPUT
The data interface format is determined by setting the
FORMATx pins. The logic state of the FORMATx pins is read
on power-up and determines how many data lines (DOUTx) the
ADC conversions are output on.
Because the FORMATx pins are read on power-up of the
AD7761 and the device remains in this output configuration,
this function must always be hardwired and cannot be altered
dynamically. Table 30, Figure 69, Figure 70, and Figure 71 show
the formatting configuration for the digital output pins on the
AD7761.
Table 30. FORMATx Truth Table
FORMAT1
FORMAT0 Description
0
0
Each ADC channel outputs on its own
dedicated pin. DOUT0 to DOUT7 are
in use.
Calculate the minimum required DCLK rate for a given data
interface configuration as follows:
0
1
1
The ADCs share the DOUT0 and
DOUT1 pins: Channel 0 to Channel 3
output on DOUT0. Channel 4 to
Channel 7 output on DOUT1. The ADC
channels share data pins in time
division multiplexed (TDM) output.
DOUT0 and DOUT1 are in use.
DCLK (minimum) = Output Data Rate × Channels per
DOUTx × 24
where MCLK ≥ DCLK.
For example, if MCLK = 32.768 MHz, with two DOUTx lines,
DCLK (minimum) = 256 kSPS × 4 channels per DOUTx ×
24 = 24.576 MHz
X
All channels output on the DOUT0 pin,
in TDM output. Only DOUT0 is in use.
Therefore, DCLK = MCLK/1 is required.
Alternatively, if MCLK = 32.768 MHz, with eight DOUTx lines,
DCLK (minimum) = 256 kSPS × 1 channel per DOUTx ×
24 = 6.144 MHz
Therefore, DCLK = MCLK/4 (DCLK = 8.192 MHz) is
sufficient.
AD7761
DRDY
DCLK
CH 0
CH 1
DOUT0
DOUT1
FORMAT0
FORMAT1
EACH ADC HAS A
DEDICATED DOUTx PIN
0
0
CH 7
DOUT7
DGND
DAISY-CHAINING IS
NOT POSSIBLE IN THIS FORMAT
Figure 69. FORMATx = 00, Eight Data Output Pins
AD7761
DRDY
DCLK
IOVDD
CHANNEL 0 TO CHANNEL 3
DOUT0
DOUT1
1
0
OUTPUT ON DOUT0
FORMAT0
FORMAT1
CHANNEL 4 TO CHANNEL 7
OUTPUT ON DOUT1
DGND
DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT
Figure 70. FORMATx = 01, Two Data Output Pins
Rev. A | Page 49 of 75
AD7761
Data Sheet
AD7761
DRDY
DCLK
IOVDD
CHANNEL0 TO CHANNEL7
OUTPUT ON DOUT0
1
1
FORMAT0
FORMAT1
DOUT0
DAISY-CHAINING IS
POSSIBLE IN THIS FORMAT
Figure 71. FORMATx = 10 or 11, One Data Output Pin
wideband and sinc5 filters are shown in Table 25 and Table 26,
respectively. This bit is set if this settling delay has not yet elapsed.
ADC CONVERSION OUTPUT: HEADER AND DATA
The AD7761 data is output on the DOUT0 to DOUT7 pins,
depending on the FORMATx pins. The actual structure of the
data output for each ADC result is shown in Figure 72. Each
ADC result comprises 24 bits. The first eight bits are the header
status bits, which contain status information and the channel
number. The names of each of the header status bits are shown
in Table 31, and their functions are explained in the subsequent
sections. This header is followed by a 16-bit ADC output in
twos complement coding, MSB first.
Repeated Data
If different channels use different decimation rates, data outputs
are repeated for the slower speed channels. In these cases, the
header is output as normal with the repeated data bit set to 1,
and the following repeated ADC result is output as all zeros.
This bit indicates that the conversion result of all zeros is not
real; it indicates that there is a repeated data condition because
two different decimation rates are selected. This condition can
only occur during SPI control of the AD7761.
DRDY
Transitions on the
and the DOUTx pins are aligned with
the rising edge of DCLK. See Figure 2 and Table 2 for details.
Filter Type
In pin control mode, all channels operate using one filter
selection. The filter selected in pin control mode is determined
by the logic level of the FILTER pin. In SPI control mode, the
digital filters can be selected on a per channel basis, using the
mode registers. This header bit is 0 for channels using the
wideband filter, and 1 for channels using the sinc5 filter.
DRDY
ADC DATA N
16 BITS
N – 1
HEADER N
8 BITS
DOUTx
Figure 72. ADC Output: 8-Bit Header, 16-Bit ADC Conversion Data
Filter Saturated
Table 31. Header Status Bits
The filter saturated bit indicates that the filter output is clipping at
either positive or negative full scale. The digital filter clips if the
signal goes beyond the specification of the filter; it does not wrap.
The clipping may be caused by the analog input exceeding the
analog input range, or by a step change in the input, which may
cause overshoot in the digital filter. Clipping may also occur
when the combination of the analog input signal and the channel
gain register setting causes the signal seen by the filter to be
higher than the analog input range.
Bit
Bit Name
7
6
5
4
3
[2:0]
ERROR_FLAGGED
Filter not settled
Repeated data
Filter type
Filter saturated
Channel ID[2:0]
ERROR_FLAGGED
The ERROR_FLAGGED bit indicates when a serious error
occurs. If this bit is set, a reset is required to clear this bit. This bit
indicates that the external clock is not detected, a memory map
bit unexpectedly changes state, or an internal CRC error is
detected.
Channel ID
The channel ID bits indicate the ADC channel from which the
succeeding conversion data originates (see Table 32).
Table 32. Channel ID vs. Channel Number
Channel
Channel ID 2
Channel ID 1
Channel ID 0
When an external clock is not detected, the conversion results are
output as all zeros regardless of the analog input voltages
applied to the ADC channels.
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Filter Not Settled
After power-up, reset, or synchronization, the AD7761 clears the
digital filters and begins conversion. Due to the weighting of the
digital filters, there is a delay from the first conversion to fully
settled data. The settling times for the AD7761 when using the
Rev. A | Page 50 of 75
Data Sheet
AD7761
Data Interface: Standard Conversion Operation
Figure 73, Figure 74, and Figure 75 are distinct examples of the
impact of the FORMATx pins on the AD7761 output operating in
standard conversion operation.
In standard mode operation, the AD7761 operates as the master
and streams data to the DSP or FPGA. The AD7761 supplies the
data, the data clock (DCLK), and a falling edge framing signal
Figure 73 to Figure 75 represent running the AD7761 at
maximum data rate for the three FORMATx options.
DRDY
(
) to the slave device. All of these signals are synchronous.
The data interface connections to DSP/FPGA are shown in
Figure 76. The FORMATx pins determine how the data is
output from the AD7761.
Figure 73 shows FORMATx = 00. Each ADC has its own data out
pin running at the MCLK/4 bit rate. In pin control mode, this is
achieved by selecting Mode 0xA (fast mode, DCLK = MCLK/4,
standard conversion, see Table 18) with the decimation rate set
as ×32.
Figure 73 through Figure 75 show the data interface operating
in standard mode at the maximum data rate. In all
DRDY
instances,
the data conversion is made available on the data pin.
DRDY
is asserted one clock cycle before the MSB of
Figure 74 shows FORMATx = 01 sharing DOUT1 at the
maximum bit rate. In pin control mode, this is achieved by
selecting Mode 0x8 (fast mode, DCLK = MCLK/1, standard
conversion) with a decimation rate of ×32.
Each
falling edge starts the output of the new ADC con-
DRDY
version data. The first eight bits output after the
falling edge
are the header bits; the last 16 bits are the ADC conversion result.
If running in pin control mode, the example shown in Figure 75
represents Mode 0x4 (median mode, DCLK = MCLK/1,
standard conversion) with a decimation rate of ×32, giving the
maximum output data capacity possible on one DOUTx pin.
DCLK
SAMPLE N
SAMPLE N + 1
DRDY
DOUT0
DOUT1
DOUT7
Figure 73. FORMATx = 00: Each ADC Has a Dedicated Data Output Pin, Maximum Data Rate
DCLK
SAMPLE N
SAMPLE N + 1
DRDY
CH0 (N)
CH4 (N)
CH1 (N)
CH5 (N)
CH2 (N)
CH6 (N)
CH3 (N)
CH0 (N + 1) CH1 (N + 1) CH2 (N + 1) CH3 (N + 1)
CH4 (N + 1) CH5 (N + 1) CH6 (N + 1) CH7 (N + 1)
DOUT0
CH7 (N)
DOUT1
DOUT2
DOUT7
Figure 74. FORMATx = 01: Channel 0 to Channel 3 Share DOUT0, and Channel 4 to Channel 7 Share DOUT1, Maximum Data Rate
(DOUT6 and DOUT7 Are Inputs in This Configuration)
Rev. A | Page 51 of 75
AD7761
Data Sheet
DCLK
SAMPLE N
SAMPLE N + 1
SAMPLE N + 2
DRDY
DOUT0
DOUT1
DOUT7
Figure 75. FORMATx = 11 or 10: Channel 0 to Channel 7 Output on DOUT0 Only, Maximum Data Rate (DOUT6 and DOUT7 Are Inputs in This Configuration)
DSP/FPGA
AD7761
DCLK
DRDY
DOUT0 TO
DOUT7
MCLK
Figure 76. Data Interface: Standard Conversion Operation, AD7761 = Master, DSP/FPGA = Slave
SYNC_IN
tSETTLE
SETTLED
DATA
SETTLED
DATA
DOUT0
DOUT1
SETTLED
DATA
SETTLED
DATA
SETTLED
DATA
SETTLED
DATA
DOUT7
DRDY
24 DCLKs
24 DCLKs
Figure 77. One-Shot Mode
Rev. A | Page 52 of 75
Data Sheet
AD7761
Data Interface: One-Shot Conversion Operation
Daisy-Chaining
One-shot mode is available in both SPI and pin control modes.
This conversion mode is available by selecting one of Mode 0xC to
Mode 0xF when in pin control mode. In SPI control mode, set
Bit 4 (one-shot mode) of Register 0x06, the data control register.
Figure 77 shows the device operating in one-shot mode.
Daisy-chaining devices allows numerous devices to use the
same data interface lines by cascading the outputs of multiple
ADCs from separate AD7761 devices. Only one ADC device
has its data interface in direct connection with the digital host.
For the AD7761, this connection can be implemented by
cascading DOUT0 and DOUT1 through a number of devices, or
using only DOUT0; whether two data output pins or only one
data output pin is enabled depends on the FORMATx pins. The
ability to daisy-chain devices and the limit on the number of
devices that can be handled by the chain is dependent on the
power mode, DCLK, and the decimation rate employed.
In one-shot mode, the AD7761 is a pseudoslave. Conversions
occur on request by the master device, for example, the DSP or
SYNC_IN
FPGA. The
one-shot mode, all ADCs run continuously; however, the rising
SYNC_IN
pin initiates the conversion request. In
edge of the
pin controls the point in time from which
data is output.
The maximum usable DCLK frequency allowed when daisy-
chaining devices is limited by the combination of timing
specifications in Table 2 or Table 4, as well as by the propagation
delay of the data between devices and any skew between the MCLK
signals at each AD7761 device. The propagation delay and MCLK
skew are dependent on the PCB layout and trace lengths.
SYNC_IN
DRDY
low.
To receive data, the master must pulse the
pin to
subsequently goes
high to indicate to the master device that the device has valid
DRDY
DRDY
reset the filter and force
settled data available. Unlike standard mode,
remains
high for the number of clock periods of valid data before it goes
low again; thus, in this conversion mode, it is an active high
frame of the data.
This feature is especially useful for reducing component count
and wiring connections, for example, in isolated multiconverter
applications or for systems with a limited interfacing capacity.
SYNC_IN
When the master pulses
and the AD7761 receives the
rising edge of this signal, the digital filter is reset and the full
settling time of the filter elapses before the data is available. The
duration of the settling time depends on the filter path and
decimation rate. Running one-shot mode with the sinc5 filter
allows the fastest throughput, because this filter has a lower
settling time than the wideband filter.
When daisy-chaining on the AD7761, DOUT6 and DOUT7
become serial data inputs, and DOUT0 and DOUT1 remain as
serial data outputs under the control of the FORMATx pins.
AD7761
START
SYNC_OUT
MCLK
SYNCHRONIZATION
LOGIC
As soon as settled data is available on any channel, the device
outputs data from all channels. The contents of Bit 6 of the channel
header status bits indicates whether the data is fully settled.
DIGITAL FILTER
DRDY
DOUT0
DOUT1
DOUT6 DOUT7 SYNC_IN
The period before the data is settled on all channels is shown in
Figure 77. The settling time (tSETTLE) for the AD7761 in one-shot
mode is equivalent to the number of clock cycles specified as
DSP/
FPGA
IOVDD
Delay from First MCLK Rise After
Rise to Earliest
SYNC_IN
AD7761
Settled Data,
Rise in Table 26. After the data has settled
DRDY
START
SYNC_OUT
DRDY
MCLK
MASTER
CLOCK
SYNCHRONIZATION
LOGIC
DRDY
DNC
DNC
on all channels,
is asserted high and the device outputs the
DRDY
required settled data on all channels before
is asserted low.
DIGITAL FILTER
If the user configures the same filter and decimation rate on each
DRDY
DOUT0
DOUT1
ADC, the data is settled for all channels on the first
DOUT6 DOUT7 SYNC_IN
output frame, which avoids a period of unsettled data prior to
the settled data and ensures that all data is output at the same time
IOVDD
SYNC_IN
on all ADCs. The device then waits for another
before outputting more data.
signal
AD7761
START
MCLK
SYNC_OUT
DRDY
SYNCHRONIZATION
LOGIC
DNC
DNC
Because all the ADCs are sampling continuously, one-shot
mode affects the sampling theory of the AD7761. Particularly, a
DIGITAL FILTER
SYNC_IN
user periodically sending a
form of subsampling of the ADC output. The subsampling occurs
SYNC_IN SYNC_IN
pulse must be
pulse to the device is a
DOUT0
DOUT1
DOUT6 DOUT7 SYNC_IN
at the rate of the
pulses. The
Figure 78. Daisy-Chaining Multiple AD7761 Devices
synchronous with the master clock to ensure coherent sampling
and to reduce the effects of jitter on the frequency response.
Rev. A | Page 53 of 75
AD7761
Data Sheet
Figure 78 shows an example of daisy-chaining AD7761 devices,
when FORMATx = 01. In this case, the DOUT1 and DOUT0 pins
of the AD7761 devices are cascaded to the DOUT6 and DOUT7
pins of the next device in the chain. Data readback is analogous
to clocking a shift register where data is clocked out on the rising
edge of DCLK. Input data on the DOUT6 and DOUT7 pins is
sampled on the falling edge of DCLK.
Synchronization
An important consideration for daisy-chaining more than two
AD7761 devices is synchronization. The basic provision for
synchronizing multiple devices is that each device is clocked
with the same base MCLK signal.
The AD7761 offers three options to allow ease of system synchro-
nization. Choosing between the options depends on the system, but
is determined by whether the user can supply a synchronization
pulse that is truly synchronous with the base MCLK signal.
The scheme operates by passing the output data of the DOUT0
and DOUT1 pins of an AD7761 upstream device to the DOUT6
and DOUT7 inputs of the next AD7761 device downstream in the
chain. The data then continues through the chain until it is clocked
onto the DOUT0 and DOUT1 pins of the final downstream
device in the chain.
If the user cannot provide a signal that is synchronous to the
base MCLK signal, one of the following two methods can be
employed:
START
•
Apply a
AD7761 device samples the asynchronous
SYNC_OUT
pulse to the first AD7761 device. The first
Daisy-chaining can be achieved in a similar manner on the
AD7761 when using only the DOUT0 pin. In this case, only
Pin 21 of the AD7761 is used as the serial data input pin.
START
pulse
of the first device
and generates a pulse on
related to the base MCLK signal for distribution locally.
Use synchronization over SPI (only available in SPI control
mode) to write a synchronization command to the first
In a daisy-chained system of AD7761 devices, two successive
synchronization pulses must be applied to guarantee that all ADCs
are synchronized. Two synchronization pulses are also required in a
system of more than one AD7761 device sharing a single MCLK
•
START
AD7761 device. Similarly to the
pin method, the
of the first device
related to the base MCLK signal for distribution locally.
SYNC_OUT
SPI sync generates a pulse on
DRDY
signal, where the
new data.
pin of only one device is used to detect
SYNC_OUT
pin of that same device and to the
In both cases, route the
pin of the first device to
The maximum DCLK frequency that can be used when daisy-
chaining devices is a function of the AD7761 timing specifications
(t4, and t11 in Table 4), the MCLK duty cycle, and any timing
differences between the AD7761 devices due to layout and spacing
of devices on the PCB.
SYNC_IN
SYNC_IN
pins
the
of all other devices that are to be synchronized (see Figure 79).
SYNC_OUT
The
pins of the other devices must remain open
START
circuit. Tie all unused
resistors.
pins to a Logic 1 through pull-up
Use the following formula to aid in determining the maximum
operating frequency of the interface:
AD7761
1
START
fMAX
=
SYNC_OUT
MCLK
SYNCHRONIZATION
2×
t
11 + t4 + tP + tSKEW
LOGIC
where:
MAX is the maximum useable DCLK frequency.
t11 and t4 are the AD7761 timing specifications (see Table 4).
tP is the maximum propagation delay of the data between
successive AD7761 devices in the chain.
DIGITAL FILTER
SYNC_IN
DRDY
DOUT0
DOUT1
f
DSP/
FPGA
MASTER
CLOCK
IOVDD
tSKEW is the maximum skew in the MCLK signal seen by any pair of
AD7761 devices in the chain.
AD7761
START
The MCLK duty cycle is 50:50, or DCLK is set to MCLK/2,
MCLK/4, or MCLK/8.
SYNC_OUT
DRDY
MCLK
DNC
DNC
SYNCHRONIZATION
LOGIC
In the case where the MCLK duty cycle is not 50:50 and the
interface is configured with DCLK = MCLK/1, ensure that the
applied MCLK signal meets the minimum MCLK high pulse width
requirement, as calculated by the following formula:
DIGITAL FILTER
SYNC_IN
SYNC_OUT
Figure 79. Synchronizing Multiple AD7761 Devices Using
MCLK Minimum High Pulse Width = t11 + t4 + tP + tSKEW
Rev. A | Page 54 of 75
Data Sheet
AD7761
If the user can provide a signal that is synchronous to the base
The following is an example of how the CRC works for four-
SYNC_IN
sample mode (see Figure 81):
MCLK, this signal can be applied directly to the
Route the signal from a star point and connect it directly to
SYNC_IN
pin.
1. After a synchronization pulse is applied to the AD7761, the
CRC register is cleared to 0xFF.
the
pin of each AD7761 device (see Figure 80). The
signal is sampled on the rising MCLK edge; setup and hold
2. The next four 16-bit conversion data samples (N to N + 3)
for a given channel stream into the CRC calculation.
3. For the first three samples that are output after the
synchronization pulse (N to N + 2), the header contains
the normal status bits.
4. For the fourth sample after the synchronization pulse
(N + 3), the 8-bit CRC is sent out instead of the normal
header status bits, followed by the sample conversion data.
This CRC calculation includes the conversion data that is
output immediately after the CRC header.
SYNC_IN
times are associated with the
AD7761 MCLK rising edge.
input are relative to the
START
In this case, tie the
SYNC_OUT
pin to Logic 1 through a pull-up
is not used and can remain open circuit.
resistor;
IOVDD
AD7761
START
MCLK
SYNCHRONIZATION
LOGIC
5. The CRC register is then cleared back to 0xFF and the
cycle begins again for the fifth to eighth samples after the
synchronization pulse.
DIGITAL FILTER
SYNC_IN
DRDY
DOUT0
DOUT1
DSP/
FPGA
It is possible to have channels outputting at different rates (for
example, decimation by 32 on Channel 0 and decimation by 64 on
Channel 1). In such cases, the CRC header still appears across all
IOVDD
AD7761
DRDY
channels at the same time, that is, at every fourth
a synchronization. For the channels operating at a relatively slower
DRDY
pulse after
START
MCLK
SYNCHRONIZATION
LOGIC
DRDY
DOUT0
DOUT1
ODR, the CRC is still calculated and emitted every 4 or 16
DIGITAL FILTER
SYNC_IN
cycles, even if this means that the nulled data is included.
Therefore, a CRC is calculated for only nulled samples or for a
combination of nulled samples and actual conversion data.
SYNC_IN
Figure 80. Synchronizing Multiple AD7761 Devices Using Only
The AD7761 uses a CRC polynomial to calculate the CRC
message. The 8-bit CRC polynomial used is x8 + x2 + x + 1.
CRC Check on Data Interface
The AD7761 delivers 24 bits per channel as standard, which by
default consists of 8 status header bits and 16 bits of data.
The CRC Code Example section shows a snippet of the C code,
which shows how the CRC value can be calculated for a given
set of ADC conversion results. Running this code on sets of 4 or
16 conversion results gives the CRC value that the AD7761 gives
per channel. The user can then compare the computed value
from this code to the actual CRC value read from the AD7761,
and so confirm that the data read is without error.
The header bits move to the default value per the description in
Table 31. However, there is also the option to employ a CRC
check on the ADC conversion data. This functionality is available
only when operating in SPI control mode. The function is
controlled by CRC_SELECT in the interface configuration
register (Register 0x07). When employed, the CRC message is
calculated internally by the AD7761 on a per channel basis. The
CRC then replaces the 8-bit header every four samples or every
16 samples.
DOUT0
N – 1
HEADER N
8 BITS
DATA N
16 BITS
HEADER N + 1
8 BITS
DATA N + 1
16 BITS
HEADER N + 2
8 BITS
DATA N + 2
16 BITS
CRC
DATA N + 3
16 BITS
8 BITS
Figure 81. CRC 4-Bit Stream
Rev. A | Page 55 of 75
AD7761
Data Sheet
CRC Code Example
#include <stdio.h>
FILE *fi1;
FILE *fo1;
main(){
int num_data_bits=16; // 24 or 16
int num_data_words=4; //4 or 16
int data;
int crc[8],crc_new[8];
int i,j,n,k,num,bit,result;
const int num_crc_bits=8;
int bit_sel[num_data_bits];
bit_sel[23] = 0x800000;
bit_sel[22] = 0x400000;
bit_sel[21] = 0x200000;
bit_sel[20] = 0x100000;
bit_sel[19] = 0x080000;
bit_sel[18] = 0x040000;
bit_sel[17] = 0x020000;
bit_sel[16] = 0x010000;
bit_sel[15] = 0x008000;
bit_sel[14] = 0x004000;
bit_sel[13] = 0x002000;
bit_sel[12] = 0x001000;
bit_sel[11] = 0x000800;
bit_sel[10] = 0x000400;
bit_sel[9] = 0x000200;
bit_sel[8] = 0x000100;
bit_sel[7] = 0x000080;
bit_sel[6] = 0x000040;
bit_sel[5] = 0x000020;
bit_sel[4] = 0x000010;
bit_sel[3] = 0x000008;
bit_sel[2] = 0x000004;
bit_sel[1] = 0x000002;
bit_sel[0] = 0x000001;
fi1 = fopen("adcdata.txt", "r");
fo1 = fopen("crc_out.txt", "w");
j = 1;
Rev. A | Page 56 of 75
Data Sheet
AD7761
//initialise CRC to FF
for (i=0;i<num_crc_bits;i++) crc[i]=1;
result = ((crc[7]<<7) & 0x0080)
| ((crc[6]<<6) & 0x0040)
| ((crc[5]<<5) & 0x0020)
| ((crc[4]<<4) & 0x0010)
| ((crc[3]<<3) & 0x0008)
| ((crc[2]<<2) & 0x0004)
| ((crc[1]<<1) & 0x0002)
| ((crc[0]<<0) & 0x0001);
printf("CRC Initialised to 0x%.02X \n",result);
fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"CRC Initialised to 0x%.02X \n",result);
//run CRC on data
for (n = 0; n < num_data_words; n++){
fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"Loop %d start\n",n+1);
fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"ADC Data values\n");
fprintf(fo1,"--------------------------------\n");
fscanf(fi1,"%x\n",&num);
fprintf(fo1,"0x%.06X\n",num);
fprintf(fo1,"--------------------------------\n");
fprintf(fo1,"CRC values\n");
fprintf(fo1,"--------------------------------\n");
for (k=num_data_bits-1;k>=0;k--){
//for (i=7;i>=0;i--){
//
printf("%1d",crc[i]);
//}
bit = (num & bit_sel[k]); // msb first
data = bit>>(k);
printf(" bit_sel is: %.06X - data is : %X
crc_new[0]=data^crc[7];
",bit_sel[k], data);
//debug printf(" qq(0) = %1d ",qq[0]);
crc_new[1]=data^crc[7]^crc[0];
crc_new[2]=data^crc[7]^crc[1];
crc_new[3]=crc[2];
crc_new[4]=crc[3];
crc_new[5]=crc[4];
crc_new[6]=crc[5];
crc_new[7]=crc[6];
//debug
printf("%8d
",j);
Rev. A | Page 57 of 75
AD7761
Data Sheet
for (i=num_crc_bits-1;i>=0;i--){
crc[i]=crc_new[i];
printf("%1d",crc[i]);
}
//debug
printf("\n");
result = ((crc[7]<<7) & 0x0080)
| ((crc[6]<<6) & 0x0040)
| ((crc[5]<<5) & 0x0020)
| ((crc[4]<<4) & 0x0010)
| ((crc[3]<<3) & 0x0008)
| ((crc[2]<<2) & 0x0004)
| ((crc[1]<<1) & 0x0002)
| ((crc[0]<<0) & 0x0001);
printf(" intermediate res is 0x%.02X\n",result);
fprintf(fo1,"intermediate res is 0x%.02X\n",result);
if (k == 0) {
printf("loop %d:res is 0x%.02X\n",n,result);
}
}
}
fprintf(fo1,"--------------------------------\n");
printf("Final CRC value = 0x%.02X\n",result);
fprintf(fo1,"CRC value = 0x%.02X\n",result);
Rev. A | Page 58 of 75
Data Sheet
AD7761
FUNCTIONALITY
11
12
13
14
15
16
FILTER/GPIO4
MODE0/GPIO0
MODE1/GPIO1
MODE2/GPIO2
MODE3/GPIO3
ST0/CS
GPIO FUNCTIONALITY
The AD7761 has additional GPIO functionality when operated
in SPI control mode. This fully configurable mode allows the
device to operate five GPIOs. The GPIOx pins can be set as inputs
or outputs (read or write) on a per pin basis.
17 18 19 20 21 22 23 24 25
In write mode, these GPIO pins can be used to control other
circuits such as switches, multiplexers, and buffers, over the
same SPI interface as the AD7761. Sharing the SPI interface in
this way allows the user to use a lower overall number of data
lines from the controller compared to a system where multiple
control signals are required. This sharing is especially useful in
systems where reducing the number of control lines across an
isolation barrier is important. See Figure 82 for details of the
GPIOx pin options available on the AD7761.
TO DSP/FPGA
Figure 82. GPIO Functionality
Configuration control and readback of the GPIOx pins are set
in Register 0x0E, Register 0x0F, and Register 0x10 (see Table 45,
Table 46, and Table 47 for more information).
Similarly, a GPIO read is a useful feature because it allows a
peripheral device to send information to the input GPIO and
then this information can be read from the SPI interface of the
AD7761.
Rev. A | Page 59 of 75
AD7761
Data Sheet
REGISTER MAP DETAILS (SPI CONTROL)
REGISTER MAP
Table 33. Detailed Register Map
Reg. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x00 RW
0x0D RW
0x0D RW
0x00 Channel Standby CH_7
0x01 Channel Mode A
CH_6
CH_5
CH_4
CH_3
CH_2
CH_1
CH_0
Unused
Unused
FILTER_TYPE_A
FILTER_TYPE_B
CH_3_MODE
DEC_RATE_A
DEC_RATE_B
CH_1_MODE
0x02 Channel Mode B
0x03 Channel Mode
Select
CH_7_MODE CH_6_MODE
CH_5_MODE CH_4_MODE
CH_2_MODE
CH_0_MODE 0x00 RW
0x04 POWER_MODE
SLEEP_MODE Unused
POWER_MODE
LVDS_ENABLE
Reserved
Unused
Unused
MCLK_DIV
VCM_VSEL
0x00 RW
0x08 RW
0x05 General
Configuration
Unused
CLK_QUAL_DIS RETIME_EN VCM_PD
0x06 Data Control
SPI_SYNC
Unused
Unused
SINGLE_SHOT_EN
Unused
CRC_SELECT
SPI_RESET
DCLK_DIV
0x80 RW
0x07 Interface
Configuration
0x0
0x0
0x0
RW
RW
R
0x08 BIST Control
Unused
RAM_BIST_
START
0x09 Device Status
Unused
CHIP_ERROR
REVISION_ID
NO_CLOCK_
ERROR
RAM_BIST_PASS RAM_BIST_
RUNNING
0x0A Revision ID
0x0B Reserved
0x0C Reserved
0x0D Reserved
0x0E GPIO Control
0x06
0x00
0x00
0x00
R
R
R
R
Reserved
Reserved
Reserved
UGPIO_
ENABLE
Unused
GPIOE4_FILTER GPIOE3_MODE3 GPIOE2_MODE2 GPIOE1_MODE1 GPIO0_MODE0 0x00 RW
0x0F GPIO Write Data
0x10 GPIO Read Data
Unused
Unused
GPIO4_WRITE
GPIO4_READ
GPIO3_WRITE
GPIO3_READ
GPIO2_WRITE
GPIO2_READ
GPIO1_WRITE
GPIO1_READ
GPIO0_WRITE 0x00 RW
GPIO0_READ 0x00
R
0x11 Precharge Buffer 1 CH3_PREBUF_ CH3_PREBUF_ CH2_PREBUF_ CH2_PREBUF_
NEG_EN POS_EN NEG_EN POS_EN
0x12 Precharge Buffer 2 CH7_PREBUF_ CH7_PREBUF_ CH6_PREBUF_ CH6_PREBUF_
CH1_PREBUF_
NEG_EN
CH1_PREBUF_
POS_EN
CH0_PREBUF_
NEG_EN
CH0_PREBUF_ 0xFF RW
POS_EN
CH5_PREBUF_
NEG_EN
CH5_PREBUF_
POS_EN
CH4_PREBUF_
NEG_EN
CH4_PREBUF_ 0xFF RW
POS_EN
NEG_EN
POS_EN
NEG_EN
POS_EN
0x13 Positive Reference CH7_REFP_
CH6_REFP_
BUF
CH5_REFP_ CH4_REFP_BUF CH3_REFP_BUF CH2_REFP_BUF CH1_REFP_BUF CH0_REFP_
BUF BUF
CH5_REFN_ CH4_REFN_BUF CH3_REFN_BUF CH2_REFN_BUF CH1_REFN_BUF CH0_REFN_
BUF BUF
0x00 RW
0x00 RW
0x00 RW
Precharge Buffer
BUF
0x14 Negative Reference CH7_REFN_
CH6_REFN_
BUF
Precharge Buffer
BUF
0x1E Channel 0 Offset
CH0_OFFSET_MSB
CH0_OFFSET_MID
CH0_OFFSET_LSB
CH1_OFFSET_MSB
CH1_OFFSET_MID
CH1_OFFSET_LSB
CH2_OFFSET_MSB
CH2_OFFSET_MID
CH2_OFFSET_LSB
CH3_OFFSET_MSB
CH3_OFFSET_MID
CH3_OFFSET_LSB
CH4_OFFSET_MSB
CH4_OFFSET_MID
CH4_OFFSET_LSB
CH5_OFFSET_MSB
CH5_OFFSET_MID
CH5_OFFSET_LSB
CH6_OFFSET_MSB
CH6_OFFSET_MID
CH6_OFFSET_LSB
CH7_OFFSET_MSB
CH7_OFFSET_MID
CH7_OFFSET_LSB
CH0_GAIN_MSB
0x1F
0x20
0x21 Channel 1 Offset
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0xXX RW
0x22
0x23
0x24 Channel 2 Offset
0x25
0x26
0x27 Channel 3 Offset
0x28
0x29
0x2A Channel 4 Offset
0x2B
0x2C
0x2D Channel 5 Offset
0x2E
0x2F
0x30 Channel 6 Offset
0x31
0x32
0x33 Channel 7 Offset
0x34
0x35
0x36 Channel 0 Gain
0x37
0x38
CH0_GAIN_MID
CH0_GAIN_LSB
Rev. A | Page 60 of 75
Data Sheet
AD7761
Reg. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset RW
0x39 Channel 1 Gain
CH1_GAIN_MSB
CH1_GAIN_MID
CH1_GAIN_LSB
CH2_GAIN_MSB
CH2_GAIN_MID
CH2_GAIN_LSB
CH3_GAIN_MSB
CH3_GAIN_MID
CH3_GAIN_LSB
CH4_GAIN_MSB
CH4_GAIN_MID
CH4_GAIN_LSB
CH5_GAIN_MSB
CH5_GAIN_MID
CH5_GAIN_LSB
CH6_GAIN_MSB
CH6_GAIN_MID
CH6_GAIN_LSB
CH7_GAIN_MSB
CH7_GAIN_MID
CH7_GAIN_LSB
CH0_SYNC_OFFSET
0xXX RW
0x3A
0x3B
0x3C Channel 2 Gain
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0xXX RW
0x3D
0x3E
0x3F Channel 3 Gain
0x40
0x41
0x42 Channel 4 Gain
0x43
0x44
0x45 Channel 5 Gain
0x46
0x47
0x48 Channel 6 Gain
0x49
0x4A
0x4B Channel 7 Gain
0x4C
0x4D
0x4E Channel 0 Sync
Offset
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x00 RW
0x4F Channel 1 Sync
Offset
CH1_SYNC_OFFSET
CH2_SYNC_OFFSET
CH3_SYNC_OFFSET
CH4_SYNC_OFFSET
CH5_SYNC_OFFSET
CH6_SYNC_OFFSET
CH7_SYNC_OFFSET
0x50 Channel 2 Sync
Offset
0x51 Channel 3 Sync
Offset
0x52 Channel 4 Sync
Offset
0x53 Channel 5 Sync
Offset
0x54 Channel 6 Sync
Offset
0x55 Channel 7 Sync
Offset
0x56 Diagnostic Rx
CH7_RX
Unused
CH6_RX
CH5_RX
CH4_RX
CH3_RX
Unused
CH2_RX
CH1_RX
CH0_RX
0x00 RW
0x00 RW
0x57 Diagnostic Mux
Control
GRPB_SEL
Unused
Unused
GRPA_SEL
Reserved
GRPB_CHOP
0x58 Modulator Delay
Control
CLK_MOD_DEL_EN
GRPA_CHOP
0x02 RW
0x0A RW
0x59 Chop Control
Rev. A | Page 61 of 75
AD7761
Data Sheet
CHANNEL STANDBY REGISTER
Address: 0x00, Reset: 0x00, Name: Channel Standby
Each of the ADC channels can be put into standby mode independently by setting the appropriate bit in the channel standby register.
When a channel is in standby mode, its position in the data output stream is held. The 8-bit header is all zeros, as is the conversion result
output of 16 zeros.
The VCM voltage output is associated with the Channel 0 circuitry. If Channel 0 is put into standby mode, the VCM voltage output is also
disabled for maximum power savings. Channel 0 must be enabled while VCM is being used externally to the AD7761.
The crystal excitation circuitry is associated with the Channel 4 circuitry. If Channel 4 is put into standby mode, the crystal circuitry is
also disabled for maximum power savings. Channel 4 must be enabled while the external crystal is used on the AD7761.
Table 34. Bit Descriptions for Channel Standby
Bits
Bit Name
Settings
Description
Channel 7
Enabled
Standby
Channel 6
Enabled
Standby
Channel 5
Enabled
Standby
Channel 4
Enabled
Standby
Channel 3
Enabled
Standby
Channel 2
Enabled
Standby
Channel 1
Enabled
Standby
Channel 0
Enabled
Standby
Reset
Access
7
CH_7
0x0
RW
0
1
6
5
4
3
2
1
0
CH_6
CH_5
CH_4
CH_3
CH_2
CH_1
CH_0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. A | Page 62 of 75
Data Sheet
AD7761
CHANNEL MODE A REGISTER
Address: 0x01, Reset: 0x0D, Name: Channel Mode A
Two mode options are available on the AD7761 ADCs. The channel modes are defined by the contents of the Channel Mode A and
Channel Mode B registers. Each mode is then mapped as desired to the required ADC channel. Channel Mode A and Channel Mode B
allow different filter types and decimation rates to be selected and mapped to any of the ADC channels.
When different decimation rates are selected, the AD7761 outputs a data ready signal at the fastest selected decimation rate. Any channel
that runs at a lower output data rate is updated only at that slower rate. In between valid result data, the data for that channel is set to zero
and the repeated data bit is set in the header status bits to distinguish it from a real conversion result (see the ADC Conversion Output:
Header and Data section).
Table 35. Bit Descriptions for Channel Mode A
Bits
Bit Name
Settings
Description
Reset
Access
3
FILTER_TYPE_A
Filter selection
Wideband filter
Sinc5 filter
0x1
RW
0
1
[2:0]
DEC_RATE_A
Decimation rate selection
0x5
RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024
111 ×1024
CHANNEL MODE B REGISTER
Address: 0x02, Reset: 0x0D, Name: Channel Mode B
Table 36. Bit Descriptions for Channel Mode B
Bits
Bit Name
Settings
Description
Reset
Access
3
FILTER_TYPE_B
Filter selection
Wideband filter
Sinc5 filter
0x1
RW
0
1
[2:0]
DEC_RATE_B
Decimation rate selection
0x5
RW
000 ×32
001 ×64
010 ×128
011 ×256
100 ×512
101 ×1024
110 ×1024
111 ×1024
Rev. A | Page 63 of 75
AD7761
Data Sheet
CHANNEL MODE SELECT REGISTER
Address: 0x03, Reset: 0x00, Name: Channel Mode Select
This register selects the mapping of each ADC channel to either Channel Mode A or Channel Mode B.
Table 37. Bit Descriptions for Channel Mode Select
Bits
Bit Name
Settings
Description
Channel 7
Mode A
Reset
Access
7
CH_7_MODE
0x0
RW
0
1
Mode B
6
5
4
3
2
1
0
CH_6_MODE
CH_5_MODE
CH_4_MODE
CH_3_MODE
CH_2_MODE
CH_1_MODE
CH_0_MODE
Channel 6
Mode A
Mode B
0x0
0x0
0x0
0x0
0x0
0x0
0x0
RW
RW
RW
RW
RW
RW
RW
0
1
Channel 5
Mode A
Mode B
0
1
Channel 4
Mode A
Mode B
0
1
Channel 3
Mode A
Mode B
0
1
Channel 2
Mode A
Mode B
0
1
Channel 1
Mode A
Mode B
0
1
Channel 0
Mode A
Mode B
0
1
POWER MODE SELECT REGISTER
Address: 0x04, Reset: 0x00, Name: POWER_MODE
Table 38. Bit Descriptions for POWER_MODE
Bits
Bit Name
Settings Description
Reset
Access
7
SLEEP_MODE
In sleep mode, many of the digital clocks are disabled and all of the ADCs are 0x0
RW
disabled. The analog LDOs are not disabled.
The AD7761 SPI is live and is available to the user. Writing to this bit brings
the AD7761 out of sleep mode again.
0
1
Normal operation.
Sleep mode.
[5:4]
POWER_MODE
Power mode. The power mode bits control the power mode setting for the
bias currents used on all ADCs on the AD7761. The user can select the
current consumption target to meet the application. The power modes of
fast, median, and low power give optimum performance when mapped to
the correct MCLK division setting. These power mode bits do not control the
MCLK division of the ADCs. See the MCLK_DIV bits for control of the division
of the MCLK input.
0x0
RW
00 Low power.
10 Median.
11 Fast.
3
LVDS_ENABLE
LVDS clock.
0x0
RW
0
1
LVDS input clock disabled.
LVDS input clock enabled.
Rev. A | Page 64 of 75
Data Sheet
AD7761
Bits
Bit Name
Settings Description
MCLK division. The MCLK division bits control the divided ratio between the
Reset
Access
[1:0]
MCLK_DIV
0x0
RW
MCLK applied at the input to the AD7761 and the clock used by each of the
ADC modulators. The appropriate division ratio depends on the following
factors: power mode, decimation rate, and the base MCLK available in the
system. See the Clocking, Sampling Tree, and Power Scaling section for more
information on setting MCLK_DIV correctly.
00 MCLK/32: with a base MCLK of 32.768 MHz, set to MCLK/32 for low power mode.
10 MCLK/8: with a base MCLK of 32.768 MHz, set to MCLK/8 for median mode.
11 MCLK/4: with a base MCLK of 32.768 MHz, set to MCLK/4 for fast mode.
GENERAL DEVICE CONFIGURATION REGISTER
Address: 0x05, Reset: 0x08, Name: General Configuration
Table 39. Bit Descriptions for General Configuration
Bits
Bit Name
Settings
Description
Reset
Access
6
CLK_QUAL_DIS
Clock qualification disable bit. Allows the user to disable
the external clock source qualification. Following a reset,
the frequency of the externally applied MCLK is checked.
It is accepted as valid if it is greater than approximately
1.15 MHz. The AD7761 then hands control over to the
external clock source. If this qualification check fails, the
NO_CLOCK_ERROR bit is set and the AD7761 continues to
run using the internal startup clock.
0x0
RW
Users can disable this qualification check to force the
AD7761 to accept and pass control to an external clock
source with a lower frequency.
0
1
Enabled. Clock qualification check is performed.
Disabled. Clock qualification check is not performed.
SYNC_OUT signal retime enable bit.
5
RETIME_EN
0x0
RW
0
1
Disabled: normal timing of SYNC_OUT.
Enabled: SYNC_OUT signal derived from alternate
MCLK edge.
4
VCM_PD
VCM buffer power-down.
Enabled: VCM buffer normal mode.
Powered down: VCM buffer powered down.
0x0
0x0
RW
RW
0
1
[1:0]
VCM_VSEL
VCM voltage. These bits select the output voltage of the
VCM pin. This voltage is derived from the AVDD1 supply
and can be output as half of that AVDD1 voltage, or other
fixed voltages, with respect to AVSS. The VCM voltage
output is associated with the Channel 0 circuitry. If
Channel 0 is put into standby mode, the VCM voltage
output is also disabled for maximum power savings.
Channel 0 must be enabled while VCM is being used
externally to the AD7761.
00 (AVDD1 − AVSS)/2 V.
01 1.65 V.
10 2.5 V.
11 2.14 V.
Rev. A | Page 65 of 75
AD7761
Data Sheet
DATA CONTROL: SOFT RESET, SYNC, AND SINGLE-SHOT CONTROL REGISTER
Address: 0x06, Reset: 0x80, Name: Data Control
Table 40. Bit Descriptions for Data Control
Bits
Bit Name
Settings
Description
Reset
Access
7
SPI_SYNC
Software synchronization of the AD7761. This command has the same
effect as sending a signal pulse to the START pin. To operate the SPI_SYNC,
the user must write to this bit two separate times. First, write a zero,
putting SPI_SYNC low, and then write a 1 to set SPI_SYNC logic high
again. The SPI_SYNC command is recognized after the last rising edge of
SCLK in the SPI instruction where the SPI_SYNC bit is changed from low to
high. The SPI_SYNC command is then output synchronous to the AD7761
MCLK on the SYNC_OUT pin. The user must connect the SYNC_OUT signal
to the SYNC_IN pin on the PCB. The SYNC_OUT pin can also be routed to
the SYNC_IN pins of other AD7761 devices, allowing larger channel count
simultaneous sampling systems. As per any synchronization pulse seen by
the SYNC_IN pin, the digital filters of the AD7761 are reset. The full settling
time of the filters must elapse before data is output on the data interface. In a
daisy-chained system of AD7761 devices, two successive synchronization
pulses must be applied to guarantee that all ADCs are synchronized. Two
synchronization pulses are also required in a system of more than one
AD7761 device sharing a single MCLK signal, where the DRDY pin of only
one device is used to detect new data.
0x1
RW
0
1
Change to SPI_SYNC low.
Change to SPI_SYNC high.
4
SINGLE_SHOT_EN
SPI_RESET
One-shot mode. Enables one-shot mode. In one-shot mode, the AD7761
0x0
0x0
RW
RW
SYNC_IN
outputs a conversion result in response to a
rising edge.
0
1
Disabled.
Enabled.
[1:0]
Soft reset. These bits allow a full device reset over the SPI port. Two
successive commands must be received in the correct order to generate a
reset: first, write 0x03 to the soft reset bits, and then write 0x02 to the soft
reset bits. This sequence causes the digital core to reset and all registers
return to their default values. Following a soft reset, if the SPI master
sends a command to the AD7761, the device responds on the next frame
to that command with an output of 0x0E00.
00 No effect.
01 No effect.
10 Second reset command.
11 First reset command.
INTERFACE CONFIGURATION REGISTER
Address: 0x07, Reset: 0x0, Name: Interface Configuration
Table 41. Bit Descriptions for Interface Configuration
Bits
Bit Name
Settings
Description
Reset
Access
[3:2]
CRC_SELECT
CRC select. These bits allow the user to implement a CRC on the data
interface. When selected, the CRC replaces the header every fourth or 16th
output sample depending on the CRC option chosen. There are two
options for the CRC; both use the same polynomial: x8 + x2 + x + 1. The
options offer the user the ability to reduce the duty cycle of the CRC
calculation by performing it less often: in the case of having it every 16th
sample, or more often in the case of every fourth conversion. The CRC is
calculated on a per channel basis and it includes conversion data only.
0x0
RW
00 No CRC. Status bits with every conversion.
01 Replace the header with CRC message every 4 samples.
10 Replace the header with CRC message every 16 samples.
11 Replace the header with CRC message every 16 samples.
Rev. A | Page 66 of 75
Data Sheet
AD7761
Bits
Bit Name
Settings
Description
Reset
0x0
Access
[1:0]
DCLK_DIV
DCLK divider. These bits control division of the DCLK clock used to clock
out conversion data on the DOUTx pins. The DCLK signal is derived from
the MCLK signal applied to the AD7761. The DCLK divide mode allows the
user to optimize the DCLK output to fit the application. Optimizing the
DCLK signal per application depends on the requirements of the user. When
the AD7761 uses the highest capacity output on the fewest DOUTx pins, for
example, running in decimate by 32 using the DOUT0 and DOUT1 pins, the
DCLK signal must equal the MCLK signal; thus, in this case, choosing the
no division setting is the only way the user can output all the data within
the conversion period. There are other cases, however, when the ADC may
be running in fast mode with high decimation rates, or in median or low
power mode where the DCLK signal does not need to run at the same
speed as MCLK. In these cases, the DCLK divide allows the user to reduce
the clock speed and makes routing and isolating such signals easier.
RW
00 Divide by 8.
01 Divide by 4.
10 Divide by 2.
11 No division.
DIGITAL FILTER RAM BUILT IN SELF TEST (BIST) REGISTER
Address: 0x08, Reset: 0x0, Name: BIST Control
Table 42. Bit Descriptions for BIST Control
Bits Bit Name
Settings Description
Reset Access
0x0 RW
0
RAM_BIST_START
RAM BIST. Filter RAM BIST is a built in self test of the internal RAM. Normal ADC
conversion is disrupted when this test is run. A synchronization pulse is required
after this test is complete to resume normal ADC operation. The test can be run at
intervals depending on user preference. The status and result of the RAM BIST is
available in the device status register; see the RAM_BIST_PASS and
RAM_BIST_RUNNING bits in Table 43.
0
1
Off.
Begin RAM BIST.
STATUS REGISTER
Address: 0x09, Reset: 0x0, Name: Device Status
Table 43. Bit Descriptions for Device Status
Bits Bit Name
Settings Description
Chip error. Chip error is a global error flag that is output within the status byte
Reset Access
3
CHIP_ERROR
0x0
R
of each ADC conversion output. The following bits lead to the chip error bit
being set to logic high: CRC check on internally hard coded settings (after power-
up) does not pass; XOR check on the internal memory does not pass (this check
runs continuously in the background); and clock error is detected on power-up.
0
1
No error present.
Error has occurred.
2
NO_CLOCK_ERROR
External clock check. This bit indicates whether the externally applied MCLK is 0x0
detected correctly. If the MCLK is not applied correctly to the ADC at power-
up, this bit is set and the DCLK frequency is approximately 16 MHz. If this bit is set,
the chip error bit is set to logic high in the status bits of the data output
headers, and the conversion results are output as all zeros regardless of the
analog input voltages applied to the ADC channels.
R
0
1
MCLK detected.
No MCLK detected.
1
RAM_BIST_PASS
BIST pass/fail. RAM BIST result status. This bit indicates the result of the most
recent RAM BIST. The result is latched to this register and is only cleared by a
device reset.
0x0
R
0
1
BIST failed or not run.
BIST passed.
Rev. A | Page 67 of 75
AD7761
Data Sheet
Bits Bit Name
Settings Description
BIST status. Reading back the value of this bit allows the user to poll when the
Reset Access
0
RAM_BIST_RUNNING
0x0
R
BIST test has finished.
BIST not running.
BIST running.
0
1
REVISION IDENTIFICATION REGISTER
Address: 0x0A, Reset: 0x06, Name: Revision ID
Table 44. Bit Descriptions for Revision ID
Bits
Bit Name
Description
Reset
Access
[7:0]
REVISION_ID
ASIC revision. 8-bit ID for revision details.
0x06
R
GPIO CONTROL REGISTER
Address: 0x0E, Reset: 0x00, Name: GPIO Control
Table 45. Bit Descriptions for GPIO Control
Bits
Bit Name
Setting
Description
Reset
Access
7
UGPIO_ENABLE
User GPIO enable. The GPIOx pins are dual purpose and can be operated only
when the device is in SPI control mode. By default, when the AD7761 is powered
up in SPI control mode, the GPIOx pins are disabled. This bit is a universal enable/
disable for all GPIOx input/outputs. The direction of each general-purpose pin
is determined by Bits[4:0] of this register.
0x0
RW
0
1
GPIO disabled.
GPIO enabled.
4
3
2
1
0
GPIOE4_FILTER
GPIOE3_MODE3
GPIOE2_MODE2
GPIOE1_MODE1
GPIO0_MODE0
GPIO4 direction. This bit assigns the direction of GPIO4 as either an input or an 0x0
output. For SPI control, GPIO4 maps to Pin 11, which is the FILTER/GPIO4 pin.
Input.
RW
RW
RW
RW
RW
0
1
Output.
GPIO3 direction. This bit assigns the direction of GPIO3 as either an input or an 0x0
output. For SPI control, GPIO3 maps to Pin 15, which is the MODE3/GPIO3 pin.
Input.
0
1
Output.
GPIO2 direction. This bit assigns the direction of GPIO2 as either an input or an 0x0
output. For SPI control, GPIO2 maps to Pin 14, which is the MODE2/GPIO2 pin.
Input.
0
1
Output.
GPIO1 direction. This bit assigns the direction of GPIO1 as either an input or an 0x0
output. For SPI control, GPIO1 maps to Pin 13, which is the MODE1/GPIO1 pin.
Input.
0
1
Output.
GPIO0 direction. This bit assigns the direction of GPIO0 as either an input or an 0x0
output. For SPI control, GPIO0 maps to Pin 12, which is the MODE0/GPIO0 pin.
0
1
Input.
Output.
Rev. A | Page 68 of 75
Data Sheet
AD7761
GPIO WRITE DATA REGISTER
Address: 0x0F, Reset: 0x00, Name: GPIO Write Data
This register writes the values to be set on each of the general-purpose pins when selected as general-purpose outputs. Each bit, from
Bits[4:0], maps directly to the GPIOx pins.
Table 46. Bit Descriptions for GPIO Write Data
Bits
Bit Name
Description
Reset
0x0
Access
RW
4
GPIO4_WRITE
GPIO3_WRITE
GPIO2_WRITE
GPIO1_WRITE
GPIO0_WRITE
FILTER/GPIO4
MODE3/GPIO3
MODE2/GPIO2
MODE1/GPIO1
MODE0/GPIO0
3
0x0
RW
2
0x0
RW
1
0x0
RW
0
0x0
RW
GPIO READ DATA REGISTER
Address: 0x10, Reset: 0x00, Name: GPIO Read Data
This register reads back the value of the logic input level at the general-purpose pins when selected to operate as general-purpose inputs.
Each bit, from Bits[4:0], maps directly to the GPIO0 to GPIO4 pins.
Table 47. Bit Descriptions for GPIO Read Data
Bits
Bit Name
Description
Reset
0x0
Access
4
GPIO4_READ
GPIO3_READ
GPIO2_READ
GPIO1_READ
GPIO0_READ
FILTER/GPIO4
MODE3/GPIO3
MODE2/GPIO2
MODE1/GPIO1
MODE0/GPIO0
R
R
R
R
R
3
0x0
2
0x0
1
0x0
0
0x00
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 0 TO CHANNEL 3
Address: 0x11, Reset: 0xFF, Name: Precharge Buffer 1
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.
Table 48. Bit Descriptions for Precharge Buffer 1
Bits
Bit Name
Settings
Description
Off
On
Reset
7
CH3_PREBUF_NEG_EN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0x1
6
5
4
3
2
1
0
CH3_PREBUF_POS_EN
CH2_PREBUF_NEG_EN
CH2_PREBUF_POS_EN
CH1_PREBUF_NEG_EN
CH1_PREBUF_POS_EN
CH0_PREBUF_NEG_EN
CH0_PREBUF_POS_EN
Off
On
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Rev. A | Page 69 of 75
AD7761
Data Sheet
ANALOG INPUT PRECHARGE BUFFER ENABLE REGISTER CHANNEL 4 TO CHANNEL 7
Address: 0x12, Reset: 0xFF, Name: Precharge Buffer 2
This register turns on or off the precharge buffers on the analog inputs. When writing to these registers, the user must write the inverse of
the required bit settings. For example, to clear Bit 1 of this register, the user must write 0x01 to the register. This clears Bit 1 and sets all
other bits. If the user reads the register again after writing 0x01, the data read is 0xFE, as required.
Table 49. Bit Descriptions for Precharge Buffer 2
Bits
Bit Name
Settings
Description
Off
On
Reset
7
CH7_PREBUF_NEG_EN
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0x1
6
5
4
3
2
1
0
CH7_PREBUF_POS_EN
CH6_PREBUF_NEG_EN
CH6_PREBUF_POS_EN
CH5_PREBUF_NEG_EN
CH5_PREBUF_POS_EN
CH4_PREBUF_NEG_EN
CH4_PREBUF_POS_EN
Off
On
0x1
0x1
0x1
0x1
0x1
0x1
0x1
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
POSITIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x13, Reset: 0x00, Name: Positive Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference positive input to each of the ADCs from Channel 0 to Channel 7.
Table 50. Bit Descriptions for Positive Reference Precharge Buffer
Bits
Bit Name
Settings
Description
Off
On
Reset
7
CH7_REFP_BUF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0x0
6
5
4
3
2
1
0
CH6_REFP_BUF
CH5_REFP_BUF
CH4_REFP_BUF
CH3_REFP_BUF
CH2_REFP_BUF
CH1_REFP_BUF
CH0_REFP_BUF
Off
On
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Rev. A | Page 70 of 75
Data Sheet
AD7761
NEGATIVE REFERENCE PRECHARGE BUFFER ENABLE REGISTER
Address: 0x14, Reset: 0x00, Name: Negative Reference Precharge Buffer
This register turns on or off the precharge buffers on the reference negative input to each of the ADCs from Channel 0 to Channel 7.
Table 51. Bit Descriptions for Negative Reference Precharge Buffer
Bits
Bit Name
Settings
Description
Off
On
Reset
7
CH7_REFN_BUF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0x0
6
5
4
3
2
1
0
CH6_REFN_BUF
CH5_REFN_BUF
CH4_REFN_BUF
CH3_REFN_BUF
CH2_REFN_BUF
CH1_REFN_BUF
CH0_REFN_BUF
Off
On
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
OFFSET REGISTERS
The CHx_OFFSET_MSB, CHx_OFFSET_MID, and CHx_OFFSET_LSB registers are 24 bit, signed twos complement registers for channel
offset adjustment. If the channel gain setting is at its ideal nominal value of 0x555555, an LSB of offset register adjustment changes the digital
output by −1/192 LSBs. For example, changing the offset register from 0 to 4800 changes the digital output by −25 LSBs. Because offset
adjustment occurs before gain adjustment, the ratio of 1/192 changes linearly with gain adjustment via the CHx_GAIN_x registers. After a
reset or power cycle, the register values revert to the default factory setting.
Table 52. Per Channel 24-Bit Offset Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, Mid, and LSB
Address
Reset
MSB Mid
LSB
Name
Description
MSB Mid
LSB
Access
0x1E 0x1F 0x20 Channel 0 offset Channel 0 offset registers: upper, middle, and lower bytes (24 bits in total)
0x21 0x22 0x23 Channel 1 offset Channel 1 offset registers: upper, middle, and lower bytes (24 bits in total)
0x24 0x25 0x26 Channel 2 offset Channel 2 offset registers: upper, middle, and lower bytes (24 bits in total)
0x27 0x28 0x29 Channel 3 offset Channel 3 offset registers: upper, middle, and lower bytes (24 bits in total)
0x2A 0x2B 0x2C Channel 4 offset Channel 4 offset registers: upper, middle, and lower bytes (24 bits in total)
0x2D 0x2E 0x2F Channel 5 offset Channel 5 offset registers: upper, middle, and lower bytes (24 bits in total)
0x30 0x31 0x32 Channel 6 offset Channel 6 offset registers: upper, middle, and lower bytes (24 bits in total)
0x33 0x34 0x35 Channel 7 offset Channel 7 offset registers: upper, middle, and lower bytes (24 bits in total)
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
0x00 0x00 0x00 RW
Rev. A | Page 71 of 75
AD7761
Data Sheet
GAIN REGISTERS
Each ADC channel has an associated gain coefficient. The coefficient is stored in three single-byte registers split up as MSB, MID, and
LSB. Each of the gain registers are factory programmed. Nominally, this gain is around the value 0x555555 (for an ADC channel). The
user can overwrite the gain register setting; however, after a reset or power cycle, the gain register values revert to the hard coded
programmed factory setting.
Table 53. Per Channel 24-Bit Gain Registers, Three 8-Bit Registers for Each Channel, Split Up as MSB, Mid, and LSB
Address
Reset
MSB Mid
LSB
Name
Description
MSB Mid
LSB
Access
0x36 0x37 0x38 Channel 0 gain Channel 0 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x39 0x3A 0x3B Channel 1 gain Channel 1 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x3C 0x3D 0x3E Channel 2 gain Channel 2 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x3F 0x40 0x41 Channel 3 gain Channel 3 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x42 0x43 0x44 Channel 4 gain Channel 4 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x45 0x46 0x47 Channel 5 gain Channel 5 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x48 0x49 0x4A Channel 6 gain Channel 6 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
0x4B 0x4C 0x4D Channel 7 gain Channel 7 gain registers: upper, middle, and lower bytes (24 bits in total) 0xXX 0xXX 0xXX RW
SYNC PHASE OFFSET REGISTERS
The AD7761 has one synchronization signal for all channels. The sync phase offset register allows the user to vary the phase delay on each
SYNC_IN
of the channels relative to the synchronization edge received on the
on the use of this function.
pin. See the Sync Phase Offset Adjustment section for details
Table 54. Per Channel 8-Bit Sync Phase Offset Registers
Address
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
Name
Description
Reset
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Access
RW
RW
RW
RW
RW
RW
RW
RW
Channel 0 sync offset
Channel 1 sync offset
Channel 2 sync offset
Channel 3 sync offset
Channel 4 sync offset
Channel 5 sync offset
Channel 6 sync offset
Channel 7 sync offset
Channel 0 sync phase offset register
Channel 1 sync phase offset register
Channel 2 sync phase offset register
Channel 3 sync phase offset register
Channel 4 sync phase offset register
Channel 5 sync phase offset register
Channel 6 sync phase offset register
Channel 7 sync phase offset register
ADC DIAGNOSTIC RECEIVE SELECT REGISTER
Address: 0x56, Reset: 0x00, Name: Diagnostic Rx
The AD7761 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can
be converted to verify the correct operation of the ADC channel. This register enables the diagnostic. Enable the receive (Rx) for each
channel and set each bit in this register to 1.
The ADC diagnostic feature depends on some features of the analog input precharge buffers. The user must ensure that the analog input
precharge buffers are enabled on the channels that are selected to receive the diagnostic voltages internally.
Table 55. Bit Descriptions for Diagnostic Rx
Bits
Bit Name
Settings
Description
Channel 7
Not in use
Receive
Reset
Access
7
CH7_RX
0x0
RW
0
1
6
CH6_RX
Channel 6
Not in use
Receive
0x0
RW
0
1
Rev. A | Page 72 of 75
Data Sheet
AD7761
Bits
Bit Name
Settings
Description
Channel 5
Not in use
Receive
Reset
Access
5
CH5_RX
CH4_RX
CH3_RX
CH2_RX
CH1_RX
CH0_RX
0x0
RW
RW
RW
RW
RW
RW
0
1
4
3
2
1
0
Channel 4
Not in use
Receive
0x0
0x0
0x0
0x0
0x0
0
1
Channel 3
Not in use
Receive
0
1
Channel 2
Not in use
Receive
0
1
Channel 1
Not in use
Receive
0
1
Channel 0
Not in use
Receive
0
1
ADC DIAGNOSTIC CONTROL REGISTER
Address: 0x57, Reset: 0x00, Name: Diagnostic Mux Control
The AD7761 ADC diagnostic allows the user to select a zero-scale, positive full-scale, or negative full-scale input to the ADC, which can
be converted to verify the correct operation of the ADC channel. This register controls the voltage that is applied to each of the ADC
channels for the diagnostic. There are three input voltage options that the user can select. The voltage selected is mapped to the channels based
on the mode (Channel Mode A or Channel Mode B) they belong to, which is set according to the channel mode select register (Register 0x03).
Set Bits[7:0] to 1 in the ADC diagnostic receive select register, then select the voltage check desired for the channels on Channel Mode A
and the channels on Channel Mode B through Bits[2:0] and Bits[6:4], respectively.
Table 56. Bit Descriptions for Diagnostic Mux Control
Bits Bit Name Settings Description
[6:4] GRPB_SEL Mux B.
000 Off.
Reset Access
0x0
RW
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to
the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied
internally to the ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.
[2:0] GRPA_SEL
Mux A.
0x0
RW
000 Off.
011 Positive full-scale ADC check. A voltage close to positive full scale is applied internally to
the ADC channel.
100 Negative full-scale ADC check. A voltage close to negative (or minus) full scale is applied
internally to the ADC channel.
101 Zero-scale ADC check. A voltage close to 0 V is applied internally to the ADC channel.
Rev. A | Page 73 of 75
AD7761
Data Sheet
MODULATOR DELAY CONTROL REGISTER
Address: 0x58, Reset: 0x02, Name: Modulator Delay Control
Table 57. Bit Descriptions for Modulator Delay Control
Bits
Bit Name
Settings
Description
Reset
Access
[3:2] CLK_MOD_DEL_EN
Enable delayed modulator clock.
0x0
RW
00 Disabled delayed clock for all channels.
01 Enable delayed clock for Channel 0 to Channel 3 only on the AD7761.
10 Enable delayed clock for Channel 4 to Channel 7 only on the AD7761.
11 Enable delayed clock for all channels.
[1:0] Reserved
10 Not a user option. Must be set to 0x2.
0x2
RW
CHOPPING CONTROL REGISTER
Address: 0x59, Reset: 0x0A, Name: Chop Control
Table 58. Bit Descriptions for Chop Control
Bits
Bit Name
Settings
Description
Group A chopping
01 Chop at fMOD/8
10 Chop at fMOD/32
Group B chopping
01 Chop at fMOD/8
10 Chop at fMOD/32
Reset
Access
[3:2]
GRPA_CHOP
0x2
RW
[1:0]
GRPB_CHOP
0x2
RW
Rev. A | Page 74 of 75
Data Sheet
AD7761
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
0.75
0.60
0.45
1.60
MAX
64
49
1
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
16
33
0.15
0.05
SEATING
17
32
PLANE
VIEW A
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
Figure 83. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7761BSTZ
AD7761BSTZ-RL7
EVAL-AD7761FMCZ
EVAL-SDP-CH1Z
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
Package Option
64-Lead Low Profile Quad Flat Package [LQFP]
64-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
ST-64-2
ST-64-2
Controller Board
1 Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14285-0-9/17(A)
Rev. A | Page 75 of 75
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