EVAL-AD7767-2EDZ_技术文档

24-Bit, 8.5 mW, 109 dB,

128/64/32 kSPS ADCs

AD7767

FEATURES

GENERAL DESCRIPTION

Oversampled successive approximation (SAR) architecture

High performance ac and dc accuracy, low power

115.5 dB dynamic range, 32 kSPS (AD7767-2)

112.5 dB dynamic range, 64 kSPS (AD7767-1)

109.5 dB dynamic range, 128 kSPS (AD7767)

−118 dB THD

The AD7767/AD7767-1/AD7767-2 are high performance

24-bit oversampled SAR analog-to-digital converters (ADC).

The AD7767/AD7767-1/AD7767-2 combine the benefits of a

large dynamic range and input bandwidth, consuming 15 mW,

10.5 mW, and 8.5 mW power, respectively, all contained in a

16-lead TSSOP package.

Exceptionally low power

Ideal for ultralow power data acquisition (such as PCI- and

USB-based systems), the AD7767/AD7767-1/AD7767-2

provide 24-bit resolution. The combination of exceptional SNR,

wide dynamic range, and outstanding dc accuracy make the

AD7767/AD7767-1/AD7767-2 ideally suited for measuring

small signal changes over a wide dynamic range. This is

particularly suitable for applications where small changes on the

input are measured on larger ac or dc signals. In such an

application, the AD7767/AD7767-1/AD7767-2 accurately

gather both ac and dc information.

8.5 mW, 32 kSPS (AD7767-2)

10.5 mW, 64 kSPS (AD7767-1)

15 mW, 128 kSPS (AD7767)

High dc accuracy

24 bits, no missing codes (NMC)

INL: 3 ppm (typical), 7.6 ppm (maximum)

Low temperature drift

Zero error drift: 15 nV/°C

Gain error drift: 0.0075% FS

On-chip low-pass FIR filter

The AD7767/AD7767-1/AD7767-2 include an on-board digital

filter (complete with linear phase response) that acts to elimi-

nate out-of-band noise by filtering the oversampled input

voltage. The oversampled architecture also reduces front-end

antialias requirements. Other features of the AD7767 include a

Linear phase response

Pass-band ripple: 0.005 dB

Stop-band attenuation: 100 dB

2.5 V supply with 1.8 V/2.5 V/3 V/3.6 V logic interface options

Flexible interfacing options

SYNC PD

/

(synchronization/power-down) pin, allowing the

Synchronization of multiple devices

Daisy chain capability

Power-down function

synchronization of multiple AD7767 devices. The addition of

an SDI pin provides the option of daisy chaining multiple

AD7767 devices.

Temperature range: −40°C to +105°C

The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply

using a 5 V reference. The devices operate from −40°C to +105°C.

APPLICATIONS

Low power PCI/USB data acquisition systems

Low power wireless acquisition systems

Vibration analysis

Instrumentation

High precision medical acquisition

RELATED DEVICES

Table 1. 24-Bit Analog-to-Digital Converters

Part No.

Description

AD7760

2.5 MSPS, 100 dB dynamic range¹, on-board differential

amp and reference buffer, parallel, variable decimation

FUNCTIONAL BLOCK DIAGRAM

625 kSPS, 109 dB dynamic range¹, on-board differential

amp and reference buffer, parallel/serial, variable

decimation

AV

AGND MCLK

DV

V

DGND

AD7762/

AD7763

DD

DRIVE

V

REF+

312 kSPS, 109 dB dynamic range¹, on-board differential

amp and reference buffer, variable decimation (pin)

156 kSPS, 112 dB dynamic range¹, on-board differential

amp and reference buffer, variable decimation (pin)

128 kSPS, 109.5 dB¹, 15 mW, 16-bit INL, serial interface

64 kSPS 112.5 dB¹,10.5 mW, 16-bit INL, serial interface

32 kSPS, 115.5 dB¹, 8.5 mW, 16-bit INL, serial interface

V

IN+

AD7764

AD7765

DIGITAL

FIR FILTER

SUCCESSIVE-

APPROXIMATION

ADC

SYNC/PD

CS

V

IN–

SERIAL INTERFACE

AND

CONTROL LOGIC

REFGND

AD7766

AD7767/

AD7767-1/

AD7767-2

AD7766-1

AD7766-2

SCLK DRDY SDO SDI

¹Dynamic range at maximum output data rate.

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7767

TABLE OF CONTENTS

Features .............................................................................................. 1

AD7767 Interface ........................................................................... 17

Initial Power-Up ......................................................................... 17

Reading Data............................................................................... 17

Power-Down, Reset, and Synchronization ............................. 17

Daisy Chaining ............................................................................... 18

Reading Data in Daisy Chain Mode........................................ 18

Choosing the SCLK Frequency ................................................ 18

Daisy Chain Mode Configuration and Timing Diagrams.... 19

Driving the AD7767....................................................................... 20

Differential Signal Source ......................................................... 20

Single-Ended Signal Source ...................................................... 20

Antialiasing ................................................................................. 21

Power Dissipation....................................................................... 21

V_REF+Input Signal ....................................................................... 22

Multiplexing Analog Input Channels...................................... 22

Outline Dimensions....................................................................... 23

Ordering Guide .......................................................................... 23

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 15

AD7767/AD7767-1/AD7767-2 Transfer Function................ 15

Converter Operation.................................................................. 15

Analog Input Structure.............................................................. 16

Supply and Reference Voltages ................................................. 16

REVISION HISTORY

8/07—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD7767

SPECIFICATIONS

AV_DD= DV_DD= 2.5 V 5ꢀ, V_DRIVE= 1.8 V to 3.6 V, V_REF= 5 V, MCLK = 1 MHz, common-mode input = V_REF/2, T_A= −40°C to +105°C,

unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

OUTPUT DATA RATE

AD7767

AD7767-1

Decimate by 8

Decimate by 16

Decimate by 32

128

64

32

kHz

AD7767-2

ANALOG INPUT¹

Differential Input Voltage

Absolute Input Voltage

V_IN+− V_IN−

V_IN+

V_REF

+V_REF+ 0.1

V p-p

V

−0.1

V_IN−

+V_REF+ 0.1

V_REF/2 + 5%

V

pF

Common-Mode Input Voltage

Input Capacitance

V_REF/2 − 5% V_REF/2

22

DYNAMIC PERFORMANCE

AD7767

Decimate by 8, ODR = 128 kHz

Shorted inputs

Dynamic Range²

108

107

109.5

108.5

−128

−118

dB

Signal-to-Noise Ratio (SNR)²

Spurious Free Dynamic Range (SFDR)²

Total Harmonic Distortion (THD)²

Intermodulation Distortion (IMD)²

Full-scale input amplitude, 1 kHz tone

Tone A = 49.7 kHz, Tone B = 53 kHz

Second-order terms

−116

−105

−133

−109

dB

Third-order terms

AD7767-1

Dynamic Range²

Decimate by 16, ODR = 64 kHz

Shorted inputs

111

110

112.5

111.5

−128

−118

dB

Signal-to-Noise Ratio (SNR)²

Spurious Free Dynamic Range (SFDR)²

Total Harmonic Distortion (THD)²

Intermodulation Distortion (IMD)²

Full-scale input amplitude, 1 kHz tone

Tone A = 24.7 kHz, Tone B = 25.3 kHz

Second-order terms

−116

−105

−133

−108

Third-order terms

AD7767-2

Dynamic Range²

Decimate by 32, ODR = 32 kHz

Shorted inputs

114

112

115.5

113.5

−128

−118

dB

Signal-to-Noise Ratio (SNR)²

Spurious Free Dynamic Range (SFDR)²

Total Harmonic Distortion (THD)²

Intermodulation Distortion (IMD)²

Full-scale input amplitude, 1 kHz tone

Tone A = 11.7 kHz, Tone B = 12.3 kHz

Second-order terms

−116

−105

−137

−108

Third-order terms

DC ACCURACY¹

For all devices

Resolution

No missing codes

24

Bits

Differential Nonlinearity²

Integral Nonlinearity²

Zero Error²

Guaranteed monotonic to 24 bits

18-bit linearity

3

20

0.0075

15

0.4

7.6

ppm

μV

% FS

nV/°C

ppm/°C

dB

Gain Error²

0.075

Zero Error Drift²

Gain Error Drift²

Common-Mode Rejection Ratio²

50 Hz tone

−110

Rev. 0 | Page 3 of 24

AD7767

Parameter

DIGITAL FILTER RESPONSE¹

Test Conditions/Comments

Min

Typ

Max

Unit

Group Delay

37/ODR

74/ODR

ꢀs

Settling Time (Latency)

Pass-Band Ripple

Pass Band

−3 dB Bandwidth

Stop Band Frequency

Stop-Band Attenuation

REFERENCE INPUT¹

V_REF+Input Voltage

DIGITAL INPUTS (Logic Levels)¹

V_IL

Complete settling

0.005

dB

Hz

dB

0.453 × ODR

0.49 × ODR

0.547 × ODR

100

+2.4

2 × AV_DD

V

−0.3

0.7 × V_DRIVE

0.3 × V_DRIVE

V_DRIVE+ 0.3

1

V

V_IH

Input Leakage Current

Input Capacitance

Master Clock Rate

Serial Clock Rate

DIGITAL OUTPUTS¹

Data Format

μA/pin

pF

MHz

Hz

5

1.024

1/t₈

Serial 24 bits, twos complement (MSB

first)

V_OL

V_OH

I_SINK= +500 μA

I_SOURCE= −500 ꢀA

0.4

V

V_DRIVE– 0.3

POWER REQUIREMENTS¹

AV_DD

DV_DD

V_DRIVE

5%

+2.5

V

+1.7

+3.6

CURRENT SPECIFICATIONS

MCLK = 1.024 MHz

AD7767 (Operational Current)

128 kHz output data rate

AI_DD

DI_DD

I_REF

1.3

3.9

0.35

1.5

4.8

0.425

mA

AD7767-1 (Operational Current)

AI_DD

DI_DD

I_REF

64 kHz output data rate

32 kHz output data rate

1.3

2.2

0.35

1.5

2.85

0.425

mA

AD7767-2 (Operational Current)

AI_DD

DI_DD

I_REF

1.3

1.37

0.35

1.5

1.86

0.425

mA

Static Current (MCLK Stopped)

AI_DD

DI_DD

Power-Down Mode Current

AI_DD

For all devices

0.9

1

93

mA

μA

0.1

1

6

93

μA

DI_DD

POWER DISSIPATION

AD7767 (Operational Power)

AD7767-1 (Operational Power)

AD7767-2 (Operational Power)

MCLK = 1.024 MHz

128 kHz output data rate

64 kHz output data rate

32 kHz output data rate

15

10.5

8.5

18

13

10.5

mW

¹Specifications for all devices, AD7767, AD7767-1, and AD7767-2.

²See the Terminology section.

Rev. 0 | Page 4 of 24

AD7767

TIMING SPECIFICATIONS

AV_DD= DV_DD= 2.5 V 5ꢀ, V_DRIVE= 1.7 V to 3.6 V, V_REF= 5 V, common-mode input = V_REF/2, T_A= −40°C (T_MIN) to +105°C (T_MAX),

unless otherwise noted ¹

Table 3.

Parameter

DRDY Operation

t₁

Limit at T_MIN, T_MAX

Unit

Description

510

100

900

265

128

71

ns typ

MCLK rising edge to DRDY falling edge

2

t₂

ns min MCLK high pulse width

ns max MCLK low pulse width

t₃

t₄

ns typ

MCLK rising edge to DRDY rising edge (AD7767)

MCLK rising edge to DRDY rising edge (AD7767-1)

MCLK rising edge to DRDY rising edge (AD7767-2)

DRDY pulse width (AD7767)

t₅

294

435

492

DRDY pulse width (AD7767-1)

DRDY pulse width (AD7767-2)

3

t_READ

DRDY low period, read data during this period

t_DRDY− t₅

n × 8 × t_MCLK

ns typ

DRDY period

3

t_DRDY

Read Operation

t₆

t₇

t₈

0

ns min DRDY falling edge to CS setup time

6

ns max CS falling edge to SDO three-state disabled

ns max Data access time after SCLK falling edge (V_DRIVE= 1.7 V)

ns max Data access time after SCLK falling edge (V_DRIVE= 2.3 V)

ns max Data access time after SCLK falling edge (V_DRIVE= 2.7 V)

ns max Data access time after SCLK falling edge (V_DRIVE= 3.0 V)

ns min SCLK falling edge to data valid hold time (V_DRIVE= 3.6 V)

ns min SCLK high pulse width

60

50

25

24

10

1/t₈

6

t₉

t₁₀

t₁₁

t_SCLK

t₁₂

t₁₃

ns min SCLK low pulse width

min

Minimum SCLK period

ns max Bus relinquish time after CS rising edge

ns min CS rising edge to DRDY rising edge

0

Read Operation with CS Low

t₁₄

t₁₅

0

ns min DRDY falling edge to data valid setup time

ns max DRDY rising edge to data valid hold time

Daisy Chain Operation

t₁₆

t₁₇

1

2

ns min SDI valid to SCLK falling edge setup time

ns max SCLK falling edge to SDI valid hold time

SYNC/PD Operation

t₁₈

t₁₉

t₂₀

t₂₁

1

ns typ

SYNC/PD falling edge to MCLK rising edge

20

MCLK rising edge to DRDY rising edge going into SYNC/PD

1

ns min SYNC/PD rising edge to MCLK rising edge

510

ns typ

t_MCLK

MCLK rising edge to DRDY falling edge coming out of SYNC/PD

Filter settling time after a reset or power-down

3

t_SETTLING

592 × (n + 2)

¹Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV_DD) and timed from a voltage level of 1.7 V.

²t₂and t₃allow a ~90% to 10% duty cycle to be used for the MCLK input where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum

MCLK frequency is 1.024 MHz.

³n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.

Rev. 0 | Page 5 of 24

AD7767

TIMING DIAGRAMS

t₂

1

8 × n

t₄

1

8 × n

MCLK

t₃

t₁

t₅

t_READ

DRDY

t_DRDY

DRDY

Figure 2.

vs. MCLK Timing Diagram, n = 1 for AD7767 (Decimate by 8), n = 2 for AD7767-1 (Decimate by 16), n = 4 for AD7767-2 (Decimate by 32)

t_DRDY

t_READ

DRDY

t₁₃

t₆

CS

t₁₀

1

23

SCLK

t₁₁

t₈

t₉

t₇

t₁₂

SDO

MSB

D22

D21

D20

D1

LSB

CS

Figure 3. Serial Timing Diagram, Reading Data Using

CS = 0

DRDY

t_DRDY

t_READ

t₁₄

t₁₀

1

23

24

SCLK

SDO

t₁₁

t₈

t₉

t₁₅

DATA

INVALID

DATA

INVALID

MSB

D22

D21

D20

D1

LSB

CS

Figure 4. Serial Timing Diagram, Reading Data Setting Logic Low

Rev. 0 | Page 6 of 24

AD7767

PART OUT OF POWER-DOWN

FILTER RESET

PART IN POWER-DOWN

A

BEGINS SAMPLING

MCLK (I)

B

C

D

t₂₀

t₁₈

SYNC/PD (I)

t₂₁

t₁₉

DRDY (O)

DOUT (O)

t_SETTLING

VALID DATA

INVALID DATA

VALID DATA

Figure 5. Reset, Synchronization, and Power-Down Timing Diagram

Rev. 0 | Page 7 of 24

AD7767

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 4.

Parameter

Rating

AV_DDto AGND

DV_DDto DGND

AV_DDto DV_DD

V_REF+to REFGND

REFGND to AGND

V_DRIVEto DGND

V_IN+,V_IN–to AGND

Digital Inputs to DGND

Digital Outputs to DGND

AGND to DGND

−0.3 V to +3 V

−0.3 V to +0.3 V

−0.3 V to +7 V

−0.3 V to + 0.3 V

−0.3 V to +6 V

−0.3 V to V_REF+0.3 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to +0.3 V

10 mA

ESD CAUTION

Input Current to Any Pin Except

Supplies¹

Operating Temperature Range

Storage Temperature Range

Junction Temperature

TSSOP Package

−40°C to +105°C

−65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 sec)

Infrared (15 sec)

150.4°C/W

27.6°C/W

215°C

220°C

1 kV

ESD

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. 0 | Page 8 of 24

AD7767

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AV

CS

DD

SDI

V

REF+

AD7767/

AD767-1/

AD7767-2

TOP VIEW

(Not to Scale)

REFGND

MCLK

SCLK

DRDY

DGND

SDO

V

IN+

V

IN–

AGND

SYNC/PD

DV

V

DRIVE

DD

Figure 6. 16-Lead TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

2

AV_DD

V_REF+

+2.5 V Analog Power Supply.

Reference Input for the AD7767. An external reference must be applied to this input pin. The V_REF+input can range

from 2.4 V to 5 V. The reference voltage input is independent of the voltage magnitude applied to the AV_DDpin.

3

REFGND

Reference Ground. Ground connection for the reference voltage. The input reference voltage (V_REF+) should be

decoupled to this pin.

4

5

6

7

V_IN+

V_IN−

AGND

SYNC/PD

Positive Input of the Differential Analog Input.

Negative Input of the Differential Analog Input.

Power Supply Ground for Analog Circuitry.

Synchronization and Power-Down Input Pin. This pin has dual functionality. It can be used to synchronize multiple

AD7767 devices and/or put the AD7767 device into power-down mode. See the Power-Down, Reset, and

Synchronization section for further details.

8

9

DV_DD

V_DRIVE

Digital Power Supply Input. This pin can be connected directly to V_DRIVE.

Logic Power Supply Input, +1.8 V to +3.6 V. The voltage supplied at this pin determines the operating voltage of

the digital logic interface.

10

SDO

Serial Data Output (SDO). The conversion result from the AD7767 is output on the SDO pin as a 24-bit, twos

complement, MSB first, serial data stream.

11

12

DGND

DRDY

Digital Logic Power Supply Ground.

Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data result is available in the

output register of the AD7767. See the AD7767 Interface section for further details.

13

SCLK

Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the AD7767 device. See

the AD7767 Interface section for further details.

14

15

16

MCLK

SDI

CS

Master Clock Input. The AD7767 sampling frequency is equal to the MCLK frequency.

Serial Data Input. This is the daisy chain input of the AD7767. See the Daisy Chaining section for further details.

Chip Select Input. The CS input selects the AD7767 device and acts as an enable on the SDO pin. In cases where CS

is used, the MSB of the conversion result is clocked onto the SDO line on the CS falling edge. The CS input allows

multiple AD7767 devices to share the same SDO line. This allows the user to select the appropriate device by

supplying it with a logic low CS signal, which enables the SDO pin of the device concerned. See the AD7767

Interface section for further details.

Rev. 0 | Page 9 of 24

AD7767

TYPICAL PERFORMANCE CHARACTERISTICS

AV_DD= DV_DD= 2.5 V 5ꢀ, V_DRIVE= 1.8 V to 3.6 V, V_REF= 5 V, MCLK = 1 MHz, common-mode input = V_REF/2. T_A= 25°C, unless

otherwise noted. All FFTs were generated using 8192 samples using a 4-term Blackman-Harris window.

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

8k

16k

24k

32k

40k

48k

56k

64k

0

8k

16k

24k

32k

40k

48k

56k

64k

FREQUENCY (Hz)

Figure 10. AD7767 FFT, 1 kHz, −6 dB Input Tone

Figure 7. AD7767 FFT, 1 kHz, −0.5 dB Input Tone

0

–20

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

4k

8k

12k

16k

20k

24k

28k

32k

0

4k

8k

12k

16k

20k

24k

28k

32k

FREQUENCY (Hz)

Figure 11. AD7767-1 FFT, 1 kHz, −6 dB Input Tone

Figure 8. AD7767-1 FFT, 1 kHz, −0.5 dB Input Tone

0

–20

0

–20

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

4k

8k

12k

16k

0

4k

8k

12k

16k

FREQUENCY (Hz)

Figure 9. AD7767-2 FFT, 1 kHz, −0.5 dB Input Tone

Figure 12. AD7767-2 FFT, 1 kHz, −6 dB Input Tone

Rev. 0 | Page 10 of 24

AD7767

0

–20

0

–20

TONE A: 49.7kHz

TONE B: 50.3kHz

SECOND-ORDER IMD = –133.71dB

THIRD-ORDER IMD = –109.05dB

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0

8k

16k

24k

32k

40k

48k

56k

64k

32k

16k

0

8k

16k

24k

32k

40k

48k

56k

64k

32k

16k

FREQUENCY (Hz)

Figure 13. AD7767 FFT, 1 kHz, −60 dB Input Tone

Figure 16. AD7767 IMD FFT, 50 kHz Center Frequency

0

–20

0

–20

TONE A: 24.7kHz

TONE B: 25.3kHz

SECOND-ORDER IMD = –133.33dB

THIRD-ORDER IMD = –108.15dB

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

4k

8k

12k

16k

20k

24k

28k

0

4k

8k

12k

16k

20k

24k

28k

FREQUENCY (Hz)

Figure 14. AD7767-1 FFT, 1 kHz, −60 dB Input Tone

Figure 17. AD7767-1 IMD FFT, 25 kHz Center Frequency

0

–20

0

–20

TONE A: 11.7kHz

TONE B: 12.3kHz

SECOND-ORDER IMD = –137.96dB

THIRD-ORDER IMD = –108.1dB

–40

–60

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

4k

8k

12k

0

4k

8k

12k

FREQUENCY (Hz)

Figure 15. AD7767-2 FFT, 1 kHz, −60 dB Input Tone

Figure 18. AD7767-2 IMD FFT, 12 kHz Center Frequency

Rev. 0 | Page 11 of 24

AD7767

–110

–112

–114

–116

–118

–120

–122

–124

–126

–128

120

115

110

105

100

95

DYNAMIC RANGE

AD7767-2

OPEN INPUTS

AD7767-1

AD7767

FULL-SCALE 921Hz

–130

0

90

100k 200k 300k 400k 500k 600k 700k 800k 900k 1M

FREQUENCY (Hz)

0

10k

20k

30k

40k

50k

60k

f_NOISE(Hz)

Figure 19. AD7767/AD7767-1/AD7767-2 THD vs. MCLK Frequency

Figure 22. AD7767 CMRR vs. Common-Mode Ripple Frequency

115

200

MAX = 8388637

MIN = 8388493

SPREAD = 145

180

160

140

120

100

80

114

AD7767-2

113

112

111

AD7767-1

110

60

109

AD7767

40

108

107

20

0

100k 200k 300k 400k 500k 600k 700k 800k 900k 1M

FREQUENCY (Hz)

CODES

Figure 20. AD7767/AD7767-1/AD7767-2 SNR and THD vs. MCLK Frequency

Figure 23. AD7767 24-Bit Histogram

150

250

200

150

100

50

AV

DD

DV

MAX = 8388507

DD

MIN = 8388608

SPREAD = 102 CODES

140

130

120

110

100

V

DRIVE

0

10k

20k

30k

f_NOISE(Hz)

40k

50k

60k

CODES

Figure 21. AD7767 Power Supply Sensitivity vs. Supply Ripple Frequency with

Decoupling Capacitors

Figure 24. AD7767-1 24-Bit Histogram

Rev. 0 | Page 12 of 24

AD7767

3.80

3.04

2.28

1.52

0.76

0

MAX = 8388593

LOW TEMPERATURE

NOMINAL TEMPERATURE

HIGH TEMPERATURE

350

300

250

200

150

100

50

MIN = 8388526

SPREAD = 69 CODES

–0.76

–1.52

–2.28

–3.04

–3.80

0

4194304

2097152 6291456

24-BIT CODES

8388608

12582912

16777216

10485760

14680064

CODES

Figure 25. AD7767-2 24-Bit Histogram

Figure 27. AD7767/AD7767-1/AD7767-2, 24-Bit INL

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

4194304

2097152 6291456

24-BIT CODES

8388608

12582912

16777216

10485760

14680064

Figure 26. AD7767/AD7767-1/AD7767-2, 24-Bit DNL

Rev. 0 | Page 13 of 24

AD7767

TERMINOLOGY

Signal-to-Noise Ratio (SNR)

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in decibels.

SNR is the ratio of the rms value of the actual input signal to the

rms sum of all other spectral components below the Nyquist

frequency, excluding harmonics and dc. The value for SNR is

expressed in decibels.

Integral Nonlinearity (INL)

INL is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of harmonics to the fundamen-

tal. For the AD7767, it is defined as

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal

1 LSB change between any two adjacent codes in the ADC.

V₂²+ V₃²+ V₄²+ V₅²+ V₆²

Zero Error

THD

where:

(dB) = 20 log

Zero error is the difference between the ideal midscale input

voltage (when both inputs are shorted together) and the actual

voltage producing the midscale output code.

V₁

V₁is the rms amplitude of the fundamental.

V₂, V₃, V₄, V₅, and V₆are the rms amplitudes of the second to

the sixth harmonics.

Zero Error Drift

Zero error drift is the change in the actual zero error value due

to a temperature change of 1°C. It is expressed as a percentage

of full scale at room temperature.

Nonharmonic Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of the rms signal amplitude to the rms value

of the peak spurious spectral component, excluding harmonics.

Gain Error

The first transition (from 100…000 to 100…001) should occur

for an analog voltage ½ LSB above the nominal negative full

scale. The last transition (from 011…110 to 011…111) should

occur for an analog voltage 1½ LSB below the nominal full

scale. The gain error is the deviation of the difference between

the actual level of the last transition and the actual level of the

first transition, from the difference between the ideal levels.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to

the rms noise measured with the inputs shorted together. The

value for the dynamic range is expressed in decibels.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n are equal to 0. For example,

the second-order terms include (fa + fb) and (fa − fb), and the

third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and

(fa − 2fb).

Gain Error Drift

Gain error drift is the change in the actual gain error value due

to a temperature change of 1°C. It is expressed as a percentage

of full scale at room temperature.

Common-Mode Rejection Ratio (CMRR)

CMRR is defined as the ratio of the power in the ADC output

at full-scale frequency f to the power of a 100 mV sine wave

applied to the common-mode voltage of the V_IN+and V_IN−

inputs at frequency fs.

The AD7767 is tested using the CCIF standard, where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, and the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification, where it is the ratio of the rms

CMRR (dB) = 10 log(Pf/Pfs)

where Pf is the power at the frequency f in the ADC output and

Pfs is the power at the frequency fs in the ADC output.

Rev. 0 | Page 14 of 24

AD7767

THEORY OF OPERATION

The AD7767/AD7767-1/AD7767-2 operate using a fully

differential analog input applied to a successive approximation

(SAR) core. The output of the oversampled SAR is filtered using

a linear phase digital FIR filter. The fully filtered data is output

in a serial format, with the MSB being clocked out first.

The digital filtering that follows the converter output acts to

remove the out-of-band quantization noise (see Figure 30). This

also has the effect of reducing the data rate from f_MCLKat the

input of the filter to f_MCLK/8, f_MCLK/16, or f_MCLK/32 at the digital

output, depending on which model of the device is being used.

The digital filter consists of three separate filter blocks. Figure 31

shows the three constituent blocks of the filter. The order of

decimation of the first filter block is set as 2, 4, or 8. The

remaining sections both operate in decimate by 2.

AD7767/AD7767-1/AD7767-2 TRANSFER

FUNCTION

The conversion results of the AD7767/AD7767-1/AD7767-2 are

output in a twos complement, 24-bit serial format. The fully

differential inputs V_IN+and V_IN−are scaled by the AD7767/

AD7767-1/AD7767-2 relative to the reference voltage input

(V_REF+), as shown in Figure 28.

DIGITAL FILTER

STAGE 1

STAGE 2

STAGE 3

DATA

STREAM

SINC FILTER

FIR FILTER

SDO

24 BITS

TWOS

COMPLEMENT

DEC × (2 × n)

DEC × 2

011...111

011...110

Figure 31. FIR Filter Stages

(n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2)

000...010

000...001

Table 6 shows the three available models of the AD7767, listing

the change in output data rate relative to the order of decimation

rate implemented. This brings into focus the trade-off that

exists between extra filtering and reduction in bandwidth,

whereby using a filter option with a larger decimation rate

increases the noise performance while decreasing the usable

input bandwidth.

000...000

111...111

111...110

100...001

100...000

Table 6. AD7767 Models

V

= 0V

V

= V

– 1LSB

IN+

REF

2

REF

IN+

REF

Model

Decimation Rate

Output Data Rate (ODR)

V

=

IN+

V

= V

– 1LSB

V

= 0V

IN–

REF

IN–

AD7767

AD7767-1

AD7767-2

8

16

32

128 kHz

64 kHz

32 kHz

IN–

2

Figure 28. AD7767/AD7767-1/AD7767-2 Transfer Function

CONVERTER OPERATION

Note that the output data rates shown in Table 6 are realized

when using the maximum MCLK input frequency of 1.024 MHz.

The output data rate scales linearly with the MCLK frequency,

as does the digital power dissipated in the device.

Internally, the input waveform applied to the SAR core is

converted and an equivalent digital word is output to the digital

filter at a rate equal to MCLK. By employing oversampling, the

quantization noise of the converter is spread across a wide

bandwidth from 0 to f_MCLK.This means that the noise energy

contained in the signal band of interest is reduced (see

Figure 29).

The settling time of the filter implemented on the AD7767,

AD7767-1, and AD7767-2 is related to the length of the filter

employed. The response of the filter in the time domain sets the

filter settling time. Table 7 shows the filter settling times of the

AD7767/AD7767-1/AD7767-2.

The frequency responses of the digital filters on the AD7767,

AD7767-1, and AD7767-2 are shown in Figure 32, Figure 33,

and Figure 34, respectively. At the Nyquist frequency (output

data rate/2), the digital filter provides 6 dB of attenuation. In each

case, the filter provides stop-band attenuation of 100 dB and

pass-band ripple of 0.005 dB.

QUANTIZATION NOISE

f_MCLK/2

BAND OF INTEREST

Figure 29. Quantization Noise

DIGITAL FILTER CUTOFF FREQUENCY

f_MCLK/2

BAND OF INTEREST

Figure 30. Digital Filter Cutoff Frequency

Rev. 0 | Page 15 of 24

AD7767

0

ANALOG INPUT STRUCTURE

–20

The AD7767/AD7767-1/AD7767-2 are configured as a

differential input structure. A true differential signal is sampled

between the analog inputs V_IN+and V_IN−, Pin 4 and Pin 5,

respectively. Using differential inputs provides rejection of

signals that are common to both the V_IN+and V_IN−pins.

–40

–60

–80

Figure 35 shows the equivalent analog input circuit of the

AD7767/AD7767-1/AD7767-2. The two diodes on each of the

differential inputs provide ESD protection for the analog inputs.

–100

–120

–140

V

REF+

D

–160

0

C2

R

IN

16k

32k

48k

64k

80k

96k

112k

128k

V

IN+

FREQUENCY (Hz)

C1

Figure 32. AD7767 Digital Filter Frequency Response

GND

AGND

V

REF+

0

–20

D

C2

R

IN

V

IN–

C1

D

–40

GND

AGND

–60

Figure 35. Equivalent Analog Input Structure

–80

Take care to ensure that the analog input signal does not exceed

the reference supply voltage V_REF+by more than 0.3 V as specified

in the Absolute Maximum Ratings section. The diodes become

forward biased if the input voltage exceeds this limit and start to

conduct current. The diodes can handle 130 mA maximum.

–100

–120

–140

–160

The impedance of the analog inputs can be modeled as a

parallel combination of C1 and the network formed by the

series connection of R_IN, C1, and C2. The value of C1 is

dominated by the pin capacitance. R_INis typically 1.4 kΩ, the

lumped component of serial resistors and the R_ONof the

switches. C2 is typically 22 pF, and its value is dominated by the

sampling capacitor.

0

8k

16k

24k

32k

40k

48k

56k

64k

FREQUENCY (Hz)

Figure 33. AD7767-1 Digital Filter Frequency Response

0

–20

SUPPLY AND REFERENCE VOLTAGES

–40

The AD7767/AD7767-1/AD7767-2 operate from a 2.5 V supply

applied to the DV_DD, AV_DDpins. The interface is specified to

operate between 1.7 V and 3.6 V. The AD7767/AD7767-1/

AD7767-2 operate from a 5 V reference applied to the V_REF+pin.

The recommended reference devices are the ADR445 or the

ADR425. The 5 V reference operates both as a reference supply

and as a power supply to the AD7767/AD7767-1/AD7767-2

device. This feature means that the full-scale differential input

range of the AD7767/AD7767-1/AD7767-2 is 10 V. See the

Driving the AD7767 section for details on the maximum input

voltage.

–60

–80

–100

–120

–140

–160

0

4k

8k

12k

16k

20k

24k

28k

32k

FREQUENCY (Hz)

Figure 34. AD7767-2 Digital Filter Frequency Response

Rev. 0 | Page 16 of 24

AD7767

AD7767 INTERFACE

The AD7767 provides the user with a flexible serial interface,

enabling the user to implement the most desirable interfacing

scheme for their application. The AD7767 interface comprises

seven different signals. Five of these signals are inputs: MCLK,

CS

is logic

devices indicating permission to use the bus. When

high, the SDO line of the AD7767 is tristated.

There are two distinct patterns that can be initiated to read data

CS

from the AD7767 device; these are for the cases when the

falling edge occurs after the falling edge and for the case

CS SYNC PD

,

/

, SCLK, and SDI. There are two output signals:

DRDY

falling edge occurs before the

is set to logic low).

DRDY

and SDO.

CS

when the

CS

falling edge

DRDY

INITIAL POWER-UP

(when

When the

MSB of the conversion result is available on the SDO line on

CS

On initial power-up, apply a continuous MCLK signal. It is

recommended that the user reset the AD7767 to clear the filters

and ensure correct operation. The reset is completed as described

in Figure 5, with all events occurring relative to the rising edge

CS

falling edge occurs after

falling edge, the

DRDY

this

falling edge. The remaining bits of the conversion result

(MSB-1, MSB-2, and so on) are clocked onto the SDO line by

of MCLK. A negative pulse on the

/

input initiates the

SYNC PD

CS

the falling edges of SCLK that follow the

details this interfacing scheme.

falling edge. Figure 3

reset, and the

output switches to logic high and remains

DRDY

high until valid data is available. Following the power-up of the

SYNC PD

CS

When

is tied low, the AD7767 serial interface can operate in

3-wire mode as shown in Figure 4. In this case, the MSB of the

conversion result is available on the SDO line on the falling

. The remaining bits of the data conversion result

(MSB-1, MSB-2, and so on) are clocked onto the SDO line by

the subsequent SCLK falling edges.

AD7767 by transitioning the

/

pin to logic high, a

settling time is required before valid data is output by the

device. This settling time, t_SETTLING, is a function of the MCLK

frequency and the decimation rate. Table 7 lists the settling time

of each of the AD7767 models and should be referenced to

Figure 5.

DRDY

edge of

POWER-DOWN, RESET, AND SYNCHRONIZATION

SYNC PD

Table 7. Filter Settling Time After

/

SYNC

1

The AD7767

/

pin allows the user to synchronize

PD

Model

Decimation Rate

t_SETTLING

multiple AD7767 devices. This pin also allows the user to reset

and power down the AD7767 device. These features are

implemented relative to the rising edges of MCLK and are

shown in Figure 5.

AD7767

AD7767-1

AD7767-2

8

16

32

594 × (t_MCLK+ t₂₁)

1186 × (t_MCLK+ t₂₁)

2370 × (t_MCLK+ t₂₁)

¹t_SETTLINGis measured from the first MCLK rising edge after the rising edge of

to the falling edge of

/

.

DRDY

SYNC PD

To power down, reset, or synchronize a device, the AD7767

/

pin should be taken low. On the first rising edge of

SYNC PD

READING DATA

MCLK, the AD7767 is powered down. The

pin transi-

DRDY

tions to logic high, indicating that the data in the output register

is no longer valid. The status of the pin is checked on

The AD7767 outputs its data conversion results in an MSB first,

twos complement, 24-bit format on the serial data output pin

(SDO). MCLK is the master clock, which controls all the AD7767

conversions. The SCLK is the serial clock input for the device.

All data transfers take place with respect to the SCLK signal.

/

SYNC PD

each subsequent rising edge of MCLK. On the first rising edge

of MCLK after the pin is taken high, the AD7767 is

/

SYNC PD

taken out of power-down. On the next rising edge, the filter of

the AD7767 is reset. On the following rising edge, the first new

sample is taken.

The

line is used as a status signal to indicate when the

DRDY

data is available to be read from the AD7767. The falling edge of

indicates that a new data-word is available in the output

DRDY

register of the device.

A settling time, t_SETTLING, from the filter reset, must pass before

valid data is output by the device (as listed in Table 7). The

stays low during the period that

DRDY

output data is permitted to be read from the SDO pin. The

signal returns to logic high to indicate when not to read

DRDY

output goes logic low after t_SETTLINGto indicate when

valid data is available on SDO for readback.

DRDY

from the device. Ensure that a data read is not attempted during

this period as the output register is being updated.

The AD7767 offers the user the option of using a chip select

CS

input signal ( ) in its data read cycle. The

signal is a gate

for the SDO pin and allows many AD7767 devices to share the

same serial bus, acting as an instruction signal to each of these

Rev. 0 | Page 17 of 24

AD7767

DAISY CHAINING

Daisy chaining devices allows numerous devices to use the same

digital interface lines by cascading the outputs of multiple ADCs

on a single data line. This feature is especially useful for reduc-

ing component count and wiring connections, for example, in

isolated multiconverter applications or for systems with a limited

interfacing capacity. Data readback is analogous to clocking a

shift register where data is clocked on the falling edge of SCLK.

DRDY

signal is active low. This is

illustrated in the example shown where the conversion results

from devices A, B, C, and D are clocked onto SDO (A) in the

device in the chain while its

DRDY

time between the falling edge of

DRDY

(A) and the rising edge

of

(A).

CHOOSING THE SCLK FREQUENCY

As shown in Figure 36, the number of SCLK falling edges that

The block diagram in Figure 36 shows the way in which devices

must be connected in order to achieve daisy chain functionality.

This scheme operates by passing the output data of the SDO pin

of an AD7767 device to the SDI input of the next AD7767 device

in the chain. The data then continues through the chain until it

is clocked onto the SDO pin of the first device on the chain.

DRDY

occur during the period when

(A) is active low must

match the number of devices in the chain multiplied by 24 (the

number of bits that must be clocked through onto SDO (A) for

each device).

The period of SCLK (t_SCLK) required for a known daisy chain

length using a known common MCLK frequency must

therefore be established in advance. Note that the maximum

SCLK frequency is governed by t₈and is specified in the Timing

Specifications table for different V_DRIVEvoltages.

READING DATA IN DAISY CHAIN MODE

An example of a daisy chain of four AD7767 devices is shown in

Figure 36 and Figure 37. In the case illustrated in Figure 36, the

output of AD7767 (A) is the output of the full daisy chain. The

last device in the chain (AD7767 (D)) has its serial data in (SDI)

pin connected to ground. All the devices in the chain must use

CS

In the case where

is tied logic low,

t_READ

⎡

⎤

t_SCLK

≤

(1)

⎢

⎣

⎥

CS

SYNC PD

common MCLK, SCLK, , and

/ signals.

24 × K

⎦

To enable the daisy chain conversion process, apply a common

SYNC PD

the chain (see the Power-Down, Reset, and Synchronization

section).

where:

K is the number of AD7767 devices in the chain.

/

pulse to all devices, synchronizing all the devices in

t

_SCLKis the period of the SCLK.

t

_READequals t_DRDY− t₅.

SYNC PD

pulse to all the devices, there is a

After applying a

/

CS

In the case where

is used in the daisy chain interface,

delay (as listed in Table 7) before valid conversion data appears

at the output of the chain of devices. As shown in Figure 37,

the first conversion result is output from the device labeled

AD7767 (A). This 24-bit conversion result is followed by the

conversion results from the devices B, C, and D, respectively,

with all conversion results output in an MSB first sequence. The

stream of conversion results is clocked through each device in

the chain and is eventually clocked onto the SDO pin of the

AD7767 (A) device. The conversion results of the all the devices

in the chain must be clocked onto the SDO pin of the final

(

t

)

−

(

t₆+ t₇+ t₁₃

)

⎡

⎤

READ

t_SCLK

≤

(2)

⎢

⎣

⎥

⎦

24 × K

where:

K is the number of AD7767 devices in the chain.

Note that the maximum value of SCLK is governed by t₈and is

specified in the Timing Specifications table for different V_DRIVE

voltages.

Rev. 0 | Page 18 of 24

AD7767

DAISY CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS

SYNC/PD

CS

SYNC/PD

CS DRDY

CS

AD7767

(D)

AD7767

(C)

AD7767

(B)

AD7767

(A)

SDO

SDI

SDO

SDI

SDO

SDI

SDO

SDI

SCLK

MCLK

SCLK

MCLK

Figure 36. AD7767 Daisy Chain Configuration with Four AD7767 Devices

1

8 × n

MCLK

DRDY (A)

CS

24 × t_SCLK

SCLK

AD7767 (A)

AD7767 (B)

AD7767 (C)

AD7767 (D)

AD7767 (B)

AD7767 (C)

AD7767 (D)

AD7767 (C)

AD7767 (D)

AD7767 (A)

AD7767 (B)

AD7767 (C)

AD7767 (D)

SDO (A)

SDI (A) = SDO (B)

SDI (B) = SDO (C)

SDI (C) = SDO (D)

Figure 37. AD7767 Daisy Chain Timing Diagram (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) Driving the AD7767

1

MCLK

DRDY (A)

CS

SDO (A)

SCLK

MSB (A)

LSB (A) MSB (B)

LSB (B) MSB (C)

LSB (C)

t₁₆

t₁₇

MSB (B)

LSB (B) MSB (C)

LSB (C) MSB (D)

LSB (D)

SDI (A) = SDO (B)

Figure 38. AD7767 Daisy Chain SDI Setup and Hold Timing

Rev. 0 | Page 19 of 24

AD7767

DRIVING THE AD7767

The AD7767 must be driven with fully differential inputs. The

common-mode voltage of the differential inputs to the AD7767

device and thus the limits on the differential inputs are set by

the reference voltage V_REFapplied to the device. The common-

mode voltage of the AD7767 is V_REF/2. Where the AD7767 V_REF+

pin is supplied with a 5 V supply (the ADR445 or ADR425), the

common mode is at 2.5 V. This means that the maximum inputs

that can be applied on the AD7767 differential inputs are a

5 V p-p input around 2.5 V.

DIFFERENTIAL SIGNAL SOURCE

An example of some recommended driving circuitry that can

be employed in conjunction with the AD7767/AD7767-1/

AD7767-2 is shown in Figure 40. Figure 40 shows how the

ADA4841-1 device can be used to drive an input to the AD7767/

AD7767-1/AD7767-2 from a differential source. Each of the

differential paths is driven by an ADA4841-1 device.

499Ω

3.3nF

V

REF

499Ω

2.5V

1

A

IN+

3.3Ω

V

ADA4841-1

V

REF

2

IN+

4

5

V

AV

DD

IN+

499Ω

10nF

AD7767

0V

3.3nF

V

REF+

IN–

V

REF

2

499Ω

1kΩ

A

IN–

3.3Ω

V

IN–

ADR425

ADA4841-1

V

REF

2

2× V

CM

1kΩ

0V

Figure 40. Driving the AD7767 from a Fully Differential Source

Figure 39. Maximum Differential Inputs to the AD7767

SINGLE-ENDED SIGNAL SOURCE

An analog voltage of 2.5 V supplies the AD7767 AV_DDpin.

However, the AD7767 allows the user to apply a reference

voltage of up to 5 V. This provides the user with an increased

full-scale range, offering the user the option of using the

AD7767 with a larger LSB voltage size. Figure 39 shows the

maximum and minimum inputs to the AD7767.

In the case where the AD7767 is being supplied from a single-

ended source, the application circuit in Figure 41 can be used to

drive the AD7767 device. Figure 41 shows how the ADA4941-1

single-to-differential amplifier can be used to create a fully

differential input to the AD7767. The single-ended signal input

is applied to the positive input of the ADA4941-1 device.

Arrange the values of the resistor elements to create a 2.5 V

common-mode input to the AD7767/AD7767-1/AD7767-2

device. R3 and C2 default to 3.3 Ω and 10 nF, respectively.

V

SS–

R1

A

IN+

R1

C1

2.5V

8

7

6

5

1

R3

4

5

V

AV

IN+

DD

C2

R3

AD7767

V

REF+

IN–

ADA4941-1

2

ADR425

1

2

3

4

R4

C3

V

OFFSET

R2

V

SS+

R5

2× V

CM

R2

R

FB

C

FB

Figure 41. Driving the AD7767 from a Single-Ended Source

Rev. 0 | Page 20 of 24

AD7767

in use. For instance, operating the AD7767 device with an

MCLK of 800 kHz gives an output data rate of 100 kHz due to

the decimate by 8 filtering.

ANTIALIASING

The AD7767/AD7767-1/AD7767-2 sample the analog input

at a maximum rate of 1.024 MHz. The on-board digital filter

provides up to 100 dB attenuation of any possible aliasing

frequencies in the range from the beginning of the filter stop

band (0.547 × ODR) to where the image of the digital filter pass

band occurs at MCLK − filter stop band (MCLK − 0.547 × ODR),

which is the first alias point. This is illustrated in Figure 42.

4.5

4.0

3.5

DI

DD

3.0

2.5

2.0

1.5

f_MCLK

AI

I

DD

DIGITAL FILTER

IMAGE AT f_MCLK

1.0

0.5

0

DIGITAL FILTER 100dB

ANTIALIAS PROTECTION

REF

f_MCLK– (0.547 × ODR)

FIRST ALIAS POINT

BAND OF INTEREST

0

100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k

FREQUENCY (Hz)

Figure 42. AD7767/AD7767-1/AD7767 Spectrum

Figure 43. AD7767 Current vs. MCLK Frequency

Table 8 shows the attenuation achieved by various orders of

front-end antialias filters prior to the AD7767/AD7767-1/

AD7767-2 at the image of the digital filter stop band, which is

1.024 MHz − 0.547 × ODR.

2.5

2.0

1.5

1.0

0.5

0

Table 8. Antialias Filter Order Attenuation at First Alias Point

DI

DD

Attenuation at

1.024 MHz – 0.547 × ODR

Model

Filter Order

AD7767

1^st

27 dB

50 dB

70 dB

33 dB

62 dB

89 dB

38 dB

74 dB

110 dB

2^nd

3^rd

1^st

2^nd

3^rd

1^st

AI

DD

AD7767-1

AD7767-2

I

REF

2^nd

3^rd

0

100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k

FREQUENCY (Hz)

Figure 44. AD7767-1 Current vs. MCLK Frequency

The AD7764 and AD7765 sigma-delta devices are available to

customers that require extra antialias protection. These devices

sample internally at a rate of 20 MHz to achieve up to a maxi-

mum of 156 kHz or 312 kHz output data rate. This means that

the first alias point of these devices when run at the maximum

speeds are 19.921 MHz and 19.843 MHz, respectively.

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

DI

DD

AI

DD

POWER DISSIPATION

The AD7767/AD7767-1/AD7767-2 offer exceptional perform-

ance at ultralow power. Figure 43, Figure 44, and Figure 45

show how the current consumption of the AD7767/AD7767-1/

AD7767-2 scales with the MCLK frequency applied to the

device. Both the digital and analog currents scale as the MCLK

frequency is reduced. The actual throughput of each of the

AD7767/AD7767-1/AD7767-2 equals the MCLK frequency

applied divided by the decimation rate employed by the device

I

REF

0

100k 200k 300k 400k 500k 600k 700k 800k 900k 1000k

FREQUENCY (Hz)

Figure 45. AD7767-2 Current vs. MCLK Frequency

Rev. 0 | Page 21 of 24

AD7767

V_REF+INPUT SIGNAL

MULTIPLEXING ANALOG INPUT CHANNELS

The AD7767/AD7767-1/AD7767-2 V_{REF +}pin is supplied with a

5 V input, which is generated by a low noise voltage reference.

Either the ADR445 or the ADR425 can be used with the AD7767/

AD7767-1/AD7767-2 device. This reference voltage input also

acts as a power supply to the AD7767/AD7767-1/AD7767-2

device.

The AD7767/AD7767-1/AD7767-2 can be used with a multi-

plexer configuration. As per any converter that uses a digital

filtering block, the maximum switching rate, or output data rate

per channel, is a function of the digital filter settling time.

A user multiplexing the analog inputs to a converter that

employs a digital filter must wait the full digital filter settling

time before a valid conversion result is achieved; at this point,

the channel can be switched. After switching the channel, the

full settling time must again be observed before a valid conver-

sion result is available and the input is switched once more.

The output of the low noise voltage reference does not require a

buffer; however, it is important to provide a passive filter network

between the V_OUTpin of the voltage reference and the V_REF+

input on the ADC. Figure 46 shows a reference signal network

that can be used with both the ADR445 and the ADR425.

The AD7767 filter settling time equals 74 divided by the output

data rate in use. The maximum switching frequency in a

multiplexed application is therefore 1/(74/ODR), where the

output data rate (ODR) is a function of the applied MCLK

frequency and the decimation rate employed by the device in

question. For example, applying a 1.024 MHz MCLK frequency

to the AD7767 gives a maximum output data rate of 128 kHz,

which in turn allows a 1.729 kHz multiplexer switching rate.

The 100 nF capacitor on the output of the ADR445 or ADR425

stabilizes the reference output voltage. The series resistor coupled

with the other capacitive values on the reference acts as a low-

pass filter. Figure 46 shows the optimal reference voltage input

circuit.

100Ω

5V

V

REF+

OUT

ADR445

OR

ADR425

C39

100nF

C40

100µF

C15

10µF

C38

100nF

AD7767/

AD7767-1/

AD7767-2

The AD7767-1 and the AD7767-2 employ digital filters with

longer settling time to achieve greater precision; thus, the

maximum switching frequency for these devices is 864 Hz and

432 Hz, respectively.

Figure 46. AD7767/AD7767-1/AD7767-2 Reference Filtering,

ADR445 or ADR425 Circuit Topology

For the capacitor designated C40 in Figure 46, either an

electrolytic or tantalum capacitor can be used. This capacitor

acts as a reservoir of charge. Further decoupling capacitors are

placed as close as possible to the V_REF+pin.

Rev. 0 | Page 22 of 24

AD7767

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +105°C

Package Description

Package Option

AD7767BRUZ¹

16-Lead Thin Shrink Small Outline Package [TSSOP]

Evaluation Board

Converter Evaluation and Development Board

RU-16

AD7767BRUZ-RL7¹

AD7767BRUZ-1¹

AD7767BRUZ-1-RL7¹

AD7767BRUZ-2¹

AD7767BRUZ-2-RL7¹

EVAL-AD7767EDZ¹

EVAL-AD7767-1EDZ¹

EVAL-AD7767-2EDZ¹

EVAL-CED1Z¹

¹Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

AD7767

NOTES

registered trademarks are the property of their respective owners.

D06859-0-8/07(0)

Rev. 0 | Page 24 of 24


型号：	EVAL-AD7767-2EDZ
厂家：	ADI
描述：	24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs 24位， 8.5毫瓦， 109分贝， 128/64/32 kSPS的模数转换器转换器模数转换器
文件：	总24页 (文件大小：2200K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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