EVAL-AD7789EB [ADI]
Low Power, 16-/24-Bit, Sigma-Delta ADCs; 低功耗， 16位/ 24位Σ-Δ型ADC
| 型号： | EVAL-AD7789EB |
| 厂家： | 
ADI |
| 描述： | Low Power, 16-/24-Bit, Sigma-Delta ADCs |
| 文件： | 总20页 (文件大小：382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, 16-/24-Bit,
Sigma-Delta ADCs
AD7788/AD7789
FUNCTIONAL BLOCK DIAGRAM
FEATURES
REFIN(+) REFIN(–) GND
V
DD
AD7788: 16-bit resolution
AD7789: 24-bit resolution
Power
AD7788/
AD7789
CLOCK
Supply: 2.5 V to 5.25 V operation
Normal: 75 μA maximum
Power-down: 1 μA maximum
RMS noise: 1.5 μV
DOUT/RDY
DIN
AIN(+)
AIN(–)
SERIAL
INTERFACE
AND
CONTROL
LOGIC
Σ-Δ
ADC*
SCLK
CS
AD7788: 16-bit p-p resolution
AD7789: 19-bit p-p resolution (21.5 bits effective)
Integral nonlinearity: 3.5 ppm typical
Simultaneous 50 Hz and 60 Hz rejection
Internal clock oscillator
*AD7788: 16-BIT ADC
AD7789: 24-BIT ADC
Figure 1.
GENERAL DESCRIPTION
VDD monitor channel
The AD7788/AD7789 are low power, low noise, analog front
ends for low frequency measurement applications. The AD7789
contains a low noise, 24-bit, ∑-Δ ADC with one differential
input. The AD7788 is a 16-bit version of the AD7789.
10-lead MSOP
INTERFACE
3-wire serial
The devices operate from an internal clock. Therefore, the
user does not have to supply a clock source to the devices.
The output data rate is 16.6 Hz, which gives simultaneous
50 Hz/60 Hz rejection.
SPI®-, QSPI™-, MICROWIRE™-, and DSP-compatible
Schmitt trigger on SCLK
APPLICATIONS
The parts operate with a single power supply from 2.5 V to
5.25 V. When operating from a 3 V supply, the power dissi-
pation for the part is 225 μW maximum. The AD7788/AD7789
are available in a 10-lead MSOP.
Smart transmitters
Battery applications
Portable instrumentation
Sensor measurement
Temperature measurement
Pressure measurement
Weigh scales
4 to 20 mA loops
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7788/AD7789
TABLE OF CONTENTS
Features .............................................................................................. 1
Interface ............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7789.......................................................................................... 3
AD7788.......................................................................................... 4
AD7788/AD7789.......................................................................... 5
Timing Characteristics ................................................................ 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
On-Chip Registers.......................................................................... 11
Communications Register......................................................... 11
Status Register............................................................................. 12
Mode Register............................................................................. 13
Data Register............................................................................... 13
ADC Circuit Information.............................................................. 14
Noise Performance..................................................................... 14
Digital Interface.......................................................................... 14
Circuit Description......................................................................... 17
Analog Input Channel ............................................................... 17
Bipolar/Unipolar Configuration .............................................. 17
Data Output Coding .................................................................. 17
Reference Input........................................................................... 17
VDD Monitor................................................................................ 18
Grounding and Layout .............................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/06—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 19
11/04—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added Footnote 2 to Integral Nonlinearity A Grade................... 4
Changes to Figure 5.......................................................................... 9
Updated Outline Dimensions....................................................... 19
Changes to Ordering Guide .......................................................... 19
8/03—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD7788/AD7789
SPECIFICATIONS
AD7789
VDD = 2.5 V to 5.25 V; REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
AD7789B
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATION
Output Update Rate
ADC CHANNEL
16.6
Hz nom
No Missing Codes2
24
19
1.5
15
3
Bits min
Bits p-p
μV rms typ
ppm of FSR max
μV typ
Resolution
Output Noise
Integral Nonlinearity
Offset Error
Offset Error Drift vs. Temperature
Full-Scale Error3
Gain Drift vs. Temperature
Power Supply Rejection
ANALOG INPUTS
10
10
0.5
90
nV/°C typ
μV typ
ppm/°C typ
dB min
100 dB typ, AIN = 1 V
Differential Input Voltage Ranges
Absolute AIN Voltage Limits2
REFIN
GND − 30 mV
VDD + 30 mV
V nom
V min
V max
REFIN = REFIN(+) − REFIN(−)
Analog Input Current
Average Input Current2
Average Input Current Drift
Normal-Mode Rejection2
@ 50 Hz, 60 Hz
Common-Mode Rejection
@ DC
@ 50 Hz, 60 Hz2
Input current varies with input voltage
400
50
nA/V typ
pA/V/°C typ
65
dB min
50 Hz 1 Hz, 60 Hz 1 Hz
AIN = 1 V
100 dB typ
90
100
dB min
dB min
50 Hz 1 Hz, 60 Hz 1 Hz
REFERENCE INPUT
REFIN Voltage
Reference Voltage Range2
2.5
0.1
V nom
V min
REFIN = REFIN(+) − REFIN(−)
VDD
V max
V min
V max
μA/V typ
nA/V/°C typ
Absolute REFIN Voltage Limits2
GND − 30 mV
VDD + 30 mV
0.5
Average Reference Input Current
Average Reference Input Current Drift
Normal-Mode Rejection2
@ 50 Hz, 60 Hz
0.03
65
dB min
50 Hz 1 Hz, 60 Hz 1 Hz
AIN = 1 V
Common-Mode Rejection
@ DC
@ 50 Hz, 60 Hz
110
110
dB typ
dB typ
50 Hz 1 Hz, 60 Hz 1 Hz
1 Temperature range: −40°C to +105°C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).
Rev. B | Page 3 of 20
AD7788/AD7789
AD7788
VDD = 2.5 V to 5.25 V (B grade); VDD = 2.7 V to 5.25 V (A grade); REFIN(+) = 2.5 V; REFIN(−) = GND; GND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
AD7788 A, AD7788B
Unit
Test Conditions/Comments
ADC CHANNEL SPECIFICATION
Output Update Rate
ADC CHANNEL
16.6
Hz nom
No Missing Codes2
16
16
1.5
15
50
3
Bits min
Bits p-p
μV rms typ
ppm of FSR max
ppm of FSR max
μV typ
Resolution
Output Noise
Integral Nonlinearity
B grade
A grade2
Offset Error
Offset Error Drift vs. Temperature
Full-Scale Error3
Gain Drift vs. Temperature
Power Supply Rejection
10
10
0.5
90
90
nV/°C typ
μV typ
ppm/°C typ
dB min
B grade
A grade
dB typ
ANALOG INPUTS
Differential Input Voltage Ranges
Absolute AIN Voltage Limits2
REFIN
GND − 30 mV
VDD + 30 mV
V nom
V min
V max
REFIN = REFIN(+) − REFIN(−)
Analog Input Current
Input current varies with input
voltage
Average Input Current2
Average Input Current Drift
Normal-Mode Rejection2
@ 50 Hz, 60 Hz
400
50
nA/V typ
pA/V/°C typ
65
60
dB min
dB min
B grade, 50 Hz 1 Hz, 60 Hz 1 Hz
A grade, 50 Hz 1 Hz, 60 Hz 1 Hz
AIN = 1 V
B grade, 100 dB typ
A grade
Common-Mode Rejection
@ DC
90
90
100
100
dB min
dB typ
dB min
dB typ
@ 50 Hz, 60 Hz2
B grade, 50 Hz 1 Hz, 60 Hz 1 Hz
A grade, 50 Hz 1 Hz, 60 Hz 1 Hz
REFERENCE INPUT
REFIN Voltage
Reference Voltage Range2
2.5
0.1
V nom
V min
REFIN = REFIN(+) − REFIN(−)
VDD
V max
V min
V max
μA/V typ
nA/V/°C typ
Absolute REFIN Voltage Limits2
GND − 30 mV
VDD + 30 mV
0.5
Average Reference Input Current
Average Reference Input Current Drift
Normal-Mode Rejection2
0.03
@ 50 Hz, 60 Hz
65
60
dB min
dB min
B grade, 50 Hz 1 Hz, 60 Hz 1 Hz
A grade
Common-Mode Rejection
@ DC
@ 50 Hz, 60 Hz
AIN = 1 V
100
110
dB typ
dB typ
50 Hz 1 Hz, 60 Hz 1 Hz
1 Temperature range: B grade: −40°C to +105°C; A grade: −40°C to +85°C.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V).
Rev. B | Page 4 of 20
AD7788/AD7789
AD7788/AD7789
Table 3.
Parameter
AD7788A, AD7788B/AD7789B
Unit
Test Conditions/Comments
LOGIC INPUTS
All Inputs Except SCLK1
VINL, Input Low Voltage
0.8
0.4
2.0
V max
V max
V min
VDD = 5 V
VDD = 3 V
VDD = 3 V or 5 V
VINH, Input High Voltage
SCLK Only (Schmitt-Triggered Input)1
VT(+)
VT(−)
VT(+) − VT(−)
VT(+)
VT(−)
VT(+) − VT(−)
1.4/2
0.8/1.4
0.3/0.85
0.9/2
0.4/1.1
0.3/0.85
1
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
V min/V max
μA max
VDD = 5 V
VDD = 5 V
VDD = 5 V
VDD = 3 V
VDD = 3 V
VDD = 3 V
VIN = VDD
Input Currents
Input Capacitance
10
pF typ
All digital inputs
LOGIC OUTPUTS
VOH, Output High Voltage1
VOL, Output Low Voltage1
VOH, Output High Voltage1
VOL, Output Low Voltage1
Floating-State Leakage Current
Floating-State Output Capacitance
Data Output Coding
POWER REQUIREMENTS2
Power Supply Voltage
V
0.4
4
0.4
DD − 0.6
V min
V max
V min
V max
μA max
pF typ
VDD = 3 V, ISOURCE = 100 μA
VDD = 3 V, ISINK = 100 μA
VDD = 5 V, ISOURCE = 200 μA
VDD = 5 V, ISINK = 1.6 mA
1
10
Offset binary
V
DD − GND
2.5/5.25
2.7/5.25
V min/max
V min/max
AD7789, AD7788 B grade
AD7788 A grade
Power Supply Currents
IDD Current
75
80
1
μA max
μA max
μA max
65 μA typ, VDD = 3.6 V
73 μA typ, VDD = 5.25 V
IDD (Power-Down Mode)
1 Specification is not production tested but is supported by characterization data at initial product release.
2 Digital inputs equal to VDD or GND.
Rev. B | Page 5 of 20
AD7788/AD7789
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.25 V (AD7788B and AD7789); VDD = 2.7 V to 5.25 V (AD7788A); GND = 0 V; REFIN(+) = 2.5 V; REFIN(−) = GND;
Input Logic 0 = 0 V; Input Logic 1 = VDD, unless otherwise noted.
Table 4.
Parameter1, 2
Limit at TMIN, TMAX (B Version)
Unit
Description
t3
t4
100
100
ns min
ns min
SCLK high pulse width
SCLK low pulse width
Read Operation
t1
0
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS falling edge to DOUT/RDY active time
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK active edge to data valid delay4
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
60
80
0
60
80
10
80
0
3
t2
5, 6
t5
t6
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
t7
10
Write Operation
t8
0
ns min
ns min
ns min
ns min
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
t9
t10
t11
30
25
0
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 3 and Figure 4.
3 These numbers are measured with the load circuit of, and defined as, the time required for the output to cross the VOL or VOH limits.
4 SCLK active edge is the falling edge of SCLK.
5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Characteristics are the true
bus relinquish times of the part and, as such, are independent of external bus loading capacitances.
6 RDY
RDY
returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, the same data can be read again, if required, while
is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
Rev. B | Page 6 of 20
AD7788/AD7789
TIMING DIAGRAMS
I
(1.6mA WITH V = 5V,
DD
SINK
100µA WITH V = 3V)
DD
TO OUTPUT
PIN
1.6V
50pF
I
(200µA WITH V = 5V,
DD
SOURCE
100µA WITH V = 3V)
DD
Figure 2. Load Circuit for Timing Characterization
CS (I)
t6
t1
t5
MSB
LSB
t7
DOUT/RDY (O)
t2
t3
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 3. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
DIN (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 4. Write Cycle Timing Diagram
Rev. B | Page 7 of 20
AD7788/AD7789
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
Analog Input Voltage to GND
Reference Input Voltage to GND
Total AIN/REFIN Current (Indefinite)
Digital Input Voltage to GND
Digital Output Voltage to GND
Operating Temperature Range
B Grade
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
30 mA
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−40°C to +85°C
−65°C to +150°C
150°C
A Grade
Storage Temperature Range
Maximum Junction Temperature
10-Lead MSOP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
206°C/W
44°C/W
300°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 8 of 20
AD7788/AD7789
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCLK
1
2
3
4
5
10 DIN
AD7788/
AD7789
TOP VIEW
(Not to Scale)
CS
9
8
7
6
DOUT/RDY
AIN(+)
AIN(–)
REFIN(+)
V
DD
GND
REFIN(–)
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
SCLK
Serial Clock Input for Data Transfers to and from the ADC. The SCLK has a Schmitt-triggered input, making the
interface suitable for opto-isolated applications. The serial clock can be continuous, with all data transmitted in
a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-
mitted to or from the ADC in smaller batches of data.
2
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT/RDY used to interface with the device.
3
4
5
AIN(+)
AIN(−)
REFIN(+)
Analog Input. AIN(+) is the positive terminal of the fully differential analog input.
Analog Input. AIN(–) is the negative terminal of the fully differential analog input.
Positive Reference Input. REFIN(+) can lie anywhere between VDD and GND + 0.1 V. The nominal reference
voltage (REFIN(+) − REFIN(−)) is 2.5 V, but the part functions with a reference from 0.1 V to VDD.
6
7
8
9
REFIN(−)
GND
VDD
Negative Reference Input. This reference input can lie anywhere between GND and VDD − 0.1 V.
Ground Reference Point.
Supply Voltage. 3 V or 5 V nominal.
DOUT/RDY The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data/control word
information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge.
The end of a conversion is also indicated by the RDY bit in the status register. When CS is high, the DOUT/RDY
pin is three-stated, but the RDY bit remains active.
10
DIN
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control
registers within the ADC; the register selection bits of the communications register identify the appropriate
register.
Rev. B | Page 9 of 20
AD7788/AD7789
TYPICAL PERFORMANCE CHARACTERISTICS
8388625
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
V
= 3V, V
= 2.048V,
= 25°C, RMS NOISE = 1.25µV
DD
REF
T
A
8388591
0
200
400
600
800
1000
0
20
40
60
80
100
120
140
160
FREQUENCY (Hz)
READ NO.
Figure 6. Frequency Response with 16.6 Hz Update Rate
Figure 8. AD7789 Noise Plot
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
= 3V
DD
V
= 5V
DD
UPDATE RATE = 16.6Hz
T = 25°C
A
= 2.048V
REF
70
60
50
40
30
20
10
0
T
= 25°C
A
RMS NOISE = 1.25µV
8388591
8388625
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
CODE
V
REF
Figure 7. AD7789 Noise Histogram
Figure 9. AD7788/AD7789 Noise vs. VREF
Rev. B | Page 10 of 20
AD7788/AD7789
ON-CHIP REGISTERS
The ADC is controlled and configured via a number of on-chip
registers, which are described on the following pages. In the
following descriptions, set implies a Logic 1 state and cleared
implies a Logic 0 state, unless otherwise stated.
For read or write operations, once the subsequent read or write
operation to the selected register is complete, the interface returns
to where it expects a write operation to the communications
register. This is the default state of the interface and, on power-up
or after a reset, the ADC is in this default state waiting for a write
operation to the communications register. In situations where the
interface sequence is lost, a write operation of at least 32 serial
clock cycles with DIN high returns the ADC to this default state
by resetting the entire part. Table 7 outlines the bit designations
for the communications register. CR0 through CR7 indicate the
bit location, CR denoting the bits are in the communications
register. CR7 denotes the first bit of the data stream. The number
in brackets indicates the power-on/reset default status of that bit.
COMMUNICATIONS REGISTER
(RS1, RS0 = 0, 0)
The communications register is an 8-bit, write only register. All
communications to the part must start with a write operation to
the communications register. The data written to the commun-
ications register determines whether the next operation is a read
or write operation, and to which register this operation takes
place.
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
WEN[0]
0[0]
RS1[0]
RS0[0]
R/W[0]
CREAD[0]
CH1[0]
CH0[0]
Table 7. Communications Register Bit Designations
Bit Location Bit Name Description
CR7
WEN
Write Enable Bit. A 0 must be written to this bit so that the write to the communications register actually
occurs. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register. It stays at
this bit location until a 0 is written to this bit. Once a 0 is written to the WEN bit, the next seven bits are
loaded to the communications register.
CR6
0
This bit must be programmed with a Logic 0 for correct operation.
CR5 to CR4
RS1 to RS0
Register Address Bits. These address bits are used to select which of the ADC registers are being selected
during this serial interface communication (see Table 8).
CR3
CR2
R/W
A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position
indicates that the next operation is a read from the designated register.
CREAD
Continuous Read of the Data Register. When this bit is set to 1 (and the data register is selected), the serial
interface is configured so that the data register can be continuously read, that is, the contents of the data
register are placed on the DOUT/RDY pin automatically when the SCLK pulses are applied. The
communications register does not have to be written to for data reads. To enable continuous read mode,
the instruction 001111XX must be written to the communications register. To exit the continuous read
mode, the instruction 001110XX must be written to the communications register while the DOUT/RDY pin
is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN.
Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the
device.
CR1 to CR0
CH1 to CH0 These bits are used to select the analog input channel. The differential channel can be selected
AIN(+)/AIN(−) or an internal short AIN(−)/AIN(−) can be selected. Alternatively, the power supply can be
selected, that is, the ADC can measure the voltage on the power supply, which is useful for monitoring
power supply variation. The power supply voltage is divided by 5 and then applied to the modulator for
conversion. The ADC uses a 1.17 V 5% on-chip reference as the reference source for the analog-to-digital
conversion. Any change in channel resets the filter and a new conversion is started.
Rev. B | Page 11 of 20
AD7788/AD7789
Table 8. Register Selection
RS1
RS0
Register
Register Size
8-bit
0
0
Communications register during a write operation
0
0
0
1
Status register during a read operation
Mode register
8-bit
8-bit
1
0
Reserved
8-bit
1
1
Data register
16-bit (AD7788)
24-bit (AD7789)
Table 9. Channel Selection
CH1
CH0
Channel
0
0
1
1
0
1
0
1
AIN(+) − AIN(−)
Reserved
AIN(−) − AIN(−)
VDD monitor
STATUS REGISTER
(RS1, RS0 = 0, 0; Power-On/Reset = 0x88 for AD7788 and 0x8C for AD7789)
The status register is an 8-bit, read only register. To access the ADC status register, the user must write to the communications register,
select the next operation to be a read, and load Bit RS1 and Bit RS0 with 0. Table 10 outlines the bit designations for the status register.
SR0 through SR7 indicate the bit locations, SR denoting the bits are in the status register. SR7 denotes the first bit of the data stream. The
number(s) in brackets indicates the power-on/reset default status of that bit.
MSB
SR7
LSB
SR6
SR5
SR4
SR3
SR2
SR1
SR0
RDY[1]
ERR[0]
0[0]
0[0]
1[1]
WL[1/0]
CH1[0]
CH0[0]
Table 10. Status Register Bit Designations
Bit Location Bit Name Description
SR7
RDY
Ready Bit for ADC. Cleared when data is written to the ADC data register. The RDY bit is set automatically
after the ADC data register has been read or a period of time before the data register is updated with a
new conversion result to tell the user not to read the conversion data. It is also set when the part is
placed in power-down mode. The end of a conversion is indicated by the DOUT/RDY pin. This pin can be
used as an alternative to the status register for monitoring the ADC for conversion data.
SR6
ERR
ADC Error Bit. This bit is written to at the same time as the RDY bit. Set to indicate that the result written
to the ADC data register has been clamped to all 0s or all 1s. Error sources include overrange, under-
range. Cleared by a write operation to start a conversion.
SR5
SR4
SR3
SR2
0
0
1
WL
This bit is cleared automatically.
This bit is cleared automatically.
This bit is set automatically.
AD7788/AD7789 Identifier. This bit is cleared automatically if the device is an AD7788 and it is set
automatically if the device is an AD7789. This bit is used to distinguish between the AD7788 and
AD7789.
SR1 to SR0
CH1 to CH0
These bits indicate which channel is being converted by the ADC.
Rev. B | Page 12 of 20
AD7788/AD7789
MODE REGISTER
(RS1, RS0 = 0, 1; Power-On/Reset = 0x02)
The mode register is an 8-bit register from which data can be read from or written to. This register is used to configure the ADC for
range, to set unipolar or bipolar mode, to enable or disable the buffer, or to place the device into power-down mode. Table 11 outlines the
bit designations for the mode register. MR0 through MR7 indicate the bit locations, MR denoting the bits are in the mode register. MR7
denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Any write to the
setup register resets the modulator and filter, and sets the
bit.
RDY
MSB
LSB
MR7
MR6
MR5
MR4
MR3
MR2
MR1
MR0
MD1[0]
MD0[0]
0[0]
0[0]
0[0]
U/B[0]
1[1]
0[0]
Table 11. Mode Register Bit Designations
Bit Location Bit Name Description
MR7 to MR6
MD1 to MD0
Mode Select Bits. These bits select between continuous conversion mode, single conversion mode, and
standby mode. In continuous conversion mode, the ADC continuously performs conversions and places
the result in the data register. DOUT/ RDY goes low when a conversion is complete. The user can read these
conversions by placing the device in continuous read mode whereby the conversions are automatically
placed on the DOUT/ RDY line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to
output the conversion by writing to the communications register. After power-on, the first conversion is
available after a period 2/ fADC while subsequent conversions are available at a frequency of fADC. In single
conversion mode, the ADC is placed in power-down mode when conversions are not being performed.
When single conversion mode is selected, the ADC powers up (which takes 1 ms) and performs a single
conversion, requiring a duration of 2/fADC. The conversion result is placed in the data register, DOUT/ RDY
goes low, and the ADC returns to power-down mode. The conversion remains in the data register and
DOUT/ RDY remains active (low) until the data is read or another conversion is performed (see Table 12).
MR5 to MR3
MR2
0
U/B
These bits must be programmed with a Logic 0 for correct operation.
Unipolar/Bipolar Bit. Set by user to enable unipolar coding; that is, zero differential input results in
000…000 output, and a full-scale differential input results in 111…111 output. Cleared by the user to
enable bipolar coding. Negative full-scale differential input results in an output code of 000…000, zero
differential input results in an output code of 100…000, and a positive full-scale differential input results in
an output code of 111…111.
MR1
MR0
1
0
This bit must be programmed with a Logic 1 for correct operation.
This bit must be programmed with a Logic 0 for correct operation.
Table 12. Operating Modes
MD1
MD0
Mode
0
0
1
1
0
1
0
1
Continuous conversion mode (default)
Reserved
Single conversion mode
Power-down mode
DATA REGISTER
(RS1, RS0 = 1, 1; Power-On/Reset = 0x0000 for the AD7788 and 0x000000 for the AD7789)
The conversion result from the ADC is stored in this data register. This is a read only register. On completion of a read operation from
this register, the
bit/pin is set.
RDY
Rev. B | Page 13 of 20
AD7788/AD7789
ADC CIRCUIT INFORMATION
operation or a write operation, and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the devices begins with a
write operation to the communications register followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register followed by a read
operation from the selected register.
The AD7788/AD7789 are low power ADCs that incorporate a
Σ-ꢀ modulator and on-chip digital filtering intended for the
measurement of wide dynamic range, low frequency signals,
such as those in pressure transducers, weigh scales, and temper-
ature measurement applications. The part has one unbuffered
differential input. The device requires an external reference
voltage between 0.1 V and VDD. Figure 10 shows the basic
connections required to operate the part.
POWER
SUPPLY
The AD7788/AD7789 serial interface consists of four signals:
, DIN, SCLK, and DOUT/
. The DIN line is used to
CS
RDY
0.1µF
10µF
transfer data into the on-chip registers and DOUT/
is used
RDY
for accessing data from the on-chip registers. SCLK is the serial
clock input for the device, and all data transfers (either on DIN
V
DD
REFIN(+)
or DOUT/
) occur with respect to the SCLK signal. The
pin operates as a data ready signal also, the line
RDY
IN+
AD7788/
AD7789
DOUT/
RDY
OUT–
OUT+
CS
AIN(+)
goes low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the data register
update to indicate when not to read from the device; this
ensures that a data read is not attempted while the register is
DOUT/RDY
SCLK
MICROCONTROLLER
AIN(–)
IN–
REFIN(–)
GND
being updated.
is used to select a device. It can be used to
CS
Figure 10. Basic Connection Diagram
decode the AD7788/AD7789 in systems where several compo-
nents are connected to the serial bus.
The output rate of the AD7788/AD7789 (fADC) is 16.6 Hz with
the settling time equal to 2 × tADC (120.4 ms). Normal-mode
rejection is the major function of the digital filter. Simultaneous
50 Hz and 60 Hz rejection is optimized as notches are placed at
both 50 Hz and 60 Hz with this update rate (see Figure 6).
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7788/AD7789 with
Figure 3 shows the timing for a read operation from the output
shift register, while Figure 4 shows the timing for a write opera-
tion to the input shift register. In all modes except continuous
read mode, it is possible to read the same word from the data
being used to decode the devices.
CS
NOISE PERFORMANCE
Typically, the devices have an rms noise of 1.5 μV rms that
corresponds to a peak-to-peak resolution of 16 bits for the
AD7788 and 19 bits (equivalent to an effective resolution of
21.5 bits) for the AD7789. These numbers are for the bipolar
input range with a reference of 2.5 V. The noise was measured
with a differential input voltage of 0 V. The peak-to-peak
resolution figures represent the resolution for which there is no
code flicker within a six-sigma limit. The output noise comes
from two sources. The first is the electrical noise in the semi-
conductor devices (device noise) used in the implementation of
the modulator. The second is quantization noise, added when
the analog input is converted into the digital domain.
register several times even though the DOUT/
line returns
RDY
high after the first read operation. However, care must be taken
to ensure that the read operations have been completed before
the next output update occurs. In continuous read mode, the
data register can be read only once.
The serial interface can operate in 3-wire mode by tying
low.
CS
In this case, the SCLK, DIN, and DOUT/
lines are used to
RDY
communicate with the AD7788/AD7789. The end of conversion
can be monitored using the bit in the status register. This
RDY
scheme is suitable for interfacing to microcontrollers. If
is
CS
required as a decoding signal, it can be generated from a port
pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.
DIGITAL INTERFACE
As previously outlined, the AD7788/AD7789 programmable
functions are controlled using a set of on-chip registers. Data is
written to these registers via the serial interface and read access
to the on-chip registers is also provided by this interface. All
communications with the devices must start with a write to the
communications register. After power-on or reset, the devices
expect a write to the communications register. The data written
to this register determines whether the next operation is a read
The AD7788/AD7789 can operate with
being used as a
CS
frame synchronization signal. This scheme is useful for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by , because
normally occurs after the falling edge of
CS
CS
SCLK in DSPs. The SCLK can continue to run between data
transfers, provided the timing numbers are obeyed.
Rev. B | Page 14 of 20
AD7788/AD7789
The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7788/AD7789 for
at least 32 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or a glitch in the
system. Reset returns the interface to the state in which it is
expecting a write to the communications register. This oper-
ation resets the contents of all registers to their power-on values.
When the data-word has been read from the data register,
DOUT/ goes high. If is low, DOUT/ remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
RDY
CS
RDY
DOUT/
has gone high.
RDY
Continuous Conversion Mode
This is the default power-up mode. The AD7788/AD7789
continuously convert, the
low each time a conversion is complete. If
pin in the status register going
RDY
The AD7788/AD7789 can be configured to continuously
convert or to perform a single conversion. See Figure 11
through Figure 13.
is low, the
CS
DOUT/
line also goes low when a conversion is complete.
RDY
To read a conversion, the user can write to the communications
register, indicating that the next operation is a read of the data
Single Conversion Mode
register. The digital conversion is placed on the DOUT/
RDY
In single-conversion mode, the AD7788/AD7789 are placed in
power-down mode between conversions. When a single conver-
sion is initiated by setting MD1 to 1 and MD0 to 0 in the mode
register, the AD7788/AD7789 power up, perform a single con-
version, and then return to power-down mode. The devices
require 1 ms to power up and settle. The AD7788/AD7789
then perform a conversion, requiring a time period of
pin as soon as SCLK pulses are applied to the ADC. DOUT/
returns high when the conversion is read. The user can
RDY
read this register additional times, if required. However, the
user must ensure that the data register is not being accessed
at the completion of the next conversion or else the new
conversion word is lost.
2 × tADC. DOUT/
goes low to indicate the completion of a
RDY
conversion.
CS
0x10
0x82
0x38
DIN
DATA
DOUT/RDY
SCLK
Figure 11. Single Conversion
CS
0x38
0x38
DIN
DATA
DATA
DOUT/RDY
SCLK
Figure 12. Continuous-Conversion Mode
Rev. B | Page 15 of 20
AD7788/AD7789
Continuous Read Mode
If the data-word has not read the conversion before the
completion of the next conversion, or if insufficient serial clocks
are applied to the AD7788/AD7789 to read the word, the serial
output register is reset when the next conversion is complete
and the new conversion is placed in the output serial register.
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7788/AD7789
can be placed in continuous read mode. By writing 001111XX
to the communications register, the user needs only to apply the
appropriate number of SCLK cycles to the ADC and the data-
To exit continuous read mode, the instruction 001110XX must
be written to the communications register while the DOUT/
word is automatically placed on the DOUT/
line when a
RDY
conversion is complete.
pin is low. While in continuous read mode, the ADC
RDY
monitors activity on the DIN line so that it can receive the
instruction to exit continuous read mode. Additionally, a
reset occurs if 32 consecutive 1s are seen on DIN. Therefore,
DIN should be held low in continuous read mode until an
instruction is to be written to the device.
When DOUT/
goes low to indicate the end of a conver-
RDY
sion, sufficient SCLK cycles must be applied to the ADC and
the data conversion is placed on the DOUT/ line. When
RDY
returns high until the next
the conversion is read, DOUT/
RDY
conversion is available. In this mode, the data can be read only
once. Also, the user must ensure that the data-word is read
before the next conversion is complete.
CS
0x3C
DIN
DATA
DATA
DATA
DOUT/RDY
SCLK
Figure 13. Continuous-Read Mode
Rev. B | Page 16 of 20
AD7788/AD7789
CIRCUIT DESCRIPTION
ANALOG INPUT CHANNEL
DATA OUTPUT CODING
The AD7788/AD7789 have one differential analog input
channel that is connected to the modulator, thus, the input is
unbuffered. Note that this unbuffered input path provides a
dynamic load to the driving source. Therefore,
resistor/capacitor combinations on the input pins can cause dc
gain errors, depending on the output impedance of the source
that is driving the ADC input. Table 13 shows the allowable
external resistance/capacitance values such that no gain error at
the 16-bit level is introduced (AD7788). Table 14 shows the
allowable external resistance/capacitance values such that no
gain error at the 20-bit level is introduced (AD7789).
When the ADC is configured for unipolar operation, the output
code is natural (straight) binary with a zero differential input
voltage resulting in a code of 000...000, a midscale voltage
resulting in a code of 100...000, and a full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as
Code = 2N × (AIN/VREF
)
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000...000, a zero differential input voltage resulting
in a code of 100...000, and a positive full-scale input voltage
resulting in a code of 111...111. The output code for any analog
input voltage can be represented as
Table 13. External R-C Combination for No 16-Bit Gain
Error (AD7788)
C (pF)
R (Ω)
22.8 k
13.1 k
3.3 k
1.8 k
360
50
100
500
1000
5000
Code = 2N – 1 × [(AIN/VREF) + 1]
where:
AIN is the analog input voltage.
N = 16 for the AD7788, 24 for the AD7789.
Table 14. External R-C Combination for No 20-Bit Gain
Error (AD7789)
REFERENCE INPUT
The AD7788/AD7789 have a fully differential input capability
for the channel. The common-mode range for these differential
inputs is from GND to VDD. The reference input is unbuffered
and, therefore, excessive R-C source impedances introduce gain
errors. The reference voltage REFIN [REFIN(+) − REFIN(−)] is
2.5 V nominal, but the AD7788/AD7789 are functional with
reference voltages from 0.1 V to VDD. In applications where the
excitation (voltage or current) for the transducer on the analog
input also drives the reference voltage for the parts, the effect of
the low frequency noise in the excitation source is removed
because the application is ratiometric. If the AD7788/AD7789
are used in a nonratiometric application, a low noise reference
should be used.
C (pF)
R (Ω)
16.7 k
9.6 k
2.2 k
1.1 k
160
50
100
500
1000
5000
The absolute input voltage includes the range between GND −
30 mV and VDD + 30 mV. The negative absolute input voltage
limit does allow the possibility of monitoring small true bipolar
signals with respect to GND.
BIPOLAR/UNIPOLAR CONFIGURATION
The analog input to the devices can accept either unipolar or
bipolar input voltage ranges. A bipolar input range does not
imply that the parts can tolerate large negative voltages with
respect to system GND. Unipolar and bipolar signals on the
AIN(+) input are referenced to the voltage on the AIN(−) input.
For example, if AIN(−) is 2.5 V and the ADC is configured for
unipolar mode, the input voltage range on the AIN(+) pin is
2.5 V to 5 V. If the ADC is configured for bipolar mode, the
analog input range on the AIN(+) input is 0 V to 5 V. The
Recommended 2.5 V reference voltage sources for the AD7788/
AD7789 include the ADR381 and ADR391, because they are
low noise, low power references. If the analog circuitry uses a
2.5 V power supply, the reference voltage source requires some
headroom. In this case, a 2.048 V reference such as the ADR380
or ADR390 can be used. Again, these are low power, low noise
references. Also note that the reference inputs provide a high
impedance, dynamic load. Because the input impedance of each
reference input is dynamic, resistor/capacitor combinations on
these inputs can cause dc gain errors, depending on the output
impedance of the source that is driving the reference inputs.
bipolar/unipolar option is chosen by programming the U/ bit
B
in the mode register.
Rev. B | Page 17 of 20
AD7788/AD7789
The printed circuit board that houses the AD7788/AD7789
should be designed such that the analog and digital sections
are separated and confined to certain areas of the board. A
minimum etch technique is generally best for ground planes
because it gives the best shielding.
Reference voltage sources like those recommended in the pre-
vious section (for example, ADR391) typically have low output
impedances and are, therefore, tolerant to having decoupling
capacitors on REFIN(+) without introducing gain errors in the
system. Deriving the reference input voltage across an external
resistor means that the reference input sees a significant exter-
nal source impedance. External decoupling on the REFIN pins
is not recommended in this type of circuit configuration.
It is recommended that the AD7788/AD7789 GND pins be tied
to the AGND plane of the system. In any layout, it is important
that the user consider the flow of currents in the system,
ensuring that the return paths for all currents are as close as
possible to the paths the currents took to reach their
destinations. Avoid forcing digital currents to flow through the
AGND sections of the layout.
VDD MONITOR
Along with converting external voltages, the analog input
channel can be used to monitor the voltage on the VDD pin.
When Bit CH1 and Bit CH0 in the communications register are
set to 1, the voltage on the VDD pin is internally attenuated by 5
and the resultant voltage is applied to the Σ-ꢀ modulator using
an internal 1.17 V reference for analog-to-digital conversion.
This is useful because variations in the power supply voltage
can be monitored.
The AD7788/AD7789 ground plane should be allowed to run
under the devices to prevent noise coupling. The power supply
lines to the AD7788/AD7789 should use as wide a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals, such
as clocks, should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never be run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough through the board. A microstrip technique is by
far the best, but it is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground planes, with signals placed on the solder
side.
GROUNDING AND LAYOUT
Because the analog inputs and reference inputs of the ADC are
differential, most of the voltages in the analog modulator are
common-mode voltages. The excellent common-mode
rejection of the part removes common-mode noise on these
inputs. The digital filter provides rejection of broadband noise
on the power supply, except at integer multiples of the
modulator sampling frequency. The digital filter also removes
noise from the analog and reference inputs, provided that these
noise sources do not saturate the analog modulator. As a result,
the AD7788/AD7789 are more immune to noise interference
than conventional high resolution converters. However, because
the resolution of the AD7788/AD7789 is so high, and the noise
levels from the AD7788/AD7789 are so low, care must be taken
with regard to grounding and layout.
Good decoupling is important when using high resolution
ADCs. VDD should be decoupled with a 10 μF tantalum in
parallel with 0.1 μF capacitors to GND. To achieve the best
from these decoupling components, they should be placed as
close as possible to the device, ideally right up against the
device. All logic chips should be decoupled with 0.1 μF
ceramic capacitors to DGND.
Rev. B | Page 18 of 20
AD7788/AD7789
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 14. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Model
Package Description
Package Option
RM-10
Branding
COX
COX
C3G
AD7788BRM
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
AD7788BRM-REEL
AD7788BRMZ1
AD7788BRMZ-REEL1
AD7788ARM
AD7788ARM-REEL
AD7788ARMZ1
AD7789BRM
AD7789BRM-REEL
AD7789BRMZ1
AD7789BRMZ-REEL1
EVAL-AD7788EB
EVAL-AD7789EB
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
C3G
COZ
COZ
C4T
COY
COY
C43
C43
Evaluation Board
1 Z = Pb-free part.
Rev. B | Page 19 of 20
AD7788/AD7789
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03539-0-3/06(B)
Rev. B | Page 20 of 20
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