EVAL-AD7762EB [ADI]
625 kSPS, 24-Bit, 109 dB ADC With On-Chip Buffer; 625 kSPS时， 24位， 109分贝ADC ，带有片上缓冲器
| 型号： | EVAL-AD7762EB |
| 厂家： | 
ADI |
| 描述： | 625 kSPS, 24-Bit, 109 dB ADC With On-Chip Buffer |
| 文件： | 总28页 (文件大小：566K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
625 kSPS, 24-Bit, 109 dB Σ−Δ ADC
With On-Chip Buffer
AD7762
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
120 dB dynamic range at 78 kHz output data rate
109 dB dynamic range at 625 kHz output data rate
112 dB SNR at 78 kHz output data rate
106 dB SNR at 625 kHz output data rate
625 kHz maximum fully filtered output word rate
Programmable over-sampling rate (32× to 256×)
Fully differential modulator input
IN– IN+
MULTIBIT
AV
AV
AV
AV
DD1
DD2
DD3
DD4
DIFF
Σ-Δ
MODULATOR
V
REF+
RECONSTRUCTION
BUF
DECAPA/B
R
BIAS
On-chip differential amplifier for signal buffering
Low-pass finite impulse response (FIR) filter with default or
user-programmable coefficients
Overrange alert bit
Digital offset and gain correction registers
Filter bypass modes
PROGRAMMABLE
DECIMATION
AD7762
AGND
V
DRIVE
MCLK
SYNC
DV
CONTROL LOGIC
I/O
OFFSET AND GAIN
REGISTERS
DD
DGND
FIR FILTER
ENGINE
RESET
Low power and power-down modes
Synchronization of multiple devices via SYNC pin
CS RD/WR DRDY DB0 TO DB15
Figure 1.
APPLICATIONS
Data acquisition systems
Vibration analysis
Instrumentation
GENERAL DESCRIPTION
The AD7762 is a high performance, 24-bit Σ-Δ analog-to-
digital converter (ADC). It combines wide input bandwidth
and high speed with the benefits of Σ-Δ conversion with a
performance of 106 dB SNR at 625 kSPS, making it ideal for
high speed data acquisition. Wide dynamic range combined
with significantly reduced antialiasing requirements simplify
the design process. An integrated buffer to drive the reference,
a differential amplifier for signal buffering and level shifting, an
overrange flag, internal gain and offset registers, and a low-pass
digital FIR filter make the AD7762 a compact, highly integrated
data acquisition device requiring minimal peripheral com-
ponent selection. In addition, the device offers programmable
decimation rates, and the digital FIR filter can be adjusted if
the default characteristics are not appropriate to the application.
The AD7762 is ideal for applications demanding high SNR
without a complex front end signal processing design.
coefficients. The sample rate, filter corner frequencies, and output
word rate are set by a combination of the external clock frequency
and the configuration registers of the AD7762.
The reference voltage supplied to the AD7762 determines the
analog input range. With a 4 V reference, the analog input range
is ±±.2 V differential biased around a common mode of 2 V.
This common-mode biasing can be achieved using the on-chip
differential amplifier, further reducing the external signal
conditioning requirements.
The AD7762 is available in an exposed paddle, 64-lead TQFP
and is specified over the industrial temperature range from
−40°C to +85°C.
Table 1. Related Devices
Part No.
AD7760
AD7763
Description
24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface
24-bit, 625 kSPS, 109 dB Σ-Δ, serial interface
The differential input is sampled at up to 40 MSPS by an analog
modulator. The modulator output is processed by a series of low-
pass filters, the final filter having default or user-programmable
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD7762
TABLE OF CONTENTS
General Description......................................................................... 1
Bias Resistor Selection ............................................................... 17
Decoupling and Layout Recommendations................................ 18
Supply Decoupling ..................................................................... 19
Additional Decoupling .............................................................. 19
Reference Voltage Filtering ....................................................... 19
Differential Amplifier Components ........................................ 19
Layout Considerations............................................................... 19
Programmable FIR Filter............................................................... 20
Downloading a User-Defined Filter ............................................ 21
Example Filter Download ......................................................... 21
AD7762 Registers........................................................................... 2±
Control Register 1—Reg 0x0001.............................................. 2±
Control Register 2—Address 0x0002 ...................................... 2±
Status Register (Read Only)...................................................... 24
Offset Register—Address 0x000±............................................. 24
Gain Register—Address 0x0004............................................... 24
Overrange Register—Address 0x0005..................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Specifications..................................................................................... ±
Timing Specifications....................................................................... 5
Timing Diagrams.......................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 1±
AD7762 Interface............................................................................ 14
Reading Data............................................................................... 14
Sharing the Parallel Bus............................................................. 14
Writing to the AD7762 .............................................................. 14
Reading Status and Other Registers......................................... 14
Clocking the AD7762 ................................................................ 15
Example 1 .................................................................................... 15
Example 2 .................................................................................... 15
Driving the AD7762....................................................................... 16
Using the AD7762 ...................................................................... 17
REVISION HISTORY
8/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD7762
SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD± = AVDD4 = 5 V, VREF = 4.096 V, MCLK amplitude = 5 V, TA = 25°C, normal mode,
using on-chip amplifier with components as shown in Table 8, unless otherwise noted.1
Table 2.
Parameter
Test Conditions/Comments
Specification Unit
DYNAMIC PERFORMANCE
Decimate by 256
Dynamic Range
MCLK = 40 MHz, ODR = 78 kHz, FIN = 1 kHz
Modulator inputs shorted
119
120.5
112
59
126
77
−105
−106
−75
dB min
dB typ
Signal-to-Noise Ratio (SNR)2
Input amplitude = −0.5 dBFS
Input amplitude = −60 dBFS
Nonharmonic, input amplitude = −6 dBFS
Input amplitude = −60 dBFS
Input amplitude = −0.5 dBFS
Input amplitude = −6 dBFS
Input amplitude = −60 dBFS
dB typ
dB typ
dBc typ
dBc typ
dB typ
dB typ
dB typ
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Decimate by 64
Dynamic Range
MCLK = 40 MHz, ODR = 312.5 kHz, FIN = 1 kHz
Modulator inputs shorted
112
114
dB min
dB typ
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)
Decimate by 32
Input amplitude = −0.5 dBFS
109.5
126
dB typ
dBc typ
Nonharmonic, input amplitude = −6 dBFS
MCLK = 40 MHz, ODR = 625 kHz, FIN =100 kHz
Modulator inputs shorted
Dynamic Range
108
109.5
107
120
−108
−106
dB min
dB typ
Signal-to-Noise Ratio (SNR)2
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Input amplitude = −0.5 dBFS
Nonharmonic, input amplitude = −6 dBFS
Input amplitude = −0.5 dBFS
Input amplitude = −6 dBFS
dB typ
dBc typ
dB typ
dB typ
DC ACCURACY
Resolution
24
Bits
Differential Nonlinearity
Integral Nonlinearity
Zero Error
Guaranteed monotonic to 24 bits
0.00076
0.014
0.02
0.015
0.019
0.0002
% typ
% typ
% max
% typ
%/°C typ
%/°C typ
Gain Error
Zero Error Drift
Gain Error Drift
DIGITAL FILTER RESPONSE
Decimate by 32
Group Delay
Decimate by 64
Group Delay
Decimate by 256
Group Delay
MCLK = 40 MHz
MCLK = 40 MHz
MCLK = 40 MHz
47
μs typ
μs typ
μs typ
91.5
358
ANALOG INPUT
Differential Input Voltage
VIN(+) – VIN(−), VREF = 2.5 V
VIN(+) – VIN(−), VREF = 4.096 V
At internal buffer inputs
At modulator inputs
2
3.25
5
V p-p
V p-p
pF typ
pF typ
Input Capacitance
55
Rev. 0 | Page 3 of 28
AD7762
Parameter
Test Conditions/Comments
Specification Unit
REFERENCE INPUT/OUTPUT
VREF Input Voltage
VDD3 = 3.3 V 5%
VDD3 = 5 V 5%
+2.5
+4.096
V max
V max
VREF Input DC Leakage Current
VREF Input Capacitance
6
5
μA max
pF max
POWER DISSIPATION
Total Power Dissipation
Normal mode
Low power mode
Clock stopped
958
661
6.35
mW max
mW max
mW max
Standby Mode
POWER REQUIREMENTS
AVDD1 (Modulator Supply)
AVDD2 (General Supply)
AVDD3 (Diff Amp Supply)
AVDD4 (Ref Buffer Supply)
DVDD
5%
5%
+2.5
+5
+3.15/+5.25
+3.15/+5.25
+2.5
V
V
V min/max
V min/max
V
5%
VDRIVE
+1.65/+2.7
V min/max
Normal Mode
AIDD1 (Modulator)
AIDD2 (General)
AIDD4 (Reference Buffer)
Low Power Mode
AIDD1 (Modulator)
AIDD2 (General)
49/51
40/42
34/36
mA typ/max
mA typ/max
mA typ/max
AVDD4 = 5 V
AVDD4 = 5 V
26/28
20/23
9/10
mA typ/max
mA typ/max
mA typ/max
AIDD4 (Reference Buffer)
AIDD3 (Diff Amp)
DIDD
AVDD3 = 5 V, both modes
Both modes
41/44
63/70
mA typ/max
mA typ/max
DIGITAL I/O
MCLK Input Amplitude3
5
V typ
Input Capacitance
Input Leakage Current
Three-State Leakage Current (D15:D0)
VINH
VINL
7.3
5
5
0.7 × VDRIVE
0.3 × VDRIVE
1.5
pF typ
ꢀA max
ꢀA max
V min
V max
V min
V max
4
VOH
VOL
4
0.1
1 See the Terminology section.
2 SNR specifications in dBs are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
3 While the AD7762 can function with an MCLK amplitude of less than 5 V, this is the recommended amplitude to achieve the performance as stated.
4 Tested with a 400 μA load current.
Rev. 0 | Page 4 of 28
AD7762
TIMING SPECIFICATIONS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD± = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMCLK
1
40
500
20
MHz min
MHz max
kHz min
MHz max
typ
Applied master clock frequency
fICLK
Internal modulator clock derived from MCLK
1, 2
t1
0.5 × tICLK
DRDY pulse width
t2
10
ns min
ns min
max
DRDY falling edge to CS falling edge
RD/WR setup time to CS falling edge
Data access time
t3
3
t4
(0.5 × tICLK) + 16 ns
t5
tICLK
min
CS low read pulse width
t6
tICLK
min
CS high pulse width between reads
RD/WR hold time to CS rising edge
Bus relinquish time
CS low write pulse width
CS high period between address and data
Data setup time
t7
3
ns min
ns max
min
t8
t9
11
4 × tICLK
t10
t11
t12
4 × tICLK
min
5
0
ns min
ns min
Data hold time
1 tICLK = 1/fICLK
When ICLK = MCLK,
.
2
DRDY
pulse width depends on the mark/space ratio of applied MCLK.
TIMING DIAGRAMS
DRDY
CS
t5
t6
t1
t2
t7
t3
RD/WR
D[0:15]
t8
t4
DATA MSW
LSW + STATUS
Figure 2. Parallel Interface Timing Diagram
CS
t9
t10
RD/WR
D[0:15]
t11
t12
REGISTER ADDRESS
REGISTER DATA
Figure 3. AD7762 Register Write
Rev. 0 | Page 5 of 28
AD7762
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameters
Rating
AVDD1 to GND
AVDD2–AVDD4 to GND
DVDD to GND
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to +3 V
−0.3 V to +3 V
−0.3 V to +6 V
−0.3 V to DVDD + 0.3 V
−0.3 V to +6 V
−0.3 V to AVDD4 + 0.3 V
−0.3 V to +0.3 V
10 mA
VDRIVE to GND
VIN+, VIN– to GND
Digital input voltage to GND1
MCLK to MCLKGND
VREF to GND2
AGND to DGND
Input Current to Any Pin
Except Supplies3
Operating Temperature Range
Commercial
−40°C to +85°C
−65°C to +150°C
150°C
Storage Temperature Range
Junction Temperature
TQFP Exposed Paddle Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
92.7°C/W
5.1°C/W
215°C
220°C
600 V
ESD
1 Absolute maximum voltage on digital inputs is 3.0 V or DVDD + 0.3 V,
whichever is lower.
2 Absolute maximum voltage on VREF input is 6.0 V or AVDD4 + 0.3 V,
whichever is lower.
3 Transient currents of up to 200 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 28
AD7762
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DGND
DB12
DB13
DB14
DB15
PIN 1
2
3
MCLKGND
MCLK
4
AV
DD2
5
AGND2
V
DRIVE
6
AV
DGND
DGND
DD1
AD7762
7
AGND1
DECAPA
REFGND
TOP VIEW
(Not to Scale)
8
DV
CS
DD
9
10
11
12
13
14
15
16
V
RD/WR
DRDY
REF+
AGND4
AV
RESET
SYNC
DD4
AGND2
AV
AV
DGND
AGND1
DD2
DD2
AGND2
AV
DD1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 4. 64-Lead TQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
6, 33
AVDD1
2.5 V Power Supply for Modulator. These pins should be decoupled to AGND1 with 100 nF and 10 μF
capacitors on each pin.
4, 14, 15, 27
AVDD2
AVDD3
AVDD4
AGND1
5 V Power Supply. These pins should be decoupled to AGND2 with 100 nF capacitors on each of Pin 4,
Pin 14, and Pin 15. Pin 27 should be connected to Pin 14 via a 15 nH inductor.
3.3 V to 5 V Power Supply for Differential Amplifier. These pins should be decoupled to AGND3 with a
100 nF capacitor.
3.3 V to 5 V Power Supply for Reference Buffer. This pin should be decoupled to AGND4 with a
10 nF capacitor in series with a 10 Ω resistor.
24
12
7, 34
Power Supply Ground for Analog Circuitry Powered by AVDD1
Power Supply Ground for Analog Circuitry Powered by AVDD2
Power Supply Ground for Analog Circuitry Powered by AVDD3
Power Supply Ground for Analog Circuitry Powered by AVDD4
.
.
.
.
5, 13, 16, 18, 28 AGND2
23, 29, 31, 32
11
9
41
AGND3
AGND4
REFGND
DVDD
Reference Ground. Ground connection for the reference voltage.
2.5 V Power Supply for Digital Circuitry and FIR Filter. This pin should be decoupled to DGND with a
100 nF capacitor.
44, 63
VDRIVE
Logic Power Supply Input, 1.8 V to 2.5 V. The voltage supplied at these pins determines the operating
voltage of the logic interface. Both these pins must be connected together and tied to the same supply.
Each pin should also be decoupled to DGND with a100 nF capacitor.
1, 35, 42, 43,
53, 62, 64
DGND
Ground Reference for Digital Circuitry.
19
20
21
22
25
26
10
VINA+
VINA−
VOUTA−
VOUTA+
VIN+
Positive Input to Differential Amplifier.
Negative Input to Differential Amplifier.
Negative Output from Differential Amplifier.
Positive Output from Differential Amplifier.
Positive Input to the Modulator.
Negative Input to the Modulator.
Reference Input. The input range of this pin is determined by the reference buffer supply voltage
(AVDD4). See the Reference Voltage Filtering section for more details.
VIN−
VREF+
8
DECAPA
Decoupling Pin. A 100 nF capacitor must be inserted between this pin and AGND1.
Rev. 0 | Page 7 of 28
AD7762
Pin No.
30
17
Mnemonic
DECAPB
RBIAS
Description
Decoupling Pin. A 33 pF capacitor must be inserted between this pin and AGND3.
Bias Current Setting Pin. A resistor must be inserted between this pin and AGND1. For more details, see
the Bias Resistor Selection section.
45 to 52,
54 to 61
DB15 to DB8
DB7 to DB0
16-Bit Bidirectional Data Bus. These are three-state pins that are controlled by the CS pin and the RD/WR
pin. The operating voltage for these pins is determined by the VDRIVE voltage. See the AD7762 Interface
section for more details.
37
3
RESET
MCLK
A falling edge on this pin resets all internal digital circuitry and powers down the part. Holding this pin
low keeps the AD7762 in a reset state.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends
on the frequency of this clock. See the section Clocking the AD7762 for more details.
2
36
MCLKGND
SYNC
Master Clock Ground Sensing Pin.
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to
synchronize multiple devices in a system.
39
RD/WR
Read/Write Input. This pin, in conjunction with the chip select pin, is used to read and write data to and
from the AD7762. If this pin is low when CS is low, a read takes place. If this pin is high and CS is low, a
write occurs. See the AD7762 Interface section for more details.
38
40
DRDY
CS
Data Ready Output. Each time that new conversion data is available, an active low pulse, ½ ICLK period
wide, is produced on this pin. See the AD7762 Interface section for more details.
Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from the
AD7762. See the AD7762 Interface section for more details.
Rev. 0 | Page 8 of 28
AD7762
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
Differential Nonlinearity (DNL)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
The difference between the measured and the ideal 1-LSB
change between any two adjacent codes in the ADC.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) and the actual voltage producing the
midscale output code.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7762, it is defined as
Zero Error Drift
V22 +V32 +V42 +V52 +V62
The change in the actual zero error value due to a temperature
change of 1°C. It is expressed as a percentage of the zero error at
room temperature.
THD dB = 20 log
( )
V1
where:
Gain Error
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5,.and V6 are the rms amplitudes of the second to
the sixth harmonics.
The first transition (from 100…000 to 100…001) should occur
for an analog voltage 1/2 LSB above the nominal negative full
scale. The last transition (from 011…110 to 011…111) should
occur for an analog voltage 1 1/2 LSB below the nominal full
scale. The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition, from the difference between the ideal levels.
Nonharmonic Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, excluding harmonics.
Dynamic Range
Gain Error Drift
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
The change in the actual gain error value due to a temperature
change of 1°C. It is expressed as a percentage of the gain error at
room temperature.
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
Rev. 0 | Page 9 of 28
AD7762
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD± = AVDD4 = 5 V, VREF = 4.096 V, TA = 25°C, normal mode, unless otherwise noted. All FFTs
are generated from 655±6 samples using a 7-term Blackman-Harris window.
0
0
–25
–25
–50
–50
–75
–75
–100
–125
–150
–175
–200
–100
–125
–150
–175
–200
0
4000
8000
12000
16000
20000
24000
0
4000
8000
12000
16000
20000
24000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 8. Low Power FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation
Figure 5. Normal Mode FFT, 1 kHz, −0.5 dB Input Tone, 256× Decimation
0
–25
0
–25
–50
–50
–75
–75
–100
–125
–150
–175
–200
–100
–125
–150
–175
–200
0
4000
8000
12000
16000
20000
24000
0
4000
8000
12000
16000
20000
24000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 6. Normal Mode FFT, 1 kHz, −6 dB Input Tone, 256× Decimation
Figure 9. Low Power FFT, 1 kHz, −6 dB Input Tone, 256× Decimation
0
–25
0
–25
–50
–50
–75
–75
–100
–125
–150
–175
–200
–100
–125
–150
–175
–200
0
4000
8000
12000
16000
20000
24000
0
4000
8000
12000
16000
20000
24000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 7. Normal Mode FFT, 1 kHz, −60 dB Input Tone, 256× Decimation
Figure 10. Low Power FFT, 1 kHz, −60 dB Input Tone, 256× Decimation
Rev. 0 | Page 10 of 28
AD7762
0
–25
0
–25
–50
–50
–75
–75
–100
–125
–150
–175
–200
–100
–125
–150
–175
–200
0
60000
120000
180000
240000
300000
0
60000
120000
180000
240000
300000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 11. Normal Mode FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation
Figure 14. Low Power FFT, 100 kHz, −0.5 dB Input Tone, 32× Decimation
0
–25
0
–25
–50
–50
–75
–75
–100
–125
–150
–175
–200
–100
–125
–150
–175
–200
0
60000
120000
180000
240000
300000
0
60000
120000
180000
240000
300000
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Normal Mode FFT, 100 kHz, −6 dB Input Tone, 32× Decimation
Figure 15. Low Power FFT, 100 kHz, −6 dB Input Tone, 32× Decimation
120
116
–60dB
118
–60dB
116
112
108
104
–6dB
–6dB
114
–0.5dB
112
–0.5dB
110
108
106
0
64
128
192
256
0
64
128
192
256
DECIMATION RATE (x)
DECIMATION RATE (x)
Figure 13. Normal Mode SNR vs. Decimation Rate, 1 kHz Input Tone
Figure 16. Low Power SNR vs. Decimation Rate, 1 kHz Input Tone
Rev. 0 | Page 11 of 28
AD7762
4500
4000
3500
3000
2500
2000
1500
1000
500
3000
2500
2000
1500
1000
500
0
0
8385222
8385238
8385254
8385270
8383530 83835246 8383562 8383578 8383594 8383610
24-BIT CODE
24-BIT CODE
Figure 17. Normal Mode, 24-Bit Histogram, 256× Decimation
Figure 20. Low Power, 24-Bit Histogram, 256× Decimation
0.0010
0.0015
+85°C
+85°C
+25°C
0.0010
0.0005
0
0.0005
+25°C
0
–40°C
–40°C
–0.0005
–0.0010
–0.0005
–0.0010
0
4194304
8388608
12582912
16777216
0
4194304
8388608
12582912
16777216
24-BIT CODE
24-BIT CODE
Figure 18. 24-Bit INL, Normal Mode
Figure 21. 24-Bit INL, Low Power Mode
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
4194304
8388608
12582912
16777216
24-BIT CODE
Figure 19. 24-Bit DNL
Rev. 0 | Page 12 of 28
AD7762
THEORY OF OPERATION
The AD7762 employs a Σ-Δ conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word to the digital filter at a rate equal to ICLK.
rate to be chosen from 4× to ±2×. The third filter has a fixed
decimation rate of 2×, is user programmable, and has a default
configuration. It is described in detail in the Programmable FIR
Filter section. This filter can be bypassed.
Due to the high oversampling rate, that spreads the
Table 6 lists some characteristics of the default filter. The group
delay of the filter is defined to be the delay to the center of the
impulse response and is equal to the computation + filter delays.
The delay until valid data is available (the DVALID status bit is
set) is equal to 2× the filter delay + the computation delay.
quantization noise from 0 to fICLK, the noise energy contained in
the band of interest is reduced (Figure 22 a). To further reduce
the quantization noise, a high order modulator is employed to
shape the noise spectrum; so that most of the noise energy is
shifted out of the band of interest (Figure 22 b).
a.
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (Figure 22 c) while also
reducing the data rate from fICLK at the input of the filter to
fICLK/8 or less at the output of the filter, depending on the
decimation rate used.
QUANTIZATION NOISE
f
\2
ICLK
BAND OF INTEREST
b.
Digital filtering has certain advantages over analog filtering. It
does not introduce significant noise or distortion and can be
made perfectly linear phase.
NOISE SHAPING
f
\2
ICLK
The AD7762 employs three FIR filters in series. By using
different combinations of decimation ratios and filter selection
and bypassing, data can be obtained from the AD7762 at a large
range of data rates. The first filter receives data from the
modulator at ICLK MHz where it is decimated by four to
output data at ICLK/4 MHz. This partially filtered data can also
be output at this stage. The second filter allows the decimation
BAND OF INTEREST
c.
DIGITAL FILTER CUTOFF FREQUENCY
f
\2
ICLK
BAND OF INTEREST
Figure 22. Σ-Δ ADC
Table 6. Configuration with Default Filter
ICLK
Frequency
Computation
Delay
Pass-Band
Bandwidth
Output Data
Rate (ODR)
Filter 1
4×
Filter 2
4×
Filter 3
2×
Data State
Filter Delay
44.4 μs
20 MHz
Fully filtered
1.775 μs
250 kHz
625 kHz
20 MHz
4×
8×
Bypassed
2×
Partially filtered 2.6 μs
Fully filtered 2.25 μs
Partially filtered 4.175 μs
Fully filtered 3.1 μs
Partially filtered 7.325 μs
10.8 μs
140.625 kHz 625 kHz
125 kHz 312.5 kHz
70.3125 kHz 312.5 kHz
20 MHz
4×
8×
87.6 μs
20 MHz
4×
16×
16×
32×
32×
8×
Bypassed
2×
20.4 μs
20 MHz
4×
174 μs
62.5 kHz
35.156 kHz
31.25 kHz
76.8 kHz
38.4 kHz
21.6 kHz
19.2 kHz
156.25 kHz
156.25 kHz
78.125 kHz
192 kHz
96 kHz
20 MHz
4×
Bypassed
2×
39.6 μs
20 MHz
4×
Fully filtered
Fully filtered
Fully filtered
4.65 μs
3.66 μs
5.05 μs
346.8 μs
142.6 μs
283.2 μs
64.45 μs
564.5 μs
12.288 MHz
12.288 MHz
12.288 MHz
12.288 MHz
4×
2×
4×
16×
32×
32×
2×
4×
Bypassed
2×
Partially filtered 11.92 μs
Fully filtered 7.57 μs
96 kHz
4×
48 kHz
Rev. 0 | Page 13 of 28
AD7762
AD7762 INTERFACE
READING DATA
WRITING TO THE AD7762
The AD7762 uses a 16-bit bidirectional parallel interface. This
While the AD7762 is configured to convert analog signals with
the default settings on reset, there are many features and
parameters on this part that the user can change by writing to
the device. Because some of the programmable registers are
16 bits wide, two write operations are required to program a
register. The first write contains the register address while the
second write contains the register data. An exception is when a
user filter is being downloaded to the AD7762. This is
described in detail in the Downloading a User-Defined Filter
section. The AD7762 Registers section contains the register
addresses and more details.
interface is controlled by the
/WR and
pins.
RD
CS
When a new conversion result is available, an active low pulse is
output on the pin. To read a conversion result from the
DRDY
AD7762, two 16-bit read operations are performed. The
DRDY
pulse indicates that a new conversion result is available. Both
/WR and go low to perform the first read operation.
RD
CS
Shortly after both these lines go low, the data bus becomes
active and the 16 most significant bits (MSBs) of the conversion
result are output. The
/WR and
lines must return high
RD
CS
for a full ICLK period before the second read is performed. This
second read contains the 8 least significant bits (LSBs) of the
conversion result along with 6 status bits. These status bits are
shown in Table 7. Descriptions of the other status bits are in
Table 15.
Figure ± shows a write operation to the AD7762. The
/WR
RD
line is held high while the
line is brought low for a minimum
CS
of 4 ICLK periods. The register address is latched during this
period. The line is brought high again for a minimum of
CS
4 ICLK periods before the register data is put onto the data bus.
If a read operation occurs between the writing of the register
address and the register data, the register address is cleared and
the next write must be the register address again. This also
provides a method to get back to a known situation if the user
forgets whether the next write is an address or data.
Table 7. Status Bits During Data Read
D7
D0
DValid Ovr
UFilt
LPwr FiltOk DLOk
0
0
Shortly after
/WR and
return high, the data bus returns
CS
RD
to a high impedance state. Both read operations must be
completed before a new conversion result is available because
the new result overwrites the contents on the output register.
Generally, the AD7762 is written to and configured on power-
up and very infrequently, if at all, after that. Following any write
operation, the full group delay of the filter must pass before
valid data is output from the AD7762.
If a
pulse occurs during a read operation, the data read
DRDY
is invalid.
READING STATUS AND OTHER REGISTERS
SHARING THE PARALLEL BUS
The AD7762 features a number of programmable registers. To
read back the contents of these registers or the status register, the
user must first write to the control register of the device, setting
a bit corresponding to the register to be read. The next read
operation outputs the contents of the selected register instead
of a conversion result. The AD7762 Registers section provides
more information on the relevant bits in the control register.
By its nature, the high accuracy of the AD7762 makes it
sensitive to external noise sources. These include digital activity
on the parallel bus. For this reason, it is recommended that the
AD7762 data lines are isolated from the system data bus by
means of a latch or buffer to ensure that there is no digital
activity on the D0 to D15 pins that is not controlled by the
AD7762. If multiple, synchronized AD7762 parts that share a
properly distributed common MCLK signal exist in a system,
these parts can share a common bus without being isolated
from each other. This bus can then be isolated from the system
bus by a single latch or buffer.
Rev. 0 | Page 14 of 28
AD7762
CLOCKING THE AD7762
EXAMPLE 2
The AD7762 requires an external low jitter clock source. This
signal is applied to the MCLK pin, and the MCLKGND pin is
used to sense the ground from the clock source. An internal
clock signal (ICLK) is derived from the MCLK input signal.
The ICLK controls the internal operations of the AD7762. The
maximum ICLK frequency is 20 MHz, but due to an internal
clock divider, a range of MCLK frequencies can be used. There
are two ways to generate the ICLK:
Take a second example from Table 6, where:
ODR = 48 kHz
fICLK = 12.288 MHz
fIN (max) = 19.2 kHz
SNR = 120 dB
256
t j(rms)
=
=1±± ps
2 × π×19.2 ×10± ×106
ICLK = MCLK (
= 1)
CDIV
The input amplitude also has an effect on these jitter figures.
If, for example, the input level was ± dB below full scale, the
allowable jitter would be increased by a factor of √2, increasing
the first example to 2.5± ps rms. This happens when the
maximum slew rate is decreased by a reduction in amplitude.
Figure 2± and Figure 24 illustrate this point, showing the
maximum slew rate of a sine wave of the same frequency but
with different amplitudes.
ICLK = MCLK/2 (
= 0)
CDIV
These options are selected from the control register (see the
AD7762 Registers section for more details). On power-up, the
default is ICLK = MCLK/2 to ensure that the part can handle
the maximum MCLK frequency of 40 MHz. For output data
rates equal to those used in audio systems, a 12.288 MHz ICLK
frequency can be used. As shown in Table 6, output data rates
of 192 kHz, 96 kHz, and 48 kHz are achievable with this ICLK
frequency. As mentioned previously, this ICLK frequency can
be derived from different MCLK frequencies.
1
0.5
0
The MCLK jitter requirements depend on a number of factors
and are given by
OSR
t j(rms)
=
SNR(dB)
20
2×π× fIN ×10
–0.5
where:
OSR = Over-sampling ratio =
fICLK
ODR
–1.0
fIN = Maximum input frequency
SNR(dB) = Target SNR
Figure 23. Maximum Slew Rate of Sine Wave with Amplitude of 2 V p-p
EXAMPLE 1
1
0.5
This example can be taken from Table 6, where:
ODR = 625 kHz
fICLK = 20 MHz
fIN (max) = 250 kHz
SNR = 108 dB
0
±2
tj(rms)
=
= ±.6ps
2× π×250×10± ×106
–0.5
–1.0
This is the maximum allowable clock jitter for a full-scale,
250 kHz input tone with the given ICLK and output data rate.
Figure 24. Maximum Slew Rate of Same Frequency Sine Wave with
Amplitude of 1 V p-p
Rev. 0 | Page 15 of 28
AD7762
DRIVING THE AD7762
+2.5V
0V
+3.685V
+2.048V
+0.410V
The AD7762 has an on-chip differential amplifier that operates
with a supply voltage (AVDD±) from ±.15 V to 5.25 V. For a 4.096
V reference, the supply voltage must be 5 V.
V
+
IN
A
To achieve the specified performance in normal mode, the
differential amplifier should be configured as a first-order
antialias filter, as shown in Figure 25. Any additional filtering
should be carried out in previous stages using low noise, high
performance op amps, such as the AD8021.
–2.5V
+2.5V
0V
+3.685V
+2.048V
+0.410V
B
V
–
IN
Suitable component values for the first-order filter are listed in
Table 8. The values in Table 8 yield a 10 dB attenuation at the
first alias point of 19 MHz.
–2.5V
C
Figure 26. Differential Amplifier Signal Conditioning
FB
C
FB
R
FB
R
2R
FB
R
R
R
R
IN
M
M
A
B
V
V
–
+
IN
2R
V
IN
C
A1
R
R
R
M
S
IN
AD8021
V
V
–
+
IN
IN
C
A1
IN
S
R
M
R
R
FB
FB
IN
R
C
IN
FB
C
FB
Figure 25. Differential Amplifier Configuration
Table 8. Normal Mode Component Values
Figure 27. Single-Ended-to-Differential Conversion
VREF
RIN
RFB
RM
CS
CFB
4.096 V
1 kΩ
655 Ω
18 Ω
5.6 pF
33 pF
V
+
IN
CS1
SS1
SH1
Figure 26 shows the signal conditioning that occurs using the
circuit in Figure 25 with a ±2.5 V input signal biased around
ground and having the component values and conditions in
Table 8. The differential amplifier always biases the output
signal to sit on the optimum common mode of VREF/2, in this
case 2.048 V. The signal is also scaled to give the maximum
allowable voltage swing with this reference value. This is
calculated as 80% of VREF, that is, 0.8 × 4.096 V ≈ ±.275 V p-p
on each input.
SH3
CPA
SS3
CPB1
ANALOG
MODULATOR
CS2
SS2
SH2
SH4
SS4
CPB2
To obtain maximum performance from the AD7762, it is
advisable to drive the ADC with differential signals. Figure 27
shows how a bipolar, single-ended signal biased around ground
can drive the AD7762 with the use of an external op amp, such
as the AD8021.
Figure 28. Equivalent Input Circuit
The AD7762 employs a double sampling front end, as shown in
Figure 28. For simplicity, only the equivalent input circuit for VIN+
is shown. The equivalent input circuitry for VIN− is the same.
With a 4.096 V reference, a 5 V supply must be provided to the
reference buffer (AVDD4). With a 2.5 V reference, a ±.± V supply
must be provided to AVDD4
.
Rev. 0 | Page 16 of 28
AD7762
The sampling switches SS1 and SS± are driven by ICLK, whereas
the sampling switches SS2 and SS4 are driven by . When
Data can then be read from the part using the default filter,
offset, gain, and overrange threshold values. The conversion
data read is not valid, however, until the group delay of the filter
has passed. When this has occurred, the DVALID bit read with
the data LSW is set, indicating that the data is indeed valid.
ICLK
ICLK is high, the analog input voltage is connected to CS1. On
the falling edge of ICLK, the SS1 and SS± switches open, and the
analog input is sampled on CS1. Similarly, when ICLK is low, the
analog input voltage is connected to CS2. On the rising edge of
ICLK, the SS2 and SS4 switches open, and the analog input is
sampled on CS2.
The user can then download a different filter, if required
(see Downloading a User-Defined Filter). Values for gain, offset,
and overrange threshold registers can be written or read at this
stage.
Capacitors CPA, CPB1, and CPB2 represent parasitic capacitances
that include the junction capacitances associated with the MOS
switches.
BIAS RESISTOR SELECTION
The AD7762 requires a resistor to be connected between the
Table 9. Equivalent Component Values
RBIAS pin and AGND1. The value for this resistor is dependant
Mode
CS1
CS2
CPA
CPB1/2
20 pF
5 pF
on the reference voltage being applied to the device. The resistor
value should be selected to give a current of 25 μA through the
resistor to ground. For a 2.5 V reference voltage, the correct
resistor value is 100 kΩ and for a 4.096 V reference, the correct
resistor value is 160 kΩ.
Normal
Low Power
51 pF
13 pF
51 pF
13 pF
12 pF
12 pF
USING THE AD7762
The following is the recommended sequence for powering up
and using the AD7762.
1. Apply power.
2. Start the clock oscillator, applying MCLK.
±. Take
low for a minimum of 1 MCLK cycle.
RESET
4. Wait a minimum of 2 MCLK cycles after
released.
has been
RESET
5. Write to Control Register 2 to power up the ADC and the
differential amplifier as required. The correct clock divider
(
) ratio should be programmed now.
CDIV
6. Write to Control Register 1 to set the output data rate.
7. Wait a minimum of 5 MCLK cycles after
released.
has been
CS
8. Take
low for a minimum of 4 MCLK cycles, if
SYNC
required, to synchronize multiple parts.
Rev. 0 | Page 17 of 28
AD7762
DECOUPLING AND LAYOUT RECOMMENDATIONS
Due to the high performance nature of the AD7762, correct decoupling and layout techniques are required to obtain the performance as
stated within this datasheet. Figure 29 shows a simplified connection diagram for the AD7762.
U2
DB (0:15)
61
60
59
58
57
56
55
54
52
51
50
49
48
47
46
45
19
20
21
22
DB0
INA+
INA–
V
V
V
V
A+
A–
DB0
DB1
IN
DB1
IN
DB2
OUTA–
OUTA+
A–
A+
DB2
OUT
OUT
DB3
DB3
DB4
DB4
DB5
DB5
8
DB6
DECAPA
DECAPB
DB6
30
DB7
DB7
DB8
DB8
DB9
DB9
25
26
DB10
DB11
DB12
DB13
DB14
DB15
VIN+
VIN–
V
V
+
–
DB10
DB11
DB12
DB13
DB14
DB15
IN
C7
100nF
C64
33pF
IN
AD7762BSV
10
9
VREF
V
+
REF
REFGND
40
39
17
R
CS
CS
BIAS
RD/WR
RD/WR
1
35
42
43
53
62
64
DGND
DGND
DGND
DGND
DGND
DGND
DGND
37
36
38
RESET
SYNC
DRDY
RESET
SYNC
DRDY
R19
160kΩ
3
2
MCLK
MCLK
MCLKGND
AV
DD2
AV
DD4
AV
DD1
AV
DD3
V
DV
DD
DRIVE
PIN 12
(VBUF)
L4
L1
L3
L2
L5
L11
L6
L7
L12
C57
L8
PIN 4
(RHS)
PIN 15
(VBIAS)
PIN 14
(LHS)
PIN 5
(VMOD1)
PIN 33
(VMOD2)
PIN 24
(VDIF1)
PIN 44
(VDRV1)
PIN 63
PIN 41
(DVDD)
PIN 27
(VDRV2)
L9
R38
10Ω
C48
100nF
C50
100nF
C62
100nF
C59
10nF
C52
100nF
C53
100nF
C54
100nF
C56
100nF
C58
100nF
100nF
Figure 29. Simplified Connection Diagram
Rev. 0 | Page 18 of 28
AD7762
SUPPLY DECOUPLING
DIFFERENTIAL AMPLIFIER COMPONENTS
Every supply pin must be connected to the appropriate supply
via a ferrite bead and decoupled to the correct ground pin with
a 100 nF, 060± case size, X7R dielectric capacitor. There are two
exceptions to this:
The correct components for use around the on-chip differential
amplifier are detailed in Table 8. Matching the components on
both sides of the differential amplifier is important to minimize
distortion of the signal applied to the amplifier. A tolerance of
0.1% or better is required for these components. Symmetrical
routing of the tracks on both sides of the differential amplifier
also assists in achieving stated performance.
•
Pin 12 (AVDD4) must have a 10 ꢀ resistor inserted between
the pin and a 10 nF decoupling capacitor.
•
Pin 27 (AVDD2) does not require a separate decoupling
capacitor or a direct connection to the supply, but instead
is connected to Pin 14 via a 15 nH inductor.
LAYOUT CONSIDERATIONS
While using the correct components is essential to achieve
optimum performance, the correct layout is just as important.
The Design Tools section of the AD7762 product page on
the Analog Devices website contains the gerber files for the
AD7762 evaluation board. These files should be used as a
reference when designing any system using the AD7762.
ADDITIONAL DECOUPLING
There are two other decoupling pins on the AD7762—Pin 8
(DECAPA) and Pin ±0 (DECAPB). Pin 8 should be decoupled
with a 100 nF capacitor, and Pin ±0 requires a ±± pF capacitor.
The location and orientation of some of the components
mentioned in previous sections is critical, and particular
attention must be paid to the components which are located
close to the AD7762. Locating these components further away
from the devices can have a direct impact on the maximum
performance achievable.
REFERENCE VOLTAGE FILTERING
A low noise reference source, such as the ADR4±1 (2.5 V) or
ADR4±4 (4.096 V), is suitable for use with the AD7762. The
reference voltage supplied to the AD7762 should be decoupled
and filtered, as shown in Figure ±0.
The recommended scheme for the reference voltage supply
is a 100 ꢀ series resistor connected to a 100 ꢁF tantalum
capacitor, followed by series resistor of 10 ꢀ, and finally a
10 nF decoupling capacitor very close to the VREF+ pin.
The use of ground planes also should be carefully considered.
To ensure that the return currents through the decoupling
capacitors are flowing to the correct ground pin, the ground
side of the capacitors should be as close to the ground pin
associated with that supply. A ground plane should not be relied
on as the sole return path for decoupling capacitors because the
return current path using ground planes is not easily
predictable.
U3
R30
100Ω
R17
10Ω
ADR434
+VIN VOUT
2
6
+12V
PIN10
+
+
GND
4
C15
10μF
C9
100nF
C10
100nF
C11
100μF
C46
10nF
Figure 30. Reference Connection
Rev. 0 | Page 19 of 28
AD7762
PROGRAMMABLE FIR FILTER
As previously mentioned, the third FIR filter on the AD7762 is
user programmable. The default coefficients that are loaded on
reset are given in Table 10 and the frequency responses are
shown in Figure ±1. The frequencies quoted in Figure ±1 scale
directly with the output data rate.
To create a filter, note the following:
•
•
The filter must be even, symmetrical FIR.
The coefficients are in sign-and-magnitude format with
26 magnitude bits and sign coded as positive = 0.
Table 10. Default Filter Coefficients
•
•
The filter length must be between 12 taps and 96 taps in
steps of 12.
Dec.
No. Value
Hex
Value
Dec.
Hex
Value
No. Value
0
1
2
3
4
5
6
7
53656736
332BCA0
17FA5A0
444A196
4B62067
4140C31
6A734E
31DDDB
439E6B2
4392E4A
1709D9
344EF8
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
700847
−70922
−583959 408E917
−175934 402AF3E
388667
294000
−183250 402CBD2
−302597 4049E05
16034
238315
88266
−143205 4022F65
−128919 401F797
51794
121875
16426
−90524
−63899
45234
114720
102357
52669
15559
1963
AB1AF
401150A
Because the filter is symmetrical, the number of
coefficients that must be downloaded is half the filter
length. The default filter coefficients exemplify this with
only 48 coefficients listed for a 96-tap filter.
25142688
−4497814
−11935847
−1313841
6976334
3268059
−3794610
−3747402
1509849
3428088
80255
−2672124
−1056628
1741563
1502200
−835960
−1528400
93626
5EE3B
47C70
•
•
Coefficients are written from the center of impulse
response (adjacent to the point of symmetry) outwards.
The coefficients are scaled so that the in-band gain of the
filter is equal to 1±4217726 with the coefficients rounded
to the nearest integer. For a low-pass filter, this is the
equivalent of having the coefficients sum arithmetically
(including sign) to a 6710886± (0x±FF FFFF) positive
value over the half-impulse response coefficient set
(maximum 48 coefficients). Any deviation from this
introduces a gain error.
8
9
3EA2
3A2EB
158CA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1397F
428C5FC
4101F74
1A92FB
16EBF8
40CC178
4175250
16DBA
135EFE
6466D
40D2F26
40A242E
6A139
CA52
1DC13
402A
401619C
400F99B
B0B2
1C020
18FD5
CDBD
3CC7
0
PASS-BAND RIPPLE = 0.05dB
–0.1dB FREQUENCY = 251kHz
–3dB FREQUENCY = 256kHz
STOP BAND = 312.5kHz
–20
1269502
411245
−864038
−664622
434489
–40
–60
–80
7AB
–100
–120
–140
–160
The default filter should be sufficient for almost all applications.
It is a standard brick wall filter with a symmetrical impulse
response. The default filter has a length of 96 taps in non-
aliasing with 120 dB of attenuation at Nyquist. This filter not
only performs signal antialiasing, but also suppresses out-of-
band quantization noise produced by the analog-to-digital
conversion process. Any significant relaxation in the stop-band
attenuation or transition bandwidth relative to the default filter
can result in a failure to meet the SNR specifications.
0
100
200
300
400
500
600
FREQUENCY (kHz)
Figure 31. Default Filter Frequency Response (625 kHz ODR)
The procedure for downloading a user-defined filter is detailed
in the Downloading a User-Defined Filter section.
Rev. 0 | Page 20 of 28
AD7762
DOWNLOADING A USER-DEFINED FILTER
As previously mentioned, the filter coefficients are 27 bits in
length; 1 sign and 26 magnitude bits. Because the AD7762
has a 16-bit parallel bus, the coefficients are padded with
5 MSB 0s to generate a ±2-bit word and split into two 16-bit
words for downloading. The first 16-bit word for each coefficient
becomes (00000, Sign bit, Magnitude [25:16]), while the second
word becomes (Magnitude [15:0]). To ensure that a filter is
down-loaded correctly, a checksum must also be generated and
then downloaded following the final coefficient. The checksum
is a 16-bit word generated by splitting each ±2-bit word into
4 bytes and summing all bytes from all coefficients up to a
maximum of 192 bytes (48 coefficients × 4 bytes). The same
checksum is generated internally in the AD7762 and compared
with the checksum downloaded. The DL_OK bit in the status
register is set if these two checksums agree.
EXAMPLE FILTER DOWNLOAD
The following is an example of downloading a short user-
defined filter with 24 taps. The frequency response is shown
in Figure ±2.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
To download a user filter:
1. Write to Control Register 1, setting the DL_Filt bit and
also the correct filter length bits corresponding to the
length of the filter to be downloaded (see Table 11).
0
100
200
300
400
500
600
FREQUENCY (kHz)
Figure 32. 24-Tap FIR Frequency Response
2. Write the first half of the current coefficient data
(00000, Sign bit, Magnitude [25:16]). The first coefficient
to be written must be the one adjacent to the point of filter
symmetry.
The coefficients for the filter are listed in Table 12 and are
shown from the center of symmetry outwards. The raw
coefficients were generated using a commercial filter
design tool and scaled appropriately so their sum equals
6710886± (0x±FF FFFF).
±. Write the second half of the current coefficient data
(Magnitude [15:0]).
Table 12. 24-Tap FIR Coefficients
Coefficient
Raw
Scaled
4. Repeat Step 2 and Step ± for each coefficient.
5. Write the 16-bit checksum.
1
2
3
4
5
6
7
8
0.365481974
0.201339905
0.009636604
−0.075708848
−0.042856209
0.019944246
0.036437914
0.007592007
−0.021556583
−0.024888355
−0.012379538
−0.001905756
53188232
29300796
1402406
−11017834
−6236822
2902466
5302774
1104856
−3137108
−3621978
−1801582
−277343
6. Use these methods to verify that the filter coefficients are
downloaded correctly:
a. Read the status register, checking the DL_OK bit.
b. Read data and observe the status of the DL_OK bit.
9
Note that because the user coefficients are stored in RAM, they
10
11
12
are cleared after a
operation or a loss of power.
RESET
Table 11. Filter Length Values
FLEN[3:0]
0000
0001
Number of Coefficients
Filter Length
Default
6
Default
12
0011
12
24
0101
18
36
0111
24
48
1001
30
60
1011
36
72
1101
42
84
1111
48
96
Rev. 0 | Page 21 of 28
AD7762
Table 1± shows the hex values (in sign and magnitude format)
that are downloaded to the AD7762 to realize this filter. The
table is also split into the bytes that are all summed to produce
the checksum. The checksum generated from these coefficients
is 0x0E6B.
Table 14 lists the 16-bit words the user would write to the
AD7762 to set up the ADC and download this filter, assuming
an output data rate of 625 kHz has already been selected.
Table 14.
Word
Description
Table 13. Filter Hex Values
0x0001
0x8079
Address of Control Register 1.
Control register data. DL filter, set filter length = 24,
set output data rate = 625 kHz.
First coefficient, Word 1.
First coefficient, Word 2.
Second coefficient, Word 1.
Second coefficient, Word 2.
Other coefficients.
Twelfth (final) coefficient, Word 1.
Final coefficient, Word 2.
Checksum. Wait (0.5 × tICLK × Number of Unused
Coefficients) for AD7762 to fill remaining unused
coefficients with 0s.
Word 1
Word 2
Byte 4
Coefficient Byte 1
Byte 2
Byte 3
96
18
66
1E
2A
49
E9
DB
DE
44
7D
3B
0x032B
0x9688
0x01BF
0x183C
…
0x0404
0x3B5F
0x0E6B
1
2
3
4
5
6
7
8
03
01
00
04
04
00
00
00
04
04
04
04
2B
BF
15
A8
5F
2C
50
10
2F
37
1B
04
88
3C
26
6A
96
C2
F6
D8
54
5A
6E
5F
9
10
11
12
0x0001
0x0879
Address of control register.
Control register data. Set read status and maintain
filter length and decimation settings. Read contents
of status register. Check Bit 7 (DL_OK) to determine
that the filter was downloaded correctly.
Rev. 0 | Page 22 of 28
AD7762
AD7762 REGISTERS
The AD7762 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter
configuration, the clock divider, and so on. There are also digital gain, offset, and overrange threshold registers. Writing to these registers
involves writing the register address first, then a 16-bit data-word. Register addresses, details of individual bits, and default values are
given here.
CONTROL REGISTER 1—REG 0X0001
Default Value 0x001A
MSB
LSB
BYP F3
DL_ Filt RD Ovr RD Gain RD Off RD Stat
0
SYNC FLEN3 FLEN2 FLEN1 FLEN0
1
DEC2 DEC1 DEC0
Table 15.
Bit Mnemonic Description
15
DL_Filt1
Download Filter. Before downloading a user-defined filter, this bit must be set. The Filter Length bits must also be set at
this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until all the
coefficients and the checksum have been written.
Read Overrange. If this bit has been set, the next read operation outputs the contents of the Overrange Threshold
Register instead of a conversion result.
14
RD Ovr1, 2
13
12
11
10
9
RD Gain1, 2
RD Off1, 2
RD Stat1, 2
0
Read Gain. If this bit has been set, the next read operation outputs the contents of the digital gain register.
Read Offset. If this bit has been set, the next read operation outputs the contents of the digital offset register.
Read Status. If this bit has been set, the next read operation outputs the contents of the status register.
0 must be written to this bit.
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously on multiple
devices synchronizes all filters.
SYNC1
8-5 FLEN3:0
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
Bypass Filter 3. If this bit is 0, Filter 3 (programmable FIR) is bypassed.
1 must be written to this bit.
4
3
BYP F3
1
2-0 DEC2:0
Decimation Rate. These bits set the decimation rate of Filter 2. All 0s implies that the filter is bypassed. A value of 1
corresponds to 2× decimation, a value of 2 corresponds to 4× decimation, and so on up to the maximum value of 5,
corresponding to 32× decimation.
1 Bit 15 to Bit 9 are all self clearing bits.
2 Only one of the bits from Bit 14 to Bit 11 can be set in any write operation because it determines the contents of the next read operation.
CONTROL REGISTER 2—ADDRESS 0X0002
Default Value 0x009B
MSB
LSB
CDIV
0
0
0
0
0
0
0
0
0
0
0
PD
LPWR
1
D1PD
Table 16.
Bit Mnemonic Description
5
CDIV
Clock Divider Bit. This sets the divide ratio of the MCLK signal to produce the internal ICLK. Setting CDIV = 0 divides the
MCLK by 2. If CDIV = 1, then the ICLK frequency is equal to the MCLK.
3
2
PD
LPWR
Power Down. Setting this bit powers down the AD7762, reducing the power consumption to 6.35 mW.
Low Power. If this bit is set, the AD7762 is operating in a low power mode. The power consumption is reduced for a 6 dB
reduction in noise performance.
1
0
1
Write 1 to this bit.
D1PD
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
Rev. 0 | Page 23 of 28
AD7762
STATUS REGISTER (READ ONLY)
MSB
LSB
PART 1 PART 0 DIE 2 DIE 1 DIE 0 DVALID LPWR OVR DL OK Filter OK U Filter BYP F3
1
DEC2 DEC1 DEC0
Table 17.
Bit
Mnemonic
PART1:0
DIE2:0
DVALID
LPWR
Comment
15, 14
13 to 11
10
9
Part Number. These bits are constant for the AD7762.
Die Number. These bits reflect the current AD7762 die number for identification purposes within a system.
Data Valid. This bit corresponds to the DVALID bit in the status word output in the second 16-bit read operation.
Low Power. If the AD7762 is operating in low power mode, this bit is set to 1.
8
OVR
If the current analog input exceeds the current overrange threshold, this bit is set.
7
DL OK
When downloading a user filter to the AD7762, a checksum is generated. This checksum is compared to the one
downloaded following the coefficients. If these checksums agree, this bit is set.
6
Filter OK
When a user-defined filter is in use, a checksum is generated when the filter coefficients pass through the filter. This
generated checksum is compared to the one downloaded. If they match, this bit is set.
5
4
U Filter
BYP F3
1
If a user-defined filter is in use, this bit is set.
Bypass Filter 3. If Filter 3 is bypassed by setting the relevant bit in Control Register 1, this bit is also set.
This bit is always set.
3
2-0
DEC2:0
Decimation Rate. These correspond to the bits set in Control Register 1.
OFFSET REGISTER—ADDRESS 0X0003
Non-bitmapped, Default Value 0x0000
The offset register uses twos complement notation and is scaled such that 0x7FFF (maximum positive value) and 0x8000 (maximum
negative value) correspond to an offset of +0.78125% and −0.78125%, respectively. Offset correction is applied after any gain correction.
Using the default gain value of 1.25 and assuming a reference voltage of 4.096V, the offset correction range is approximately ±25 mV.
GAIN REGISTER—ADDRESS 0X0004
Non-bitmapped, Default Value 0xA000
The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This gives a
full-scale digital output when the input is at 80% of VREF. This ties in with the maximum analog input range of ±80% of VREF p-p.
OVERRANGE REGISTER—ADDRESS 0X0005
Non-bitmapped, Default Value 0xCCCC
The overrange register value is compared with the output of the first decimation filter to obtain an overload indication with minimum
propagation delay. This is prior to any gain scaling or offset adjustment. The default value is 0xCCCC which corresponds to 80% of VREF
(the maximum permitted analog input voltage). Assuming VREF = 4.096 V, the bit is then set when the input voltage exceeds
approximately 6.55 V p-p differential. Note that the overrange bit is also set immediately if the analog input voltage exceeds 100% of VREF
for more than four consecutive samples at the modulator rate.
Rev. 0 | Page 24 of 28
AD7762
OUTLINE DIMENSIONS
12.20
12.00 SQ
11.80
1.20
MAX
0.75
0.60
0.45
64
49
49
64
1
1
48
48
PIN 1
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
EXPOSED
PAD
7.50
BSC SQ
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
16
16
33
33
3.5°
17
32
32
17
0.15
0.05
0°
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.50
BSC
LEAD PITCH
0.38
0.32
0.22
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HD
Figure 33. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
SV-64-4
SV-64-4
AD7762BSVZ1
64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
64-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
Evaluation Board
AD7762BSVZ-REEL1
EVAL-AD7762EB
1 Z = Pb-free part.
Rev. 0 | Page 25 of 28
AD7762
NOTES
Rev. 0 | Page 26 of 28
AD7762
Rev. 0 | Page 27 of 28
AD7762
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05477–0–8/05(0)
Rev. 0 | Page 28 of 28
相关型号：
EVAL-AD7768-4FMCZ
8-/4-Channel, 24-Bit, Simultaneous Sampling ADCs with Power Scaling, 110.8 kHz BW
ADI
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