EVAL-AD7755EB [ADI]
Energy Metering IC with Pulse Output; 电能计量IC，具有脉冲输出
| 型号： | EVAL-AD7755EB |
| 厂家： | 
ADI |
| 描述： | Energy Metering IC with Pulse Output |
| 文件： | 总16页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Energy Metering IC
with Pulse Output
a
AD7755*
FEATURES
GENERAL DESCRIPTION
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of
500 to 1
The AD7755 Supplies Average Real Power on the
Frequency Outputs F1 and F2
The AD7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements
as quoted in the IEC1036 standard. See Analog Devices’
Application Note AN-559 for a description of an IEC1036
watt-hour meter reference design.
The High Frequency Output CF Is Intended for
Calibration and Supplies Instantaneous Real Power
The Logic Output REVP Can Be Used to Indicate a
Potential Miswiring or Negative Power
Direct Drive for Electromechanical Counters and
Two Phase Stepper Motors (F1 and F2)
A PGA in the Current Channel Allows the Use of Small
Values of Shunt and Burden Resistance
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
The only analog circuitry used in the AD7755 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli-
cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The AD7755 supplies average real power information on the
low frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration
purposes, or interfacing to an MCU.
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V 6 8% (30 ppm/8C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process
The AD7755 includes a power supply monitoring circuit on the
AVDD supply pin. The AD7755 will remain in a reset condition
until the supply voltage on AVDD reaches 4 V. If the supply falls
below 4 V, the AD7755 will also be reset and no pulses will be
issued on F1, F2 and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Chan-
nel 1 is on or off. An internal no-load threshold ensures that the
AD7755 does not exhibit any creep when there is no load.
The AD7755 is available in 24-lead DIP and SSOP packages.
FUNCTIONAL BLOCK DIAGRAM
AV
DV
G0 G1
AGND
AC/DC
DGND
DD
DD
AD7755
POWER
SUPPLY MONITOR
PHASE
SIGNAL
PROCESSING
BLOCK
CORRECTION
...110101...
V1P
V1N
ADC
⌽
PGA
x1, x2, x8, x16
HPF
LPF
MULTIPLIER
...11011001...
V2P
V2N
ADC
DIGITAL-TO-FREQUENCY
CONVERTER
RESET
4k⍀
2.5V
REFERENCE
CLKIN CLKOUT
S0
REVP
F1
REF
CF
SCF
S1
F2
IN/OUT
*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,
TMIN to TMAX = –40؇C to +85؇C)
AD7755–SPECIFICATIONS
Parameter
A Version B Version Unit
Test Conditions/Comments
ACCURACY1, 2
Measurement Error1 on Channel 1
Gain = 1
Gain = 2
Gain = 8
Channel 2 with Full-Scale Signal ( 660 mV), 25°C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
% Reading typ Over a Dynamic Range 500 to 1
% Reading typ Over a Dynamic Range 500 to 1
% Reading typ Over a Dynamic Range 500 to 1
% Reading typ Over a Dynamic Range 500 to 1
Line Frequency = 45 Hz to 65 Hz
Gain = 16
Phase Error1 Between Channels
V1 Phase Lead 37°
(PF = 0.8 Capacitive)
V1 Phase Lag 60°
(PF = 0.5 Inductive)
AC Power Supply Rejection1
Output Frequency Variation (CF)
0.1
0.1
0.2
0.1
0.1
0.2
Degrees(°) max AC/DC = 0 and AC/DC = 1
Degrees(°) max AC/DC = 0 and AC/DC = 1
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
% Reading typ V1 = 100 mV rms, V2 = 100 mV rms, @ 50 Hz
Ripple on AVDD of 200 mV rms @ 100 Hz
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
DC Power Supply Rejection1
Output Frequency Variation (CF)
0.3
0.3
% Reading typ V1 = 100 mV rms, V2 = 100 mV rms,
AVDD = DVDD = 5 V 250 mV
ANALOG INPUTS
Maximum Signal Levels
Input Impedance (DC)
Bandwidth (–3 dB)
ADC Offset Error1, 2
Gain Error1
See Analog Inputs Section
V1P, V1N, V2N and V2P to AGND
CLKIN = 3.58 MHz
CLKIN/256, CLKIN = 3.58 MHz
Gain = 1, See Terminology and Performance Graphs
External 2.5 V Reference, Gain = 1
V1 = 470 mV dc, V2 = 660 mV dc
External 2.5 V Reference
1
1
V max
kΩ min
kHz typ
mV max
% Ideal typ
390
14
25
390
14
25
7
7
Gain Error Match1
0.2
0.2
% Ideal typ
REFERENCE INPUT
REFIN/OUT Input Voltage Range
2.7
2.7
V max
V min
kΩ min
pF max
2.5 V + 8%
2.5 V – 8%
2.3
3.2
10
2.3
3.2
10
Input Impedance
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
Nominal 2.5 V
200
30
200
30
60
mV max
ppm/°C typ
ppm/°C max
CLKIN
Note All Specifications for CLKIN of 3.58 MHz
Input Clock Frequency
4
1
4
1
MHz max
MHz min
LOGIC INPUTS3
SCF, S0, S1, AC/DC,
RESET, G0 and G1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
3
2.4
0.8
3
V min
DVDD = 5 V 5%
DVDD = 5 V 5%
Typically 10 nA, VIN = 0 V to DVDD
V max
µA max
pF max
Input Capacitance, CIN
10
10
LOGIC OUTPUTS3
F1 and F2
Output High Voltage, VOH
ISOURCE = 10 mA
DVDD = 5 V
ISINK = 10 mA
DVDD = 5 V
4.5
0.5
4.5
0.5
V min
V max
Output Low Voltage, VOL
CF and REVP
Output High Voltage, VOH
ISOURCE = 5 mA
DVDD = 5 V
ISINK = 5 mA
DVDD = 5 V
4
4
V min
V max
Output Low Voltage, VOL
0.5
0.5
REV. B
–2–
AD7755
Parameter
A Version B Version Unit
Test Conditions/Comments
POWER SUPPLY
AVDD
For Specified Performance
5 V – 5%
5 V + 5%
5 V – 5%
5 V + 5%
4.75
5.25
4.75
5.25
3
4.75
5.25
4.75
5.25
3
V min
V max
V min
V max
mA max
mA max
DVDD
AIDD
DIDD
Typically 2 mA
Typically 1.5 mA
2.5
2.5
NOTES
1See Terminology section for explanation of specifications.
2See Plots in Typical Performance Graphs.
3Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
(AVDD = DVDD = 5 V ؎ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz, TMIN to
TMAX = –40؇C to +85؇C)
TIMING CHARACTERISTICS1, 2
Parameter
A, B Versions
Unit
Test Conditions/Comments
3
t1
t2
275
See Table III
1/2 t2
ms
sec
sec
ms
sec
sec
F1 and F2 Pulsewidth (Logic Low)
Output Pulse Period. See Transfer Function Section
Time Between F1 Falling Edge and F2 Falling Edge
CF Pulsewidth (Logic High)
CF Pulse Period. See Transfer Function Section
Minimum Time Between F1 and F2 Pulse
t33, 4
t4
t5
t6
90
See Table IV
CLKIN/4
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter.
2See Figure 1.
3The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4The CF pulse is always 18 µs in the high frequency mode. See Frequency Outputs section and Table IV.
Specifications subject to change without notice.
t1
F1
.t6
.t2
F2
.t3
.t5
t4
CF
Figure 1. Timing Diagram for Frequency Outputs
ORDERING GUIDE
Model
Package Description
Package Options
AD7755AAN
AD7755AARS
AD7755ABRS
Plastic DIP
Shrink Small Outline Package
Shrink Small Outline Package
N-24
RS-24
RS-24
EVAL-AD7755EB AD7755 Evaluation Board
AD7755AAN-REF AD7755 Reference Design PCB (See AN-559)
REV. B
–3–
AD7755
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND
24-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . . 260°C
24-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . 450 mW
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7755 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
MEASUREMENT ERROR
ADC OFFSET ERROR
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see a small dc signal (offset). The offset
decreases with increasing gain in channel V1. This specification
is measured at a gain of 1. At a gain of 16, the dc offset is typi-
cally less than 1 mV. However, when the HPF is switched on,
the offset is removed from the current channel and the power
calculation is not affected by this offset.
The error associated with the energy measurement made by the
AD7755 is defined by the following formula:
Energy Registered by the AD7755 – True Energy
Percentage Error =
× 100%
True Energy
PHASE ERROR BETWEEN CHANNELS
The HPF (High Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels, a phase correction network is also
placed in Channel 1. The phase correction network matches the
phase to within 0.1° over a range of 45 Hz to 65 Hz and 0.2°
over a range 40 Hz to 1 kHz. See Figures 22 and 23.
GAIN ERROR
The gain error of the AD7755 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in channel V1.
The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the AD7755 transfer func-
tion—see Transfer Function section.
POWER SUPPLY REJECTION
This quantifies the AD7755 measurement error as a percentage
of reading when the power supplies are varied.
GAIN ERROR MATCH
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the same
input signal levels. Any error introduced is expressed as a per-
centage of reading—see Measurement Error definition.
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a
gain of 2, 8, or 16. It is expressed as a percentage of the out-
put frequency obtained under a gain of 1. This gives the gain
error observed when the gain selection is changed from 1 to 2,
8 or 16.
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
REV. B
–4–
AD7755
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DVDD
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7755.
The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
2
3
AC/DC
High Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current channel).
A logic one on this pin enables the HPF. The associated phase response of this filter has been inter-
nally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be enabled in
power metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7755.
The supply should be maintained at 5 V 5% for specified operation. Every effort should be made to
minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin should
be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
AVDD
4, 19
5, 6
NC
V1P, V1N
No Connect.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with
a maximum differential signal level of 470 mV for specified operation. Channel 1 also has a PGA and
the gain selections are outlined in Table I. The maximum signal level at these pins is 1 V with respect
to AGND. Both inputs have internal ESD protection circuitry and in addition an overvoltage of 6 V
can be sustained on these inputs without risk of permanent damage.
7, 8
V2N, V2P
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential
input pair. The maximum differential input voltage is 660 mV for specified operation. The maximum
signal level at these pins is 1 V with respect to AGND. Both inputs have internal ESD protection
circuitry and an overvoltage of 6 V can also be sustained on these inputs without risk of permanent
damage.
9
RESET
Reset Pin for the AD7755. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7755 internal registers.
10
REFIN/OUT
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may
also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF
ceramic capacitor and 100 nF ceramic capacitor.
11
AGND
This provides the ground reference for the analog circuitry in the AD7755, i.e., ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. For
good noise suppression the analog ground plane should only connected to the digital ground plane at
one point. A star ground configuration will help to keep noisy digital currents away from the analog
circuits.
12
SCF
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table IV shows how the calibration frequencies are selected.
13, 14
S1, S0
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency con-
version. This offers the designer greater flexibility when designing the energy meter. See Selecting a
Frequency for an Energy Meter Application section.
15, 16
17
G1, G0
CLKIN
These logic inputs are used to select one of four possible gains for Channel 1, i.e., V1. The possible
gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7755. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and
33 pF (ceramic) should be used with the gate oscillator circuit.
18
20
CLKOUT
REVP
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7755. The CLKOUT pin can drive one CMOS load when an external clock is supplied at
CLKIN or by the gate oscillator circuit.
This logic output will go logic high when negative power is detected, i.e., when the phase angle between
the voltage and current signals is greater that 90°. This output is not latched and will be reset when
positive power is once again detected. The output will go high or low at the same time as a pulse is
issued on CF.
REV. B
–5–
AD7755
Pin No.
Mnemonic
Description
21
DGND
This provides the ground reference for the digital circuitry in the AD7755, i.e., multiplier, filters and
digital-to-frequency converter. This pin should be tied to the analog ground plane of the PCB. The
digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and
digital), MCUs and indicator LEDs. For good noise suppression the analog ground plane should only
be connected to the digital ground plane at one point only, e.g., a star ground.
22
CF
Calibration Frequency Logic Output. The CF logic output gives instantaneous real power informa-
tion. This output is intended to be used for calibration purposes. Also see SCF pin description.
23, 24
F2, F1
Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs
can be used to directly drive electromechanical counters and two phase stepper motors. See Transfer
Function section.
PIN CONFIGURATION
DIP and SSOP Packages
1
2
24
23
22
21
20
19
18
17
16
15
14
13
DV
DD
F1
F2
AC/DC
AV
3
CF
DD
4
DGND
REVP
NC
NC
V1P
5
AD7755
TOP VIEW
(Not to Scale)
6
V1N
7
CLKOUT
CLKIN
G0
V2N
8
V2P
9
RESET
10
11
12
G1
REF
IN/OUT
AGND
S0
S1
SCF
NC = NO CONNECT
REV. B
–6–
Typical Performance Characteristics–AD7755
0.5
0.4
0.5
–40؇C
0.4
–40؇C
0.3
0.2
0.3
0.2
0.1
0.0
PF = 1
GAIN = 16
0.1
ON-CHIP REFERENCE
+25؇C
+85؇C
+25؇C
+85؇C
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
PF = 1
GAIN = 1
ON-CHIP REFERENCE
100
10
1
0.01
0.1
100
10
1
0.01
0.1
Amps
Amps
Figure 2. Error as a % of Reading (Gain = 1)
Figure 5. Error as a % of Reading (Gain = 16)
0.5
0.6
PF = 0.5
–40؇C
GAIN = 1
0.4
ON-CHIP REFERENCE
0.4
0.3
0.2
–40؇C PF = 0.5
0.2
0.1
+25؇C PF = 1
+25؇C
0.0
0.0
–0.1
+25؇C PF = 0.5
–0.2
+85؇C
–0.2
–0.3
–0.4
–0.5
+85؇C PF = 0.5
–0.4
PF = 1
GAIN = 2
ON-CHIP REFERENCE
–0.6
0.01
100
10
1
0.01
0.1
100
10
1
0.1
Amps
Amps
Figure 3. Error as a % of Reading (Gain = 2)
Figure 6. Error as a % of Reading (Gain = 1)
0.6
0.6
PF = 0.5
GAIN = 2
0.5
–40؇C
ON-CHIP REFERENCE
0.4
0.4
0.3
0.2
0.1
–40؇C PF = 0.5
0.2
PF = 1
GAIN = 8
+25؇C PF = 1
ON-CHIP REFERENCE
0.0
+25؇C
+85؇C
0.0
–0.1
–0.2
–0.3
–0.4
+25؇C PF = 0.5
–0.2
+85؇C PF = 0.5
–0.4
–0.6
0.01
100
10
1
0.1
100
10
1
0.01
0.1
Amps
Amps
Figure 7. Error as a % of Reading (Gain = 2)
Figure 4. Error as a % of Reading (Gain = 8)
REV. B
–7–
AD7755
0.4
0.3
0.8
0.6
0.4
PF = 1
PF = 0.5
GAIN = 16
GAIN = 8
EXTERNAL REFERENCE
ON-CHIP REFERENCE
–40؇C PF = 0.5
–40؇C
0.2
0.1
0.2
0.0
+25؇C
+25؇C PF = 1
0.0
–0.1
–0.2
+25؇C PF = 0.5
–0.2
–0.4
–0.6
+85؇C
+85؇C PF = 0.5
–0.3
–0.4
–0.8
0.01
100
10
1
0.01
0.1
100
10
1
0.1
Amps
Amps
Figure 11. Error as a % of Reading over Temperature with
an External Reference (Gain = 16)
Figure 8. Error as a % of Reading (Gain = 8)
0.8
0.6
0.4
–40؇C PF = 0.5
0.2
0.0
PF = 1
0.4
+25؇C PF = 1
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
PF = 0.5
+25؇C PF = 0.5
+85؇C PF = 0.5
0.0
–0.2
–0.4
–0.6
PF = 0.5
GAIN = 16
ON-CHIP REFERENCE
45
50
55
60
65
70
75
100
10
1
0.01
0.1
FREQUENCY – Hz
Amps
Figure 12. Error as a % of Reading over Frequency
Figure 9. Error as a % of Reading (Gain = 16)
V
DD
100nF
100nF
10F
10F
40A TO
40mA
0.4
K7
K8
AVDD AC/DC AVDD
U3
PF = 1
F1
F2
CF
NC
1k⍀
GAIN = 2
0.3
0.2
0.1
0.0
U1
AD7755
V1P
EXTERNAL REFERENCE
500⍀
1.5m⍀
10m⍀
33nF
1k⍀
REVP
NC
–40؇C
V1N
V2N
PS2501-1
33nF
33pF
33pF
CLKOUT
+25؇C
1M⍀
1k⍀
Y1
3.58MHz
33nF
220V
CLKIN
G0
V
DD
–0.1
–0.2
1k⍀
GAIN
SELECT
+85؇C
V2P
REF
10k⍀
G1
33nF
S0
S1
IN/OUT
–0.3
–0.4
100nF
10F
SCF
10nF
10nF
10nF
RESET AGND DGND
100
10
1
0.01
0.1
Amps
NC = NO CONNECT
V
DD
Figure 10. Error as a % of Reading over Temperature with
an External Reference (Gain = 2)
Figure 13. Test Circuit for Performance Curves
REV. B
–8–
AD7755
16
14
12
10
8
30
DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –2.48959
MINIMUM: –9.78871
GAIN = 1
TEMPERATURE = +25؇C
25
20
15
10
MAXIMUM: 7.2939
MEAN: –1.73203
STD. DEV: 3.61157
MAXIMUM: 5.81126
GAIN = 8
TEMPERATURE = +25؇C
MEAN: –1.26847
STD. DEV: 1.57404
6
4
5
0
2
0
–15
–9
–3
3
9
15
–15
–9
–3
3
9
15
FREQUENCY – Hz
FREQUENCY – Hz
Figure 14. Channel 1 Offset Distribution (Gain = 1)
Figure 17. Channel 1 Offset Distribution (Gain = 8)
18
35
GAIN = 2
TEMPERATURE = +25؇C
DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
DISTRIBUTION
CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –5.61779
MAXIMUM: 6.40821
MEAN: –0.01746
16
14
MINIMUM: –1.96823
MAXIMUM: 5.71177
MEAN: –1.48279
30
25
20
15
GAIN = 16
TEMPERATURE = +25؇C
STD. DEV: 1.47802
STD. DEV: 2.35129
12
10
8
6
10
5
4
2
0
–15
0
–15
–9
–3
3
9
15
–9
–3
3
9
15
FREQUENCY – Hz
FREQUENCY – Hz
Figure 15. Channel 1 Offset Distribution (Gain = 2)
Figure 18. Channel 1 Offset Distribution (Gain = 16)
0.5
0.5
0.4
0.4
5.25V
5.25V
0.3
0.2
0.3
0.2
0.1
0.1
5V
5V
0
0
–0.1
–0.2
–0.1
–0.2
4.75V
4.75V
–0.3
–0.4
–0.5
–0.6
–0.3
–0.4
–0.5
–0.6
0.01
0.1
1
10
100
0.01
0.1
1
10
100
Amps
Amps
Figure 19. PSR with External Reference (Gain = 16)
Figure 16. PSR with Internal Reference (Gain = 16)
REV. B
–9–
AD7755
THEORY OF OPERATION
the voltage by 60°. If we assume the voltage and current wave-
forms are sinusoidal, the real power component of the instanta-
neous power signal (i.e., the dc term) is given by
The two ADCs digitize the voltage signals from the current and
voltage transducers. These ADCs are 16-bit second order
sigma-delta with an oversampling rate of 900 kHz. This analog
input structure greatly simplifies transducer interfacing by
providing a wide dynamic range for direct connection to the
transducer and also simplifying the antialiasing filter design. A
programmable gain stage in the current channel further facili-
tates easy transducer interfacing. A high pass filter in the current
channel removes any dc component from the current signal.
This eliminates any inaccuracies in the real power calculation
due to offsets in the voltage or current signals—see HPF and
Offset Effects section.
V × I
× cos (60°).
2
This is the correct real power calculation.
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
REAL POWER SIGNAL
V
؋
I 2
The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. In order
to extract the real power component (i.e., the dc component),
the instantaneous power signal is low-pass filtered. Figure 20
illustrates the instantaneous real power signal and shows how the
real power information can be extracted by low-pass filtering the
instantaneous power signal. This scheme correctly calculates real
power for nonsinusoidal current and voltage waveforms at all
power factors. All signal processing is carried out in the digital
domain for superior stability over temperature and time.
0V
CURRENT
VOLTAGE
INSTANTANEOUS
POWER SIGNAL
INSTANTANEOUS
REAL POWER SIGNAL
V
؋
I 2
؋
cos(60؇) 0V
DIGITAL-TO-
FREQUENCY
VOLTAGE
CURRENT
HPF
F1
F2
60؇
⌺
CH1
CH2
PGA
ADC
MULTIPLIER
LPF
Figure 21. DC Component of Instantaneous Power Signal
Conveys Real Power Information PF < 1
DIGITAL-TO-
FREQUENCY
ADC
⌺
CF
Nonsinusoidal Voltage and Current
The real power calculation method also holds true for nonsinu-
soidal current and voltage waveforms. All voltage and current
waveforms in practical applications will have some harmonic
content. Using the Fourier Transform, instantaneous voltage
and current waveforms can be expressed in terms of their har-
monic content.
INSTANTANEOUS
INSTANTANEOUS REAL
POWER SIGNAL
POWER SIGNAL – p(t)
V
؋
I p(t) = i(t)
؋
v(t) WHERE:
V
؋
I 2
v(t) = V
؋
cos(t) i(t) = I
؋
cos(t) V
؋
I {1+cos (2t)}
V
؋
I 2
p(t) =
∞
2
v(t) = VO
+
2 × Vh × sin(hωt + αh)
∑
(1)
TIME
h≠0
Figure 20. Signal Processing Block Diagram
where:
The low frequency output of the AD7755 is generated by accu-
mulating this real power information. This low frequency inher-
ently means a long accumulation time between output pulses.
The output frequency is therefore proportional to the average
real power. This average real power information can, in turn, be
accumulated (e.g., by a counter) to generate real energy infor-
mation. Because of its high output frequency and hence shorter
integration time, the CF output is proportional to the instanta-
neous real power. This is useful for system calibration purposes
that would take place under steady load conditions.
v(t) is the instantaneous voltage
VO is the average value
Vh is the rms value of voltage harmonic h
and
␣h
is the phase angle of the voltage harmonic.
∞
i(t) = IO
+
2 ×
Ih × sin(hωt + βh)
∑
(2)
h≠0
where:
i(t) is the instantaneous current
Power Factor Considerations
IO
Ih
is the dc component
is the rms value of current harmonic h
The method used to extract the real power information from the
instantaneous power signal (i.e., by low-pass filtering) is still
valid even when the voltage and current signals are not in phase.
Figure 21 displays the unity power factor condition and a DPF
(Displacement Power Factor) = 0.5, i.e., current signal lagging
and
h is the phase angle of the current harmonic.
REV. B
–10–
AD7755
Using Equations 1 and 2, the real power P can be expressed in
terms of its fundamental real power (P1) and harmonic real
power (PH).
Table I. Gain Selection for Channel 1
Maximum
Differential Signal
G1
G0
Gain
P = P + PH
1
0
0
1
1
0
1
0
1
1
2
8
16
470 mV
235 mV
60 mV
30 mV
where:
P = V1 × I1 cos φ1
1
(3)
φ1 = α1 – β1
Channel V2 (Voltage Channel)
and
The output of the line voltage transducer is connected to the
AD7755 at this analog input. Channel V2 is a fully differential
voltage input. The maximum peak differential signal on Chan-
nel 2 is 660 mV. Figure 23 illustrates the maximum signal
levels that can be connected to the AD7755 Channel 2.
∝
PH
=
Vh × Ih cos φh
∑
h≠1
(4)
φh = αh – βh
As can be seen from Equation 4 above, a harmonic real power
component is generated for every harmonic, provided that har-
monic is present in both the voltage and current waveforms.
The power factor calculation has previously been shown to be
accurate in the case of a pure sinusoid, therefore the harmonic
real power must also correctly account for power factor since it
is made up of a series of pure sinusoids.
V2
+660mV
V2P
V2N
DIFFERENTIAL INPUT
V2
؎660mV MAX PEAK
V
CM
COMMON-MODE
V
CM
؎100mV MAX
Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.
AGND
–660mV
ANALOG INPUTS
Channel V1 (Current Channel)
Figure 23. Maximum Signal Levels, Channel 2
Channel 2 must be driven from a common-mode voltage, i.e.,
the differential voltage signal on the input must be referenced to
a common mode (usually AGND). The analog inputs of the
AD7755 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However best results are
achieved using a common mode equal to AGND.
The voltage output from the current transducer is connected to
the AD7755 here. Channel V1 is a fully differential voltage
input. V1P is the positive input with respect to V1N.
The maximum peak differential signal on Channel 1 should be
less than 470 mV (330 mV rms for a pure sinusoidal signal) for
specified operation. Note that Channel 1 has a programmable
gain amplifier (PGA) with user selectable gain of 1, 2, 8 or 16
(see Table I). These gains facilitate easy transducer interfacing.
Typical Connection Diagrams
Figure 24 shows a typical connection diagram for Channel V1.
A CT (current transformer) is the current transducer selected for
this example. Notice the common-mode voltage for Channel 1
is AGND and is derived by center tapping the burden resistor
to AGND. This provides the complementary analog input sig-
nals for V1P and V1N. The CT turns ratio and burden resistor
Rb are selected to give a peak differential voltage of 470 mV/
Gain at maximum load.
V1
+470mV
V1P
DIFFERENTIAL INPUT
V1
؎470mV MAX PEAK
V1N
V
CM
COMMON-MODE
؎100mV MAX
V
CM
Rf
V1P
V1N
AGND
CT
–470mV
Cf
Cf
؎470mV
GAIN
Rb
Figure 22. Maximum Signal Levels, Channel 1, Gain = 1
AGND
PHASE NEUTRAL
IP
Rf
The diagram in Figure 22 illustrates the maximum signal levels
on V1P and V1N. The maximum differential voltage is 470 mV
divided by the gain selection. The differential voltage signal on
the inputs must be referenced to a common mode, e.g. AGND.
The maximum common mode signal is 100 mV as shown in
Figure 22.
Figure 24. Typical Connection for Channel 1
REV. B
–11–
AD7755
Figure 25 shows two typical connections for Channel V2. The
first option uses a PT (potential transformer) to provide com-
plete isolation from the mains voltage. In the second option the
AD7755 is biased around the neutral wire, and a resistor divider
is used to provide a voltage signal that is proportional to the line
voltage. Adjusting the ratio of Ra, Rb and VR is also a conve-
nient way of carrying out a gain calibration on the meter.
HPF and Offset Effects
Figure 27 shows the effect of offsets on the real power calcula-
tion. As can be seen, an offset on Channel 1 and Channel 2 will
contribute a dc component after multiplication. Since this dc
component is extracted by the LPF and used to generate the
real power information, the offsets will have contributed a con-
stant error to the real power calculation. This problem is easily
avoided by enabling the HPF (i.e., pin AC/DC is set logic high)
in Channel 1. By removing the offset from at least one channel,
no error component can be generated at dc by the multiplica-
tion. Error terms at cos(ωt) are removed by the LPF and the
digital-to-frequency conversion—see Digital-to-Frequency
Conversion section.
V2P
V2N
Rf
CT
Cf
Cf
؎660mV
Rf
AGND
PHASE NEUTRAL
Vcos ωt + VOS × Icos ωt + IOS
=
(
)
(
)
{
}
{
}
Cf
Ra
*
V × I
Rb
*
+ VOS × IOS + VOS × Icos ωt + IOS × Vcos ωt
(
)
(
)
V2P
V2N
؎660mV
2
VR
*
V × I
Rf
+
× cos 2ωt
(
)
2
Cf
*
*
Ra >> Rb + VR
Rb + VR = Rf
PHASE NEUTRAL
Figure 25. Typical Connections for Channel 2
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION
POWER SUPPLY MONITOR
V
؋
I OS
OS
The AD7755 contains an on-chip power supply monitor. The
Analog Supply (AVDD) is continuously monitored by the AD7755.
If the supply is less than 4 V 5%, the AD7755 will be reset.
This is useful to ensure correct device start-up at power-up and
power-down. The power supply monitor has built in hysteresis
and filtering. This gives a high degree of immunity to false trig-
gering due to noisy supplies.
V
؋
I 2
I
؋
V ؋
I OS
V
OS
2
FREQUENCY – RAD/S
0
As can be seen from Figure 26, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about 5%. The
power supply and decoupling for the part should be such that
the ripple at AVDD does not exceed 5 V 5% as specified for
normal operation.
Figure 27. Effect of Channel Offset on the Real Power
Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 28 and 29 show the phase error between
channels with the compensation network activated. The AD7755
is phase compensated up to 1 kHz as shown. This will ensure
correct active harmonic power calculation even at low power
factors.
AV
DD
5V
4V
0V
TIME
INTERNAL
RESET
RESET
ACTIVE
RESET
Figure 26. On-Chip Power Supply Monitor
REV. B
–12–
AD7755
Figure 30 shows the instantaneous real power signal at the output
of the CPF which still contains a significant amount of instanta-
neous power information, i.e., cos (2ωt). This signal is then
passed to the digital-to-frequency converter where it is integrated
(accumulated) over time in order to produce an output fre-
quency. This accumulation of the signal will suppress or average
out any non-dc components in the instantaneous real power
signal. The average value of a sinusoidal signal is zero. Hence
the frequency generated by the AD7755 is proportional to the
average real power. Figure 30 shows the digital-to-frequency
conversion for steady load conditions, i.e., constant voltage and
current.
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05
–0.10
F1
0
100 200 300 400 500 600 700 800 900 1000
DIGITAL-TO-
FREQUENCY
FREQUENCY – Hz
F1
F2
Figure 28. Phase Error Between Channels (0 Hz to 1 kHz)
⌺
V
LPF
TIME
MULTIPLIER
I
DIGITAL-TO-
FREQUENCY
FOUT
0.30
0.25
0.20
0.15
0.10
0.05
0
⌺
CF
LPF TO EXTRACT
REAL POWER
(DC TERM)
V
؋
I 2
TIME
cos(2t)
ATTENUATED BY LPF
2
0
FREQUENCY – RAD/S
INSTANTANEOUS REAL POWER SIGNAL
(FREQUENCY DOMAIN)
–0.05
–0.10
40
45
50
55
60
65
70
Figure 30. Real Power-to-Frequency Conversion
FREQUENCY – Hz
As can be seen in the diagram, the frequency output CF is seen
to vary over time, even under steady load conditions. This fre-
quency variation is primarily due to the cos (2 ωt) component in
the instantaneous real power signal. The output frequency on
CF can be up to 2048 times higher than the frequency on F1
and F2. This higher output frequency is generated by accumu-
lating the instantaneous real power signal over a much shorter
time while converting it to a frequency. This shorter accumula-
tion period means less averaging of the cos (2 ωt) component.
As a consequence, some of this instantaneous power signal passes
through the digital-to-frequency conversion. This will not be a
problem in the application. Where CF is used for calibration
purposes, the frequency should be averaged by the frequency
counter. This will remove any ripple. If CF is being used to
measure energy, e.g., in a microprocessor-based application, the
CF output should also be averaged to calculate power. Because
the outputs F1 and F2 operate at a much lower frequency, a lot
more averaging of the instantaneous real power signal is carried
out. The result is a greatly attenuated sinusoidal content and a
virtually ripple-free frequency output.
Figure 29. Phase Error Between Channels (40 Hz to 70 Hz)
DIGITAL-TO-FREQUENCY CONVERSION
As previously described, the digital output of the low-pass filter
after multiplication contains the real power information. How-
ever since this LPF is not an ideal “brick wall” filter implemen-
tation, the output signal also contains attenuated components
at the line frequency and its harmonics, i.e., cos(hωt) where
h = 1, 2, 3, . . . etc.
The magnitude response of the filter is given by:
1
| H( f )| =
(5)
1 + ( f / 8.9 Hz)
For a line frequency of 50 Hz this would give an attenuation of
the 2ω (100 Hz) component of approximately –22 dBs. The
dominating harmonic will be at twice the line frequency, i.e.,
cos (2ωt) and this is due to the instantaneous power signal.
REV. B
–13–
AD7755
Interfacing the AD7755 to a Microcontroller for Energy
Measurement
Power Measurement Considerations
Calculating and displaying power information will always have
some associated ripple that will depend on the integration period
used in the MCU to determine average power and also the load.
For example, at light loads the output frequency may be 10 Hz.
With an integration period of two seconds, only about 20 pulses
will be counted. The possibility of missing one pulse always exists
as the AD7755 output frequency is running asynchronously to
the MCU timer. This would result in a one-in-twenty or 5%
error in the power measurement.
The easiest way to interface the AD7755 to a microcontroller is
to use the CF high frequency output with the output frequency
scaling set to 2048 × F1, F2. This is done by setting SCF = 0
and S0 = S1 = 1, see Table IV. With full-scale ac signals on the
analog inputs, the output frequency on CF will be approximately
5.5 kHz. Figure 31 illustrates one scheme which could be used
to digitize the output frequency and carry out the necessary
averaging mentioned in the previous section.
CF
TRANSFER FUNCTION
Frequency Outputs F1 and F2
FREQUENCY
RIPPLE
The AD7755 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract real power information. This real power information
is then converted to a frequency. The frequency information is
output on F1 and F2 in the form of active low pulses. The pulse
rate at these outputs is relatively low, e.g., 0.34 Hz maximum
for ac signals with S0 = S1 = 0—see Table III. This means that
the frequency at these outputs is generated from real power
information accumulated over a relatively long period of time.
The result is an output frequency that is proportional to the
average real power. The averaging of the real power signal is
implicit to the digital-to-frequency conversion. The output
frequency or pulse rate is related to the input voltage signals by
the following equation.
AVERAGE
؎10%
FREQUENCY
TIME
MCU
AD7755
COUNTER
CF
UP/DOWN
REVP
*
TIMER
8.06 × V1 × V2 × Gain × F1−4
Freq =
2
VREF
*
REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR
DIRECTION OF ENERGY FLOW IS NEEDED
where:
Figure 31. Interfacing the AD7755 to an MCU
Freq
V1
= Output frequency on F1 and F2 (Hz)
As shown, the frequency output CF is connected to an MCU
counter or port. This will count the number of pulses in a given
integration time which is determined by an MCU internal timer.
The average power is proportional to the average frequency is
given by:
= Differential rms voltage signal on Channel 1 (volts)
= Differential rms voltage signal on Channel 2 (volts)
V2
Gain = 1, 2, 8 or 16, depending on the PGA gain selection
made using logic inputs G0 and G1
VREF = The reference voltage (2.5 V 8%) (volts)
Counter
Average Frequency = Average Real Power =
F1–4
= One of four possible frequencies selected by using the
logic inputs S0 and S1—see Table II.
Timer
The energy consumed during an integration period is given by:
Table II. F1–4 Frequency Selection
Counter
S1
S0
F1–4 (Hz)
XTAL/CLKIN*
Energy = Average Power × Time =
× Time = Counter
Time
0
0
1
1
0
1
0
1
1.7
3.4
6.8
13.6
3.579 MHz/221
3.579 MHz/220
3.579 MHz/219
3.579 MHz/218
For the purpose of calibration, this integration time could be 10
to 20 seconds in order to accumulate enough pulses to ensure
correct averaging of the frequency. In normal operation the inte-
gration time could be reduced to one or two seconds depending,
for example, on the required undate rate of a display. With
shorter integration times on the MCU the amount of energy in
each update may still have some small amount of ripple, even
under steady load conditions. However, over a minute or more
the measured energy will have no ripple.
NOTE
*F1–4 is a binary fraction of the master clock and therefore will vary if the speci-
fied CLKIN frequency is altered.
REV. B
–14–
AD7755
Example 1
the logic inputs S0, S1 and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous real power. As is the case with F1 and F2, the
frequency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this real power information is accumulated over a much shorter
time. Hence less averaging is carried out in the digital-to-
frequency conversion. With much less averaging of the real
power signal, the CF output is much more responsive to power
fluctuations—see Signal Processing Block in Figure 20.
Thus if full-scale differential dc voltages of +470 mV and –660 mV
are applied to V1 and V2 respectively (470 mV is the maximum
differential voltage that can be connected to Channel 1 and
660 mV is the maximum differential voltage that can be con-
nected to Channel 2), the expected output frequency is calcu-
lated as follows:
Gain
F1–4
V1
=
=
=
=
=
1, G0 = G1 = 0
1.7 Hz, S0 = S1 = 0
Table IV. Maximum Output Frequency on CF
+470 mV dc = 0.47 V (rms of dc = dc)
–660 mV dc = 0.66 V (rms of dc = |dc|)
2.5 V (nominal reference value).
V2
SCF S1
S0 F1–4 (Hz)
CF Max for AC Signals (Hz)
VREF
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1.7
1.7
3.4
3.4
6.8
6.8
13.6
13.6
128 × F1, F2 = 43.52
64 × F1, F2 = 21.76
64 × F1, F2 = 43.52
32 × F1, F2 = 21.76
32 × F1, F2 = 43.52
16 × F1, F2 = 21.76
16 × F1, F2 = 43.52
2048 × F1, F2 = 5.57 kHz
NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of 8%.
8.06 × 0.47 × 0.66 × 1 × 1.7
Freq =
= 0.68
2.52
Example 2
In this example, with ac voltages of 470 mV peak applied to
V1 and 660 mV peak applied to V2, the expected output fre-
quency is calculated as follows:
SELECTING A FREQUENCY FOR AN ENERGY METER
APPLICATION
Gain
F1–4
V1
= 1, G0 = G1 = 0
As shown in Table II, the user can select one of four frequen-
cies. This frequency selection determines the maximum fre-
quency on F1 and F2. These outputs are intended to be used to
drive the energy register (electromechanical or other). Since only
four different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant of
100 imp/kWhr with a maximum current of between 10 A and
120 A. Table V shows the output frequency for several maxi-
mum currents (IMAX) with a line voltage of 220 V. In all cases
the meter constant is 100 imp/kWhr.
= 1.7 Hz, S0 = S1 = 0
= rms of 470 mV peak ac = 0.47/√2 volts
= rms of 660 mV peak ac = 0.66/√2 volts
= 2.5 V (nominal reference value).
V2
VREF
NOTE: If the on-chip reference is used, actual
output frequencies may vary from device to device
due to reference tolerance of 8%.
8.06 × 0.47 × 0.66 × 1 × 1.7
Freq =
= 0.34
Table V. F1 and F2 Frequency at 100 imp/kWhr
2 × 2 × 2.52
IMAX
F1 and F2 (Hz)
As can be seen from these two example calculations, the maxi-
mum output frequency for ac inputs is always half of that for dc
input signals. Table III shows a complete listing of all maximum
output frequencies.
12.5 A
25 A
40 A
60 A
80 A
0.076
0.153
0.244
0.367
0.489
0.733
Table III. Maximum Output Frequency on F1 and F2
120 A
Max Frequency
Max Frequency
S1
S0
for DC Inputs (Hz)
for AC Inputs (Hz)
The F1–4 frequencies allow complete coverage of this range of
output frequencies on F1 and F2. When designing an energy
meter the nominal design voltage on Channel 2 (voltage) should
be set to half-scale to allow for calibration of the meter constant.
The current channel should also be no more than half-scale
when the meter sees maximum load. This will allow over current
signals and signals with high crest factors to be accommodated.
Table VI shows the output frequency on F1 and F2 when both
analog inputs are half-scale. The frequencies listed in Table
VI align very well with those listed in Table V for maximum load.
0
0
1
1
0
1
0
1
0.68
1.36
2.72
5.44
0.34
0.68
1.36
2.72
Frequency Output CF
The pulse output CF (Calibration Frequency) is intended for
use during calibration. The output pulse rate on CF can be up
to 2048 times the pulse rate on F1 and F2. The lower the F1–4
frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = 0, S1 = S0 = 1). Table IV shows
how the two frequencies are related, depending on the states of
REV. B
–15–
AD7755
Table VI. F1 and F2 Frequency with Half-Scale AC Inputs
The high frequency CF output is intended to be used for com-
munications and calibration purposes. CF produces a 90 ms-
wide active high pulse (t4) at a frequency proportional to active
power. The CF output frequencies are given in Table IV. As in
the case of F1 and F2, if the period of CF (t5) falls below 180 ms,
the CF pulsewidth is set to half the period. For example, if the CF
frequency is 20 Hz, the CF pulsewidth is 25 ms.
Frequency on F1 and F2–
CH1 and CH2 Half-Scale AC Inputs
S1
S0
F1–4
0
0
1
1
0
1
0
1
1.7
3.4
6.8
13.6
0.085 Hz
0.17 Hz
0.34 Hz
0.68 Hz
NOTE: When the high frequency mode is selected, (i.e., SCF =
0, S1 = S0 = 1) the CF pulsewidth is fixed at 18 µs. Therefore t4
will always be 18 µs, regardless of output frequency on CF.
When selecting a suitable F1–4 frequency for a meter design, the
frequency output at IMAX (maximum load) with a meter con-
stant of 100 imp/kWhr should be compared with Column 4 of
Table VI. The frequency that is closest in Table VI will deter-
mine the best choice of frequency (F1–4). For example, if a meter
with a maximum current of 25 A is being designed, the out-
put frequency on F1 and F2 with a meter constant of 100 imp/
kWhr is 0.153 Hz at 25 A and 220 V (from Table V). Looking
at Table VI, the closest frequency to 0.153 Hz in column four is
0.17 Hz. Therefore F2 (3.4 Hz—see Table II) is selected for this
design.
NO LOAD THRESHOLD
The AD7755 also includes a “no load threshold” and “start-up
current” feature that will eliminate any creep effects in the
meter. The AD7755 is designed to issue a minimum output
frequency on all modes except when SCF = 0 and S1 = S0 = 1.
The no-load detection threshold is disabled on this output mode
to accommodate specialized application of the AD7755. Any
load generating a frequency lower than this minimum frequency
will not cause a pulse to be issued on F1, F2 or CF. The mini-
mum output frequency is given as 0.0014% of the full-scale
output frequency for each of the F1–4 frequency selections—see
Table II. For example, an energy meter with a meter constant
of 100 imp/kWhr on F1, F2 using F2 (3.4 Hz), the maximum
output frequency at F1 or F2 would be 0.0014% of 3.4 Hz or
4.76 × 10–5 Hz. This would be 3.05 × 10–3 Hz at CF (64 × F1 Hz).
In this example the no-load threshold would be equivalent to
1.7 W of load or a start-up current of 8 mA at 220 V. Compar-
ing this value to the IEC1036 specification which states that the
meter must start up with a load equal to or less than 0.4% Ib.
For a 5A (Ib) meter 0.4% of Ib is equivalent to 20 mA.
Frequency Outputs
Figure 1 shows a timing diagram for the various frequency out-
puts. The outputs F1 and F2 are the low frequency outputs that
can be used to directly drive a stepper motor or electromechani-
cal impulse counter. The F1 and F2 outputs provide two alter-
nating low going pulses. The pulsewidth (t1) is set at 275 ms and
the time between the falling edges of F1 and F2 (t3) is approxi-
mately half the period of F1 (t2). If however the period of F1
and F2 falls below 550 ms (1.81 Hz) the pulsewidth of F1 and
F2 is set to half of their period. The maximum output frequen-
cies for F1 and F2 are shown in Table III.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP
(N-24)
24-Lead Shrink Small Outline Package
(RS-24)
0.328 (8.33)
0.318 (8.08)
1.275 (32.30)
1.125 (28.60)
24
13
12
0.280 (7.11)
0.240 (6.10)
24
13
12
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.207)
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.195 (4.95)
0.115 (2.93)
0.150
(3.81)
MIN
1
0.200 (5.05)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.100
(2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.070 (1.77) SEATING
PLANE
PIN 1
0.07 (1.78)
0.066 (1.67)
0.045 (1.15)
0.078 (1.98)
0.068 (1.73)
8°
0°
0.0256
(0.65)
BSC
0.015 (0.38)
0.010 (0.25)
0.008 (0.203)
0.002 (0.050)
SEATING 0.009 (0.229)
0.037 (0.94)
0.022 (0.559)
PLANE
0.005 (0.127)
REV. B
–16–
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