ADP3110AKRZ [ADI]
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable; 双自举，与输出禁用12 V MOSFET驱动器
| 型号： | ADP3110AKRZ |
| 厂家： | 
ADI |
| 描述： | Dual Bootstrapped, 12 V MOSFET Driver with Output Disable |
| 文件： | 总16页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Bootstrapped, 12 V MOSFET
Driver with Output Disable
ADP3110A
FEATURES
GENERAL DESCRIPTION
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross conduction protection circuitry
The ADP3110A is a dual, high voltage MOSFET driver
optimized for driving two N-channel MOSFETs, the two
switches in a nonisolated synchronous buck power converter.
Each driver is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 30 ns transition time. One of the
drivers can be bootstrapped and is designed to handle the high
voltage slew rate associated with floating high-side gate drivers.
The ADP3110A includes overlapping drive protection to
prevent shoot-through current in the external MOSFETs.
OD
for disabling the driver outputs
Meets CPU VR requirement when used with
Analog Devices Flex-Mode™1 controller
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
OD
The
pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3110A is specified over the commercial temperature
range of 0°C to 85°C and is available in an 8-lead SOIC_N or an
8-lead LFCSP_VD package.
1 Flex-Mode™ is protected by U.S. Patent 6683441; other patents pending.
FUNCTIONAL BLOCK DIAGRAM
12V
D1
VCC
4
BST
ADP3110A
1
8
C
BST2
C
LATCH
R1
BST1
2
R
G
IN
DRVH
R2
S
Q
Q1
DELAY
R
BST
TO
INDUCTOR
SW
7
CMP
VCC
6
CMP
1V
DRVL
PGND
CONTROL
LOGIC
5
6
Q2
DELAY
3
OD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADP3110A
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation .........................................................................9
Low-Side Driver ............................................................................9
High-Side Driver...........................................................................9
Overlap Protection Circuit...........................................................9
Application Information................................................................ 10
Supply Capacitor Selection ....................................................... 10
Bootstrap Circuit........................................................................ 10
MOSFET Selection..................................................................... 10
PC Board Layout Considerations............................................. 11
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
3/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3110A
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 25°C, unless otherwise noted.1
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DIGITAL INPUTS (PWM, OD)
Input Voltage High2
Input Voltage Low2
2.0
V
V
μA
mV
0.8
+1
Input Current2
−1
90
Hysteresis2
250
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
BST to SW = 12 V
BST to SW = 12 V
BST to SW = 0 V
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
See Figure 3
2.6
1.4
10
40
30
45
25
20
3.4
1.8
Ω
Ω
kΩ
ns
ns
ns
ns
ns
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
55
45
65
35
35
Propagation Delay Times
t
pdl
OD
See Figure 3
SW to PGND
40
10
55
ns
t
pdh
OD
SW Pull-Down Resistance
LOW-SIDE DRIVER
kΩ
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
2.5
1.4
10
40
20
15
30
20
3.4
1.8
Ω
Ω
VCC = PGND
kΩ
ns
ns
ns
ns
ns
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
See Figure 3
50
30
35
40
35
Propagation Delay Times
t
pdl
OD
pdh
See Figure 3
110
190
ns
t
OD
Timeout Delay
SW = 5 V
SW = PGND
110
95
190
150
ns
ns
SUPPLY
Supply Voltage Range2
Supply Current2
UVLO Voltage2
Hysteresis2
VCC
ISYS
4.15
1.5
13.2
5
3.0
V
mA
V
BST = 12 V, IN = 0 V
VCC rising
2
350
mV
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2 Specifications apply over the full operating temperature range TA = 0°C to 85°C.
Rev. 0 | Page 3 of 16
ADP3110A
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VCC
−0.3 V to +15 V
BST
DC
−0.3 V to VCC + 15 V
−0.3 V to +35 V
−0.3 V to +15 V
<200 ns
BST to SW
SW
Unless otherwise specified, all voltages are referenced to PGND.
DC
−5 V to +15 V
−10 V to +25 V
<200 ns
DRVH
DC
SW − 0.3 V to BST + 0.3 V
SW − 2 V to BST + 0.3 V
<200 ns
DRVL
DC
−0.3 V to VCC + 0.3 V
−2 V to VCC + 0.3 V
−0.3 V to 6.5 V
<200 ns
OD
IN,
θJA, SOIC_N
2-Layer Board
4-Layer Board
123°C/W
90°C/W
Operating Ambient Temperature
Range
0°C to 85°C
Junction Temperature Range
Storage Temperature Range
Lead Temperature
0°C to 150°C
−65°C to +150°C
Soldering (10 sec)
300°C
215°C
260°C
Vapor Phase (60 sec)
Infrared (15 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 16
ADP3110A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST
1
2
3
4
8
7
6
5
DRVH
ADP3110A
IN
SW
OD
PGND
DRVL
TOP VIEW
(Not to Scale)
VCC
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET while it is switching.
2
IN
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.
3
4
5
6
7
OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1 μF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Connect this pin closely to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET source.
It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to
prevent the lower MOSFET from turning on until the voltage is below ~1 V.
VCC
DRVL
PGND
SW
8
DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.
Rev. 0 | Page 5 of 16
ADP3110A
TIMING CHARACTERISTICS
Timing is referenced to the 90% and 10% points, unless otherwise noted.
OD
tpdlOD
tpdhOD
90%
DRVH
OR
DRVL
10%
Figure 3. Output Disable Timing Diagram
IN
tpdlDRVL
tfDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH trDRVH
DRVH-SW
V
V
TH
TH
tpdhDRVL
SW
1V
Figure 4. Timing Diagram
Rev. 0 | Page 6 of 16
ADP3110A
TYPICAL PERFORMANCE CHARACTERISTICS
24
22
20
18
16
14
V
= 12V
LOAD
CC
IN
C
= 3nF
DRVH
DRVL
DRVH
DRVL
0
25
50
75
100
125
5.0
5.0
JUNCTION TEMPERATURE (°C)
Figure 5. DRVH Rise and DRVL Fall Times
CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 8. DRVH and DRVL Fall Times vs. Temperature
40
35
30
25
20
15
10
5
T
V
= 25°C
= 12V
A
CC
DRVH
IN
DRVL
DRVL
DRVH
2.0
2.5
3.0
3.5
4.0
4.5
LOAD CAPACITANCE (nF)
Figure 6. DRVH Fall and DRVL Rise Times
LOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
C
35
30
25
20
15
35
V
T
= 12V
V
C
= 12V
= 3nF
CC
= 25°C
CC
LOAD
A
30
25
20
15
10
5
DRVH
DRVH
DRVL
DRVL
0
25
50
75
100
125
2.0
2.5
3.0
3.5
4.0
4.5
JUNCTION TEMPERATURE (°C)
LOAD CAPACITANCE (nF)
Figure 7. DRVH and DRVL Rise Times vs. Temperature
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
Rev. 0 | Page 7 of 16
ADP3110A
12
11
10
9
60
T
C
= 25°C
A
T
V
C
= 25°C
A
= 3nF
LOAD
= 12V
CC
= 3nF
LOAD
45
30
15
0
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12
0
200
400
600
800
1000
1200
1400
V
(V)
FREQUENCY (kHz)
CC
Figure 11. Supply Current vs. Frequency
Figure 13. DRVL Output Voltage vs. Supply Voltage
13
V
= 12V
CC
C
= 3nF
LOAD
= 250kHz
f
IN
12
11
10
9
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
Figure 12. Supply Current vs. Temperature
Rev. 0 | Page 8 of 16
ADP3110A
THEORY OF OPERATION
pulling the gate down to the voltage at the SW pin. When the
low-side MOSFET, Q2, turns on, the SW pin is pulled to
ground. This allows the bootstrap capacitor to charge up to VCC
again.
The ADP3110A is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
A functional block diagram of the ADP3110A is shown in
Figure 1.
The high-side driver is in phase with the PWM input. When the
driver is disabled, the high-side gate is held low.
OVERLAP PROTECTION CIRCUIT
LOW-SIDE DRIVER
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This
prevents shoot-through currents from flowing through both
power switches and the associated losses that can occur during
their on/off transitions. The overlap protection circuit accom-
plishes this by adaptively controlling the delay from the Q1
turn-off to the Q2 turn-on, and by internally setting the delay
from the Q2 turn-off to the Q1 turn-on.
The low-side driver is designed to drive a ground referenced
N-channel MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and PGND.
When the ADP3110A is enabled, the driver output is 180° out
of phase with the PWM input. When the ADP3110A is
disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
To prevent the overlap of the gate drives during the Q1 turn-off
and the Q2 turn-on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from
The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit that is connected
between the BST and SW pins.
The bootstrap circuit comprises Diode D1 and Bootstrap
Capacitor CBST1. CBST2 and RBST are included to reduce the high-
side gate drive voltage and limit the switch node slew rate
(referred to as a Boot-Snap™ circuit, see the Application
Information section for more details). When the ADP3110A is
starting up, the SW pin is at ground; therefore, the bootstrap
capacitor charges up to VCC through D1. When the PWM input
goes high, the high-side driver begins to turn on the high-side
MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1
turns on, the SW pin rises up to VIN and forces the BST pin to
VIN to 1 V. Once the voltage on the SW pin falls to 1 V, Q2
begins turn-on. If the SW pin has not gone high first, the Q2
turn-on is delayed by a fixed 150 ns. By waiting for the voltage
on the SW pin to reach 1 V or for the fixed delay time, the
overlap protection circuit ensures that Q1 is off before Q2 turns
on, regardless of variations in temperature, supply voltage, input
pulse width, gate charge, and drive current. If SW does not go
below 1 V after 190 ns, DRVL turns on. This can occur if the
current flowing in the output inductor is negative and flows
through the high-side MOSFET body diode.
VIN + VC(BST). This holds Q1 on because enough gate-to-source
voltage is provided. To complete the cycle, Q1 is switched off by
Rev. 0 | Page 9 of 16
ADP3110A
APPLICATION INFORMATION
A small signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by VCC. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3110A, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents that are drawn. Use a 4.7 μF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3110A.
(5)
IF(AVG) = QGATE × fMAX
where fMAX is the maximum switching frequency of the
controller.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST1
)
The peak surge current rating should be calculated by
and a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that can handle twice the
maximum supply voltage. A minimum 50 V rating is recom-
mended. The capacitor values are determined using the
following equations:
VCC −VD
(6)
I F(PEAK )
=
RBST
MOSFET SELECTION
When interfacing the ADP3110A to external MOSFETs, the
designer should consider ways to make a robust design that
minimizes stresses on both the driver and the MOSFETs. These
stresses include exceeding the short time duration voltage
ratings on the driver pins as well as the external MOSFET.
QGATE
(1)
CBST1 + CBST 2 = 10×
VGATE
CBST1
VGATE
(2)
=
CBST1 + CBST 2 VCC −VD
It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.
where:
QGATE is the total gate charge of the high-side MOSFET at VGATE.
V
GATE is the desired gate drive voltage (usually in the range of
5 V to 10 V, 7 V being typical).
High-Side (Control) MOSFETs
VD is the voltage drop across D1.
The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see the ADP3186 or ADP3188 data
sheets for Flex-Mode controller details). This usually implies a
low gate resistance and low input capacitance/charge device.
Yet, a significant source lead inductance can also exist that
depends mainly on the MOSFET package; it is best to contact
the MOSFET vendor for this information.
Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
QGATE
(3)
C BST1 = 10×
VCC −VD
CBST2 can then be found by rearranging Equation 1
QGATE
(4)
C BST 2 = 10×
− CBST1
VGATE
The ADP3110A DRVH output impedance and the input
resistance of the MOSFETs determine the rate of charge delivery
to the internal capacitance of the gate. This determines the
speed at which the MOSFETs turn on and off. However, because
of potentially large currents flowing in the MOSFETs at the on
and off times (this current is usually larger at turn-off due to
ramping up of the output current in the output inductor), the
source lead inductance generates a significant voltage when the
high-side MOSFETs switch off. This creates a significant drain-
source voltage spike across the internal die of the MOSFETs and
can lead to a catastrophic avalanche. The mechanisms involved
in this avalanche condition are referenced in literature from the
MOSFET suppliers.
For example, an NTD60N02 has a total gate charge of about
12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, then
CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic
capacitors should be used.
RBST is used to limit slew rate and minimize ringing at the switch
node. It also provides peak current limiting through D1. An
RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor needs
to handle at least 250 mW due to the peak currents that flow
through it.
Rev. 0 | Page 10 of 16
ADP3110A
to go below one sixth of VCC; then, a delay is added. Due to the
Miller capacitance and internal delays of the low-side MOSFET
gate, ensure the Miller-to-input capacitance ratio is low enough,
and the low-side MOSFET internal delays are not so large as to
allow accidental turn on of the low-side MOSFET when the
high-side MOSFET turns on.
The MOSFET vendor should provide a rating for the maximum
voltage slew rate at drain current around which this can be
designed. When this rating is obtained, determine the expected
maximum current in the MOSFET by
D
MAX
(7)
I
= I (per phase) +
(
V
−V
)
×
MAX
DC
CC
OUT
f
× L
MAX
OUT
Contact Sales for an updated list of recommended low-side
MOSFETs.
where:
D
MAX is determined for the VR controller that is used with the
driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards:
LOUT is the output inductor value.
•
•
•
•
•
Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
Minimize trace inductance between the DRVH and DRVL
outputs and the MOSFET gates.
Connect the PGND pin of the ADP3110A as closely as
possible to the source of the lower MOSFET.
Locate the VCC bypass capacitor as closely as possible to the
VCC and PGND pins.
When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor slows down the dV/dt, but it
also increases the switching losses in the high-side MOSFETs.
The ADP3110A is optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently, yet minimizes dV/dt. However, some high speed
MOSFETs can require this external gate resistor, depending on
the currents being switched in the MOSFET.
Use vias to other layers, when possible, to maximize
thermal conduction away from the IC.
The circuit in Figure 15 shows how four drivers can be
combined with the ADP3181 to form a total power conversion
solution for generating VCC(CORE) for an Intel® CPU that is
VRD 10.x compliant.
Low-Side (Synchronous) MOSFETs
The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to ensure the power delivery from the ADP3110A DRVL does
not exceed the thermal rating of the driver (see the ADP3186,
ADP3188, or ADP3189 data sheets for Flex-Mode controller
details).
Figure 14 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the Layout and Component Placement section in the
ADP3181 data sheet.
C
BST1
The next concern for the low-side MOSFETs is to prevent them
from inadvertently being switched on when the high-side
MOSFET turns on. This occurs due to the drain gate (Miller
capacitance, also specified as Crss capacitance) of the MOSFET.
When the drain of the low-side MOSFET is switched to VCC by
the high-side turning on (at a rate dV/dt), the internal gate of
the low-side MOSFET is pulled up by an amount roughly equal
to VCC × (Crss/Ciss). It is important to make sure this does not put
the MOSFET into conduction.
R
C
BST
BST2
D1
Another consideration is the nonoverlap circuitry of the
ADP3110A that attempts to minimize the nonoverlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin and the conditions of SW prior to switching are
monitored to adequately prevent overlap.
C
VCC
Figure 14. External Component Placement Example
However, during the low-side turn-off to high-side turn-on, the
SW pin does not contain information for determining the
proper switching time, so the state of the DRVL pin is monitored
Rev. 0 | Page 11 of 16
ADP3110A
Figure 15. VRD 10.x Compliant Power Supply Circuit
Rev. 0 | Page 12 of 16
ADP3110A
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
8
PIN 1
INDICATOR
1
PIN 1
INDICATOR
1.89
1.74
1.59
2.75
BSC SQ
TOP
VIEW
1.50
REF
0.50
BSC
4
5
1.60
1.45
1.30
0.70 MAX
0.65TYP
12° MAX
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD}
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Ordering
Quantity
Model
Package Description
Branding
ADP3110AKRZ1
ADP3110AKRZ-RL1
ADP3110AJCPZ-RL1
0°C to 85°C
0°C to 85°C
0°C to 85°C
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N], Reel
8-Lead Lead Frame Chip Scale Package [LFCSP_VD], Reel CP-8-2
R-8
R-8
98
2,500
5,000
L3E
1 Z = Pb-free part.
Rev. 0 | Page 13 of 16
ADP3110A
NOTES
Rev. 0 | Page 14 of 16
ADP3110A
NOTES
Rev. 0 | Page 15 of 16
ADP3110A
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05832-0-3/06(0)
Rev. 0 | Page 16 of 16
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