ADP3110KRZ-RL1 [ADI]
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable; 双自举，与输出禁用12 V MOSFET驱动器
| 型号： | ADP3110KRZ-RL1 |
| 厂家： | 
ADI |
| 描述： | Dual Bootstrapped, 12 V MOSFET Driver with Output Disable |
| 文件： | 总12页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Bootstrapped, 12 V MOSFET
Driver with Output Disable
ADP3110
FEATURES
GENERAL DESCRIPTION
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float
output per Intel® VRM 10 specification
The ADP3110 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two
switches in a nonisolated synchronous buck power converter.
Each of the drivers is capable of driving a 3000 pF load with a
25 ns propagation delay and a 30 ns transition time. One of the
drivers can be bootstrapped and is designed to handle the high
voltage slew rate associated with floating high-side gate drivers.
The ADP3110 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
OD
The
pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3110 is specified over the commercial temperature
range of 0°C to 85°C and is available in an 8-lead SOIC_N
package.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
12V
D1
VCC
4
BST
ADP3110
1
8
C
BST2
C
BST1
2
R
G
IN
DRVH
Q1
DELAY
R
BST
TO
INDUCTOR
SW
7
CMP
VCC
6
CMP
DRVL
PGND
1V
CONTROL
LOGIC
5
6
Q2
DELAY
3
OD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2005 Analog Devices, Inc. All rights reserved.
ADP3110
TABLE OF CONTENTS
Specifications..................................................................................... 3
Overlap Protection Circuit...........................................................7
Application Information...................................................................8
Supply Capacitor Selection ..........................................................8
Bootstrap Circuit...........................................................................8
MOSFET Selection........................................................................8
PC Board Layout Considerations................................................9
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Timing Characteristics..................................................................... 6
Theory of Operation ........................................................................ 7
Low-Side Driver............................................................................ 7
High-Side Driver .......................................................................... 7
REVISION HISTORY
6/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADP3110
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 25°C, unless otherwise noted.
Table 1.1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
PWM INPUT
Input Voltage High2
Input Voltage Low2
Input Current2
Hysteresis2
2.0
V
V
μA
mV
0.8
+1
−1
90
250
OD INPUT
Input Voltage High2
Input Voltage Low2
Input Current 2
Hysteresis2
2.0
V
V
μA
mV
ns
0.8
+1
−1
90
250
20
Propagation Delay Times3
tpdlOD
See Figure 3
See Figure 3
35
55
40
ns
tpdhOD
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
BST to SW = 12 V
BST to SW = 12 V
BST to SW = 0 V
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF,see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
SW to PGND
3.8
1.4
10
40
30
45
25
10
4.4
1.8
Ω
Ω
RDRV + SW
kΩ
ns
ns
ns
ns
kΩ
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
RSW − PGND
55
45
65
35
Propagation Delay Times3
SW Pull Down Resistance
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
3.4
1.4
10
40
20
15
30
190
150
4.0
1.8
Ω
Ω
RDRVL − PGND
VCC = PGND
kΩ
ns
ns
ns
ns
ns
ns
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
SW = 5 V
50
30
35
40
Propagation Delay Times3
Time-out Delay
110
95
SW = PGND
SUPPLY
Supply Voltage Range2
Supply Current2
UVLO Voltage2
Hysteresis2
VCC
ISYS
4.15
1.5
13.2
5
3.0
V
mA
V
BST = 12 V, IN = 0 V
VCC rising
2
350
mV
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2 Specifications apply over the full operating temperature range TA = 0°C to 85°C.
3 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
Rev. 0 | Page 3 of 12
ADP3110
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Unless otherwise specified all other voltages
are referenced to PGND.
Parameter
Rating
VCC
BST
BST to SW
SW
–0.3 V to +15 V
–0.3 V to VCC + 15 V
–0.3 V to +15 V
DC
–5 V to +15 V
–10 V to +25 V
<200 ns
DRVH
DC
SW – 0.3 V to BST + 0.3 V
SW – 2 V to BST + 0.3 V
<200 ns
DRVL
DC
–0.3 V to VCC + 0.3 V
–2 V to VCC + 0.3 V
–0.3 V to 6.5 V
<200 ns
OD
IN,
θJA, SOIC_N
2-Layer Board
4-Layer Board
123°C/W
90°C/W
Operating Ambient Temperature
Range
0°C to 85°C
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
Soldering (10 sec)
0°C to 150°C
–65°C to +150°C
300°C
215°C
260°C
Vapor Phase (60 sec)
Infrared (15 sec)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 12
ADP3110
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST
IN
1
2
3
4
8
7
6
5
DRVH
SW
ADP3110
OD
PGND
DRVL
TOP VIEW
(Not to Scale)
VCC
Figure 2. 8-Lead SOIC_N Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
2
IN
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.
3
4
5
6
7
OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1 μF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFET’s
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage
to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
VCC
DRVL
PGND
SW
8
DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.
Rev. 0 | Page 5 of 12
ADP3110
TIMING CHARACTERISTICS
OD
tpdl
OD
tpdh
OD
90%
DRVH
OR
DRVL
10%
Figure 3. Output Disable Timing Diagram
IN
tf
tpdl
DRVL
DRVL
tpdl
DRVH
tr
DRVL
DRVL
tf
DRVH
tpdh
tr
DRVH
DRVH
DRVH-SW
V
V
TH
TH
tpdh
DRVL
SW
1V
Figure 4. Timing Diagram
(Timing is Referenced to the 90% and 10% Points Unless Otherwise Noted)
Rev. 0 | Page 6 of 12
ADP3110
THEORY OF OPERATION
on. To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side
MOSFET, Q2, turns on, the SW pin is pulled to ground. This
allows the bootstrap capacitor to charge up to VCC again.
The ADP3110 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
A more detailed description of the ADP3110 and its features
follows. Refer to Figure 1.
OVERLAP PROTECTION CIRCUIT
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This
prevents shoot-through currents from flowing through both
power switches, and the associated losses that can occur during
their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn off to the Q2 turn on, and by internally setting the
delay from the Q2 turn off to the Q1 turn on.
LOW-SIDE DRIVER
The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and PGND.
When the ADP3110 is enabled, the driver’s output is
180 degrees out of phase with the PWM input. When the
ADP3110 is disabled, the low-side gate is held low.
HIGH-SIDE DRIVER
To prevent the overlap of the gate drives during the Q1 turn off
and the Q2 turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from
The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST1. CBST2 and RBST are included to reduce the high-
side gate drive voltage and limit the switch node slew rate
(referred to as a Boot-Snap™ circuit, see the Application
Information section for more details). When the ADP3110 is
starting up the SW pin is at ground; therefore the bootstrap
capacitor charges up to VCC through D1. When the PWM
input goes high, the high-side driver begins to turn on the high-
side MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As
Q1 turns on, the SW pin rises up to VIN, forcing the BST pin to
VIN to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2
begins turn on. If the SW pin had not gone high first, then the
Q2 turn on is delayed by a fixed 150 ns. By waiting for the
voltage on the SW pin to reach 1 V or for the fixed delay time,
the overlap protection circuit ensures that Q1 is off before Q2
turns on, regardless of variations in temperature, supply voltage,
input pulse width, gate charge, and drive current. If SW does
not go below 1 V after 190 ns, DRVL turns on. This can occur if
the current flowing in the output inductor is negative and is
flowing through the high-side MOSFET body diode.
V
IN + VC(BST), which is enough gate-to-source voltage to hold Q1
Rev. 0 | Page 7 of 12
ADP3110
APPLICATION INFORMATION
A small signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by VCC. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3110, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 μF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3110.
IF(AVG) = QGATE × fMAX
(5)
where fMAX is the maximum switching frequency of the
controller.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST1) and
a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that is able to handle twice
the maximum supply voltage. A minimum 50 V rating is
recommended. The capacitor values are determined using the
following equations:
The peak surge current rating should be calculated by
VCC −VD
(6)
IF(PEAK )
=
RBST
MOSFET SELECTION
When interfacing the ADP3110 to external MOSFETs, the
QGATE
designer should be aware of a few considerations. These help to
make a more robust design that minimizes stresses on both the
driver and MOSFETs. These stresses include exceeding the
short-time duration voltage ratings on the driver pins as well as
the external MOSFET.
C
BST1 + CBST2 =10×
(1)
(2)
VGATE
VGATE
BST1 +CBST2 VCC −VD
CBST1
=
C
where:
It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.
QGATE is the total gate charge of the high-side MOSFET at VGATE
VGATE is the desired gate drive voltage (usually in the range of
5 V to 10 V, 7 V being typical).
.
VD is the voltage drop across D1.
High-Side (Control) MOSFETs
Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see any ADI Flex-Mode™ controller
data sheet for more details on MOSFET losses). This usually
implies a low gate resistance and low input capacitance/charge
device. Yet, there is also a significant source lead inductance
that can exist (this depends mainly on the MOSFET package; it
is best to contact the MOSFET vendor for this information).
QGATE
VCC −VD
C
BST1= 10×
(3)
CBST2 can then be found by rearranging Equation 1
QGATE
VGATE
C
BST2 =10×
−CBST1
(4)
The ADP3110 DRVH output impedance and the external
MOSFETs’ input resistance determine the rate of charge
delivery to the MOSFETs’ gate capacitance which, in turn,
determines the switching times of the MOSFETs. A large
voltage spike can be generated across the source lead inductance
when the high-side MOSFETs switch off, due to large currents
flowing in the MOSFETs during switching (usually larger at
turn off due to ramping of the current in the output inductor).
This voltage spike occurs across the internal die of the
MOSFETs and can lead to catastrophic avalanche. The
mechanisms involved in this avalanche condition can be
referenced in literature from the MOSFET suppliers.
For example, an NTD60N02 has a total gate charge of about
12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, we find
CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic
capacitors should be used.
R
BST is used for slew rate limiting to minimize the ringing at the
switch node. It also provides peak current limiting through D1.
An RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor
needs to be able to handle at least 250 mW due to the peak
currents that flow through it.
Rev. 0 | Page 8 of 12
ADP3110
ratio is low enough and the low-side MOSFET internal delays
are not large enough to allow accidental turn on of the low-side
MOSFET when the high-side MOSFET turns on.
The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed
around. The next step is to determine the expected maximum
current in the MOSFET. This can be done by
Contact Sales for an updated list of recommended low-side
MOSFETs.
DMAX
(
VCC −VOUT ×
)
(7)
I MAX = IDC (per phase) +
f MAX × LOUT
PC BOARD LAYOUT CONSIDERATIONS
DMAX is determined for the VR controller being used with the
driver. Note this current gets divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin). LOUT is the output
inductor value.
Use the following general guidelines when designing printed
circuit boards.
1. Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
2. Minimize trace inductance between the DRVH and DRVL
outputs and the MOSFET gates.
3. Connect the PGND pin of the ADP3110 as closely as
possible to the source of the lower MOSFET.
4. The VCC bypass capacitor should be located as closely as
possible to the VCC and PGND pins.
When producing the design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFET. This resistor slows down the dV/dt, but it
also increases the switching losses in the high-side MOSFET.
The ADP3110 is optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently yet minimize dV/dt. However, some high speed
MOSFETs may require this external gate resistor, depending on
the currents being switched in the MOSFET.
5. Use vias to other layers when possible to maximize thermal
conduction away from the IC.
The circuit in Figure 6 shows how four drivers can be combined
with the ADP3181 to form a total power conversion solution for
generating VCC(CORE) for an Intel CPU that is VRD 10.x
compliant.
Figure 5 shows an example of the typical land patterns based on
the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the Layout and Component Placement section in the
ADP3181 data sheet.
Low-Side (Synchronous) MOSFETs
The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure the power delivery from the ADP3110’s DRVL
does not exceed the thermal rating of the driver.
C
BST1
The next concern for the low-side MOSFETs is to prevent them
from inadvertently being switched on when the high-side
MOSFET turns on. This occurs due to the drain-gate (Miller,
also specified as Crss) capacitance of the MOSFET. When the
drain of the low-side MOSFET is switched to VCC by the high-
side turning on (at a rate dV/dt), the internal gate of the low-
side MOSFET is pulled up by an amount roughly equal to
VCC × (Crss/Ciss). It is important to make sure this does not put
the MOSFET into conduction.
R
C
BST
BST2
D1
Another consideration is the nonoverlap circuitry of the
ADP3110, which attempts to minimize the nonoverlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin and the conditions of SW prior to switching are
monitored to adequately prevent overlap.
C
VCC
However, during the low-side turn off to high-side turn on, the
SW pin does not contain information for determining the
proper switching time, so the state of the DRVL pin is monitored
to go below one sixth of VCC and then a delay is added. Due to
the Miller capacitance and internal delays of the low-side
MOSFET gate, one must ensure the Miller-to-input capacitance
Figure 5. External Component Placement Example
Rev. 0 | Page 9 of 12
ADP3110
Figure 6. VRD 10.x Compliant Power Supply Circuit
Rev. 0 | Page 10 of 12
ADP3110
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 7. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Quantity per Reel
ADP3110KRZ1
ADP3110KRZ-RL1
1 Z = Pb-free part.
0°C to 85°C
0°C to 85°C
Standard Small Outline Package [SOIC_N]
Standard Small Outline Package [SOIC_N]
R-8
R-8
N/A
2500
Rev. 0 | Page 11 of 12
ADP3110
NOTES
©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05514–0–6/05(0)
Rev. 0 | Page 12 of 12
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