ADP3118 [ONSEMI]
Dual Bootstrapped 12 V MOSFET Driver with Output Disable; 双自举12 V MOSFET驱动器输出禁用
| 型号： | ADP3118 |
| 厂家： | 
ONSEMI |
| 描述： | Dual Bootstrapped 12 V MOSFET Driver with Output Disable |
| 文件： | 总14页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Bootstrapped 12 V
MOSFET Driver with Output Disable
ADP3118
FEATURES
GENERAL DESCRIPTION
Optimized for low gate charge MOSFETs
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs to float
output per Intel VRM 10
The ADP3118 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 25 ns prop-
agation delay and a 25 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage slew
rate associated with floating high-side gate drivers. The ADP3118
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs.
Meets CPU VR requirement when used with
Analog Devices, Inc. Flex-Mode1 controller
The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
The ADP3118 is specified over the commercial temperature
range of 0°C to 85°C and is available in 8-lead SOIC and 8-lead
LFCSP packages.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
V
12V
IN
D1
VCC
4
BST
ADP3118
1
8
C
BST2
C
BST1
2
R
G
IN
DRVH
Q1
DELAY
R
BST
TO
INDUCTOR
SW
7
CMP
VCC
6
CMP
DRVL
PGND
1V
CONTROL
LOGIC
5
6
Q2
DELAY
3
OD
Figure 1.
1Flex-Mode™ is protected by U.S. Patent 6683441.
©2008 SCILLC. All rights reserved.
January 2008 – Rev. 2
Publication Order Number:
ADP3118/D
ADP3118
TABLE OF CONTENTS
Features...............................................................................................1
Low-Side Driver............................................................................9
High-Side Driver...........................................................................9
Overlap Protection Circuit ..........................................................9
Application Information ................................................................10
Supply Capacitor Selection........................................................10
Bootstrap Circuit ........................................................................10
MOSFET Selection .....................................................................10
High-Side (Control) MOSFETs ................................................10
Low-Side (Synchronous) MOSFETs.........................................11
PC Board Layout Considerations .............................................11
Outline Dimensions........................................................................13
Ordering Guide...........................................................................13
Applications .......................................................................................1
General Description..........................................................................1
Simplified Functional Block Diagram............................................1
Revision History................................................................................2
Specifications .....................................................................................3
Absolute Maximum Ratings ............................................................4
ESD Caution ..................................................................................4
Pin Configuration and Function Descriptions .............................5
Timing Characteristics .....................................................................6
Typical Performance Characteristics..............................................7
Theory of Operation.........................................................................9
REVISION HISTORY
01/08 - Rev 2: Conversion to ON Semiconductor
9/07—Rev. 0 to Rev. A
Added LFCSP...................................................................... Universal
Updated Outline Dimensions........................................................13
Changes to Ordering Guide...........................................................13
4/05—Revision 0: Initial Version
Rev. 2 | Page 2 of 14 | www.onsemi.com
ADP3118
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
PWM INPUT
Input Voltage High
Input Voltage Low
Input Current
Hysteresis
2.0
V
V
μA
mV
0.8
+1
−1
90
250
INPUT
OD
Input Voltage High
Input Voltage Low
Input Current
Hysteresis
Propagation Delay Times2
2.0
V
V
μA
mV
ns
0.8
+1
−1
90
250
20
tpdlOD
See Figure 3
See Figure 3
35
55
tpdhOD
40
ns
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
BST − SW = 12 V
BST − SW = 12 V
BST − SW = 0 V
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
BST − SW = 12 V, CLOAD = 3 nF, see Figure 4
SW to PGND
2.2
1.0
10
25
20
25
25
10
3.5
2.5
Ω
Ω
kΩ
ns
ns
ns
ns
kΩ
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
40
30
40
35
Propagation Delay Times2
SW Pull-Down Resistance
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
2.0
1.0
10
20
16
12
30
190
150
3.2
2.5
Ω
Ω
VCC = PGND
kΩ
ns
ns
ns
ns
ns
ns
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
SW = 5 V
35
30
35
45
Propagation Delay Times2
Timeout Delay
110
95
SW = PGND
SUPPLY
Supply Voltage Range
Supply Current
UVLO Voltage
Hysteresis
VCC
ISYS
4.15
1.5
13.2
5
3.0
V
mA
V
BST = 12 V, IN = 0 V
VCC rising
2
350
mV
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2 For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low.
Rev. 2 | Page 3 of 14 | www.onsemi.com
ADP3118
ABSOLUTE MAXIMUM RATINGS
Unless otherwise specified, all voltages are referenced to PGND.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
VCC
BST
BST to SW
SW
−0.3 V to +15 V
−0.3 V to VCC + 15 V
−0.3 V to +15 V
ESD CAUTION
DC
−5 V to +15 V
−10 V to +25 V
<200 ns
DRVH
DC
<200 ns
DRVL
DC
SW − 0.3 V to BST + 0.3 V
SW − 2 V to BST + 0.3 V
−0.3 V to VCC + 0.3 V
−2 V to VCC + 0.3 V
−0.3 V to 6.5 V
<200 ns
IN,
OD
θJA, SOIC
2-Layer Board
123°C/W
90°C/W
4-Layer Board
θJA, LFCSP_VD1
4-Layer Board
50°C/W
Operating Ambient Temperature
Range
0°C to 85°C
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
0°C to 150°C
−65°C to +150°C
300°C
215°C
260°C
1 For LFCSP_VD, θJA is measured per JEDEC STD with the exposed pad
soldered to PCB.
Rev. 2 | Page 4 of 14 | www.onsemi.com
ADP3118
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BST
IN
1
2
3
4
8
7
6
5
DRVH
SW
ADP3118
OD
PGND
DRVL
TOP VIEW
(Not to Scale)
VCC
Figure 2. 8-Lead SOIC Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
2
IN
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this
pin low turns on the low-side driver; pulling it high turns on the high-side driver.
3
4
5
6
7
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with an ~1 μF ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating return
for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the
lower MOSFET until the voltage is below ~1 V.
OD
VCC
DRVL
PGND
SW
8
DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.
Rev. 2 | Page 5 of 14 | www.onsemi.com
ADP3118
TIMING CHARACTERISTICS
OD
tpdl
OD
tpdh
OD
90%
DRVH
OR
DRVL
10%
Figure 3. Output Disable Timing Diagram
IN
t
f
t
DRVL
pdlDRVL
t
t
pdlDRVH
rDRVL
DRVL
t
f
DRVH
t
t
rDRVH
pdhDRVH
DRVH – SW
V
V
TH
TH
t
pdhDRVL
SW
1V
Figure 4. Timing Diagram—Timing Is Referenced to the 90% and 10% Points, Unless Otherwise Noted
Rev. 2 | Page 6 of 14 | www.onsemi.com
ADP3118
TYPICAL PERFORMANCE CHARACTERISTICS
24
22
20
18
16
14
V
C
= 12V
LOAD
CC
IN
= 3nF
DRVH
DRVL
DRVH
DRVL
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
Figure 5. DRVH Rise and DRVL Fall Times
LOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
Figure 8. DRVH and DRVL Fall Times vs. Temperature
C
40
35
30
25
20
15
10
5
T
V
= 25°C
A
= 12V
CC
DRVH
IN
DRVL
DRVL
DRVH
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOAD CAPACITANCE (nF)
Figure 6. DRVH Fall and DRVL Rise Times
Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance
CLOAD = 6 nF for DRVL, CLOAD = 2 nF for DRVH
35
30
25
20
15
35
V
T
= 12V
V
C
= 12V
LOAD
CC
A
CC
= 25°C
= 3nF
30
25
20
15
10
5
DRVH
DRVH
DRVL
DRVL
0
25
50
75
100
125
2.0
2.5
3.0
3.5
4.0
4.5
5.0
JUNCTION TEMPERATURE (°C)
LOAD CAPACITANCE (nF)
Figure 7. DRVH and DRVL Rise Times vs. Temperature
Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance
Rev. 2 | Page 7 of 14 | www.onsemi.com
ADP3118
12
11
10
9
60
T
C
= 25°C
A
T
V
C
= 25°C
A
= 3nF
LOAD
= 12V
CC
= 3nF
LOAD
45
30
15
0
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9
10 11 12
0
200
400
600
800
1000
1200
1400
V
VOLTAGE (V)
FREQUENCY (kHz)
CC
Figure 11. Supply Current vs. Frequency
Figure 13. DRVL Output Voltage vs. Supply Voltage
13
12
11
10
9
V
C
= 12V
CC
= 3nF
= 250kHz
LOAD
f
IN
0
25
50
75
100
125
JUNCTION TEMPERATURE (°C)
Figure 12. Supply Current vs. Temperature
Rev. 2 | Page 8 of 14 | www.onsemi.com
ADP3118
THEORY OF OPERATION
The ADP3118 is a dual-MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side MOSFET,
Q2, turns on, the SW pin is pulled to ground. This allows the
bootstrap capacitor to charge up to VCC again.
The high-side driver’s output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.
A more detailed description of the ADP3118 and its features
follows (see Figure 1 for a block diagram).
OVERLAP PROTECTION CIRCUIT
LOW-SIDE DRIVER
The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn-off to the Q2 turn-on, and by internally setting the
delay from the Q2 turn-off to the Q1 turn-on.
The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is inter-
nally connected to the VCC supply and PGND.
When the driver is enabled, the driver’s output is 180° out of
phase with the PWM input. When the ADP3118 is disabled,
the low-side gate is held low.
HIGH-SIDE DRIVER
To prevent the overlap of the gate drives during the Q1 turn-off
and the Q2 turn-on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on,
the overlap protection circuit makes sure that SW has first
gone high and then waits for the voltage at the SW pin to fall
from VIN to 1 V. Once the voltage on the SW pin falls to 1 V,
Q2 begins turn-on. If the SW pin has not gone high first, the
Q2 turn-on is delayed by a fixed 150 ns. By waiting for the
voltage on the SW pin to reach 1 V or for the fixed delay time,
the overlap protection circuit ensures that Q1 is off before Q2
turns on, regardless of variations in temperature, supply voltage,
input pulse width, gate charge, and drive current. If SW does
not go below 1 V after 190 ns, DRVL turns on. This can occur
if the current flowing in the output inductor is negative and is
flowing through the high-side MOSFET body diode.
The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST1. CBST2 and RBST are included to reduce the
high-side gate drive voltage and to limit the switch node slew
rate (referred to as a Boot-Snap circuit, see the Application
Information section for more details). When the ADP3118 is
starting up, the SW pin is at ground, so the bootstrap capacitor
charges up to VCC through D1. When the PWM input goes
high, the high-side driver begins to turn on the high-side
MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As Q1
turns on, the SW pin rises up to VIN, forcing the BST pin to VIN
+ VC (BST), which is enough gate-to-source voltage to hold Q1 on.
Rev. 2 | Page 9 of 14 | www.onsemi.com
ADP3118
APPLICATION INFORMATION
A small-signal diode can be used for the bootstrap diode due
to the ample gate drive voltage supplied by VCC. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can
be estimated by
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3118, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 μF, low ESR capa-
citor. Multilayer ceramic chip capacitors (MLCC) provide the
best combination of low ESR and small size. Keep the ceramic
capacitor as close as possible to the ADP3118.
IF(AVG) = QGATE × fMAX
(3)
where fMAX is the maximum switching frequency of the controller.
The peak surge current rating should be calculated using
VCC −VD
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST
)
IF(PEAK)
=
(4)
and a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that can handle twice the
maximum supply voltage. A minimum 50 V rating is recom-
mended. The capacitor values are determined by:
QGATE
RBST
MOSFET SELECTION
When interfacing the ADP3118 to external MOSFETs, there
are a few considerations that the designer should be aware of.
These help to make a more robust design that minimizes
stresses on both the driver and the MOSFETs. These stresses
include exceeding the short-time duration voltage ratings on
the driver pins as well as the external MOSFET.
C
BST1 + CBST2 =10 ×
(1)
VGATE
VGATE
BST1 +CBST2 VCC −VD
CBST1
=
(2)
C
It is also highly recommended to use a Boot-Snap circuit to
where:
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.
Q
GATE is the total gate charge of the high-side MOSFET at VGATE
.
VGATE is the desired gate drive voltage (usually in the range of 5 V
to 10 V, 7 V being typical).
VD is the voltage drop across D1.
HIGH-SIDE (CONTROL) MOSFETS
Rearranging Equation 1 and Equation 2 to solve for CBST1 yields
The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see the ADP3186 or ADP3188 data
sheet for controller details). This usually implies a low gate resis-
tance and low input capacitance/charge device. Yet, a significant
source lead inductance can also exist. This depends mainly on
the MOSFET package; it is best to contact the MOSFET vendor
for this information.
QGATE
C BST1 =10 ×
VCC − VD
CBST2 can then be found by rearranging Equation 1.
QGATE
VGATE
CBST2 =10 ×
− CBST1
The ADP3118 DRVH output impedance and the input resistance
of the MOSFETs determine the rate of charge delivery to the
gate’s internal capacitance. This determines the speed at which
the MOSFETs turn on and off. However, due to potentially large
currents flowing in the MOSFETs at the on and off times (this
current is usually larger at turn off due to ramping up of the out-
put current in the output inductor), the source lead inductance
generates a significant voltage when the high-side MOSFETs
switch off. This creates a significant drain-source voltage spike
across the internal die of the MOSFETs and can lead to a cata-
strophic avalanche. The mechanisms involved in this avalanche
condition can be referenced in literature from the MOSFET
suppliers.
For example, an NTD60N02 has a total gate charge of about
12 nC at VGATE = 7 V. Using VCC = 12 V and VD = 1 V, one finds
CBST1 = 12 nF and CBST2 = 6.8 nF. Good quality ceramic capacitors
should be used.
RBST is used for slew-rate limiting to minimize the ringing at the
switch node. It also provides peak current limiting through D1.
An RBST value of 1.5 Ω to 2.2 Ω is a good choice. The resistor
needs to be able to handle at least 250 mW due to the peak
currents that flow through it.
Rev. 2 | Page 10 of 14 | www.onsemi.com
ADP3118
The MOSFET vendor should provide a maximum voltage
slew rate at a drain current rating such that this can be designed
around. Once the designer has this specification, determine the
maximum current you expect to see in the MOSFET. This can
be done with the following equation:
the proper switching time, so the state of the DRVL pin is
monitored to go below one sixth of VCC. A delay is then added.
Due to the Miller capacitance and internal delays of the low-
side MOSFET gate, one must ensure that the Miller-to-input
capacitance ratio is low enough and that the low-side MOSFET
internal delays are not so large as to allow accidental turn on of
the low-side when the high-side turns on.
DMAX
IMAX = IDC (per phase) +
(VCC −VOUT
)
×
(5)
fMAX ×LOUT
Contact sales for an updated list of recommended low-side
MOSFETs.
where:
MAX is determined for the VR controller being used with the
driver. This current is divided as equally as possible between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).
D
PC BOARD LAYOUT CONSIDERATIONS
Use the following general guidelines when designing printed
circuit boards.
LOUT is the output inductor value.
•
•
•
•
•
Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
When producing a design, there is no exact method for calcu-
lating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured
to determine if it is safe. If it appears that the dV/dt is too fast,
an optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor slows down the dV/dt, but it
increases the switching losses in the high-side MOSFETs. The
ADP3118 has been optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending
on the currents being switched in the MOSFET.
Minimize trace inductance between DRVH and DRVL
outputs and MOSFET gates.
Connect the PGND pin of the ADP3118 as closely as
possible to the source of the lower MOSFET.
Locate the VCC bypass capacitor as close as possible to the
VCC and PGND pins.
Use vias to other layers when possible to maximize thermal
conduction away from the IC.
The circuit in Figure 15 shows how four drivers can be com-
bined with the ADP3188 to form a total power conversion
solution for generating VCC (CORE) for an Intel® CPU that is VRD
10.x-compliant.
LOW-SIDE (SYNCHRONOUS) MOSFETS
The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies
a large input gate capacitance and gate charge. The first concern
is to make sure the power delivery from the ADP3118’s DRVL
does not exceed the thermal rating of the driver (see the ADP3186
or ADP3188 data sheet for controller details).
Figure 14 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the Layout and Component Placement section of the
ADP3188 data sheet.
The next concern for the low-side MOSFETs is based on
preventing them from inadvertently being switched on when
the high-side MOSFET turns on. This occurs due to the drain-
gate (Miller, also specified as Crss) capacitance of the MOSFET.
When the drain of the low-side MOSFET is switched to VCC by
the high-side turning on (at a rate of dV/dt), the internal gate of
the low-side MOSFET is pulled up by an amount roughly equal
to VCC × (Crss/Ciss). It is important to make sure this does not put
the MOSFET into conduction.
C
BST1
R
C
BST
BST2
D1
Another consideration is the nonoverlap circuitry of the ADP3118,
which attempts to minimize the nonoverlap period. During the
state of the high-side turning off to low-side turning on, the SW
pin is monitored (as well as the conditions of SW prior to
switching) to adequately prevent overlap.
C
VCC
However, during the low-side turn off to high-side turn on,
the SW pin does not contain information for determining
Figure 14. External Component Placement Example
Rev. 2 | Page 11 of 14 | www.onsemi.com
ADP3118
Figure 15. VRD 10-Compliant Power Supply Circuit
Rev. 2 | Page 12 of 14 | www.onsemi.com
ADP3118
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (inches)
3.25
3.00 SQ
2.75
0.60 MAX
5
0.50
BSC
0.60 MAX
8
2.95
2.75 SQ
2.55
1.60
1.45
1.30
EXPOSED
PAD
TOP
VIEW
PIN 1
INDICATOR
(BOTTOM VIEW)
4
1
PIN 1
INDICATOR
0.50
0.40
0.30
1.89
1.74
1.59
12° MAX
0.70 MAX
0.65TYP
0.90 MAX
0.85 NOM
0.05 MAX
0.01 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
Figure 17. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
(CP-8-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Ordering
Quantity
Model
Package Description
ADP3118JRZ1
ADP3118JRZ-RL1
ADP3118JCPZ-RL1
0°C to 85°C
0°C to 85°C
0°C to 85°C
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Standard Small Outline Package (SOIC_N)
8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
R-8
R-8
CP-8-2
98
2,500
2,500
1 Z = RoHS Compliant Part.
Rev. 2 | Page 13 of 14 | www.onsemi.com
ADP3118
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
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harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Toll Free USA/Canada
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Email: orderlit@onsemi.com
For additional information, please contact your local
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Rev. 2 | Page 14 of 14 | www.onsemi.com
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