ADP3110AKRZ-RL [ROCHESTER]
HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, SOIC-8;
| 型号： | ADP3110AKRZ-RL |
| 厂家： | 
Rochester Electronics |
| 描述： | HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, SOIC-8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总9页 (文件大小：810K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADP3110A
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3110A is a single Phase 12 V MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 30 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
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MARKING
DIAGRAMS
8
3110A
ALYW
G
SO−8
D SUFFIX
CASE 751
8
1
1
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
1
8
DFN8
MN SUFFIX
CASE 506BJ
L3E
ALYWG
G
1
A
L
= Assembly Location
= Wafer Lot
Y
= Year
Features
W = Work Week
G
• All−In−One Synchronous Buck Driver
• Bootstrapped High−Side Drive
• One PWM Signal Generates Both Drives
• Anticross Conduction Protection Circuitry
• OD for Disabling the Driver Outputs Meets CPU VR Requirement
when Used with Patented FlexModet Controller
• These are Pb−Free Devices
= Pb−Free Package
PIN CONNECTIONS
1
8
BST
IN
DRVH
SWN
OD
PGND
DRVL
V
CC
Applications
1
8
• Multiphase Desktop CPU Supplies
• Single−Supply Synchronous Buck Converters
BST
IN
DRVH
SWN
OD
PGND
V
CC
DRVL
(Top View)
ORDERING INFORMATION
†
Device
Package
Shipping
98 Units / Rail
ADP3110AKRZ
SO−8
(Pb−Free)
ADP3110AKRZ−RL
SO−8
(Pb−Free)
2500 Tape & Reel
5000 Tape & Reel
ADP3110AKCPZ−RL DFN8
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
August, 2008 − Rev. 4
ADP3110A/D
ADP3110A
3
2
OD
IN
V
TSD
CC
BST
1
8
UVLO
DRVH
FALLING
EDGE
DELAY
MONITOR
MONITOR
7
SWN
FALLING
EDGE
DELAY
START
STOP
NON−OVERLAP
4
V
CC
MIN DRVL
TIMERS
OFF TIMER
5
6
DRVL
PGND
Figure 1. Block Diagram
PIN DESCRIPTION
SO−8
DFN8
Symbol
Description
1
1
BST
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the ADP3110A.
2
3
4
5
6
7
8
2
3
4
5
6
7
8
IN
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
OD
V
CC
DRVL
PGND
SWN
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
DRVH
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2
ADP3110A
MAXIMUM RATINGS
Rating
Value
0 to 85
0 to 150
Unit
°C
Operating Ambient Temperature, T
A
Operating Junction Temperature, T (Note 1)
°C
J
Package Thermal Resistance: SO−8
Junction−to−Case, R
45
123
°C/W
°C/W
q
JC
Junction−to−Ambient, R
(2−Layer Board)
q
JA
Package Thermal Resistance: DFN8 (Note 2)
Junction−to−Case, R (From die to exposed pad)
q
JC
7.5
55
°C/W
°C/W
Junction−to−Ambient, R
q
JA
Storage Temperature Range, T
−65 to 150
260 peak
1
°C
°C
−
S
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
JEDEC Moisture Sensitivity Level
Pb−Free (Note 3)
SO−8 (260 peak profile)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Internally limited by thermal shutdown, 150°C min.
2
2. 2 layer board, 1 in Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
Pin Name
Main Supply Voltage Input
Ground
V
V
MIN
MAX
V
CC
15 V
0 V
−0.3 V
0 V
PGND
BST
Bootstrap Supply Voltage Input
35 V wrt/PGND
40 V < 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
SW
Switching Node
(Bootstrap Supply Return)
35 V
40 V < 50 ns
−5.0 V
−10 V < 200 ns
DRVH
DRVL
High−Side Driver Output
BST + 0.3 V
−0.3 V wrt/SW
− 2.0 V < 200 ns wrt/SW
Low−Side Driver Output
V
CC
+ 0.3 V
−0.3 V DC
−5.0 V < 200 ns
IN
DRVH and DRVL Control Input
Output Disable
6.5 V
6.5 V
−0.3 V
−0.3 V
OD
NOTE: All voltages are with respect to PGND except where noted.
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3
ADP3110A
ELECTRICAL CHARACTERISTICS (Note 4) (V = 12 V, T = 0°C to +85°C, T = 0°C to +125°C unless otherwise noted.)
CC
A
J
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
Supply
Supply Voltage Range
Supply Current
V
−
4.6
−
13.2
5.0
V
CC
I
BST = 12 V, IN = 0 V
−
0.7
mA
SYS
OD Input
Input Voltage High
Input Voltage Low
Hysteresis
V
−
2.0
−
−
−
−
0.8
−
V
V
OD_HI
V
−
OD_LO
−
−
400
−
mV
mA
Input Current
No internal pullup or pulldown resistors
−1.0
+1.0
PWM Input
Input Voltage High
Input Voltage Low
Hysteresis
V
−
2.0
−
−
−
−
0.8
−
V
V
PWM_HI
V
−
PWM_LO
−
−
−
400
−
mV
mA
Input Current
−
No internal pullup or pulldown resistors
−1.0
+1.0
High−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
−
−
−
BST − SW = 12 V
BST − SW = 12 V
BST − SW = 0 V
−
−
−
−
2.2
1.0
15
3.4
1.8
−
W
W
kW
ns
t
t
BST − SW = 12 V, C
= 3.0 nF
20
11
55
45
rDRVH
fDRVH
LOAD
(See Figure 3)
Propagation Delay Times (Note 5)
t
BST − SW = 12 V, C
= 3.0 nF
= 3.0 nF
32
45
25
70
35
ns
pdhDRVH
pdlDRVH
LOAD
BST − SW = 12 V, C
LOAD
t
(See Figure 3)
t
(See Figure 2)
(See Figure 2)
20
25
35
55
pdlOD
t
pdhOD
SW Pulldown Resitance
Low−Side Driver
−
SW to PGND
−
15
−
kW
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
−
−
−
−
−
−
−
1.8
1.0
15
3.4
1.8
−
W
W
V
= PGND
kW
ns
CC
t
t
C
C
= 3.0 nF, (See Figure 3)
16
11
50
30
rDRVL
fDRVL
LOAD
LOAD
Propagation Delay Times (Note 5)
t
= 3.0 nF, (See Figure 3)
(Note 6, t
−
12
15
35
40
ns
pdhDRVL
only)
pdhDRVL
t
pdlDRVL
t
(See Figure 2)
(See Figure 2)
20
20
35
35
pdlOD
t
pdhOD
Timeout Delay
Undervoltage Lockout
UVLO Startup
−
DRVH − SW = 0
−
85
−
ns
−
−
−
−
−
−
3.9
3.7
0.1
4.3
4.1
0.2
4.5
4.3
0.4
V
V
V
UVLO Shutdown
Hysteresis
4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
5. For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
6. Guaranteed by design; not tested in production.
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4
ADP3110A
APPLICATIONS INFORMATION
Theory of Operation
Likewise, when the PWM input pin goes low, DRVH will
go low after the propagation delay (tpdDRVH). The time to
turn off the high−side MOSFET (tfDRVH) is dependent on
the total gate charge of the high−side MOSFET. A timer will
be triggered once the high−side mosfet has stopped
conducting, to delay (tpdhDRVL) the turn on of the
low−side MOSFET
The ADP3110A are single phase MOSFET drivers
designed for driving two N−channel MOSFETs in a
synchronous buck converter topology. The ADP3110A will
operate from 5.0 V or 12 V, but have been optimized for high
current multi−phase buck regulators that convert 12 V rail
directly to the core voltage required by complex logic chips.
A single PWM input signal is all that is required to properly
drive the high−side and the low−side MOSFETs. Each driver
is capable of driving a 3 nF load at frequencies up to 1 MHz.
Power Supply Decoupling
The ADP3110A can source and sink relatively large
currents to the gate pins of the external MOSFETs. In order
Low−Side Driver
The low−side driver is designed to drive
ground−referenced low RDS(on) N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected to
the VCC supply and PGND.
to maintain a constant and stable supply voltage (V ) a low
CC
a
ESR capacitor should be placed near the power and ground
pins. A1mF to 4.7 mF multi layer ceramic capacitor (MLCC)
is usually sufficient.
Input Pins
High−Side Driver
The PWM input and the Output Disable pins of the
ADP3110A have internal protection for Electro Static
Discharge (ESD), but in normal operation they present a
relatively high input impedance. If the PWM controller does
not have internal pulldown resistors, they should be added
externally to ensure that the driver outputs do not go high
before the controller has reached its under voltage lockout
threshold. The NCP5381 controller does include a passive
internal pull−down resistor on the drive−on output pin.
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The gate voltage for the high
side driver is developed by a bootstrap circuit referenced to
Switch Node (SW) pin.
The bootstrap circuit is comprised of an external diode,
and an external bootstrap capacitor. When the ADP3110A
are starting up, the SW pin is at ground, so the bootstrap
capacitor will charge up to VCC through the bootstrap diode
See Figure 4. When the PWM input goes high, the high−side
driver will begin to turn on the high−side MOSFET using the
stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin will rise. When the high−side
MOSFET is fully on, the switch node will be at 12 V, and the
BST pin will be at 12 V plus the charge of the bootstrap
capacitor (approaching 24 V).
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal (or an external) diode. Selection of
these components can be done after the high−side MOSFET
has been chosen. The bootstrap capacitor must have a
voltage rating that is able to withstand twice the maximum
supply voltage. A minimum 50 V rating is recommended.
The capacitance is determined using the following equation:
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
Q
GATE
DV
C
+
BST
Safety Timer and Overlap Protection Circuit
BST
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive
shoot−through or cross conduction can damage the
MOSFETs, and even a small amount of cross conduction
will cause a decrease in the power conversion efficiency.
The ADP3110A prevent cross conduction by monitoring
the status of the external mosfets and applying the
appropriate amount of “dead−time” or the time between the
turn off of one MOSFET and the turn on of the other
MOSFET.
When the PWM input pin goes high, DRVL will go low
after a propagation delay (tpdlDRVL). The time it takes for
the low−side MOSFET to turn off (tfDRVL) is dependent on
the total charge on the low−side MOSFET gate. The
ADP3110A monitor the gate voltage of both MOSFETs and
the switchnode voltage to determine the conduction status of
the MOSFETs. Once the low−side MOSFET is turned off an
internal timer will delay (tpdhDRVH) the turn on of the
high−side MOSFET
where QGATE is the total gate charge of the high−side
MOSFET, and DVBST is the voltage droop allowed on the
high−side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
The bootstrap diode must be rated to withstand the
maximum supply voltage plus any peak ringing voltages
that may be present on SW. The average forward current can
be estimated by:
I
+ Q
f
GATE MAX
F(AVG)
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in−circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
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5
ADP3110A
OD
V
OD_HI
V
OD_LO
t
t
pdhOD
pdlOD
90%
DRVH
or
DRVL
10%
Figure 2. Output Disable Timing Diagram
V
t
PWM_HI
V
PWM_LO
IN
t
pdlDRVL
fDRVL
90%
90%
2V
DRVL
10%
10%
t
rDRVL
t
t
t
t
fDRVH
pdhDRVH
rDRVH
pdlDRVH
90%
90%
DRVH−SW
2V
10%
10%
t
pdhDRVL
SW
Figure 3. Nonoverlap Timing Diagram
12 V
12 V
ADP3110A
4
1
8
7
5
6
BST
DRVH
SW
Vcc
3
2
OD
IN
Vout
Output Enable
PWM in
DRVL
PGND
Figure 4. ADP3110A Example Circuit
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6
ADP3110A
PACKAGE DIMENSIONS
DFN8 3x3, 0.5P
CASE 506BJ−01
ISSUE O
EDGE OF PACKAGE
NOTES:
A
B
D
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
L
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN 1
REFERENCE
DETAIL A
E
MILLIMETERS
OPTIONAL
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
CONSTRUCTION
2X
A
L
0.10
C
A3
b
0.20 REF
0.18
0.30
2X
D
3.00 BSC
1.84
3.00 BSC
1.55
0.50 BSC
0.10
C
D2 1.64
E
E2 1.35
e
K
L
TOP VIEW
DETAIL A
OPTIONAL
DETAIL B
0.05 C
CONSTRUCTION
0.20
0.30
−−−
0.50
0.03
A
L1 0.00
8X
0.05 C
(A3)
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
A1
MOLD CMPD
DETAIL A
EXPOSED Cu
8X L
1
4
DETAIL B
E2
OPTIONAL
8X K
CONSTRUCTION
8
5
8X b
e
0.10 C A B
0.05
C
NOTE 3
BOTTOM VIEW
SOLDERMASK DEFINED
MOUNTING FOOTPRINT
1.85
8X
0.35
3.30
1.55
0.50
PITCH
8X
0.63
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
ADP3110A
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
FlexMode is a trademark of Analog Devices, Inc.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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ADP3110A/D
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