ZL30402_06_技术文档

ZL30402

SONET/SDH Network Element PLL

Data Sheet

May 2006

Features

•

Meets requirements of GR-253 for SONET

Ordering Information

stratum 3 and SONET Minimum Clocks (SMC)

Meets requirements of GR-1244 for stratum 3

ZL30402/QCC

ZL30402QCG1

80 Pin LQFP Trays

80 Pin LQFP* Trays, Bake & Drypack

*Pb Free Matte Tin

-40°C to +85°C

•

Meets requirements of G.813 Option 1 and 2 for

SDH Equipment Clocks (SEC)

•

Generates clocks for ST-BUS, DS1, DS2, DS3,

OC-3, E1, E2, E3, STM-1 and 19.44 MHz

Description

Holdover accuracy to 1x10 ^-12meets GR-1244

The ZL30402 is a Network Element Phase-Locked

Loop designed to synchronize SDH and SONET

systems. In addition, it generates multiple clocks for

legacy PDH equipment and provides timing for ST-BUS

and GCI backplanes.

Stratum 3E and ITU-T G.812 requirements

Continuously monitors Primary and Secondary

reference clocks

•

Provides “hit-less” reference switching

Compensates for Master Clock Oscillator

The ZL30402 operates in NORMAL (LOCKED),

HOLDOVER and FREE-RUN modes to ensure that in

the presence of jitter, wander and interruptions to the

reference signals, the generated clocks meet

international standards. The filtering characteristics of

the PLL are hardware or software selectable and they

do not require any external adjustable components.

The ZL30402 uses an external 20 MHz Master Clock

Oscillator to provide a stable timing source for the

HOLDOVER operation.

accuracy

•

Detects frequency of both reference clocks and

synchronizes to any combination of 8 kHz,

1.544 MHz, 2.048 MHz and 19.44 MHz reference

frequencies.

Allows Hardware or Microprocessor control

Pin compatible with MT90401 device.

•

Applications

The ZL30402 operates from a single 3.3 V power

supply and offers a 5 V tolerant microprocessor

interface.

•

Synchronization for SDH and SONET Network

Elements

•

Clock generation for ST-BUS and GCI

backplanes

VDD GND

C20i

FCS

C155P/N

C34/C44

Master Clock

Frequency

Calibration

C19o

APLL

C16o

Primary

Acquisition

PLL

PRI

C8o

C6o

Clock

C4o

Synthesizer

C2o

Core PLL

MUX

C1.5o

F16o

F8o

SEC

Secondary

Acquisition

PLL

F0o

E3DS3/OC3

RefSel

E3/DS3

Tclk

Tdi

JTAG

HW

IEEE

Control State Machine

Microport

Tdo

Tms

1149.1a

RESET

Trst

A0-A6 D0-D7

CS DS R/W

MS1 MS2 RefAlign LOCK HOLDOVER

Figure 1 - Functional Block Diagram

1

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ZL30402

Data Sheet

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.0 ZL30402 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Acquisition PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Core PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Output Clocks Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6 Control State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6.1 Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6.2 ZL30402 State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.6.3 Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.4 Free-Run State (Free-Run mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.5 Normal State (Normal Mode or Locked Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.6 Holdover State (Holdover Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.7 Auto Holdover State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6.8 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.0 Master Clock Frequency Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Microprocessor Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.0 Hardware and Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Hardware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.1 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.2 Status Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2 Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.1 Control Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.2 Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.3 ZL30402 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2.4 Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1 ZL30402 Mode Switching - Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

5.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL. . . . . . . . . . . . . . . . . . . . . 28

5.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . 29

5.1.3 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL. . . . . 30

5.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . 31

5.2 Programming Master Clock Oscillator Frequency Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

List of Figures

Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2 - Pin Connections for 80-pin LQFP package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3 - Core PLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 4 - C19o, C155o, C34/C44 Clock Generation Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5 - ZL30402 State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6 - Hardware and Software Control options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 7 - Transition from Free-Run to Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 8 - Automatic Entry into Auto Holdover State and Eecovery into Normal mode . . . . . . . . . . . . . . . . . . . . . 29

Figure 9 - Entry into Auto Holdover state and recovery into Normal mode by switching references . . . . . . . . . . . 30

Figure 10 - Manual Reference Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11 - Timing Parameters Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12 - Microport Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 13 - ST-BUS and GCI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14 - DS1, DS2 and C19o Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 15 - C155o and C19o Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 16 - Input Reference to Output Clock Phase Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 17 - Input Control Signal Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 18 - E3 and DS3 Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

List of Tables

Table 1 - Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 2 - Filter Characteristic Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 3 - Reference Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 4 - ZL30402 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 5 - Control Register 1 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6 - Status Register 1 (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7 - Control Register 2 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 8 - Phase Offset Register 2 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 9 - Phase Offset Register 1 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 10 - Device ID Register (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11 - Control Register 3 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12 - Clock Disable Register 1 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13 - Clock Disable Register 2 (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14 - Core PLL Control Register (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15 - Fine Phase Offset Register (R/W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16 - Primary Acquisition PLL Status Register (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 17 - Secondary Acquisition PLL Status Register (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 18 - Master Clock Frequency Calibration Register 4 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 19 - Master Clock Frequency Calibration Register 3 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 20 - Master Clock Frequency Calibration Register 2 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 21 - Master Clock Frequency Calibration Register 1 (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Change Summary

The following table captures the changes from the April 2005 issue.

Page

Item

Change

Updated Ordering Information.

1

5

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

1.0 ZL30402 Pinout

1.1 Pin Connections

60 58 56

54

52

50

48

46 44 42

40

38

36

34

32

30

28

26

24

22

NC

IC

OE

CS

NC

62

Tdi

64

Trst

RESET

HW

Tclk

66

68

70

72

74

76

78

80

Tms

D0

Tdo

D1

NC

D2

GND

C155P

C155N

VDD

AVDD

GND

IC

D3

ZL30402

GND

IC

VDD

D4

D5

GND

PRI

SEC

E3/DS3

E3DS3/OC3

D6

D7

R/W

A0

IC

2

4

6

8

10 12 14 16 18 20

Figure 2 - Pin Connections for 80-pin LQFP package

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Pin Description

Pin #

Name

Description

Internal Connection. Leave unconnected.

1

IC

2-5

A1-A4

Address 1 to 4 (5 V tolerant input). Address inputs for the parallel processor

interface. Connect to ground in Hardware Control.

6

GND

Ground. Negative power supply.

7-8

A5-A6

Address 5 to 6 (5 V tolerant input). Address inputs for the parallel processor

interface. Connect to ground in Hardware Control.

9

FCS

Filter Characteristic Select (Input). In Hardware Control, FCS selects the

filtering characteristics of the ZL30402. Set this pin high to have a loop filter

corner frequency of 0.1 Hz and limit the phase slope to 885 ns per second. Set

this pin low to have corner frequency of 1.1 Hz and limit the phase slope to

41 ns per 1.326 ms. Connect to ground in Software Control. This pin is

internally pulled down to GND.

10

11

12

VDD

GND

F16o

Positive Power Supply.

Ground.

Frame Pulse ST-BUS 8.192 Mb/s (CMOS tristate output). This is an 8 kHz,

61 ns wide, active low framing pulse, which marks beginning of a ST-BUS

frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s

13

14

15

16

17

C16o

C8o

C4o

C2o

F0o

Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 8.192 Mb/s.

Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 8.192 Mb/s.

Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 2.048 Mb/s.

Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 2.048 Mb/s.

Frame Pulse ST-BUS 2.048 Mb/s (CMOS tristate output). This is an 8 kHz,

244 ns, active low framing pulse, which marks the beginning of a ST-BUS

frame. This is typically used for ST-BUS operation at 2.048 Mb/s and

4.096 Mb/s.

18

19

MS1

MS2

Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30402 mode of

operation (Normal, Holdover or Free-run), see Table 1 on page 18 for details.

The logic level at this input is sampled by the rising edge of the F8o frame

pulse. Connect to ground in Software Control.

Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30402 mode of

operation (Normal, Holdover or Free-run), see Table 1 on page 18 for details.

The logic level at this input is sampled by the rising edge of the F8o frame

pulse. Connect to ground in Software Control.

7

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Pin Description (continued)

Pin #

Name

Description

20

F8o

Frame Pulse ST-BUS/GCI 8.192 Mb/s (CMOS tristate output). This is an

8 kHz, 122 ns, active high framing pulse, which marks the beginning of a ST-

BUS/GCI frame. This is typically used for ST-BUS/GCI operation at

8.192 Mb/s. See Figure 13 for details.

21

22

E3DS3/OC3

E3/DS3

E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin

enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output

(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155

clock outputs (high impedance) and sets C34/C44 output to provide C34 and

C44 clocks. In Software Control connect this pin to ground.

E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin

is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44

output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set

low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and

logic high selects 8.592 MHz clock. Connect this input to ground in Software

Control.

23

24

SEC

PRI

Secondary Reference (Input). This input is used as a secondary reference

source for synchronization. The ZL30402 can synchronize to the falling edge

of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the

19.44 MHz clock. In Hardware Control, selection of the input reference is

based upon the RefSel control input. This pin is internally pulled up to VDD.

Primary Reference (Input). This input is used as a primary reference source

for synchronization. The ZL30402 can synchronize to the falling edge of the

8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz

clock. In Hardware Control, selection of the input reference is based upon the

RefSel control input. This pin is internally pulled up to VDD.

25

26

27

28

29

GND

IC

Ground.

Internal Connection. Leave unconnected.

Ground.

GND

AVDD

VDD

Positive Analog Power Supply. Connect this pin to VDD.

Positive Power Supply.

30

31

C155N

C155P

Clock 155.52 MHz (LVDS output). Differential outputs for a 155.52 MHz clock.

These outputs are enabled by applying logic low to E3DS3/OC3 input or they

can be switched into high impedance state by applying logic high.

32

33

34

GND

NC

Ground.

No internal bonding Connection. Leave unconnected.

Tdo

IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on

this pin on the falling edge of Tclk clock. If not used, this pin should be left

unconnected.

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Pin Description (continued)

Pin #

Name

Description

35

Tms

IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the

state transition on the TAP controller. This pin is internally pulled up to VDD. If

not used, this pin should be left unconnected.

36

37

Tclk

Trst

IEEE1149.1a Test Clock Signal (5.5 V tolerant input). Input clock for the

JTAG test logic. If not used, this pin should be pulled up to VDD.

IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG

TAP controller. This pin should be pulsed low on power-up to ensure that the

device in the normal functional state. This pin is internally pulled up to VDD. If

not used, this pin should be connected to GND.

38

Tdi

IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test

instructions and data. This pin is internally pulled up to VDD. If not used, this

pin should be left unconnected.

39

40

41

42

NC

No internal bonding Connection. Leave unconnected.

Internal Connection. Leave unconnected.

IC

C1.5o

Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz

DS1 rate clock.

43

C6o

Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz

DS2 rate clock.

44

45

46

IC

Internal Connection. Connect this pin to Ground.

Ground.

GND

C19o

Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz

clock.

47

RefSel

Reference Source Select (Input). A logic low selects the PRI (primary)

reference source as the input reference signal and logic high selects the SEC

(secondary) input. The logic level at this input is sampled at the rising edge of

F8o. This pin is internally pulled down to GND.

48

RefAlign

Reference Align (Input). In Hardware Control a high to low transition at this

input initiates phase realignment between the input reference and the

generated output clocks. This pin is internally pulled down to GND.

49

50

51

VDD

NC

Positive Power Supply.

No internal bonding Connection. Leave unconnected.

C20i

Clock 20 MHz (5.5 V tolerant input). This pin is the input for the 20 MHz

Master Clock Oscillator.

52

GND

Digital Ground.

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Pin Description (continued)

Pin #

Name

Description

53

C34/C44

Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is

programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz

(for DS3 applications) when E3DS3/OC3 is high, or to be either 8.592MHz or

11.184 MHz when E3DS3/OC3 is low. See description of E3DS3/OC3 and

E3/DS3 inputs for details. In Software Control the functionality of this output is

controlled by Control Register 2 (Table 7 "Control Register 2 (R/W)").

54

55

VDD

Positive Power Supply.

HOLDOVER

Holdover Indicator (CMOS output). Logic high at this output indicates that the

device is in Holdover mode.

56

57

NC

No internal bonding Connection. Leave unconnected.

LOCK

Lock Indicator (CMOS output). Logic high at this output indicates that

ZL30402 is locked to the input reference.

58

59

NC

DS

No internal bonding Connection. Leave unconnected.

Data Strobe (5 V tolerant input). This input is the active low data strobe of the

processor interface.

60

61

62

IC

Internal Connection. Connect to ground.

Internal Connection. Leave unconnected.

OE

Output Enable (Input). Logic high on this input enables C19, F16, C16, C8,

C6, C4, C2, C1.5, F8 and F0 signals. Pulling this input low will force the output

clocks pins into a high impedance state.

63

64

CS

Chip Select (5 V tolerant input). This active low input enables the

microprocessor interface. When CS is set to high, the microprocessor interface

is idle and all Data Bus I/O pins will be in a high impedance state.

RESET

HW

RESET (5 V tolerant input). This active low input forces the ZL30402 into a

RESET state. The RESET pin must be held low for a minimum of 1µs to reset

the device properly. The ZL30402 must be reset after power-up.

65

Hardware/Software Control (Input). If this pin it tied low, the ZL30402 is

controlled via the microport. If it is tied high, the ZL30402 is controlled via the

control pins MS1, MS2, FCS, RefSel, RefAlign, E3/DS3 and E3DS3/OC3.

66-69

D0 - D3

Data 0 to Data 3 (5 V tolerant three-state I/O). These signals combined with

D4 - D7 form the bi-directional data bus of the microprocessor interface (D0 is

the least significant bit).

70

71

72

73

GND

IC

Ground.

Internal Connection (Input). Connect this pin to ground.

Positive Power Supply.

IC

VDD

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Pin Description (continued)

Pin #

Name

Description

74 - 77

D4 - D7

Data 4 to Data 7 (5 V tolerant three-state I/O). These signals combine with D0

- D3 form the bi-directional data bus of the processor interface (D7 is the most

significant bit).

78

R/W

Read/Write Strobe (5 V tolerant input). This input controls the direction of the

data bus D[0-7] during a microprocessor access. When R/W is high, the

parallel processor is reading data from the ZL30402. When low, the parallel

processor is writing data to the ZL30402.

79

80

A0

IC

Address 0 (5 V tolerant input). Address input for the microprocessor interface.

A0 is the least significant input.

Internal Connection (Input). Connect this pin to ground.

2.0 Functional Description

The ZL30402 is a Network Element PLL designed to provide timing for SDH and SONET equipment conforming to

ITU-T, ANSI, ETSI and Telcordia recommendations. In addition, it generates clocks for legacy PDH equipment

operating at DS1, DS2, DS3, E1, and E3 rates. The ZL30402 provides clocks for industry standard ST-BUS and

GCI backplanes, and it also supports H.110 timing requirements. The functional block diagram of the ZL30402 is

shown in Figure 1 "Functional Block Diagram" and its operation is described in the following section.

2.1 Acquisition PLLs

The ZL30402 has two Acquisition PLLs for monitoring availability and quality of the Primary (PRI) and Secondary

(SEC) reference clocks. Each Acquisition PLL operates independently and locks to the falling edges of one of the

three input reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz or to the rising edge of 19.44 MHz. The reference

frequency can be determined from reading the Acquisition PLL Status Register bits InpFreq1 and InpFreq0 (see

Table 16 "Primary Acquisition PLL Status Register (R)" and Table 17 "Secondary Acquisition PLL Status Register

(R)").

The Primary and Secondary Acquisition PLLs are designed to provide status information that identifies two levels of

reference clock quality. For clarity, only the Primary Acquisition PLL is referenced in the text, but the same applies

to the Secondary Acquisition PLL.

-

Reference frequency drifts more than ±30000 ppm or is lost completely. In response, the Primary Acquisition

PLL enters its own Holdover mode and indicates this by asserting the HOLDOVER bit in the Primary

Acquisition PLL Status Register (Table 16 "Primary Acquisition PLL Status Register (R)"). Entry into Holdover

forces the Core PLL into the Auto Holdover state.

-

Reference frequency drifts more than ±104 ppm. In response the Primary Acquisition PLL asserts the

Frequency Limit bit PAFL in its Primary Acquisition PLL Status Register (Table 16) indicating that the

reference frequency crossed the boundary of the capture range.

Outputs of both Acquisition PLLs are connected to a multiplexer (MUX), which allows selecting a reference signal

that guarantees better traceability to the Primary Reference Clock. This multiplexer channels binary words to the

Core PLL digital phase detector (instead of analog signals). Application of the digital phase detector in the Core

PLL eliminates quantization errors and improves phase alignment accuracy.

The bandwidth of the Acquisition PLL is much wider than the bandwidth of the following Core PLL. This feature

allows cascading Acquisition and Core PLLs without changing the transfer function of the Core PLL.

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

2.2 Core PLL

The most critical element of the ZL30402 is its Core PLL, which generates a phase-locked clock, filters jitter and

wander and suppresses input phase transients. All of these features are in agreement with international standards:

-

G.813 Option 1 and 2 clocks for SDH equipment

GR-253 for SONET stratum 3 and SONET Minimum Clocks (SMC)

GR-1244 for stratum 3 Clocks

The Core PLL supports three mandatory modes of operation: Free-run, Normal (Locked) and Holdover. Each of

these modes places specific requirements on the building blocks of the Core PLL.

-

In Free-run Mode, the Core PLL locks to the 20 MHz Master Clock Oscillator connected to pin C20i. The

stability of the generated clock remains the same as the stability of the Master Clock Oscillator but frequency

accuracy is greatly improved by the Master Clock Frequency Calibration register. This register compensates

oscillator frequency, practically eliminating manufacturing tolerances.

-

In Normal Mode, the Core PLL locks to one of the Acquisition PLLs. Both Acquisition PLLs provide

preprocessed phase data to the Core PLL including detection of reference clock quality. This preprocessing

reduces the load on the Core PLL and improves quality of the generated clock.

In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The

Core PLL enters Holdover mode if the attached Acquisition PLL switches into the Holdover state or under

external software or hardware control.

Some of the key elements of the Core PLL are shown in Figure 3 "Core PLL Functional Block Diagram".

LOCK

RefAlign

FSM

MUX

Phase

Filters

DCO

Detector

FCS

Figure 3 - Core PLL Functional Block Diagram

Digitally Controlled Oscillator (DCO): The DCO is an arithmetic unit that continuously generates a stream of

numbers that represent the phase-locked clock. These numbers are passed to the Clock Synthesizer (see

section 2.3) where they are converted into electrical clock signals of different frequencies.

Filters: In Normal mode, the clock generated by the DCO is phase-locked to the input reference signal and band-

limited to meet network synchronization standards. The ZL30402 provides two software programmable (Control

Reg 1) and two hardware selectable (FCS pin) filtering options. The filtering characteristics are similar to a first

order low pass filter with corner frequencies that support international standards:

-

0.1 Hz filter: supports G.813 Option 2 Clock, GR-253 SONET stratum 3 and GR-253 SONET Minimum clock

1.1 Hz filter: supports G.813 Option 1 and GR-1244 stratum 3 clock

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Lock Indicator: Entry into Normal mode is flagged by the LOCK status bit or pin. Lock is declared when the

Acquisition PLL is locked to the reference clock and the Core PLL is locked to the Acquisition PLL. Frequency lock

means that the center frequency of the PLL is identical to the reference frequency and phase error excursions

caused by jitter and wander are symmetrical around some long-term phase error average.

Reference Re-alignment: Reference realignment is performed to erase a residual phase error that has been

accumulated between the reference and output clocks as a result of reference switching. A high to low transition on

the RefAlign pin (or bit) initiates phase realignment with a phase slope on the output clocks limited to 41 ns in 1.326

ms for the 1.1 Hz filter and to 885 ns in 1 s for 0.1 Hz filter. Please refer to the ZLAN-27 "Phase Alignment between

8 kHz output and 8 kHz Input Reference on ZL30402" Application Note for details.

2.3 Clock Synthesizer

The output of the Core PLL is connected to the Clock Synthesizer that generates twelve clocks and three frame

pulses.

2.4 Output Clocks

The ZL30402 provides the following clocks (see Figure 13 "ST-BUS and GCI Output Timing", Figure 14 "DS1, DS2

and C19o Clock Timing", Figure 15 "C155o and C19o Timing", and Figure 18 "E3 and DS3 Output Timing" for

details):

- C1.5o

- C2o

: 1.544 MHz clock with nominal 50% duty cycle

: 2.048 MHz clock with nominal 50% duty cycle

: 4.096 MHz clock with nominal 50% duty cycle

: 6.312 MHz clock with nominal 50% duty cycle

: 8.192 MHz clock with nominal 50% duty cycle

: 8.592 MHz clock with duty cycle from 30 to 70%.

: 11.184 MHz clock with duty cycle from 30 to 70%.

: 16.384 MHz clock with nominal 50% duty cycle

: 19.44 MHz clock with nominal 50% duty cycle (with optional dejittering)

: 34.368 MHz clock with nominal 50% duty cycle

: 44.736 MHz clock with nominal 50% duty cycle

: 155.52 MHz clock with nominal 50% duty cycle.

- C4o

- C6o

- C8o

- C8.5o

- C11o

- C16o

- C19o

- C34o

- C44o

- C155

The ZL30402 provides the following frame pulses (see Figure 13 "ST-BUS and GCI Output Timing" for details). All

frame pulses have the same 125 µs period (8kHz frequency):

- F0o

- F8o

- F16o

: 244 ns wide, logic low frame pulse

: 122 ns wide, logic high frame pulse

: 61 ns wide, logic low frame pulse

The Clock Synthesizer has an internal analog PLL (APLL) that can be placed in the path of the digitally generated

clocks to multiply frequencies and reduce jitter. The combination of two pins, E3DS3/OC3 and E3DS3, controls the

placement of the APLL and allows for selection of different clock configurations e.g., if E3DS3/OC3 pin is low the

19.44 MHz clock is derived from 155.52 MHz clock with very low jitter. The same APLL can be used to generate

clocks with E3, DS3 or OC3 rates (see Figure 4 "C19o, C155o, C34/C44 Clock Generation Options" for details).

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Zarlink Semiconductor Inc.

ZL30402

C19o Output

E3DS3/OC3

Data Sheet

C155 Output

C34/44 Output

E3DS3/OC3

0

1

19.44

0

11.184 44.736

155.52

HIZ

Dejittered

1

8.592

34.368

Figure 4 - C19o, C155o, C34/C44 Clock Generation Options

All clocks and frame pulses except the C155 are output with CMOS logic levels. The C155 clock (155.52MHz) is

output in a standard LVDS format.

2.5 Output Clocks Phase Adjustment

The ZL30402 provides three control registers dedicated to programming the output clock phase offset. Clocks

C16o, C8o, C4o and C2o and frame pulses F16o, F8o, F0o are derived from 16.384 MHz and can be jointly shifted

with respect to an active reference clock by up to 125 µs with a step size of 61 ns. The required phase shift of

clocks is programmable by writing to the Phase Offset Register 2 ("Table 8") and to the Phase Offset Register 1

("Table 9"). The C1.5o clock can be shifted as well in step sizes of 81ns by programming C1.5POA bits in Control

Register 3 ("Table 11").

The coarse phase adjustment is augmented with a very fine phase offset control on the order of 477 ps per step.

This fine adjustment is programmable by writing to the Fine Phase Offset Register (Table 15 "Fine Phase Offset

Register (R/W)"). The offset moves all clocks and frame pulses generated by ZL30402 including C155 clock.

2.6 Control State Machine

2.6.1 Clock Modes

Any Network Element that operates in a synchronous network must support three Clock Modes: Free-run, Normal

(Locked) and Holdover. These clock modes determine behavior of a Network Element to the unforeseen changes in

the network synchronization hierarchy. Requirements for Clock Modes are defined in the international standards

e.g.: G.813, GR-1244-CORE and GR-253-CORE and they are very strictly enforced by network operators. The

ZL30402 supports all clock modes and each of these modes have a corresponding state in the Control State

Machine.

2.6.2 ZL30402 State Machine

The ZL30402 Control State Machine is a complex combination of many internal states supporting the three

mandatory clock modes. The simplified version of this state machine is shown in Figure 5 and it includes the

mandatory states: Free-run, Normal and Holdover. These three states are complemented by two additional states:

Reset and Auto Holdover, which are critical to the ZL30402 operation under the changing external conditions.

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

MS2, MS1 == 01 OR

RefSel change

Ref: FAIL --> OK &

NORMAL

(LOCKED)

00

MS2, MS1 == 00 &

AHRD=1 &

MHR= 0-->1 then 1-->0

{MANUAL}

Ref: OK &

Ref: OK --> FAIL &

MS2, MS1 == 00

{AUTO}

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=0 &

MS2, MS1 == 00

{AUTO}

MS2, MS1! = 10

RESET == 1

{AUTO}

AUTO

HOLD-

OVER

RefSel Change

FREE-

RUN

10

HOLD-

OVER

01

RESET

MS2, MS1 == 10 forces

unconditional return from

any state to Free-run

Notes:

==: equal

{AUTO}: Automatic transition

STATE

MS2, MS1

! =: not equal

AUTO HOLDOVER: Automatic Holdover

& =: AND Operation

0 --> 1: transition from 0 to 1

Figure 5 - ZL30402 State Machine

2.6.3 Reset State

The Reset State must be entered when ZL30402 is powered-up. In this state, all arithmetic calculations are halted,

clocks are stopped, the microprocessor port is disabled and all internal registers are reset to their default values.

The Reset state is entered by pulling the RESET pin low for a minimum of 1 µs. When the RESET pin is pulled back

high, internal logic starts a 500 µs initialization process before switching into the Free-run state (MS2, MS1 = 10).

2.6.4 Free-Run State (Free-Run mode)

The Free-run state is entered when synchronization to the network is not required or is not possible. Typically this

occurs during installation, repairs or when a Network Element operates as a master node in an isolated network. In

the Free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30402

Master Crystal Oscillator. When equipment is installed for the first time (or periodically maintained) the accuracy of

the Free-run clocks can be adjusted to within 1x10^-12by setting the offset frequency in the Master Clock Frequency

Calibration Register.

2.6.5 Normal State (Normal Mode or Locked Mode)

The Normal State is entered when a good quality reference clock from the network is available for synchronization.

The ZL30402 automatically detects the frequency of the reference clock (8 kHz, 1.544 MHz, 2.048 MHz or

19.44 MHz) and sets the LOCK status bit and pin high after acquiring synchronization. In the Normal state all

generated clocks (C1.5o, C2o, C4o, C6o, C8o, C16o, C19o, C34/C44 and C155) and frame pulses (F0o, F8o,

F16o) are derived from network timing. To guarantee uninterrupted synchronization, the ZL30402 has two

Acquisition PLLs that continuously monitor the quality of the incoming reference clocks. This dual architecture

enables quick replacement of a poor or failed reference and minimizes the time spent in other states.

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

2.6.6 Holdover State (Holdover Mode)

The Holdover State is typically entered for short durations while network synchronization is temporarily disrupted. In

Holdover Mode, the ZL30402 generates clocks, which are not locked to an external reference signal but their

frequencies are based on stored coefficients in memory that were determined while the PLL was in Normal Mode

and locked to an external reference signal.

The initial frequency offset of the ZL30402 in Holdover Mode is 1x10^-12. This is more accurate than Telcordia’s GR-

1244-CORE stratum 3E requirement of +1x10^-9. Once the ZL30402 has transitioned into Holdover Mode, holdover

stability is determined by the stability of the 20MHz Master Clock Oscillator. Selection of the oscillator requires close

examination of the crystal oscillator temperature sensitivity and frequency drift caused by aging.

2.6.7 Auto Holdover State

The Auto Holdover state is a transitional state that the ZL30402 enters automatically when the active reference fails

unexpectedly. When the ZL30402 detects loss of reference it sets the HOLDOVER status bit and waits in Auto

Holdover state until the failed reference recovers. The HOLDOVER status may alert the control processor about the

failure and in response the control processor may switch to the secondary reference clock. The Auto Holdover and

Holdover States are internally combined together and they are output as a HOLDOVER status on pin 55 and bit 4 in

Status Register 1 (Table 6 on page 22).

2.6.8 State Transitions

In a typical Network Element application, the ZL30402 will typically operate in Normal mode (MS2, MS1 == 00)

generating synchronous clocks. Its two Acquisition PLLs will continuously monitor the input references for signs of

degraded quality and output status information for further processing. The status information from the Acquisition

PLLs and the CORE PLL combined with status information from line interfaces and framers (as listed below) forms

the basis for creating reliable network synchronization.

•

Acquisition PLLs (PAH, PAFL, SAH, SAFL) and

Core PLL (LOCK, HOLDOVER, FLIM)

Line interfaces (e.g. LOS - Loss of Signal, AIS - Alarm Indication Signal) and

Framers (e.g. LOF - Loss of frame or Synchronization Status Messages carried over SONET S1 byte or

ESF-DS1 Facility Data Link).

The ZL30402 State Machine is designed to perform some transitions automatically, leaving other less time

dependent tasks to the control processor. The state machine includes two stimulus signals which are critical to

automatic operation: “OK --> FAIL” and “FAIL --> OK” that represent loss (and recovery) of reference signal or its

drift by more than ±30000 ppm. Both of them force the Core PLL to transition into and out of the Auto Holdover

state. The ZL30402 State Machine may also be driven by controlling the mode select pins or bits MS2, MS1. In

order to avoid network synchronization problems, the State Machine has built-in basic protection that does not allow

switching the Core PLL into a state where it cannot operate correctly e.g. it is not possible to force the Core PLL into

Normal mode when all references are lost.

3.0 Master Clock Frequency Calibration Circuit

In an ordinary timing generation module, the Free-run mode accuracy of generated clocks is determined by the

accuracy of the Master Crystal Oscillator. If the Master Crystal Oscillator has a manufacturing tolerance of +/-

4.6 ppm, the generated clocks will have no better accuracy.

The ZL30402 eliminates tolerance problems by providing a programmable Master Clock Frequency Calibration

circuit, which can reduce oscillator manufacturing tolerance to near zero. This feature eliminates the need for high

precision 20 MHz crystal oscillators, which could be very expensive for equipment that has to maintain accuracy

over a very long period of time (e.g., 20 years in some applications).

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

The compensation value for the Master Clock Calibration Register (MCFC3 to MCFC0) can be calculated from the

following equation:

MCFC = 45036 * ( - f_offset) where: f_offset= f_m- 20 000 000 Hz

The f_mfrequency should only be measured after the Master Crystal Oscillator has been mounted inside a system

and powered long enough for the Master Crystal Oscillator to reach a steady operating temperature. Section 5.2 on

page 31 provides two examples of how to calculate an offset frequency and convert the decimal value to a binary

format. The maximum frequency compensation range of the MCFC register is equal to ±2384 ppm (±47680 Hz).

3.1 Microprocessor Interface

The ZL30402 can be controlled by a microprocessor or by an ASIC type of device that is connected directly to the

hardware control pins. If the HW pin is tied low (see Figure 6 "Hardware and Software Control options"), an 8-bit

Motorola type microprocessor may be used to control PLL operation and check its status. Under software control,

the control pins MS2, MS1, FCS, RefSel, RefAlign are disabled and they are replaced by the equivalent control bits.

The output pins LOCK and HOLDOVER are always active and they provide current status information whether the

device is in microprocessor or hardware control. Software (microprocessor) control provides additional functionality

that is not available in hardware control such as output clock phase adjustment, master clock frequency calibration

and extended access to status registers. These registers are also accessible when the ZL30402 operates under

Hardware control.

3.2 JTAG Interface

The ZL30402 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990,

which specifies a design-for-testability technique called Boundary-Scan Test (BST). The BST architecture is made

up of four basic elements, Test Access Port (TAP), TAP Controller, Instruction Register (IR) and Test Data Registers

(TDR) and all these elements are implemented on the ZL30402.

Zarlink Semiconductor provides a Boundary Scan Description Language (BSDL) file that contains all the

information required for a JTAG test system to access the ZL30402's boundary scan circuitry. The file is available

for download from the Zarlink Semiconductor web site: www.zarlink.com.

4.0 Hardware and Software Control

The ZL30402 offers Hardware and Software Control options that simplify design of basic or complex clock

synchronization modules. Hardware control offers fewer features but still allows for building of sophisticated timing

cards without extensive programming. The complete set of control and status functions for each mode are shown in

Figure 6 "Hardware and Software Control options".

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Hardware Control

Software Control

HW = 1

HW = 0

Pins

MS2

MS1

FCS

MS2

MS1

FCS

C

O

N

T

C

O

N

T

RefSel

RefAlign

AHRD

MHR

R

O

L

R

O

L

RefSel

RefAlign

µP

LOCK

HOLDOVER

FLIM

LOCK

S

T

A

T

U

S

T

A

T

U

S

PAH

PAFL

SAH

SAFL

HOLDOVER

Figure 6 - Hardware and Software Control options

4.1 Hardware Control

The Hardware control is a subset of software control and it will only be briefly described with cross-referencing to

Software control programmable registers.

4.1.1 Control Pins

The ZL30402 has six dedicated control pins for selecting modes of operation and activating different functions.

These pins are listed below:

MS2 and MS1 pins: Mode Select: The MS2 (pin 19) and MS1 (pin 18) inputs select the PLL mode of operation.

See Table 1 for details. The logic level at these inputs is sampled by the rising edge of the F8o frame pulse.

FCS pin: Filter Characteristic Select. The FCS (pin 9) input is used to select the filtering characteristics of the

Core PLL. See Table 2 on page 19 for details.

MS2

MS1

Mode of Operation

0

1

0

1

0

1

Normal mode

Holdover mode

Free-run

Reserved

Table 1 - Operating Modes and States

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Zarlink Semiconductor Inc.

ZL30402

Data Sheet

FCS

Filtering Characteristic

Phase Slope

0

Filter corner frequency set to 1.1 Hz.

41ns

This selection meets requirements of G.813 Option 1 and GR-1244 stratum 3

clocks.

in 1.326ms

1

Filter corner frequency set to 0.1 Hz.

885ns/s

This selection meets requirements of G.813 Option 2, GR-253 for SONET stratum 3

and GR-253 for SONET Minimum Clocks (SMC).

Table 2 - Filter Characteristic Selection

RefSel: Reference Source Select. The RefSel (pin 47) input selects the PRI (primary) or SEC (secondary) input

as the reference clock for the Core PLL. The logic level at this input is sampled by the rising edge of F8o.

RefSel

Input Reference

0

1

Core PLL connected to the Primary Acquisition PLL

Core PLL connected to the Secondary Acquisition PLL

Table 3 - Reference Source Select

RefAlign: Reference Align. The RefAlign (pin 48) input controls phase realignment between the input reference

and the generated output clocks.

4.1.2 Status Pins

The ZL30402 has two dedicated status pins for indicating modes of operation. These pins are listed below:

LOCK. This output goes high when the core PLL is locked to the selected Acquisition PLL.

HOLDOVER - This output goes high when the Core PLL enters Holdover mode. The Core PLL will switch to

Holdover mode if the respective Acquisition PLL enters Holdover mode or if the mode select pins or bits are set to

Holdover (MS2, MS1 = 01).

4.2 Software Control

Software control is enabled by setting the HW pin to logic zero (HW = 0). In this mode all hardware control pins

(inputs) are disabled and status bits (outputs) are enabled. The ZL30402 has seventeen registers that provide all

the functionality available in Hardware control and in addition they offer advanced control and monitoring that is

only available in Software control (see Figure 6 "Hardware and Software Control options").

4.2.1 Control Bits

The ZL30402 has seven control bits as is shown in Figure 6 "Hardware and Software Control options". The first five

bits replace the five hardware control pins: MS2, MS1, FCS, RefSel and RefAlign and the last two bits support

recovery from Auto Holdover mode: AHRD and MHR. These bits are described in section 3.2.4.

In addition to the Control bits shown in Figure 6 "Hardware and Software Control options", the ZL30402 has a

number of bits and registers that are accessed infrequently or during configuration only e.g., Phase Offset

Adjustment or Master Clock Frequency Calibration.

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Data Sheet

4.2.2 Status Bits

The ZL30402 has seven status bits (see Figure 6 "Hardware and Software Control options"). The first two bits

perform the same function as their equivalent status pins. The last five bits perform two functions. Bits FLIM, PAFL,

SAFL indicate drift of the reference clock frequencies beyond the capture range of Acquisition and Core PLLs and

bits PAH and SAH show entry of Primary and Secondary Acquisition PLLs into Holdover mode. These bits are

described in detail in section 3.2.4. The status pins are enabled when the ZL30402 operates in software control and

they can be used to trigger interrupts.

4.2.3 ZL30402 Register Map

Addresses: 00H to 6FH

Address

hex

Read

Write

R/W

R

Register

Control Register 1

Function

00

01

04

06

07

RefSel, 0, 0, MS2, MS1, FCS, 0, RefAlign

rsv, rsv, LOCK, HOLDOVER, rsv, FLIM, rsv, rsv

E3DS3/OC3, E3/DS3, 0, 0, 0, 0, 0, 0,

Status Register 1

Control Register 2

R/W

Phase Offset Register 2

Phase Offset Register 1

0, 0, 0, 0, OffEn, C16POA10, C16POA9, C16POA8

C16POA7, C16POA6, C16POA5, C16POA4, C16POA3,

C16POA2, C16POA1, C16POA0

0F

11

13

14

19

1A

Device ID Register

R

0010 0001

Control Register 3

R/W

rsv, rsv, C1.5POA2, C1.5POA1, C1.5POA0, 0, 0, 0

0, 0, C16dis, C8dis, C4dis, C2dis, C1.5dis,0

0, 0, 0, F8odis, F0odis, F16odis, C6dis, C19dis

0, 0, 0, 0, 0, 0, MHR, AHRD, 0

Clock Disable Register 1

Clock Disable Register 2

Core PLL Control Register

Fine Phase Offset Register

FPOA7, FPOA6, FPOA5, FPOA4, FPOA3, FPOA2, FPOA1,

FPOA0

20

28

40

Primary Acquisition PLL Status

Register

R

rsv, rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, PAH,PAFL

Secondary Acquisition PLL

rsv, rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, SAH, SAFL

Status Register

Master Clock Frequency

R/W

MCFC31, MCFC30, MCFC29, MCFC28, MCFC27, MCFC26,

MCFC25, MCFC24,

Calibration Register - Byte 4

41

42

43

Master Clock Frequency

R/W

MCFC23, MCFC22, MCFC21, MCFC20, MCFC19, MCFC18,

MCFC17, MCFC16

Calibration Register - Byte 3

Master Clock Frequency

MCFC15, MCFC14, MCFC13, MCFC12, MCFC11, MCFC10,

MCFC9, MCFC8

Calibration Register - Byte 2

Master Clock Frequency

MCFC7, MCFC6, MCFC5, MCFC4, MCFC3, MCFC2, MCFC1,

MCFC0

Calibration Register - Byte 1

Table 4 - ZL30402 Register Map

Note: The ZL30402 uses address space from 00h to 6Fh. Registers at address locations not listed above must not be written or read.

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Data Sheet

4.2.4 Register Description

Address: 00 H

Bit

Name

Functional Description

Default

7

RefSel

0

Reference Select. A zero selects the PRI (Primary) reference source

as the input reference signal and a one selects the SEC (secondary)

reference.

6-5

4-3

RSV

00

10

Reserved.

MS2, MS1

Mode Select

- MS2 = 0 MS1 = 0 Normal Mode (Locked Mode)

- MS2 = 0 MS1 = 1 Holdover Mode

- MS2 = 1 MS1 = 0 Free-run Mode

- MS2 = 1 MS1 = 1 Reserved

2

FCS

0

Filter Characteristic Select

FCS = 0 Filter corner frequency set to 1.1 Hz. This selection meets

requirements of G.813 Option 1 and GR-1244 stratum 3 clocks.

FCS = 1 Filter corner frequency set to 0.1 Hz. This selection meets

requirements of G.813 Option 2, GR-253 for SONET stratum 3 and

GR-253 for SONET Minimum Clocks (SMC).

1

0

RSV

0

1

Reserved.

RefAlign

Reference Align. A high-to-low transition aligns the generated output

clocks to the input reference signal. The maximum phase slope

depends on the Filter Characteristic selected and is limited to:

- 41ns in 1.326ms for FCS = 0

- 885 ns in 1s for FCS = 1

Table 5 - Control Register 1 (R/W)

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Data Sheet

Address: 01 H

Bit

Name

Functional Description

7

6

5

RSV

Reserved.

LOCK

Lock. This bit goes high when the Core PLL is locked to the selected Acquisition

PLL.

4

HOLDOVER Holdover. This bit goes high when the Core PLL enters Holdover mode. Detection

of reference failure and subsequent transition from Normal to Holdover state takes

approximately: 0.750 µs for 19.44 MHz reference, 0.850 µs for 2.048 MHz

reference, 1.1 µs for 1.544 MHz reference and 130 µs for 8 kHz reference.

3

2

RSV

Reserved.

FLIM

Frequency Limit. This bit goes high when the Core PLL is pulled by the input

reference signal to the edge of its frequency tracking range set at ±104 ppm. This

bit may change state momentarily in the event of large jitter or wander excursions

occurring when the input reference is close to the frequency limit range.

1

0

RSV

Reserved.

Table 6 - Status Register 1 (R)

Address: 04 H

Bit

Name

Functional Description

Default

7

E3DS3/OC3 E3, DS3 or OC-3 clock select. Setting this bit to zero enables the

C155P/N outputs (pin 30 and pin 31) and enables the C34/C44 output

(pin 53) to provide C8 or C11 clocks. Logic high sets the C155 clock

outputs into high impedance and enables the C34/C44 output to

provide a C34 or C44 clock.

0

6

E3/DS3

E3 or DS3 clock select. When E3DS3/OC3 bit is set high, a logic

low on the E3/DS3 bit selects a 44.736 MHz clock on the C34/C44

output and logic high selects a 34.368 MHz clock. When the

E3DS3/OC3 bit is set low, a logic low on the E3/DS3 bit selects an

11.184 MHz clock on the C34/C44 output and a logic high selects

an 8.592 MHz clock.

0

5-0

RSV

Reserved.

000000

Table 7 - Control Register 2 (R/W)

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Data Sheet

Address: 06 H

Bit

7-4

3

Name

RSV

Functional Description

Default

0000

0

Reserved.

OffEn

Offset Enable. Set high to enable programmable phase offset

adjustments (C16 Phase Offset Adjustment and C1.5 Phase Offset

Adjustment) between the input reference and the generated clocks.

2 - 0

C16POA10

to

000

C16 Phase Offset Adjustment. These three bits (most significant) in

conjunction with the eight bits of Phase Offset Register 1 allow for

phase shifting of all clocks and frame pulses that are derived from the

C16 clock (C8o, C4o, C2o, F16o, F8o, F0o). The phase offset is an

unsigned number in a range from 0 to 2047. Each increment by one

represents phase-offset advancement by 61.035 ns with respect to

the input reference signal. The phase offset is a two-byte value and it

must be written in one step increments. For example: four writes are

required to advance clocks by 244 ns from its current position of 22H:

write 23H, 24H, 25H, 26H. Writing numbers in reverse order will delay

clocks from their present position.

C16POA8

Table 8 - Phase Offset Register 2 (R/W)

Address: 07 H

Bit

Name

Functional Description

Default

7-0

C16POA7

to

C16 Phase Offset Adjustment. The eight least significant bits of the

phase offset adjustment word. See the Phase Offset Register 2 for

details.

0000

C16POA0

Table 9 - Phase Offset Register 1 (R/W)

Address: 0F H

Bit

Name

Functional Description

7-4

ID7 - 4

Device Identification Number. These four bits represent the device part number.

The ID number for ZL30402 is 0010.

3-0

ID3 - 0

Device Revision Number. These bits represent the revision number. Number

starts from 0001.

Table 10 - Device ID Register (R)

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Data Sheet

Address: 11 H

Bit

Name

Functional Description

Default

7

6

RSV

Reserved.

0

Reserved.

5-3

C1.5POA2 C1.5 Phase Offset Adjustment. These three bits allow for changing of

000

to

the phase offset of the C1.5o clock relative to the active input reference.

C1.5POA0 The phase offset is an unsigned number in a range from 0 to 7. Each

increment by one represents phase-offset advancement by 80.96 ns.

Example: Writing 010 advances C1.5 clock by 162 ns. Successive writing

of 001 delays this clock by 80.96 ns from its present position

2-0

RSV

Reserved.

000

Table 11 - Control Register 3 (R/W)

Address: 13 H

Bit

Name

Functional Description

Default

7

6

5

RSV

Reserved.

0

C16dis 16.384 MHz Clock Disable. When set high, this bit tristates the 16.384 MHz clock

0

output.

4

3

2

1

0

C8dis

C4dis

C2dis

8.192 MHz Clock Disable. When set high, this bit tristates the 8.192 MHz clock

output.

4.096 MHz Clock Disable. When set high, this bit tristates the 4.096 MHz clock

output.

2.048 MHz Clock Disable. When set high, this bit tristates the 2.048 MHz clock

output.

C1.5dis 1.544 MHz Clock Disable. When set high, this bit tristates the 1.544 MHz clock

output.

RSV

Reserved.

Table 12 - Clock Disable Register 1 (R/W)

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Data Sheet

Address: 14 H

Bit

Name

Functional Description

Default

7-5

4

RSV

Reserved.

000

0

F8odis

F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns

active high framing pulse output.

3

2

1

0

F0odis

F0o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 244 ns

0

active low framing pulse output.

F16odis F16o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 61 ns

active low framing pulse output.

C6dis

6.312 MHz Clock Disable. When set high, this bit tristates the 6.312 MHz clock

output.

0

C19dis 19.44 MHz Clock Disable. When set high, this bit tristates the 19.44 MHz clock

output.

Table 13 - Clock Disable Register 2 (R/W)

Address: 19 H

Bit Name

Functional Description

Default

7-3

2

RSV

Reserved.

00000

0

MHR

Manual Holdover Release. A change form 0 to 1 on the MHR bit will release the Core

PLL from Auto Holdover to Normal when automatic return from Holdover is disabled

(AHRD is set to 1). This bit is level sensitive and it must be cleared immediately after it

is set to 1 (next write operation). This bit has no effect if AHRD is set to 0.

1

0

AHRD Automatic Holdover Return Disable. When set high, this bit inhibits the Core PLL

from automatically switching back to Normal mode from Auto Holdover state when the

active Acquisition PLL regains lock to input reference. The active Acquisition PLL is the

Acquisition PLL to which the Core PLL is currently connected.

0

RSV

Reserved.

Table 14 - Core PLL Control Register (R/W)

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Data Sheet

Address: 1A H

Bit Name

Functional Description

Default

7-0 FPOA7 - 0 Fine Phase Offset Adjustment. This register allows phase offset adjustment of

00000

all output clocks and frame pulses (C16o, C8o, C4o, C2o, F16o, F8o, F0o, C155,

C19o, C34/44, C1.5o, C6o) relative to the active input reference. The adjustment

can be positive (advance) or negative (delay) with a nominal step size of 477 ps

(61.035 ns / 128). The rate of phase change is limited to 885 ns/s for FCS = 1 and

41 ns in 1.326 ms for FCS = 0 selections. The phase offset value is a signed 2’s

complement number e.g.:

000

Advance: +1 step = 01H, +2 steps = 02H, +127 steps = EFH

Delay: -1 step = FFH, -2 steps = FEH, -128 steps = 80H

Example: Writing 08H advances all clocks by 3.8 ns and writing F3H delays all

clocks

Table 15 - Fine Phase Offset Register (R/W)

Address: 20 H

Bit

Name

RSV

Functional Description

7-5

4-3

Reserved.

InpFreq1- Input Frequency. These two bits identify the Primary Reference Clock frequency.

0

- 00 = 19.44 MHz

- 01 = 8 kHz

- 10 = 1.544 MHz

- 11 = 2.048 MHz

2

1

RSV

PAH

Reserved.

Primary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL

enters Holdover mode. Holdover mode is entered when the reference frequency is

- lost completely

- drifts more than ±30 000 ppm off from the nominal frequency

- a large phase hit occurs on the reference clock.

0

PAFL

Primary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition

PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large

excursion of still tolerable input jitter.

Table 16 - Primary Acquisition PLL Status Register (R)

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Data Sheet

Address: 28 H

Bit

Name

RSV

Functional Description

7-5

Reserved.

4-3 InpFreq1-0 Input Frequency. These two bits identify the Secondary Reference Clock frequency.

- 00 = 19.44 MHz

- 01 = 8 kHz

- 10 = 1.544 MHz

- 11 = 2.048 MHz

2

1

RSV

SAH

Reserved.

Secondary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL

enters Holdover mode. Holdover mode is entered when reference frequency is:

- lost completely

- drifts more than ±30 000 ppm off the nominal frequency

- a large phase hit occurs on the reference clock.

0

SAFL

Secondary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition

PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large

excursion of still tolerable input jitter.

Table 17 - Secondary Acquisition PLL Status Register (R)

Address: 40 H

Bit Name

Functional Description

Default

7-0 MCFC31 - 24 Master Clock Frequency Calibration. This most significant byte contains the

31st to 24th bit of the Master Clock Frequency Calibration Register. See

Applications section 4.2 for a detailed description of how to calculate the MCFC

value.

00000

000

Table 18 - Master Clock Frequency Calibration Register 4 (R/W)

Address: 41 H

Bit

Name

Functional Description

Default

7-0

MCFC23 - 16

Master Clock Frequency Calibration. This byte contains the 23rd

00000

000

to 16th bit of the Master Clock Frequency Calibration Register.

Table 19 - Master Clock Frequency Calibration Register 3 (R/W)

Address: 42 H

Bit

Name

MCFC15 - 8

Functional Description

Default

7-0

Master Clock Frequency Calibration. This byte contains the 15th

00000

000

to 8th bit of the Master Clock Frequency Calibration Register.

Table 20 - Master Clock Frequency Calibration Register 2 (R/W)

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Data Sheet

Address: 43 H

Bit

Name

Functional Description

Default

7-0

MCFC7 - 0

Master Clock Frequency Calibration. This byte contains bit 7 to

00000

000

bit 0 of the Master Clock Frequency Calibration Register.

Table 21 - Master Clock Frequency Calibration Register 1 (R/W)

5.0 Applications

This section contains application specific details for Mode Switching and Master Clock Oscillator calibration.

5.1 ZL30402 Mode Switching - Examples

The ZL30402 is designed to transition from one mode to the other driven by the internal State Machine or by

manual control. The following examples present a couple of typical scenarios of how the ZL30402 can be employed

in network synchronization equipment (e.g., timing modules, line cards or stand alone synchronizers).

5.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL

The FREE-RUN to HOLDOVER to NORMAL transition represents a sequence of steps that will most likely occur

during a new system installation or scheduled maintenance of timing cards. The process starts from the RESET

state and then transitions to Free-run mode where the system (card) is being initialized. At the end of this process

the ZL30402 should be switched into Normal mode (with MS2, MS1 set to 00) instead of Holdover mode. If the

reference clock is available, the ZL30402 will transition briefly into Holdover to acquire synchronization and switch

automatically to Normal mode. If the reference clock is not available at this time, as it may happen during new

system installation, then the ZL30402 will stay in Holdover indefinitely. While in Holdover mode, the Core PLL will

continue generating clocks with the same accuracy as in the Free-run mode, waiting for a good reference clock.

When the system is connected to the network (or timing card switched to a valid reference) the Acquisition PLL will

quickly synchronize and clear its own Holdover status (PAH bit). This will enable the Core PLL to start the

synchronization process. After acquiring lock, the ZL30402 will automatically switch from Holdover into Normal

mode without system intervention. This transition to the Normal mode will be flagged by the LOCK status bit and

pin.

MS2, MS1 == 01 OR

RefSel change

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=1 &

NORMAL

(LOCKED)

00

MHR= 0 -->1 then 1-->0

{MANUAL}

Ref: OK &

Ref: OK --> FAIL &

MS2, MS1 == 00

{AUTO}

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=0

MS2, MS1 == 00

{AUTO}

MS2, MS1! = 10

RESET == 1

{AUTO}

AUTO

HOLD-

OVER

RefSel Change

FREE-

RUN

10

HOLD-

OVER

01

RESET

MS2, MS1 == 10 forces

unconditional return from

any state to Free-run

Figure 7 - Transition from Free-Run to Normal Mode

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Data Sheet

5.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL

The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses

its single reference clock unexpectedly or when it has two references but switching to the secondary reference is

not a desirable option (unless primary reference is lost without chance of quick recovery).

The sequence starts with the unexpected failure of a reference signal shown as transition OK --> FAIL in Figure 7

"Transition from Free-Run to Normal Mode" at a time when ZL30402 operates in Normal mode. This failure is

detected by the active Acquisition PLL based on the following FAIL criteria:

•

Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm

(±3%).

•

Single phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock.

After detecting any of these anomalies on a reference clock the Acquisition PLL will switch itself into Holdover mode

forcing the Core PLL to automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0

and HOLDOVER = 1.

MS2, MS1 == 01 OR

RefSel change

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=1 &

NORMAL

(LOCKED)

00

MHR=0 -->1 then 1-->0

{MANUAL}

Ref: OK &

Ref: OK --> FAIL &

MS2, MS1 == 00

{AUTO}

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=0

MS2, MS1 == 00

{AUTO}

MS2, MS1! = 10

RESET == 1

{AUTO}

AUTO

HOLD-

OVER

RefSel Change

FREE-

RUN

10

HOLD-

OVER

01

RESET

Automatic return to NORMAL: AHRD=0

OR

Manual return to NORMAL: AHRD=1 & MHR= 0-->1 then 1-->0

MS2, MS1 == 10 forces

unconditional return from

any state to Free-run

Figure 8 - Automatic Entry into Auto Holdover State and Eecovery into Normal mode

There are two possible returns to Normal mode after the reference signal is restored:

•

With the AHRD (Automatic Holdover Return Disable) bit set to 0. In this case the Core PLL will automatically

return to the Normal state after the reference signal recovers from failure. This transition is shown on the

state diagram as a FAIL --> OK change. This change becomes effective when the reference is restored and

there have been no phase hits detected for at least 64 clock cycles for 1.544/2.048 MHz reference, 512

clock cycles for 19.44 MHz reference and 1 clock cycle for 8 kHz reference.

•

With the AHRD bit set to high to disable automatic return to Normal and the change of MHR (Manual

Holdover Release) bit from 0 to 1 to trigger the transition from Auto Holdover to Normal. This option is

provided to protect the Core PLL against toggling between Normal and Auto Holdover states in case of an

intermittent quality reference clock. In the case when MHR has been changed when the reference is still not

available (Acquisition PLL in Holdover mode) the transition to Normal state will not occur and MHR 0 to 1

transition must be repeated.

This transition from Auto Holdover to Normal mode is performed as “hitless” reference switching.

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Data Sheet

5.1.3 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL

The NORMAL to AUTO-HOLDOVER to HOLDOVER to NORMAL sequence represents the most likely operation of

ZL30402 in Network Equipment.

The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of

reference. The failure conditions triggering this transition were described in section 4.1.2. When in the Auto

Holdover state, the ZL30402 can return to Normal mode automatically if the lost reference is restored and the

ADHR bit is set to 0. If the reference clock failure persists for a period of time that exceeds the system design limit,

the system control processor may initiate a reference switch. If the secondary reference is available the ZL30402

will briefly switch into Holdover mode and then transition to Normal mode.

MS2, MS1 == 01 OR

RefSel change

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=1 &

NORMAL

(LOCKED)

00

MHR= 0-->1 then 1-->0

{MANUAL}

Ref: OK &

Ref: OK --> FAIL &

MS2, MS1 == 00

{AUTO}

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=0

MS2, MS1 == 00

{AUTO}

MS2, MS1! = 10

RESET == 1

{AUTO}

AUTO

HOLD-

OVER

RefSel Change

FREE-

RUN

10

HOLD-

OVER

01

RESET

AHRD=0

(automatic return enabled)

MS2, MS1 == 10 forces

unconditional return from

any state to Free-run

Figure 9 - Entry into Auto Holdover state and recovery into Normal mode by switching

references

The new reference clock will most likely have a different phase but it may also have a different fractional frequency

offset. In order to lock to a new reference with a different frequency, the Core PLL may be stepped gradually

towards the new frequency. The frequency slope will be limited to less than 2.0 ppm/sec.

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Data Sheet

5.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL

The NORMAL to HOLDOVER to NORMAL mode switching is usually performed when:

•

A reference clock is available but its frequency drifts beyond some specified limit. In a Network Element with

stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than ±12 ppm

beyond its nominal frequency.

During routine maintenance of equipment when orderly switching of reference clocks is possible. This may

happen when synchronization references must be rearranged or when a faulty line card must be replaced.

MS2, MS1 == 01 OR

RefSel change

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=1 &

NORMAL

(LOCKED)

00

MHR= 0-->1 then 1-->0

{MANUAL}

Ref: OK &

Ref: OK --> FAIL &

MS2, MS1 == 00

{AUTO}

Ref: FAIL --> OK &

MS2, MS1 == 00 &

AHRD=0

MS2, MS1 == 00

{AUTO}

MS2, MS1! = 10

RESET == 1

{AUTO}

AUTO

HOLD-

OVER

RefSel Change

FREE-

RUN

10

HOLD-

OVER

01

RESET

MS2, MS1 == 10 forces

unconditional return from

any state to Free-run

Figure 10 - Manual Reference Switching

Two types of transitions are possible:

•

Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock

without changing the mode select inputs MS2, MS1 = 00 (Normal mode). This forces ZL30402 to

momentarily transition through the Holdover state and automatically return to Normal mode after

synchronizing to a secondary reference clock.

•

Manual transition, which involves switching into Holdover mode (MS2, MS1 = 01), changing references with

RefSel, and manual return to the Normal mode (MS2, MS1 = 00).

In both cases, the change of references provides “hitless” switching.

5.2 Programming Master Clock Oscillator Frequency Calibration Register

The Master Crystal Oscillator and its programmable Master Clock Frequency Calibration register (see Table 18,

Table 19, Table 20, and Table 21) have been described in Section 3.0 "Master Clock Frequency Calibration Circuit",

on page 16. Programming of this register should be done after system has been powered long enough for the

Master Crystal Oscillator to reach a steady operating temperature. When the temperature stabilizes the crystal

oscillator frequency should be measured with an accurate frequency meter. The frequency measurement should be

substituted for the f_offsetvariable in the following equation.

MCFC = 45036 * ( - f_offset

)

where f_offsetis the crystal oscillator frequency offset from the nominal 20 000 000 Hz frequency expressed in Hz.

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Data Sheet

Example 1: Calculate the binary value that must be written to the MCFC register to correct a -1ppm offset of the

Master Crystal Oscillator. The -1ppm offset for a 20 MHz frequency is equivalent to -20 Hz:

MCFC = 45036 * 20 = 900720 = 00 0D BE 70 H

Note: Correcting the -1ppm crystal offset requires +1ppm MCFC offset.

Example 2: Calculate the binary value that must be written to the MCFC register to correct a +2 ppm offset of the

Master Crystal Oscillator. The +2 ppm offset for 20 MHz frequency is equivalent to 40 Hz:

MCFC = 45036 * (-40) = -1801440 = FF E4 83 20 H

6.0 Characteristics

6.1 AC and DC Electrical Characteristics

Absolute Maximum Ratings*

Parameter

Symbol

Min.

Max.

Units

1

2

3

4

5

6

Supply voltage

V_DDR

V_PIN

I_PIN

-0.3

7.0

VDD+0.3

30

V

Voltage on any pin

Current on any pin

mA

°C

mW

V

Storage temperature

T_ST

-55

125

Package power dissipation (80 pin LQFP)

ESD rating

P_PD

V_ESD

1000

1500

* Voltages are with respect to ground (GND) unless otherwise stated

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions*

Characteristics

Supply voltage

Operating temperature

Symbol

Min.

Typ.

Max.

Units

1

2

V_DD

T_A

3.0

-40

3.3

25

3.6

V

+85

°C

* Voltages are with respect to ground (GND) unless otherwise stated

32

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

DC Electrical Characteristics*

Characteristics

Symbol

Min.

Max. Units

Notes

1

2

3

4

5

6

7

8

9

Supply current with C20i = 20 MHz

Supply current with C20i = 0V

CMOS high-level input voltage

CMOS low-level input voltage

Input leakage current

I_DD

I_DDS

V_CIH

V_CIL

I_IL

135

2.2

mA Outputs unloaded

0.7V_DD

V

0.3V_DD

15

V

µA V_I=V_DDor GND

High-level output voltage

V_OH

V_OL

V_OD

dV_OD

2.4

V

I_OH=10 mA

I_OL=10 mA

Low-level output voltage

0.4

450

50

LVDS: Differential output voltage

250

mV Z_T=100 Ω

LVDS: Change in VOD between

complementary output states

10

11

LVDS: Offset voltage

V_OS

1.125

260

1.375

50

V

Note 1

LVDS: Change in VOS between

complementary output states

dV_OS

mV

12

13

LVDS: Output short circuit current

LVDS: Output rise and fall times

I_OS

24

mA Pin short to GND

ps Note 2

T_RF

900

* Voltages are with respect to ground (GND) unless otherwise stated

Note 1:

Note 2:

V_OSis defined as (V_OH+ V_OL) / 2

Rise and fall times are measured at 20% and 80% levels.

AC Electrical Characteristics - Timing Parameter Measurement - CMOS Voltage Levels*

Characteristics

Symbol

Level

Units

1

2

3

Threshold voltage

V_T

0.5V_DD

0.7V_DD

0.3V_DD

V

Rise and fall threshold voltage High

Rise and fall threshold voltage Low

V_HM

V_LM

* Voltages are with respect to ground (GND) unless otherwise stated

* Supply voltage and operating temperature are as per Recommended Operating Conditions

* Timing for input and output signals is based on the worst case conditions (over T_Aand V_DD

)

Timing Reference Points

V_HM

V_T

ALL SIGNALS

V_LM

t_IF,t_OF

t_IR,t_OR

Figure 11 - Timing Parameters Measurement Voltage Levels

33

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

AC Electrical Characteristics - Microprocessor Timing*

Characteristics

Symbol

t_DSL

Min.

65

100

0

Max.

Units

ns

Notes

1

2

DS Low

t_DSH

t_CSS

ns

DS High

CS Setup

CS-Hold

R/W Setup

R/W Hold

3

ns

4

t_CSH

t_RWS

t_RWH

t_ADS

0

ns

5

20

5

ns

6

ns

7

10

ns

Address Setup

Address Hold

8

t_ADH

t_DRD

t_DRH

t_DWS

t_DWH

ns

9

60

10

ns

C_L=90 pF

Data Read Delay

Data Read Hold

Data Write Setup

Data Write Hold

10

11

12

ns

10

5

ns

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t_DSL

t_DSH

V_T

DS

CS

t_CSH

t_CSS

t_RWH

t_RWS

R/W

t_ADH

t

ADS

V_T

A0-A6

t_DRH

t_DRD

VALID DATA

D0-D7

READ

V_T

t_DWH

t_DWS

VALID DATA

D0-D7

V_T

WRITE

Figure 12 - Microport Timing

34

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

AC Electrical Characteristics - ST-BUS and GCI Output Timing*

Characteristics

Symbol

t_F16L

t_F16D

t_C16L

t_C16D

t_F8H

Min.

52

Max.

61

Units

ns

Notes

1

2

F16o pulse width low (nom 61ns)

F8o to F16o delay

19

27

3

19

35

C16o pulse width low

C16o to F8o delay

4

-2

6

5

118

54

128

65

F8o pulse width high (nom 122 ns)

C8o pulse width low

C8o to F8o delay

6

t_C8L

7

t_C8D

t_F0L

-2

6

8

236

115

114

2

248

123

126

8

F0o pulse width low (nom 244)

F8o to F0o delay

9

t_F0D

10

11

12

13

t_C4L

C4o pulse width low

C4o to F8o delay

t_C4D

t_C2L

235

-2

250

6

C2o pulse width low

C2o to F8o delay

t_C2D

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t_F16L

t_F16D

F16o

V_T

tc =125µs

t_C16L

t_C16D

V_T

C16o

t_F8H

tc = 61.04 ns

F8o

C8o

t_C8L

tc =125µs

t_C8D

V_T

t_F0L

t_F0D

tc = 122.07 ns

F0o

C4o

tc =125µs

t_C4L

t_C4D

V_T

tc = 244.14 ns

tc = 488.28 ns

t_C2L

t_C2D

C2o

Figure 13 - ST-BUS and GCI Output Timing

35

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

AC Electrical Characteristics - DS1, DS2 and C19o Clock Timing*

Characteristics

C6o pulse width low

Symbol

Min.

Max.

Units

Notes

1

2

3

4

5

6

t_C6L

t_C6D

70

80

315

55

19

8

83

95

ns

F8o to C6o delay

C1.5o pulse width low

C1.5o to F8o delay

C19o pulse width high

C19o to F8o delay

t_C1.5L

t_C1.5D

t_C19H

t_C19D

330

75

35

14

* Supply voltage and operating temperature are as per Recommended Operating Conditions

V_T

F8o

t_C6D

tc =125µs

t_C6L

C6o

tc = 158.43 ns

t_C1.5L

t

C1.5D

C1.5o

V_T

t_C19H

tc = 647.67 ns

tc = 51.44 ns

t_C19D

C19o

Figure 14 - DS1, DS2 and C19o Clock Timing

36

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

AC Electrical Characteristics - C155o and C19o Clock Timing

Characteristics

C155o pulse width low

Symbol

Min.

Max.

Units

Notes

1

2

3

4

t_C155L

t_CF19DLH

t_CF19DHL

t_CF19H

2.7

-10

-7

3.7

5

ns

C155o to C19o rising edge delay

C155o to C19o falling edge delay

C19 pulse width high

7

22

33

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

C155L

1

2

3

4

5

6

7

8

1

C155p

1.25V

tc = 6.43 ns

t

CF19DLH

t

CF19DHL

V

T

C19o

Dejittered

t

CF19H

tc = 51.44 ns

Note: Delay is measured from the rising edge of C155P clock (single ended) at 1.25V threshold

to the rising and falling edges of C19o clock at V threshold

T

Figure 15 - C155o and C19o Timing

37

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

AC Electrical Characteristics - Input to Output Phase Alignment (after RefAlign change from 1 to 0)*

Characteristics

Symbol

Min.

Max.

Units

Notes

1

2

8 kHz ref pulse width high

t_R8H

t_R8D

100

-15

100

210

100

192

20

ns

F8o to 8 kHz ref input delay

115

220

202

Note 1

3

1.544 MHz ref pulse width high

1.544 MHz ref input to F8o delay

2.048 MHz ref pulse width high

2.048 MHz ref input to F8o delay

19.44 MHz ref pulse width high

F8o to 19.44 MHz ref input delay

19.44 MHz ref input to C19o delay

Reference input rise and fall time

t_R1.5H

t_R1.5D

t_R2H

4

5

6

t_R2D

7

t_R19H

t_R19D

t_R19C19D

t_IR, t_IF

8

5

14

4

9

-4

10

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Note 1: For 8 kHz reference alignment refer to Application Note ZL-27 "Phase Alignment between 8 kHz Output and 8 kHz Input Reference on

ZL30402"

t

R8H

t

R8D

PRI/SEC

8 kHz

V_T

t

R1.5H

tc = 125 s

µ

t

R1.5D

PRI/SEC

V_T

1.544 MHz

t

R2H

tc = 647.67 ns

tc = 488.28 ns

t

R2D

PRI/SEC

2.048 MHz

t

R19D

t

R19H

PRI/SEC

V_T

19.44 MHz

tc = 51.44 ns

t

R19C19D

C19o

F8o

V_T

tc = 125 s

µ

Note: Delay time measurements are done with jitter free input reference signals

Figure 16 - Input Reference to Output Clock Phase Alignment

38

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

AC Electrical Characteristics - Input Control Signals*

Characteristics

Symbol

Min.

Max.

Units

Notes

1

2

Input controls Setup time

Input controls Hold time

t_S

t_H

100

ns

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

V_T

F8o

t

H

S

MS1, MS2

RefSel, FCS,

RefAlign

E3/DS3, E3DS3/OC3

Figure 17 - Input Control Signal Setup and Hold Time

AC Electrical Characteristics - E3 and DS3 Output Timing*

Characteristics

Symbol

Min.

Max.

Units

Notes

1

2

3

4

C44o clock pulse width high

C11o clock pulse width high

C34o clock pulse width high

C8.5o clock pulse width high

t_C44H

t_C11H

t_C34H

t_C8.5L

8

12

40

15

40

ns

12

7

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

C44H

V

C44o

C11o

T

tc = 22.35 ns

tc = 89.41 ns

t

C11H

V

t

C34H

C34o

tc = 29.10 ns

tc = 116.39 ns

t

C8.5H

C8.5o

V

T

Figure 18 - E3 and DS3 Output Timing

39

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

6.2 Performance Characteristics

Performance Characteristics*

Characteristics

Typical

Units

Notes

1

2

Holdover accuracy

Holdover stability

0.000001

NA

ppm

Determined by stability of

20MHz frequency source

3

Capture range

Lock time

±104

ppm

4

5

1.1Hz Filter

70

s

±4.6ppm frequency offset

0.1Hz Filter

Output Phase variation

6

7

8

Reference switching:

50

0

ns

PRI ⇐ SEC, SEC ⇐ PRI

Switching from Normal mode to Holdover

mode

Switching from Holdover mode to Normal

mode

50

Output Phase Slope

9

G.813 Option 1, GR-1244 stratum 3

41

1.326ms

ns/s

10 G.813 Option 2

GR-253 SONET stratum 3

GR-253 SONET SMC

885

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

40

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Performance Characteristics - Jitter Generation (Intrinsic Jitter) - Filtered*

Max

Characteristics

Notes

Ulpp

ns-pp

1

2

C1.5o (1.544 MHz)

0.004

0.017

0.014

0.024

0.021

0.026

0.018

0.035

0.025

0.038

0.037

0.032

0.023

0.106

0.091

0.145

0.127

2.75

1.80

0.86

0.73

1.24

1.08

1.34

0.94

1.78

1.30

1.11

1.06

0.72

0.51

0.68

0.58

0.93

0.82

Filter: 10 Hz - 40 kHz

C2o (2.048 MHz)

Filter: 20 Hz - 100 kHz

3

C19o (19.44 MHz) Dejittered

C19o (19.44 MHz)

Filter: 100 Hz - 400 kHz OC-1

Filter: 20 kHz - 400 kHz OC-1

Filter: 500 Hz - 1.3 MHz OC-3

Filter: 65 kHz - 1.3 MHz OC-3

Filter: 100 Hz - 400 kHz OC-1

Filter: 20 kHz - 400 kHz OC-1

Filter: 500 Hz - 1.3 MHz OC-3

Filter: 65 kHz - 1.3 MHz OC-3

Filter: 100 Hz - 800 kHz

4

5

6

7

8

C19o (19.44 MHz)

9

C19o (19.44 MHz)

10

11

12

13

14

15

16

17

18

C19o (19.44 MHz)

C34o (34.368 MHz)

Filter: 10 kHz - 800 kHz

C44o (44.736 MHz)

Filter: 10 Hz - 400 kHz

C44o (44.736 MHz)

Filter: 30 kHz - 400 kHz

C155o (155.52 MHz)

Filter: 100 Hz - 400 kHz OC-1

Filter: 20 kHz - 400 kHz OC-1

Filter: 500 Hz - 1.3 MHz OC-3

Filter: 65 kHz - 1.3 MHz OC-3

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

41

Zarlink Semiconductor Inc.

ZL30402

Data Sheet

Performance Characteristics - Jitter Generation (Intrinsic Jitter) - Unfiltered*

Characteristics

Max Ulpp Max ns-pp

Notes

1

2

0.010

0.020

0.033

0.042

0.028

0.031

0.090

0.038

0.059

0.092

0.110

0.170

NA

6.5

5.8

4.8

5.2

3.3

2.8

5.5

2.0

3.0

2.7

2.5

1.1

4.7

4.0

3.1

C1.5o (1.544 MHz)

C2o (2.048 MHz)

C4o- (4.096 MHz)

C6o (6.312 MHz)

C8o (8.192 MHz)

C8.5o (8.592 MHz)

C11o (11.184 MHz)

C16o- (16.384 MHz)

C19o (19.44 MHz)

C34o (34.368 MHz)

C44o (44.736 MHz)

C155o (155.52 MHz)

F0o (8 kHz)

3

4

5

6

7

8

9

Dejittered with Analog PLL

Analog PLL bypassed

10

11

12

13

14

15

16

NA

F8o (8 kHz)

NA

F16o (8 kHz)

* Supply voltage and operating temperature are as per Recommended Operating Conditions.

42

Zarlink Semiconductor Inc.


型号：	ZL30402_06
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	SONET/SDH Network Element PLL SONET / SDH网元PLL
文件：	总44页 (文件大小：471K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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