ZL30406QGG1 [ZARLINK]

SONET/SDH Clock Multiplier PLL; SONET / SDH时钟倍频PLL


型号：	ZL30406QGG1
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	SONET/SDH Clock Multiplier PLL SONET / SDH时钟倍频PLL ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式时钟
文件：	总21页 (文件大小：249K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZL30406

SONET/SDH Clock Multiplier PLL

Data Sheet

March 2006

Features

•

Meets jitter requirements of Telcordia GR-253-

CORE for OC-48, OC-12, and OC-3 rates

Ordering Information

ZL30406QGC

ZL30406QGG1

64 Pin TQFP

Trays

Meets jitter requirements of ITU-T G.813 for STM-

16, STM-4 and STM-1 rates

64 Pin TQFP* Trays, Bake & Drypack

*Pb Free Matte Tin

Provides four LVPECL differential output clocks at

77.76 MHz

-40°C to +85°C

Description

Provides a CML differential clock programmable

to 19.44 MHz, 38.88 MHz, 77.76 MHz and

155.52 MHz

The ZL30406 is an analog phase-locked loop (APLL)

designed to provide rate conversion and jitter

attenuation for SDH (Synchronous Digital Hierarchy)

and SONET (Synchronous Optical Network)

networking equipment. The ZL30406 generates very

low jitter clocks that meet the jitter requirements of

Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1

rates and ITU-T G.813 STM-16, STM-4 and STM-1

rates.

•

Provides a single-ended CMOS clock at

19.44 MHz

•

Provides enable/disable control of output clocks

Accepts a CMOS reference at 19.44 MHz

3.3 V supply

Applications

The ZL30406 accepts a CMOS compatible reference

at 19.44 MHz and generates four LVPECL differential

output clocks at 77.76 MHz, a CML differential

clock programmable to 19.44 MHz, 38.88 MHz,

77.76 MHz and 155.52 MHz and a single-ended

CMOS clock at 19.44 MHz. The output clocks can

be individually enabled or disabled.

•

SONET/SDH line cards

Network Element timing cards

C77oEN-A

C77oEN-B

LPF

C77o,C155o

C19o, C38o,

OC-CLKoEN

CML-P/N outputs

OC-CLKoP/N

Output

C19i

Frequency

& Phase

Detector

C77oP/N-A

C77oP/N-B

C77oP/N-C

C77oP/N-D

C19o

Loop

Filter

VCO

Interface

Circuit

19.44MHz

Reference &

Bias circuit

BIAS

C19oEN

C77oEN-C

C77oEN-D

FS1-2

VDD GND VCC

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL30406

Data Sheet

64 62 60 58 56 54 52 50

65 - EP_GND

GND

VCC1

VCC

GND

VCC

VDD

GND

VCC

GND

VDD

GND

C19o

VDD

GND

OC-CLKoN

OC-CLKoP

GND

VCC2

LPF

GND

ZL30406

BIAS

OC-CLKoEN

C77oEN-A

C77oEN-B

C77oEN-C

C77oEN-D

Figure 2 - TQFP 64 pin (Top View)

Change Summary

The following table captures the changes from the February 2005 issue.

Page

Item

Change

Updated Ordering Information.

Pin Description

Pin Description Table

Pin #

Name

Description

GND

VCC1

VCC

Ground. 0 volt.

Positive Analog Power Supply. +3.3 V ±10%

OC-CLKoN

OC-CLKoP

SONET/SDH Clock (CML Output). These outputs provide a programmable

differential CML clock at 19.44 MHz, 38.88 MHz, 77.76 MHz and 155.52 MHz.

The output frequency is selected with FS2 and FS1 pins.

GND

Ground. 0 volt

VCC2

Positive Analog Power Supply. +3.3 V ±10%

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

Pin Description Table (continued)

Pin #

Name

Description

LPF

Low Pass Filter (Analog). Connect to this pin external RC network (R_Fand C_F)

for the low pass filter.

GND

Ground. 0 volt

Bias. See Figure 11 for the recommended bias circuit.

BIAS

OC-CLKoEN

SONET/SDH Clock Enable (CMOS Input). If tied high this control pin enables

the OC-CLKoP/N differential driver. Pulling this input low disables the output

clock without deactivating differential drivers.

C77oEN-A

C77oEN-B

C77oEN-C

C77oEN-D

C77 Clock Output Enable A (CMOS Input). If tied high this control pin

enables the C77oP/N-A output clock. Pulling this input low disables the output

clock without deactivating differential drivers.

C77 Clock Output Enable B (CMOS Input). If tied high this control pin

enables the C77oP/N-B output clock. Pulling this input low disables the output

clock without deactivating differential drivers.

C77 Clock Output Enable C (CMOS Input). If tied high this control pin

enables the C77oP/N-C output clock. Pulling this input low disables the output

clock without deactivating differential drivers.

C77 Clock Output Enable D (CMOS Input). If tied high this control pin

enables the C77oP/N-D output clock. Pulling this input low disables the output

clock without deactivating differential drivers.

GND

VDD

Ground. 0 volt

Positive Digital Power Supply. +3.3 V ±10%

No internal bonding Connection. Leave unconnected.

Positive Digital Power Supply. +3.3 V ±10%

Internal Connection. Connect this pin to Ground (GND).

VDD

FS2

FS1

Frequency Select 2-1 (CMOS Input). These inputs program the clock

frequency on the OC-CLKo output. The possible output frequencies are

19.44 MHz (00), 38.88 MHz (01), 77.76 MHz (10), 155.52 MHz (11).

C19oEN

C19o Output Enable (CMOS Input). If tied high this control pin enables the

C19o output clock. Pulling this pin low forces output driver into a high

impedance state.

GND

C19i

Ground. 0 volt

C19 Reference Input (CMOS Input). This pin is a single-ended input reference

source used for synchronization. This pin accepts 19.44 MHz.

VDD

GND

Positive Digital Power Supply. +3.3 V ±10%

Ground. 0 volt

No internal bonding Connection. Leave unconnected.

Ground. 0 volt.

GND

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

Pin Description Table (continued)

Pin #

Name

Description

GND

VDD

C19o

Ground. 0 volt

Positive Digital Power Supply. +3.3 V ±10%

C19 Clock Output (CMOS Output). This pin provides a single-ended CMOS

clock at 19.44 MHz.

GND

Ground. 0 volt

No internal bonding Connection. Leave unconnected.

Ground. 0 volt

GND

Ground. 0 volt

No internal bonding Connection. Leave unconnected.

Ground. 0 volt

GND

VDD

GND

VCC

GND

VDD

VCC

GND

VCC

Positive Digital Power Supply. +3.3 V ±10%

Ground. 0 volt

Positive Analog Power Supply. +3.3 V ±10%

Ground. 0 volt

Positive Digital Power Supply. +3.3 V ±10%

Positive Analog Power Supply. +3.3 V ±10%

Ground. 0 volt

Positive Analog Power Supply. +3.3 V ±10%.

C77oN-D

C77oP-D

C77 Clock Output (LVPECL Output). These outputs provide a differential

LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated

to decrease supply current.

GND

VCC

Ground. 0 volt

Positive Analog Power Supply. +3.3 V ±10%.

C77oP-C

C77oN-C

C77 Clock Output (LVPECL Output). These outputs provide a differential

LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated

to decrease supply current.

GND

VCC

Ground. 0 volt

Positive Analog Power Supply. +3.3 V ±10%.

C77oN-B

C77oP-B

C77 Clock Output (LVPECL Output). These outputs provide a differential

LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated

to decrease supply current.

GND

VCC

Ground. 0 volt

Positive Analog Power Supply. +3.3 V ±10%.

C77oP-A

C77oN-A

C77 Clock Output (LVPECL Output). These outputs provide a differential

LVPECL clock at 77.76 MHz. Unused LVPECL port should be left unterminated

to decrease supply current.

GND

Ground. 0 volt

EP_GND

Exposed die Pad Ground. 0 volt (connect to GND)

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

1.0 Functional Description

The ZL30406 is an analog phased-locked loop which provides rate conversion and jitter attenuation for

SONET/SDH OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block diagram of the

ZL30406 is shown in Figure 1 and a brief description is presented in the following sections.

1.1 Frequency/Phase Detector

The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback

signal from the Frequency Divider circuit and provides an error signal corresponding to the frequency/phase

difference between the two. This error signal is passed to the Loop Filter circuit and averaged to control the

VCO frequency.

1.2 Loop Filter

The Loop Filter is a low pass filter. This low pass filter ensures that the network jitter requirements are met for an

input reference frequency of 19.44 MHz. The corner frequency of the Loop Filter is configurable with an external

capacitor and resistor connected to the LPF pin and ground as shown below.

ZL30406

LPF

Internal Loop

R_F

Filter

C_F

RF=8.2 kΩ, CF=470 nF

(for 14 kHz PLL bandwidth)

Figure 3 - External Loop Filter

1.3 VCO

The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter, and based on the

voltage of the error signal, generates a primary frequency. The VCO output is connected to the Output Interface

Circuit that divides VCO frequency and buffers generated clocks.

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

1.4 Output Interface Circuit

The output of the VCO is used by the Output Interface Circuit to provide four LVPECL differential clocks at

77.76 MHz, one programmable CML differential clock (19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz) controlled

with FS1-2 pins and a single-ended 19.44 MHz output clock. This block provides also a 19.44 MHz feedback clock

that closes PLL loop. Each output clock can be enabled or disabled individually with the associated Output Enable

pin.

Output Clocks

Output Enable Pins

C77oP/N-A

C77oP/N-B

C77oP/N-C

C77oP/N-D

OC-CLKoP/N

C19o

C77oEN-A

C77oEN-B

C77oEN-C

C77oEN-D

OC-CLKoEN

C19oEN

Table 1 - Output Enable Control

To reduce power consumption and achieve the lowest possible intrinsic jitter the unused output clocks must be

disabled. If any of the LVPECL outputs are disabled they must be left open without any terminations.

The output clock frequency of the OC-CLKo CML differential output clock is selected with FS1-2 pins as shown in

the following table.

OC-CLKo

FS2

FS1

Frequency

19.44 MHz

38.88 MHz

77.76 MHz

155.52 MHz

Table 2 - OC-CLKo Clock Frequency Selection

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

2.0 Applications

2.1 Ultra-Low Jitter SONET/SDH Equipment Clocks

The ZL30406 functionality and performance complements the entire family of the Zarlink’s advanced network

synchronization PLLs. Its superior jitter filtering characteristics exceed requirements of SONET/SDH optical

interfaces operating at OC-48/STM-16 rate (2.5 Gbit/s). The ZL30406 in combination with the MT90401 or the

ZL30407 (SONET/SDH Network Element PLLs) provides the core building blocks for high quality equipment clocks

suitable for network synchronization (see Figure 4).

155.52 MHz, 77.76 MHz

38.88 MHz, 19.44 MHz

OC-CLKo

C77oA

C77oB

C77oC

C77oD

C19o

CML

LVPECL

CMOS

77.76 MHz

19.44 MHz

C19i

ZL30406

LPF

R_F

C_F

C19o

CMOS

LVDS

19.44 MHz

PRI

C155o

155.52 MHz

34.368 MHz or 44.736 MHz

16.384 MHz

8.192 MHz

SEC

C34o/C44o CMOS

Synchronization

Reference

Clocks

C16o

C8o

CMOS

RefSel

MT90401

RefAlign

C6o

6.312 MHz

C4o

4.096 MHz

PRIOR

SECOR

C2o

2.048 MHz

C1.5o

F16o

F8o

ZL30407

1.544 MHz

8 kHz

LOCK

HOLDOVER

8 kHz

F0o

CMOS

20 MHz

OCXO

Data Port

Controller Port

Note: Only main functional connections are shown

Figure 4 - SONET/SDH Equipment Timing Card

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

The ZL30406 in combination with the MT9046 provides an optimum solution for SONET/SDH line cards (see Figure

5).

155.52 MHz, 77.76 MHz

38.88 MHz, 19.44 MHz

OC-CLKo

C77oA

C77oB

C77oC

C77oD

C19o

CML

LVPECL

CMOS

77.76 MHz

19.44 MHz

C19i

ZL30406

LPF

R = 680

Ω

R₁

C₁

C = 820 nF

C = 22 nF

C₂

C19o

C16o

C8o

CMOS

19.44 MHz

16.384 MHz

8.192 MHz

6.312 MHz

4.096 MHz

2.048 MHz

1.544 MHz

8 kHz

PRI

SEC

RSEL

LOCK

Synchronization

Reference

Clocks

C6o

C4o

MT9046

C2o

C1.5o

F16o

F8o

HOLDOVER

8 kHz

C20i

F0o

CMOS

20 MHz

TCXO

Hardware Control

Note: Only main functional connections are shown

Figure 5 - SONET/SDH Line Card

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

2.2 Recommended Interface Circuit

2.2.1 LVPECL to LVPECL Interface

The C77oP/N-A, C77oP/N-B, C77oP/N-B, and C77oP/N-D outputs provide differential LVPECL clocks at

77.76 MHz. The LVPECL output drivers require a 50 Ω termination connected to the VCC-2V source for each

output terminal at the terminating end as shown below. The terminating resistors should be placed as close as

possible to the LVPECL receiver.

+3.3 V

0.1 uF

VCC=+3.3 V

ZL30406

VCC

LVPECL

Receiver

Z=50 Ω

LVPECL

Driver

C77oP-A

C77oN-A

GND

Typical resistor values: R1 = 130 Ω, R2 =82 Ω

Figure 6 - LVPECL to LVPECL Interface

2.2.2 CML to CML Interface

The CMLP/N output provides a differential CML/LVDS compatible clock at 19.44 MHz, 38.88 MHz, 77.76 MHz,

155.52 MHz selected with FS1-2 pins. The output drivers require a 50 Ω load at the terminating end if the receiver

is CML type.

+3.3 V

Low Impedance

DC bias source

0.1 uF

VCC

ZL30406

CML

Receiver

50 Ω

0.1 uF

CML

Driver

Z=50 Ω

OC-CLKoP

OC-CLKoN

GND

Figure 7 - CML to CML Interface

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

2.2.3 CML to LVDS Interface

To configure the driver as an LVDS driver, external biasing resistors are required to set up the common mode

voltage as specified by ANSI/TIA/EIA-644 LVDS standard. The standard specifies the V_CM(common mode voltage)

as minimum 1.125 V, typical 1.2 V, and maximum 1.375 V. The following figure provides a recommendation for

LVDS applications.

+3.3 V

0.1 uF

VCC=+3.3 V

ZL30406

VCC

LVDS

10 nF

Receiver

CML

Driver

Z=50 Ω

OC-CLKoP

OC-CLKoN

100Ω

GND

Typical resistor values: R1 = 16 kΩ, R2 = 10 kΩ

Figure 8 - LVDS Termination

2.2.4 CML to LVPECL Interface

In the case when more than four 77.76 MHz clocks are required to drive LVPECL receivers then the unused OC-

CLKo clock (CML output) can be configured to output the 77.76 MHz clock and interface to the LVPECL receiver as

is shown in the Figure 9. The terminating resistors should be placed as close as possible to the LVPECL receiver.

+3.3 V

0.1 uF

VCC

VCC=+3.3 V

ZL30406

LVPECL

Receiver

10 nF

Z=50 Ω

CML

OC-CLKoP

Driver

77.76MHz

OC-CLKoN

GND

Typical resistor values: R1 = 82 Ω, R2 =130 Ω

Figure 9 - CML to LVPECL Interface

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

2.3 Tristating LVPECL Outputs

The ZL30406 has four differential 77.76 MHz LVPECL outputs, which can be used to drive four different OC-3/OC-

12/OC-48 devices such as framers, mappers and SERDES. In the case where fewer than four clocks are required,

a user can disable unused LVPECL outputs on the ZL30406 by pulling the corresponding enable pins low. When

disabled, voltage at the both pins of the differential LVPECL output will be pulled up to Vcc - 0.7 V.

For applications requiring the LVPECL outputs to be in a tri-state mode, external AC coupling capacitors can be

used as shown in Figure 10. Typically this might be required in hot swappable applications.

Resistors R1 and R2 are required for DC bias of the LVPECL driver. Capacitors C1 and C2 are used as AC

coupling capacitors. During disable mode (C77oEN pin pulled low) those capacitors present infinite impedance to

the DC signal and to the receiving device this looks like a tristated (High-Z) output. Resistors R3, R4, R5 and R6

are used to terminate the transmission line with 50 ohm impedance and to generate DC bias voltage for the

LVPECL receiver. If the LVPECL receiver has an integrated 50 ohm termination and bias source, resistors R3, R4,

R5 and R6 should not be populated.

C77oEN

3.3 V 3.3 V

ZL30406

127

0.1 u

Z=50

0.1 u

82.5

200

82.5

Figure 10 - Tristatable LVPECL Outputs

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

2.4 Power Supply and BIAS Circuit Filtering Recommendations

Figure 11 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter

performance. The level of required filtering is subject to further optimization and simplification. Please check

Zarlink’s web site for updates.

0.1uF

0.1 uF

GND

0.1uF

+3.3 V Power Rail

0.1 uF

Ferrite Bead

64 62 60 58 56 54 52 50

GND

VCC

VDD

4.7 Ω

VCC1

VCC

33 uF

0.1 uF

10 uF 0.1 uF

0.1 uF

GND

VCC

VDD

GND

VCC2

0.1 uF

ZL30406

33 uF

GND

220 Ω

BIAS

GND

0.1 uF

GND

VDD

GND

0.1 uF

18 20 22 24 26 28

0.1uF

Notes:

1. All the ground pins (GND) and the Exposed die Pad (metal area at the back of the package) are connected to the same

2. Select Ferrite Bead with I_DC> 400mA and R_DCin a range from 0.10Ω to 0.15Ω

Figure 11 - Power Supply and BIAS circuit filtering

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

3.0 Characteristics

Absolute Maximum Ratings^†

Characteristics

Sym

_DDR, V_CCR

V_PIN

Min.^‡

Max.^‡

Units

Supply voltage

TBD

-0.5

TBD

Voltage on any pin

V_CC+ 0.5

V_DD+ 0.5

Current on any pin

ESD Rating

I_PIN

V_ESD

T_ST

-0.5

-55

1500

125

1.8

Storage temperature

Package power dissipation

°C

P_PD

† Voltages are with respect to ground unless otherwise stated.

‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions^†

Characteristics

Sym.

Min.

Typ.^‡

Max.

Units

Notes

Operating Temperature

Positive Supply

T_OP

-40

3.0

+85

3.6

°C

V_DD, V_CC

V_{CC_VCO}

3.3

† Voltages are with respect to ground unless otherwise stated.

‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.

‡

DC Electrical Characteristics^†

Characteristics

Supply Current

Sym.

Min.

Typ.^‡

Max.

Units

Notes

_DD+I_CC

140

155

LVPECL, CML

drivers

disabled and

unterminated

Incremental Supply Current to

single LVPECL driver (driver

enabled and terminated, see

Figure 6)

I_LVPECL

Note 1,2

Incremental Supply Current to

CML driver (driver enabled and

terminated, see Figure 7)

I_CML

Note 3

CMOS: High-level input

voltage

V_IH

V_IL

I_IL

0.7V_DD

V_DD

CMOS: Low-level input

voltage

0.3V_DD

CMOS: Input leakage current,

C19i

V_I= V_DD

or 0V

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

DC Electrical Characteristics^†(continued)

Characteristics

Sym.

Min.

Typ.^‡

Max.

Units

Notes

CMOS: Input bias current for

pulled-down inputs: FS1, FS2,

C77oEN-A, C77oEN-C,

I_B-PU

300

V_I= V_DD

C77oEN-D, OC-CLKoEN

CMOS: Input bias current for

pulled-up inputs: , C77oEN-B,

C19o_EN

I_B-PD

V_I= 0V

CMOS: High-level output

voltage

V_OH

V_OL

T_R

2.4

I_OH= 8 mA

I_OL= 4 mA

18 pF load

Note 2

10 CMOS: Low-level output

voltage

0.4

3.3

1.4

11 CMOS: C19o output rise time

(18pF)

1.8

1.1

12 CMOS: C19o output fall time

(18pF)

T_F

13 LVPECL: Differential output

voltage

IV_{OD_LVPECL}I

V_{OS_LVPECL}

1.30

14 LVPECL: Offset voltage

Vcc-

1.38

Vcc-

1.27

Vcc-

1.15

Note 2

15 LVPECL: Output rise/fall times

T_RF

260

Note 2

Note 3

16 CML: Differential output

voltage

IV_{OD_CML}

0.70

17 CML: Offset voltage (Also

referred to as common mode

voltage)

V_{OS_CML}

Vcc-

0.58

Vcc-

0.54

Vcc-

0.50

Note 3

18 CML: Output rise/fall times

T_RF

120

† : Voltages are with respect to ground unless otherwise stated.

‡ :Typical figures are for design aid only: not guaranteed and not subject to production testing.

Note: Supply voltage and operating temperature are as per Recommended Operating Conditions

Note 1: The I_LVPECLcurrent is determined by termination network connected to LVPECL outputs. More than 25% of this current flows

outside the chip and it does not contribute to the internal power dissipation.

Note 2: LVPECL outputs terminated with Z_T= 50 Ω resistors biased to V_CC-2V (see Figure 6)

Note 3: CML outputs terminated with Z_T= 50 Ω resistors connected to low impedance DC bias voltage source (see Figure 7)

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

AC Electrical Characteristics^†- Output Timing Parameters Measurement Voltage Levels

Characteristics

Threshold Voltage

Sym

CMOS^‡

LVPECL

CML

Units

V_T-CMOS

V_T-LVPECL

V_T-CML

0.5V_DD

0.5V_{OD_LVPECL}

0.5V_{OD_CML}

Rise and Fall Threshold Voltage High

Rise and Fall Threshold Voltage Low

V_HM

0.7V_DD

0.3V_DD

0.8V_{OD_LVPECL}

0.8V_{OD_CML}

V_LM

0.2V_{OD_LVPECL}

0.2V_{OD_CML}

Timing Reference Points

V_HM

V_T

V_LM

All Signals

t_IF, t_OF

t_IR, t_OR

Figure 12 - Output Timing Parameter Measurement Voltage Levels

AC Electrical Characteristics^†- C19i Input to C19o and C77o Output Timing

Characteristics

C19i to C19o delay

C19i to C77oA delay

Sym.

Min.

Typ.^‡

Max.

Units

Notes

t_C19D

t_C77D

6.7

-4

†

Supply voltage and operating temperature are as per Recommended Operating Conditions.

‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.

C19i

V_T-CMOS

(19.44 MHz)

t_C19D

C19o

V_T-CMOS

(19.44 MHz)

t_C77D

C77oA

V_T-LVPECL

(77.76 MHz)

Note: All output clocks have nominal 50% duty cycle.

Figure 13 - C19i Input to C19o and C77o Output Timing

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

AC Electrical Characteristics^†- C19i Input to OC-CLKo Output Delay Timing (CML)

Characteristics

Sym.

Min.

Typ.^‡

Max. Units

Notes

C19i to OC-CLKo(19) delay

C19i to OC-CLKo(38) delay

C19i to OC-CLKo(77) delay

C19i to OC-CLKo(155) delay

t_OC-CLK19D

t_OC-CLK38D

t_OC-CLK77D

t_OC-CLK155D

3.2

3.0

2.7

2.4

†

Supply voltage and operating temperature are as per Recommended Operating Conditions.

‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.

V_T-CMOS

C19i

(19.44 MHz)

tOC-CLK19D

OC-CLKo(19)

V_T-CML

(19.44 MHz)

tOC-CLK38D

OC-CLKo(38)

(38.88 MHz)

tOC-CLK77D

tOC-CLK155D

OC-CLKo(77)

(77.76 MHz)

OC-CLKo(155)

V_T-CML

(155.52 MHz)

Note: All output clocks have nominal 50% duty cycle.

Figure 14 - C19i Input to OC-CLKo Output Timing

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

AC Electrical Characteristics^†- C77 Clocks Output Timing

Characteristics

C77oA to C77oB

Sym.

Min.

Typ.^‡

Max. Units

Notes

t_C77D-AB

t_C77D-AC

t_C77D-AD

100

C77oA to C77oC

C77oA to C77oD

†

Supply voltage and operating temperature are as per Recommended Operating Conditions.

‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.

C77oA

t_C77D-AB

C77oB

V_T-LVPECL

t_C77D-AC

C77oC

V_T-LVPECL

t_C77D-AD

C77oD

V_T-LVPECL

Note: All output clocks have nominal 50% duty cycle.

Figure 15 - C77oB, C77oC, C77oD Outputs Timing

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

Performance Characteristics - Functional- (V_CC= 3.3V ±10%; T_A= -40 to 85°C)

Characteristics

Pull-in range

Lock Time

Min.

Max.

Units

Notes

±1000

ppm

300

Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance - (V_CC= 3.3V ±10%; T_A=

40 to 85°C)

GR-253-CORE Jitter Generation Requirements

ZL30406 Jitter Generation Performance

Interface

(Category

II)

Jitter

Measurement

Filter

Equivalent

Limit in

limit in time

domain

Typ.^†

Max.^‡

Units

OC-48

STS-48

0.1 UIpp

40.2

4.02

161

16.9

2.1

9.0

1.3

ps_P-P

ps_RMS

ps_P-P

ps_RMS

12 kHz - 20 MHz

12 kHz - 5 MHz

0.01UI_RMS

0.1 UIpp

1.3

OC-12

STS-12

0.01UI_RMS

16.1

0.7

† Typical figures are for design aid only: not guaranteed and not subject to production testing.

‡ Loop Filter components: R_F=8.2 kΩ, C_F=470 nF

Performance Characteristics: Output Jitter Generation - ETSI EN 300 462-7-1 conformance - (V_CC= 3.3V ±10%;

T_A= -40 to 85°C)

EN 300 462-7-1 Jitter Generation Requirements

ZL30406 Jitter Generation Performance

Jitter

Equivalent

Limit in

Interface

Measurement

Filter

limit intime

domain

Typ.^†

Max.^‡

Units

STM-16

0.1 UIpp

40.2

1.0

12.6

1.5

ps_P-P

1 MHz to 20 MHz

5 kHz to 20 MHz

250 kHz to 5 MHz

1 kHz to 5 MHz

201

ps_RMS

ps_P-P

0.5UIpp

17.1

2.2

1.3

ps_RMS

ps_P-P

STM-4

0.1 UIpp

161

5.8

0.5 UIpp

0.46

0.9

ps_RMS

ps_P-P

804

29.8

3.2

2.4

ps_RMS

† Typical figures are for design aid only: not guaranteed and not subject to production testing.

‡ Loop Filter components: R_F=8.2 kΩ, C_F=470 nF

Zarlink Semiconductor Inc.

ZL30406

Data Sheet

Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2) - (V_CC= 3.3V

±10%; T_A= -40 to 85°C)

G.813 Jitter Generation Requirements

ZL30406 Jitter Generation Performance

Jitter

Limit in

Equivalent limit

in time domain

Interface

Measurement

Filter

Typ.^†

Max.^‡

Units

Option 1

STM-16

0.1 UIpp

40.2

1.0

12.6

1.5

ps_P-P

1 MHz to 20 MHz

201

ps_RMS

ps_P-P

0.5 UIpp

17.1

2.2

5 kHz to 20 MHz

250 kHz to 5 MHz

1.3

ps_RMS

ps_P-P

STM-4

0.1 UIpp

161

5.8

0.5 UIpp

0.46

0.9

ps_RMS

ps_P-P

804

29.8

3.2

1 kHz to 5 MHz

2.4

ps_RMS

Option 2

STM-16

STM-4

0.1 UIpp

40.2

16.9

2.1

9.0

1.3

ps_P-P

ps_RMS

ps_P-P

ps_RMS

12 kHz - 20 MHz

12 kHz - 5 MHz

0.1 UIpp

161

1.3

0.7

† Typical figures are for design aid only: not guaranteed and not subject to production testing.

‡ Loop Filter components: R_F=8.2 kΩ, C_F=470 nF

Zarlink Semiconductor Inc.

Package Code

Previous package codes

ISSUE

ACN

DATE

APPRD.

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TECHNICAL DOCUMENTATION - NOT FOR RESALE

ZL30406QGG1 [ZARLINK]

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