ZL30407/QCC_技术文档

ZL30407

SONET/SDH Network Element PLL

Data Sheet

April 2003

Features

•

Meets requirements of GR-253 for SONET

Stratum 3 and SONET Minimum Clocks (SMC)

Meets requirements of GR-1244 for Stratum 3

Ordering Information

•

Meets requirements of G.813 Option 1 and 2 for

SDH Equipment Clocks (SEC)

ZL30407/QCC 80 Pin LQFP

•

Generates clocks for ST-BUS, DS1, DS2, DS3,

OC-3, E1, E3, STM-1 and 19.44 MHz

-40°C to +85°C

Meets holdover accuracy of GR-1244 Stratum 3E

and ITU-T G.812 (better than 1x10 ^-12

)

Description

Continuously monitors both references for

frequency accuracy exceeding ±12 ppm

The ZL30407 is a Network Element Phase-Locked

Loop designed to synchronize SDH and SONET

systems. In addition, it generates multiple clocks for

legacy PDH equipment and provides timing for ST-BUS

and GCI backplanes.

•

Provides “hit-less” reference switching

Compensates for Master Clock Oscillator

accuracy

•

Detects frequency of both reference clocks and

synchronizes to any combination of 8 kHz, 1.544

MHz, 2.048 MHz and 19.44 MHz reference

frequencies.

The ZL30407 operates in NORMAL (LOCKED),

HOLDOVER and FREE-RUN modes to ensure that in

the presence of jitter, wander and interruptions to the

reference signals, the generated clocks meet

international standards. The filtering characteristics of

the PLL are hardware or software selectable and they

do not require any external adjustable components.

The ZL30407 uses an external 20 MHz Master Clock

Oscillator to provide a stable timing source for the

HOLDOVER operation.

•

Allows Hardware or Microprocessor control

Pin compatible with ZL30402 and MT90401.

Applications

•

Synchronization for SDH and SONET Network

Elements

•

Clock generation for ST-BUS and GCI backplanes

The ZL30407 operates from a single 3.3 V power

supply and offers a 5 V tolerant microprocessor

interface.

VDD GND

C20i

FCS

OE

C155P/N

C34/C44

C19o

Master Clock

Frequency

Calibration

APLL

Clock

C16o

Primary

Acquisition

PLL

PRI

PRIOR

C8o

C6o

C4o

Synthesizer

C2o

Core PLL

MUX

C1.5o

F16o

F8o

SEC

SECOR

Secondary

Acquisition

PLL

F0o

E3DS3/OC3

RefSel

E3/DS3

Tclk

Tdi

JTAG

HW

IEEE

Control State Machine

Microport

Tdo

Tms

1149.1a

RESET

Trst

A0-A6 D0-D7

M02

CS DS R/W

MS1 MS2 RefAlign LOCK HOLDOVER

Figure 1 - Functional Block Diagram

1

ZL30407

Data Sheet

Table of Contents

1.0 ZL30407 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.1 Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

2.1 Acquisition PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Core PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2.1 Digitally Controlled Oscillator (DCO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.2 Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.3 Lock Indicator (LOCK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.4 Reference Alignment (RefAlign) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Clock Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.1 Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.2 Output Clocks Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Control State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.1 Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.2 ZL30407 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4.3 State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.5 Master Clock Frequency Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.7 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.0 Hardware and Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.1 Hardware Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.1.1 Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.2 Status Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Software Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.2 ZL30407 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

4.1 ZL30407 Mode Switching - Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . 31

4.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL. . . . . . . . . . . . . . . . 32

4.1.3 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL . . . . 33

4.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL . . . . . . . . . . . . . . . . . . . . 34

4.2 Programming Master Clock Oscillator Frequency Calibration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

1.0 ZL30407 Pinout

1.1 Pin Connections

60

62

58

56

54

52

50

48

46

44

42

40

38

36

34

32

30

28

26

24

22

NC

SECOR

NC

OE

CS

Tdi

64

66

68

70

72

74

76

78

80

Trst

RESET

HW

Tclk

Tms

D0

Tdo

D1

D2

NC

GND

C155P

C155N

VDD

AVDD

GND

IC

D3

GND

IC

ZL30407

IC

VDD

D4

D5

GND

PRI

SEC

E3/DS3

E3DS3/OC3

D6

D7

R/W

A0

IC

2

4

6

8

10

12

14

16

18

20

Figure 2 - Pin Connections for 80-pin LQFP package

Zarlink Semiconductor Inc.

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ZL30407

Data Sheet

Pin Description

Pin #

Name

Description

1

IC

Internal Connection. Leave unconnected.

2-5

A1-A4

Address 1 to 4 (5 V tolerant input). Address inputs for the parallel processor

interface. Connect to ground in Hardware Control.

6

GND

Ground. Negative power supply.

7-8

A5-A6

Address 5 to 6 (5 V tolerant input). Address inputs for the parallel processor

interface. Connect to ground in Hardware Control.

9

FCS

Filter Characteristic Select (Input). In Hardware Control, FCS selects the

filtering characteristics of the ZL30407. Set this pin high to have a loop filter

corner frequency of 0.1 Hz and limit the phase slope to 885 ns/sec. Set this pin

low to have corner frequency of 1.5 Hz and limit the phase slope to 41 ns per

1.326 ms. Connect to ground in Software Control. This pin is internally pulled

down to GND.

10

11

12

VDD

GND

F16o

Positive Power Supply.

Ground.

Frame Pulse ST-BUS 8.192 Mb/s (CMOS tristate output). This is an 8 kHz,

61ns wide, active low framing pulse, which marks beginning of a ST-BUS

frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mb/s.

13

14

15

16

17

C16o

C8o

C4o

C2o

F0o

Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 8.192 Mb/s.

Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 8.192 Mb/s.

Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 2.048 Mb/s.

Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS

operation at 2.048 Mb/s.

Frame Pulse ST-BUS 2.048 Mb/s (CMOS tristate output). This is an 8 kHz,

244ns, active low framing pulse, which marks the beginning of a ST-BUS

frame. This is typically used for ST-BUS operation at 2.048 Mb/s and 4.096

Mb/s.

18

19

MS1

MS2

Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30407 mode of

operation (Normal, Holdover or Free-run), see Table 1 on page 19 for details.

The logic level at this input is sampled by the rising edge of the F8o frame

pulse. Connect to ground in Software Control.

Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30407 mode of

operation (Normal, Holdover or Free-run), see Table 1 on page 19 for details.

The logic level at this input is sampled by the rising edge of the F8o frame

pulse. Connect to ground in Software Control.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Pin Description (continued)

Pin #

Name

Description

20

F8o

Frame Pulse ST-BUS/GCI 8.192 Mb/s (CMOS tristate output). This is an 8

kHz, 122 ns, active high framing pulse, which marks the beginning of a

ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at 8.192

Mb/s. See Figure 15 for details.

21

22

E3DS3/OC3

E3/DS3

E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin

enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output

(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155

clock outputs (high impedance) and sets C34/C44 output to provide C34 and

C44 clocks. In Software Control connect this pin to ground.

E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin

is set high, logic low on E3/DS3 pin selects a 44.736 MHz clock on C34/C44

output and logic high selects 34.368 MHz clock. When E3DS3/OC3 pin is set

low, logic low on E3/DS3 pin selects 11.184 MHz clock on C34/C44 output and

logic high selects 8.592 MHz clock. Connect this input to ground in Software

Control.

23

24

SEC

PRI

Secondary Reference (Input). This input is used as a secondary reference

source for synchronization. The ZL30407 can synchronize to the falling edge

of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44

MHz clock. In Hardware Control, selection of the input reference is based upon

the RefSel control input. This pin is internally pulled up to VDD.

Primary Reference (Input). This input is used as a primary reference source

for synchronization. The ZL30407 can synchronize to the falling edge of the 8

kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz

clock. In Hardware Control, selection of the input reference is based upon the

RefSel control input. This pin is internally pulled up to VDD.

25

26

27

28

29

GND

IC

Ground.

Internal Connection. Leave unconnected.

Ground.

GND

AVDD

VDD

Positive Analog Power Supply. Connect this pin to VDD.

Positive Power Supply.

30

31

C155N

C155P

Clock 155.52MHz (LVDS output). Differential outputs for the 155.52 MHz

clock. These outputs are enabled by applying logic low to E3DS3/OC3 input or

they can be disabled by applying logic high. In the disabled state the LVDS

outputs are internally terminated with an integrated 100Ω resistor (two 50Ω

resistors connected in series). The middle point of these resistors is internally

biased from a 1.25V LVDS bias source.

32

33

GND

NC

Ground.

No internal bonding Connection. Leave unconnected.

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5

ZL30407

Data Sheet

Pin Description (continued)

Pin #

Name

Description

34

Tdo

IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on

this pin on the falling edge of Tclk clock. If not used, this pin should be left

unconnected.

35

Tms

IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the

state transition on the TAP controller. This pin is internally pulled up to VDD. If

not used, this pin should be left unconnected.

36

37

Tclk

Trst

IEEE1149.1a Test Clock Signal (5 V tolerant input). Input clock for the JTAG

test logic. If not used, this pin should be pulled up to VDD.

IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG

TAP controller. This pin should be pulsed low on power-up to ensure that the

device is in the normal functional state. This pin is internally pulled up to VDD.

If this pin is not used then it should be connected to GND.

38

Tdi

IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test

instructions and data. This pin is internally pulled up to VDD. If not used, this

pin should be left unconnected.

39

40

41

NC

No internal bonding Connection. Leave unconnected.

PRIOR

Primary Reference Out of Range (Output). Logic high at this pin indicates

that the primary reference is off the PLL centre frequency by more than

12ppm. When the accuracy of the 20 MHz clock oscillator is ±4.6 ppm, the

effective out of range limits of the PRIOR signal will be +16.6 ppm to -7.4 ppm

or +7.4 ppm to -16.6 ppm. These thresholds support Stratum 3 applications.

See PRIOR bit description in Status Register 1 for details.

42

43

C1.5o

C6o

Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz

DS1 rate clock.

Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz

DS2 rate clock.

44

45

46

IC

Internal Connection. Connect this pin to Ground.

Ground.

GND

C19o

Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz

clock.

47

RefSel

Reference Source Select (Input). A logic low selects the PRI (primary)

reference source as the input reference signal and logic high selects the SEC

(secondary) input. The logic level at this input is sampled at the rising edge of

F8o. This pin is internally pulled down to GND.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Pin Description (continued)

Pin #

Name

Description

48

RefAlign

Reference Alignment (Input). In Hardware Control holding this pin low for

250µs initiates phase realignment between the input reference and the

generated output clocks. This pin should be held low only to initiate a

reference realignment and then it should be taken high. Do not tie this pin low

permanently. This pin is internally pulled down to GND. Please see

Section 2.2.4, Reference Alignment (RefAlign) for more information

49

50

51

VDD

NC

Positive Power Supply.

No internal bonding Connection. Leave unconnected.

C20i

Clock 20 MHz (5 V tolerant input). This pin is the input for the 20MHz Master

Clock Oscillator. The clock oscillator should be connected directly (not AC

coupled) to the C20i input and it must supply clock with duty cycle that is not

worse than 40/60%.

52

53

GND

Digital Ground.

C34/C44

Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is

programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz

(for DS3 applications) when E3DS3/OC3 is high, or to be either 8.592 MHz or

11.184 MHz when E3DS3/OC3 is low. See description of E3DS3/OC3 and

E3/DS3 inputs for details. In Software Control the functionality of this output is

controlled by Control Register 2 (Table 7 "Control Register 2 (R/W)").

54

55

VDD

Positive Power Supply.

HOLDOVER

Holdover Indicator (CMOS output). Logic high at this output indicates that the

device is in Holdover mode.

56

57

NC

No internal bonding Connection. Leave unconnected.

LOCK

Lock Indicator (CMOS output). Logic high at this output indicates that

ZL30407 is locked to the input reference. See LOCK bit description in Status

Register 1 for details.

58

59

NC

DS

No internal bonding Connection. Leave unconnected.

Data Strobe (5 V tolerant input). This input is the active low data strobe of the

processor interface.

60

61

IC

Internal Connection. Connect to ground.

SECOR

Secondary Reference Out of Range (Output). Logic high at this pin indicates

that the secondary reference is off the PLL center frequency by more than 12

ppm. When the accuracy of the 20 MHz clock oscillator is ±4.6 ppm, the

effective out of range limits of the SECOR signal will be +16.6 ppm to -7.4 ppm

or +7.4 ppm to -16.6 ppm. These thresholds support Stratum 3 applications.

See SECOR bit description in Status Register 1 for details.

62

OE

Output Enable (Input). Logic high on this input enables C19, F16, C16, C8,

C6, C4, C2, C1.5, F8 and F0 signals. Pulling this input low will force the output

clocks pins into a high impedance state.

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7

ZL30407

Data Sheet

Pin Description (continued)

Pin #

Name

Description

63

CS

Chip Select (5V tolerant input). This active low input enables the

microprocessor interface. When CS is set to high, the microprocessor interface

is idle and all Data Bus I/O pins will be in a high impedance state.

64

RESET

RESET (5V tolerant input). The ZL30407 must be reset after power-up in order

to set internal registers into a default state. The internal reset is performed by

forcing RESET pin low for a minimum of 1 µs after the C20 Master Clock is

applied to pin C20i. This operation forces the ZL30407 internal state machine

into a RESET state for a duration of 625 µs.

65

HW

Hardware/Software Control (Input). If this pin it tied low, the ZL30407 is

controlled via the microport. If it is tied high, the ZL30407 is controlled via the

control pins MS1, MS2, FCS, RefSel, RefAlign, E3/DS3 and E3DS3/OC3.

66-69

D0 - D3

Data 0 to Data 3 (5 V tolerant three-state I/O). These ports combined with D4 -

D7 ports form the bi-directional data bus of the microprocessor interface (D0 is

the least significant bit).

70

71

GND

IC

Ground.

Internal Connection (Input). Connect this pin to ground.

Positive Power Supply.

72

IC

73

VDD

D4 - D7

74 - 77

Data 4 to Data 7 (5 V tolerant three-state I/O). These ports combined with D0 -

D3 ports form the bi-directional data bus of the processor interface (D7 is the

most significant bit).

78

R/W

Read/Write Strobe (5 V tolerant input). This input controls the direction of the

data bus D[0-7] during a microprocessor access. When R/W is high, the

parallel processor is reading data from the ZL30407. When low, the parallel

processor is writing data to the ZL30407.

79

80

A0

IC

Address 0 (5 V tolerant input). Address input for the microprocessor interface.

A0 is the least significant input.

Internal Connection (Input). Connect this pin to ground.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

2.0 Functional Description

The ZL30407 is a Network Element PLL designed to provide timing for SDH and SONET equipment conforming to

ITU-T, ANSI, ETSI and Telcordia recommendations. In addition, it generates clocks for legacy PDH equipment

operating at DS1, DS2, DS3, E1, and E3 rates. The ZL30407 provides clocks for industry standard ST-BUS and

GCI backplanes, and it also supports H.110 timing requirements. The functional block diagram of the ZL30407 is

shown in Figure 1 "Functional Block Diagram" and its operation is described in the following sections.

2.1 Acquisition PLLs

The ZL30407 has two Acquisition PLLs for monitoring availability and quality of the Primary (PRI) and Secondary

(SEC) reference clocks. Each Acquisition PLL operates independently and locks to the falling edges of one of the

three input reference frequencies: 8 kHz, 1.544 MHz, 2.048 MHz or to the rising edge of 19.44 MHz. The reference

frequency can be determined from reading the Acquisition PLL Status Register bits InpFreq1 and InpFreq0 (see

Table 16 "Primary Acquisition PLL Status Register (R)" and Table 17 "Secondary Acquisition PLL Status Register

(R)").

The Primary and Secondary Acquisition PLLs are designed to provide status information that identifies two levels of

reference clock quality. For clarity, only the Primary Acquisition PLL is referenced in the text, but the same applies

to the Secondary Acquisition PLL.

-

Reference frequency drifts more than ±12 ppm. In response, the PRIOR (Primary Reference Out of Range)

bit and pin change state to high, in conformance with Stratum 3 requirements defined in GR-1244-CORE.

The PRIOR bit is part of Status Register 1 (Table 6 "Status Register 1 (R)").

Reference frequency drifted more than ±30000 ppm or that the reference has been lost completely. In

response, the Primary Acquisition PLL enters its own Holdover mode and indicates this by asserting the

HOLDOVER bit in the Primary Acquisition PLL Status Register (Table 16 "Primary Acquisition PLL Status

Register (R)"). Entry into Holdover forces the Core PLL into the Auto Holdover state.

-

Outputs of both Acquisition PLLs are connected to a multiplexer (MUX), which allows selection of the desired

reference. This multiplexer channels binary words to the Core PLL digital phase detector (instead of analog signals)

which eliminates quantization errors and improves phase alignment accuracy. The bandwidth of the Acquisition

PLL is much wider than the bandwidth of the following Core PLL. This feature allows cascading Acquisition and

Core PLLs without altering the transfer function of the Core PLL.

2.2 Core PLL

The most critical element of the ZL30407 is its Core PLL, which generates a phase-locked clock, filters jitter and

wander and suppresses input phase transients. All of these features are in agreement with international standards:

-

G.813 Option 1 and 2 clocks for SDH equipment

GR-253 for SONET Stratum 3 and SONET Minimum Clocks (SMC)

GR-1244 for Stratum 3 Clock

The Core PLL supports three mandatory modes of operation: Free-run, Normal (Locked) and Holdover. Each of

these modes places specific requirements on the building blocks of the Core PLL.

-

In Free-run Mode, the Core PLL derives its output clock from the 20 MHz Master Clock Oscillator connected

to pin C20i. The stability of the generated clocks remain the same as the stability of the Master Clock

Oscillator.

-

In Normal Mode, the Core PLL locks to one of the Acquisition PLLs. Both Acquisition PLLs provide

preprocessed phase data to the Core PLL including detection of reference clock quality.

In Holdover mode, the Core PLL generates a clock based on data collected from past reference signals. The

Core PLL enters Holdover mode if the attached Acquisition PLL switches into the Holdover state or under

external software or hardware control.

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ZL30407

Data Sheet

Some of the key elements of the Core PLL are shown in Figure 3 "Core PLL Functional Block Diagram".

LOCK

HOLDOVER

RefAlign

FSM

MUX

Phase

Filters

DCO

Detector

FCS

Figure 3 - Core PLL Functional Block Diagram

2.2.1 Digitally Controlled Oscillator (DCO)

The DCO is an arithmetic unit that continuously generates a stream of numbers that represent the phase-locked

clock. These numbers are passed to the Clock Synthesizer (see section 2.3) where they are converted into

electrical clock signals of various frequencies.

2.2.2 Filters

In Normal mode, the clock generated by the DCO is phase-locked to the input reference signal and band-limited to

meet network synchronization standards. The ZL30407 provides two software programmable (FCS bit in Control

Reg 1) and two hardware selectable (FCS pin) filtering options. The filtering characteristics are similar to a first

order low pass filter with corner frequencies that support international standards:

-

0.1 Hz filter: supports G.813 Option 2 Clock, GR-253 SONET Stratum 3 and GR-253 SONET Minimum clock

1.5 Hz filter: supports G.813 Option 1 and GR-1244 Stratum 3 clock

2.2.3 Lock Indicator (LOCK)

The ZL30407 is considered locked (LOCK=1) when the residual phase movement after declaring locked condition

does not exceed 20 ns; as required by standard wander generation MTIE and TDEV tests. To ensure the integrity of

the LOCK status indication, the ZL30407 holds LOCK bit/pin low for a minimum of 65 sec in the 0.1 Hz filtering

mode and 10 sec in the 1.5 Hz filtering mode.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

2.2.4 Reference Alignment (RefAlign)

When the ZL30407 finishes locking to a reference an arbitrary phase difference will remain between its output

clocks and its reference; this phase difference is part of the normal operation of the ZL30407. If so desired, the

output clocks can be brought into phase alignment with the PLL reference (see Figure 18 on page 42) by using the

RefAlign control bit/pin.

Using RefAlign with 1.544 MHz, 2.048 MHz or 19.44 MHz Reference

If the ZL30407 is locked to a 1.544 MHz, 2.048 MHz or 19.44 MHz reference, then the output clocks can be brought

into phase alignment with the PLL reference by using the RefAlign control bit/pin according to one of the

procedures below:

For 0.1 Hz filtering applications (FCS = high)

-

Wait until the ZL30407 LOCK indicator is high, indicating that it is locked

Pull FCS low

Pull Ref/Align low

Hold RefAlign low for 250 µs

Pull RefAlign high

Wait until the LOCK indicator goes high

Pull FCS high

This sequence re-initiates the ZL30407 locking procedure; the LOCK indicator will go low 1 sec after RefAlign is

pulled low and it will remain low for 10 sec.

For 1.5 Hz filtering applications (FCS = low)

-

Wait until the ZL30407 LOCK indication is high, indicating that it is locked

Pull RefAlign low

Hold RefAlign low for 250 µs

Pull RefAlign high

This sequence re-initiates the ZL30407 locking procedure; the LOCK indicator will go low 1 sec after RefAlign is

pulled low and it will remain low for 10 sec.

Using RefAlign with an 8 kHz Reference

If the ZL30407 is locked to an 8 kHz reference, then the output clocks can be brought into phase alignment with the

PLL reference by using the RefAlign control bit/pin according to one of the procedures below:

For 0.1 Hz filtering applications (FCS = high)

-

Wait until the ZL30407 LOCK indicator is high, indicating that it is locked

Pull FCS low

Pull Ref/Align low

Hold RefAlign low for 10 sec

Pull RefAlign high

Wait until the LOCK indicator goes high

Pull FCS high

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11

ZL30407

Data Sheet

This sequence re-initiates the ZL30407 locking procedure; the LOCK indicator will go low 1 sec after RefAlign is

pulled low and it will remain low to 10 sec.

For 1.5 Hz filtering applications (FCS = low)

-

Wait until the ZL30407 LOCK indication is high, indicating that it is locked

Pull RefAlign low

Hold RefAlign low for 10 s

Pull RefAlign high

This sequence re-initiates the ZL30407 locking procedure; the LOCK indicator will go low 1 sec after RefAlign is

pulled low and it will remain low for 10 sec.

2.3 Clock Synthesizer

The output of the Core PLL is connected to the Clock Synthesizer that generates twelve clocks and three frame

pulses.

2.3.1 Output Clocks

The ZL30407 provides the following clocks (see Figure 15 "ST-BUS and GCI Output Timing", Figure 16 "DS1, DS2

and C19o Clock Timing", Figure 17 "C155o and C19o Timing", and Figure 20 "E3 and DS3 Output Timing" for

details):

-

C1.5o

C2o

:

1.544 MHz clock with nominal 50% duty cycle

2.048 MHz clock with nominal 50% duty cycle

4.096 MHz clock with nominal 50% duty cycle

6.312 MHz clock with nominal 50% duty cycle

8.192 MHz clock with nominal 50% duty cycle

8.592 MHz clock with duty cycle from 30 to 70%.

11.184 MHz clock with duty cycle from 30 to 70%.

16.384 MHz clock with nominal 50% duty cycle

19.44 MHz clock with nominal 50% duty cycle

34.368 MHz clock with nominal 50% duty cycle

44.736 MHz clock with nominal 50% duty cycle

155.52 MHz clock with nominal 50% duty cycle.

C4o

C6o

C8o

C8.5o

C11o

C16o

C19o

C34o

C44o

C155

The ZL30407 provides the following frame pulses (see Figure 15 "ST-BUS and GCI Output Timing" for details). All

frame pulses have the same 125µs period (8kHz frequency):

-

F0o : 244 ns wide, logic low frame pulse

F8o : 122 ns wide, logic high frame pulse

F16o : 61 ns wide, logic low frame pulse

The combination of two pins, E3DS3/OC3 and E3/DS3, controls the selection of different clock configurations.

When the E3DS3/OC3 pin is high then the C155o (155.52 MHz) clock is disabled and the C34/44 clock is output at

its nominal frequency. The logic level on the E3/DS3 input determines if the output clock on the C34/44 output is

34.368 MHz (E3) or 44.736 MHz (DS3) (see Figure 4, “C34/C44, C155o Clock Generation Options,” on page 13 for

details).

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

C34/44 Output

C155 Output

E3DS3/OC3

0

1

0

1

0

11.184 44.736

155.52

active

disabled

1

8.592

34.368

Figure 4 - C34/C44, C155o Clock Generation Options

All clocks and frame pulses (except the C155) are output with CMOS logic levels. The C155 clock (155.52 MHz) is

output in a standard LVDS format.

2.3.2 Output Clocks Phase Adjustment

The ZL30407 provides three control registers dedicated to programming the output clock phase offset. Clocks

C16o, C8o, C4o and C2o and frame pulses F16o, F8o, F0o are derived from 16.384 MHz and can be jointly shifted

with respect to an active reference clock by up to 125 µs with a step size of 61 ns. The required phase shift of

clocks is programmable by writing to the Phase Offset Register 2 ("Table 8") and to the Phase Offset Register 1

("Table 9"). The C1.5o clock can be shifted as well in step sizes of 81 ns by programming C1.5POA bits in Control

Register 3 ("Table 11").

The coarse phase adjustment is augmented with a very fine phase offset control on the order of 477 ps per step.

This fine adjustment is programmable by writing to the Fine Phase Offset Register (Table 15 "Fine Phase Offset

Register (R/W)"). The offset moves all clocks and frame pulses generated by ZL30407 including the C155 clock.

2.4 Control State Machine

2.4.1 Clock Modes

Any Network Element that operates in a synchronous network must support three Clock Modes: Free-run, Normal

(Locked) and Holdover. A network clock will usually operate in Normal mode, the Holdover and Free-run modes are

used to cope with impairments in the synchronization hierarchy. Requirements for Clock Modes are defined in the

international standards e.g.: G.813, GR-1244-CORE and GR-253-CORE and they are enforced by network

operators. The ZL30407 supports all clock modes and each of these modes have a corresponding state in the

Control State Machine.

2.4.2 ZL30407 State Machine

The ZL30407 Control State Machine is a combination of many internal states supporting the three mandatory clock

modes. A simplified version of this state machine is shown in Figure 5; it includes the mandatory states: Free-run,

Normal and Holdover. These three states are complemented by two additional states: Reset and Auto Holdover,

which are critical to the ZL30407 operation under changing external conditions.

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ZL30407

Data Sheet

Ref: FAIL-->OK AND

MS2,MS1=00 AND

AHRD=1 AND MHR=1

{MANUAL}

MS2,MS1=01 OR

RefSel change

NORMAL

00

OR

Ref: FAIL-->OK AND

MS2,MS1=00 AND

AHRD=0

Ref: OK AND

MS2,MS1=00

{AUTO}

Ref: OK-->FAIL AND

MS2,MS1=00

{AUTO}

MS2,MS1=00

{AUTO}

RESET=1

OR

MS2,MS1=01

HOLD-

OVER

01

AUTO

HOLD-

OVER

FREE-

RESET

RUN

10

RefSel Change

AHRD=1 AND

MHR=0

OR

MS2,MS1=01

MS2,MS1=10 forces

unconditional return from

any state to Free-run

Notes:

STATE

MS2,MS1

{AUTO} - Automatic internal transition

{MANUAL} - User initiated transition

--> - External transition

Figure 5 - ZL30407 State Machine in Software Control configuration

Reset State

The Reset State must be entered when ZL30407 is powered-up. In this state, all arithmetic calculations are halted,

clocks are stopped, the microprocessor port is disabled and all internal registers are reset to their default values.

The Reset state is entered by pulling the RESET pin low for a minimum of 1µs. When the RESET pin is pulled back

high, internal logic starts a 625µs initialization process before switching into the Free-run state (MS2, MS1 = 10).

Free-Run State (Free-Run mode)

The Free-run state is entered when synchronization to the network is not required or is not possible. Typically this

occurs during installation, repairs or when a Network Element operates as a master node in an isolated network. In

the Free-run state, the accuracy of the generated clocks is determined by the accuracy and stability of the ZL30407

Master Crystal Oscillator. When equipment is installed for the first time (or periodically maintained) the accuracy of

the Free-run clocks can be adjusted to within 1x10^-12by setting the offset frequency in the Master Clock Frequency

Calibration Register.

Normal State (Normal Mode or Locked Mode)

The Normal State is entered when a good quality reference clock from the network is available for synchronization.

The ZL30407 automatically detects the frequency of the reference clock (8 kHz, 1.544 MHz, 2.048 MHz or 19.44

MHz) and sets the LOCK status bit and pin high after acquiring synchronization. In the Normal state all generated

clocks (C1.5o, C2o, C4o, C6o, C8o, C16o, C19o, C34/C44 and C155) and frame pulses (F0o, F8o, F16o) are

derived from network timing. To guarantee uninterrupted synchronization, the ZL30407 has two Acquisition PLLs

that continuously monitor the quality of the incoming reference clocks. This dual architecture enables quick

replacement of a poor or failed reference and minimizes the time spent in other states.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Holdover State (Holdover Mode)

The Holdover State is typically entered for short durations while network synchronization is temporarily disrupted. In

Holdover Mode, the ZL30407 generates clocks, which are not locked to an external reference signal but their

frequencies are based on stored coefficients in memory that were determined while the PLL was in Normal Mode

and locked to an external reference signal.

The initial frequency offset of the ZL30407 in Holdover Mode is 1x10^-12. This is more accurate than Telcordia’s

GR-1244-CORE Stratum 3E requirement of +1x10^-9. Once the ZL30407 has transitioned into Holdover Mode,

holdover stability is determined by the stability of the 20 MHz Master Clock Oscillator. Selection of the oscillator

requires close examination of the crystal oscillator temperature sensitivity and frequency drift caused by aging.

Auto Holdover State

The Auto Holdover state is a transitional state that the ZL30407 enters automatically when the active reference fails

unexpectedly. When the ZL30407 detects loss of reference it sets the HOLDOVER status bit and waits in Auto

Holdover state until the failed reference recovers. The HOLDOVER status may alert the control processor about the

failure and in response the control processor may switch to the secondary reference clock. The Auto Holdover and

Holdover States are internally combined together and they are output as a HOLDOVER status on pin 55 and bit 4 in

Status Register 1 (Table 6 on page 23).

In less demanding clocking arrangements (e.g. Line Cards), the ZL30407 can be configured to operate in the

Hardware Control mode which does not require a microprocessor. Under the Hardware Control mode the ZL30407

maintains most of its State Machine functionality as is shown in Figure 6.

MS2,MS1=01 OR

RefSel change

NORMAL

Ref: FAIL-->OK AND

00

MS2,MS1=00 AND

{AUTO}

Ref: OK AND

MS2,MS1=00

{AUTO}

Ref: OK-->FAIL AND

MS2,MS1=00

{AUTO}

MS2,MS1=00

OR

RESET=1

MS2,MS1=01

AUTO

FREE-

HOLD-

OVER

01

HOLD-

OVER

RESET

RUN

10

RefSel Change

OR

MS2,MS1=01

MS2,MS1=10 forces

unconditional return from

any state to Free-run

Figure 6 - ZL30407 State Machine in Hardware Control configuration

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15

ZL30407

Data Sheet

2.4.3 State Transitions

In a typical Network Element application, the ZL30407 will most of the time operate in Normal mode (MS2, MS1 ==

00) generating synchronous clocks. Its two Acquisition PLLs will continuously monitor the input references for signs

of degraded quality and output status information for further processing. The status information from the Acquisition

PLLs and the CORE PLL combined with status information from line interfaces and framers (as listed below) forms

the basis for creating reliable network synchronization.

-

Acquisition PLLs (PRIOR, SECOR, PAH, PAFL, SAH, SAFL)

Core PLL (LOCK, HOLDOVER, FLIM)

Line interfaces (e.g. LOS - Loss of Signal, AIS - Alarm Indication Signal)

Framers (e.g. LOF - Loss of frame or Synchronization Status Messages carried over SONET S1 byte or

ESF-DS1 Facility Data Link).

The ZL30407 State Machine is designed to perform some transitions automatically, leaving other less time

dependent tasks to the control processor. The state machine includes two stimulus signals which are critical to

automatic operation: “OK --> FAIL” and “FAIL --> OK” that represent loss (and recovery) of reference signal or its

drift by more than ±30000 ppm. Both of them force the Core PLL to transition into and out of the Auto Holdover

state. The ZL30407 State Machine may also be driven by controlling the mode select pins or bits MS2, MS1. In

order to avoid network synchronization problems, the State Machine has built-in basic protection that does not allow

switching the Core PLL into a state where it cannot operate correctly e.g. it is not possible to force the Core PLL into

Normal mode when all references are lost.

2.5 Master Clock Frequency Calibration Circuit

In an ordinary timing generation module, the Free-run mode accuracy of generated clocks is determined by the

accuracy of the Master Crystal Oscillator. If the Master Crystal Oscillator has a manufacturing tolerance of +/-4.6

ppm, the generated clocks will have no better accuracy.

The ZL30407 eliminates Crystal Oscillator tolerance problem by providing a programmable Master Clock

Frequency Calibration circuit, which can reduce oscillator manufacturing tolerance to near zero. However this

feature does not eliminate oscillator frequency drift. The value stored in the Master Clock Calibration Register can

be periodically updated to compensate for oscillator frequency drift due to ageing or due to temperature effects. The

compensation value for the Master Clock Calibration Register (MCFC3 to MCFC0) can be calculated from the

following equation:

MCFC = 45036 * (-f_offset) where: f_offset= f_m- 20 000 000 Hz

The f_mfrequency should only be measured after the Master Crystal Oscillator has been mounted inside a system

and powered long enough for the Master Crystal Oscillator to reach a steady operating temperature. Section 4.2 on

page 35 provides two examples of how to calculate an offset frequency and convert the decimal value to a binary

format. The maximum frequency compensation range of the MCFC register is equal to ±2384 ppm (±47680 Hz).

Changes to the Master Clock Calibration Register cause immediate changes in the frequency of the output clocks.

Care should be taken to ensure that changes to the Master Clock Calibration Register are made in small

increments so the frequency steps can be tolerated by downstream equipment. A rate of frequency change below

2.9ppm/sec is suggested.

All memory in the ZL30407 is volatile; so any settings of the Master Clock Calibration Register need to be reloaded

after each RESET.

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Data Sheet

ZL30407

2.6 Microprocessor Interface

The ZL30407 can be controlled by a microprocessor or by an ASIC type of device that is connected directly to the

hardware control pins. If the HW pin is tied low (see Figure 7 "Hardware and Software Control options"), an 8-bit

Motorola type microprocessor may be used to control PLL operation and check its status. Under software control,

the control pins MS2, MS1, FCS, RefSel, RefAlign are disabled and they are replaced by the equivalent control bits.

The output pins LOCK, HOLDOVER, PRIOR and SECOR are always active and they provide current status

information whether the device is in microprocessor or hardware control. Software (microprocessor) control

provides additional functionality that is not available in hardware control such as output clock phase adjustment,

master clock frequency calibration and extended access to status registers. These registers are also accessible

when the ZL30407 operates under Hardware control.

2.7 JTAG Interface

The ZL30407 JTAG (Joint Test Action Group) interface conforms to the Boundary-Scan standard IEEE1149.1-1990,

which specifies a design-for-testability technique called Boundary-Scan Test (BST). The BST architecture is made

up of four basic elements, Test Access Port (TAP), TAP Controller, Instruction Register (IR) and Test Data Registers

(TDR) and all these elements are implemented on the ZL30407.

Zarlink Semiconductor provides a Boundary Scan Description Language (BSDL) file that contains all the

information required for a JTAG test system to access the ZL30407's boundary scan circuitry. The file is available

for download from the Zarlink Semiconductor web site: www.zarlink.com.

Zarlink Semiconductor Inc.

17

ZL30407

Data Sheet

3.0 Hardware and Software Control

The ZL30407 offers Hardware and Software Control options that simplify the design of basic or complex clock

synchronization modules. Hardware control offers fewer features but still allows for building of sophisticated timing

cards without extensive programming. The complete set of control and status functions for each mode are shown in

Figure 7 "Hardware and Software Control options".

Software Control

Hardware Control

HW = 1

HW = 0

Pins

MS2

MS1

FCS

MS2

MS1

FCS

C

O

N

T

C

O

N

T

RefSel

RefAlign

AHRD

MHR

R

O

L

R

O

L

RefSel

RefAlign

µP

LOCK

HOLDOVER

PRIOR

SECOR

FLIM

LOCK

HOLDOVER

PRIOR

S

T

A

T

U

S

T

A

T

U

S

PAH

PAFL

SAH

SECOR

SAFL

Figure 7 - Hardware and Software Control options

3.1 Hardware Control

The Hardware control is a subset of software control and it will only be briefly described with cross-referencing to

Software control programmable registers.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

3.1.1 Control Pins

The ZL30407 has five dedicated control pins for selecting modes of operation and activating different functions.

These pins are listed below:

MS2 and MS1 pins: Mode Select: The MS2 (pin 19) and MS1 (pin 18) inputs select the PLL mode of operation.

See Table 1 for details. The logic level at these inputs is sampled by the rising edge of the F8o frame pulse.

MS2

MS1

Mode of Operation

0

1

0

1

0

1

Normal mode

Holdover mode

Free-run

Reserved

Table 1 - Operating Modes and States

FCS pin: Filter Characteristic Select. The FCS (pin 9) input is used to select the filtering characteristics of the

Core PLL. See Table 2 on page 19 for details.

Phase Slope

FCS

Filtering Characteristic

Limit

0

Filter corner frequency set to 1.5 Hz.

41 ns

This selection meets requirements of G.813 Option 1 and GR-1244 stratum 3

clocks.

in 1.326 ms

1

Filter corner frequency set to 0.1 Hz.

885 ns/s

This selection meets requirements of G.813 Option 2, GR-253 for SONET stratum 3

and GR-253 for SONET Minimum Clocks (SMC).

Table 2 - Filter Characteristic Selection

RefSel: Reference Source Select. The RefSel (pin 47) input selects the PRI (primary) or SEC (secondary) input

as the reference clock for the Core PLL. The logic level at this input is sampled by the rising edge of F8o.

RefSel

Input Reference

0

1

Core PLL connected to the Primary Acquisition PLL

Core PLL connected to the Secondary Acquisition PLL

Table 3 - Reference Source Select

RefAlign: Reference Alignment. The RefAlign (pin 48) input controls phase realignment between the input

reference and the generated output clocks.

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19

ZL30407

Data Sheet

3.1.2 Status Pins

The ZL30407 has four dedicated status pins for indicating modes of operation and quality of the Primary and

Secondary reference clocks. These pins are listed below:

LOCK. This output goes high after the ZL30407 has completed its locking sequence (see section 2.2.3 for details).

HOLDOVER - This output goes high when the Core PLL enters Holdover mode. The Core PLL will switch to

Holdover mode if the respective Acquisition PLL enters Holdover mode or if the mode select pins or bits are set to

Holdover (MS2, MS1 = 01).

PRIOR - This output goes high when the primary reference frequency deviates from the PLL center frequency by

more than ±12 ppm. See PRIOR pin description for details.

SECOR - This output goes high when the secondary reference frequency deviates from the PLL center frequency

by more than ±12 ppm. See SECOR pin description for details.

3.2 Software Control

Software control is enabled by setting the HW pin to logic zero (HW = 0). In this mode all hardware control pins

(inputs) are disabled and all status pins remain enabled. The ZL30407 has number of registers that provide all the

functionality available in Hardware control and in addition they offer advanced control and monitoring that is only

available in Software control (see Figure 7 "Hardware and Software Control options").

3.2.1 Control Bits

The ZL30407 has number of registers that provide greater operational flexibility than available pins in Hardware

control (see Figure 7 "Hardware and Software Control options"). The MS2, MS1, FCS, RefSel and RefAlign bits

perform the same function as the corresponding pins. Two additional bits AHRD and MHR support recovery from

Auto Holdover mode and they are described in section 3.2.4.

In addition to the Control bits shown in Figure 7 "Hardware and Software Control options", the ZL30407 has a

number of bits and registers that are accessed infrequently e.g., Phase Offset Adjustment or Master Clock

Frequency Calibration. These additional control options add flexibility to the ZL30407.

The ZL30407 has a number of status bits that provide more comprehensive monitoring of the internal operation

than is available in Hardware control (see Figure 7 "Hardware and Software Control options"). The HOLDOVER,

PRIOR and SECOR bits perform the same function as their equivalent status pins. The function of the LOCK status

bit is not identical to the function of the LOCK status pin, see the description of the LOCK status bit and the FLIM

status bit for details. The FLIM bit indicates that the output frequency of the Core PLL has reached its upper or

lower limit. The PAH and SAH status bit show entry of the Primary and Secondary acquisition PLLs into Holdover

mode. See section 3.2.4 for detailed description of the status bits. Under software control, the status pins are

always enabled and they can be used to trigger hardware interrupts.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

3.2.2 ZL30407 Register Map

Addresses: 00H to 6FH

Address

Register

hex

Read

Write

Function

00

01

04

06

07

Control Register 1

Status Register 1

Control Register 2

Phase Offset Register 2

Phase Offset Register 1

R/W

R

R/W

RefSel, 0, 0, MS2, MS1, FCS, 0, RefAlign

PRIOR, SECOR, LOCK, HOLDOVER, rsv, FLIM, rsv, rsv

E3DS3/OC3, E3/DS3, 0, 0, 0, 0, 0, 0,

0, 0, 0, 0, OffEn, C16POA10, C16POA9, C16POA8

C16POA7, C16POA6, C16POA5, C16POA4, C16POA3,

C16POA2, C16POA1, C16POA0

0F

11

13

14

19

1A

Device ID Register

Control Register 3

Clock Disable Register 1

Clock Disable Register 2

Core PLL Control Register

Fine Phase Offset Register

R

0111 0000

R/W

rsv, rsv, C1.5POA2, C1.5POA1, C1.5POA0, 0, 0, 0

0, 0, C16dis, C8dis, C4dis, C2dis, C1.5dis,0

0, 0, 0, F8odis, F0odis, F16odis, C6dis, C19dis

0, 0, 0, 0, 0, MHR, AHRD, 0

FPOA7, FPOA6, FPOA5, FPOA4, FPOA3, FPOA2,

FPOA1, FPOA0

20

28

40

41

42

43

Primary Acquisition PLL

Status Register

R

rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, PAH,PAFL

rsv, rsv, rsv, InpFreq1, InpFreq0, rsv, SAH, SAFL

Secondary Acquisition PLL

R

Status Register

Master Clock Frequency

R/W

MCFC31, MCFC30, MCFC29, MCFC28, MCFC27,

MCFC26, MCFC25, MCFC24,

Calibration Register - Byte 4

Master Clock Frequency

MCFC23, MCFC22, MCFC21, MCFC20, MCFC19,

Calibration Register - Byte 3

MCFC18, MCFC17, MCFC16

Master Clock Frequency

MCFC15, MCFC14, MCFC13, MCFC12, MCFC11,

MCFC10, MCFC9, MCFC8

Calibration Register - Byte 2

Master Clock Frequency

MCFC7, MCFC6, MCFC5, MCFC4, MCFC3, MCFC2,

Calibration Register - Byte 1

MCFC1, MCFC0

Table 4 - ZL30407 Register Map

Note: The ZL30407 uses address space from 00h to 6Fh. Registers at address locations not listed above must not be written or read.

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ZL30407

Data Sheet

3.2.3 Register Description

Address: 00 H

Bit

Name

Functional Description

Default

7

RefSel

Reference Select. A zero selects the PRI (Primary) reference source

as the input reference signal and a one selects the SEC (secondary)

reference.

0

6-5

4-3

RSV

Reserved.

00

10

MS2, MS1

Mode Select

-

MS2 = 0 MS1 = 0 Normal Mode (Locked Mode)

MS2 = 0 MS1 = 1 Holdover Mode

MS2 = 1 MS1 = 0 Free-run Mode

MS2 = 1 MS1 = 1 Reserved

2

FCS

Filter Characteristic Select

0

FCS = 0 Filter corner frequency set to 1.5 Hz. This selection meets

requirements of G.813 Option 1 and GR-1244 stratum 3 clocks.

FCS = 1 Filter corner frequency set to 0.1 Hz. This selection meets

requirements of G.813 Option 2, GR-253 for SONET stratum 3 and

GR-253 for SONET Minimum Clocks (SMC).

1

0

RSV

Reserved.

0

1

Reference Alignment. A high-to-low transition aligns the generated

output clocks to the input reference signal (see section 2.2.4 for

details). The maximum phase slope depends on the Filter

Characteristic selected and is limited to:

RefAlign

-

41 ns in 1.326 ms for FCS = 0

885 ns in one second for FCS = 1

Table 5 - Control Register 1 (R/W)

22

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Address: 01 H

Bit

Name

Functional Description

7

PRIOR

Primary Reference Out of Range. A one indicates that the primary reference is off

the nominal frequency by more than ±12 ppm. This indicator has built-in hysteresis

and returns to zero when the reference frequency pulls back into ±9.2 ppm window

centred around the nominal frequency. Monitoring is always active and the PRIOR

indicator is updated once every 10 sec regardless of the input reference frequency.

This is in full compliance with the GR-1244-CORE requirement of 10 to 30 sec

Reference Validation Time. Switching thresholds follow the accuracy of the C20

Master Clock. In an extreme case when over time the Master Clock oscillator drifts

±4.6 ppm the switching thresholds will drift as well, as is shown in Figure 8 below.

6

5

SECOR

LOCK

Secondary Reference Out of Range. A one indicates that the secondary

reference is off the nominal frequency by more than ±12 ppm. Functionally, this bit

is equivalent to the PRIOR bit for Primary Acquisition PLL.

Lock. This bit goes high when the Core PLL completes the phase locking process

to the input reference clock. After achieving lock, this bit will go low if the ZL30407

enters Holdover mode, Automatic Holdover mode or Free-run mode, or if the Core

PLL phase detector accumulates more than 22 µs of phase error, or if the RefAlign

control bit/pin is taken low.

Note that the indication of the LOCK status pin is a logical combination of the LOCK

status bit and the FLIM status bit. Please see the FLIM status bit description.

4

HOLDOVER Holdover. This bit goes high when the Core PLL enters Holdover mode. Detection

of reference failure and subsequent transition from Normal to Holdover mode takes

approximately: 0.75

1.5

µs for 19.44 MHz reference, 0.85 µs for 2.048 MHz reference,

µs for 1.544 MHz reference and 130

µs for 8 kHz reference.

3

2

RSV

Reserved.

FLIM

Frequency Limit. This bit goes high when the Core PLL is pulled by the input

reference signal to the edge of its frequency tracking range set at ±104 ppm. This

bit may change state momentarily in the event of large jitter or wander excursions

occurring when the input reference is close to the frequency limit range.

When the FLIM bit goes high it will cause the LOCK status pin to go low, but it will

not cause the LOCK status bit to go low.

1

0

RSV

Reserved.

Table 6 - Status Register 1 (R)

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23

ZL30407

Data Sheet

C20i Clock Accuracy

0 ppm

Out of Range

In Range

C20

0

-12 -9.2

9.2 12

C20

4.6

Out of Range

In Range

+4.6 ppm

-4.6 ppm

-7.4 -4.6

C20

-4.6

-5

0

13.8 16.6

Out of Range

In Range

-16.6 -13.8

-20 -15 -10

4.6 7.4

5

20

0

10

15

Frequency

Offset [ppm]

Figure 8 - Primary and Secondary Reference Out of Range Thresholds

Address: 04 H

Bit

Name

Functional Description

Default

7

E3DS3/OC3 E3, DS3 or OC-3 clock select. Setting this bit to zero enables the

C155P/N outputs (pin 30 and pin 31) and enables the C34/C44 output

(pin 53) to provide C8 or C11 clocks. Logic high disables the C155

clock LVDS outputs and enables the C34/C44 output to provide a C34

or C44 clock.

0

6

E3/DS3

E3 or DS3 clock select. When E3DS3/OC3 bit is set high, a logic low

on the E3/DS3 bit selects a 44.736 MHz clock on the C34/C44 output

and logic high selects a 34.368 MHz clock. When the E3DS3/OC3 bit is

set low, a logic low on the E3/DS3 bit selects an 11.184 MHz clock on

the C34/C44 output and a logic high selects an 8.592 MHz clock.

0

5-0

RSV

Reserved.

000000

Table 7 - Control Register 2 (R/W)

24

Zarlink Semiconductor Inc.

Data Sheet

Address: 06 H

Bit

ZL30407

Name

Functional Description

Default

7-4

3

RSV

Reserved.

0000

0

OffEn

Offset Enable. Set high to enable programmable phase offset

adjustment (C16 Phase Offset Adjustment and C1.5 Phase Offset

Adjustment) between the input reference and the generated clocks.

2 - 0

C16POA10

to

C16 Phase Offset Adjustment. These three bits (most significant) in

conjunction with the eight bits of Phase Offset Register 1 allow for

phase shifting of all clocks and frame pulses that are derived from the

C16 clock (C8o, C4o, C2o, F16o, F8o, F0o). The phase offset is an

unsigned number in a range from 0 to 2047. Each increment by one

represents a phase-offset advancement by 61.035 ns with respect to

the input reference signal. The phase offset is a two-byte value and it

must be written in one step increments. For example: four writes are

required to advance clocks by 244 ns from its current position of 22H:

write 23H, 24H, 25H, 26H. Writing numbers in reverse order will delay

clocks from their present position.

000

C16POA8

Note that phase offset adjustment is a process of shifting clocks in a

time domain which may cause momentary distortion of the generated

clocks. Therefore it is not recommended to perform phase offset

adjustments on an active ZL30407 (at the time when it generates

network clocks).

Table 8 - Phase Offset Register 2 (R/W)

Address: 07 H

Bit

Name

Functional Description

Default

7-0

C16POA7

to

C16 Phase Offset Adjustment. The eight least significant bits of the

phase offset adjustment word. See the Phase Offset Register 2 for

details.

0000

C16POA0

Table 9 - Phase Offset Register 1 (R/W)

Address: 0F H

Bit

Name

Functional Description

7-4

ID7 - 4

Device Identification Number. These four bits represent the device part number.

The ID number for ZL30407 is 0111.

3-0

ID3 - 0

Device Revision Number. These bits represent the revision number. Number

starts from 0000.

Table 10 - Device ID Register (R)

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25

ZL30407

Data Sheet

Address: 11 H

Bit

Name

Functional Description

Default

7

6

RSV

Reserved.

0

Reserved.

5-3

C1.5POA2 C1.5 Phase Offset Adjustment. These three bits allow for changing of

000

to

the phase offset of the C1.5o clock relative to the active input reference.

C1.5POA0 The phase offset is an unsigned number in a range from 0 to 7. Each

increment by one represents phase-offset advancement by 80.96 ns.

Example: Writing 010 advances C1.5 clock by 162 ns. Successive writing

of 001 delays this clock by 80.96 ns from its present position

Note that phase offset adjustment is a process of shifting clocks in a time

domain which may cause momentary distortion of the generated clocks.

Therefore it is not recommended to perform phase offset adjustments on

a ZL30407 when it is actively generating network clocks.

2-0

RSV

Reserved.

Table 11 - Control Register 3 (R/W)

000

Address: 13 H

Bit

Name

Functional Description

Default

7

6

5

RSV

Reserved.

0

C16dis

16.384 MHz Clock Disable. When set high, this bit tristates the 16.384

MHz clock output.

4

3

2

1

0

C8dis

C4dis

C2dis

C1.5dis

RSV

8.192 MHz Clock Disable. When set high, this bit tristates the 8.192

0

MHz clock output.

4.096 MHz Clock Disable. When set high, this bit tristates the 4.096

MHz clock output.

2.048 MHz Clock Disable. When set high, this bit tristates the 2.048

MHz clock output.

1.544 MHz Clock Disable. When set high, this bit tristates the 1.544

MHz clock output.

Reserved.

Table 12 - Clock Disable Register 1 (R/W)

26

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Address: 14 H

Bit

Name

Functional Description

Default

7-5

4

RSV

Reserved.

000

0

F8odis

F8o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 122 ns

active high framing pulse output.

3

2

1

0

F0odis

F0o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 244 ns

0

active low framing pulse output.

F16odis F16o Frame Pulse Disable. When set high, this bit tristates the 8 kHz 61 ns

active low framing pulse output.

C6dis

6.312 MHz Clock Disable. When set high, this bit tristates the 6.312 MHz clock

output.

0

C19dis 19.44 MHz Clock Disable. When set high, this bit tristates the 19.44 MHz clock

output.

Table 13 - Clock Disable Register 2 (R/W)

Address: 19 H

Bit

Name

Functional Description

Default

7-3

2

RSV

Reserved.

00000

0

MHR

Manual Holdover Release. A change form 0 to 1 on the MHR bit will release

the Core PLL from Auto Holdover when automatic return from Holdover is

disabled (AHRD is set to 1). This bit is level sensitive and it must be cleared

immediately after it is set to 1 (next write operation). This bit has no effect if

AHRD is set to 0.

1

0

AHRD

RSV

Automatic Holdover Return Disable. When set high, this bit inhibits the Core

PLL from automatically switching back to Normal mode from Auto Holdover

state when the active Acquisition PLL regains lock to its input reference. The

active Acquisition PLL is the Acquisition PLL to which the Core PLL is currently

connected.

0

Reserved.

Table 14 - Core PLL Control Register (R/W)

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27

ZL30407

Data Sheet

Address: 1A H

Bit

Name

Functional Description

Default

7-0

FPOA7 - 0 Fine Phase Offset Adjustment. This register allows phase offset

00000

000

adjustment of all output clocks and frame pulses (C16o, C8o, C4o, C2o,

F16o, F8o, F0o, C155, C19o, C34/44, C1.5o, C6o) relative to the active input

reference. The adjustment can be positive (advance) or negative (delay) with

a nominal step size of 477ps (61.035ns / 128). The phase offset appears at

the phase detector of the Core PLL. Changes to the offset values will result in

filtered phase transients on the PLL outputs. The rate of phase change is

limited to 885ns/s for FCS = 1 and 41 ns in 1.326 ms for FCS = 0 selections.

The phase offset value is a signed 2’s complement number e.g.:

Advance: +1 step = 01H, +2 steps = 02H, +127 steps = EFH

Delay: -1 step = FFH, -2 steps = FEH, -128 steps = 80H

Example: Writing 08H advances all clocks by 3.8 ns and writing F3H delays

all clocks

Table 15 - Fine Phase Offset Register (R/W)

Address: 20 H

Bit

Name

Functional Description

7-5

RSV

Reserved.

4-3

InpFreq1-0 Input Frequency. These two bits identify the Primary Reference Clock frequency.

- 00 = 19.44 MHz

- 01 = 8 kHz

- 10 = 1.544 MHz

- 11 = 2.048 MHz

2

1

RSV

PAH

Reserved.

Primary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL

enters Holdover mode. Holdover mode is entered when the reference frequency is

- lost completely

- drifts more than ±30 000 ppm off from the nominal frequency

- a large phase hit occurs on the reference clock.

0

PAFL

This status bit is intended to provide software compatibility with the ZL30402. It is not

required for new designs.

Table 16 - Primary Acquisition PLL Status Register (R)

28

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Address: 28 H

Bit

Name

RSV

Functional Description

7-5

Reserved.

4-3 InpFreq1-0 Input Frequency. These two bits identify the Secondary Reference Clock frequency.

-

00 = 19.44 MHz

01 = 8 kHz

10 = 1.544 MHz

11 = 2.048 MHz

2

1

RSV

SAH

Reserved.

Secondary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL

enters Holdover mode. Holdover mode is entered when reference frequency is:

-

lost completely

drifts more than ±30 000 ppm off the nominal frequency

a large phase hit occurs on the reference clock.

0

SAFL

This status bit is intended to provide software compatibility with the ZL30402. It is not

required for new designs.

Table 17 - Secondary Acquisition PLL Status Register (R)

Address: 40 H

Bit Name

Functional Description

Default

7-0 MCFC31 - 24 Master Clock Frequency Calibration. This most significant byte contains the

31st to 24th bit of the Master Clock Frequency Calibration Register. See

Applications section 4.2 for a detailed description of how to calculate the MCFC

value.

00000

000

Table 18 - Master Clock Frequency Calibration Register 4 (R/W)

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29

ZL30407

Data Sheet

Address: 41 H

Bit

Name

Functional Description

Default

7-0

MCFC23 - 16

Master Clock Frequency Calibration. This byte contains the 23rd

00000

000

to 16th bit of the Master Clock Frequency Calibration Register.

Table 19 - Master Clock Frequency Calibration Register 3 (R/W)

Address: 42 H

Bit

Name

MCFC15 - 8

Functional Description

Default

7-0

Master Clock Frequency Calibration. This byte contains the 15th

00000

000

to 8th bit of the Master Clock Frequency Calibration Register.

Table 20 - Master Clock Frequency Calibration Register 2 (R/W)

Address: 43 H

Bit

Name

MCFC7 - 0

Functional Description

Default

7-0

Master Clock Frequency Calibration. This byte contains bit 7 to

00000

000

bit 0 of the Master Clock Frequency Calibration Register.

Table 21 - Master Clock Frequency Calibration Register 1 (R/W)

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

4.0 Applications

This section contains application specific details for Mode Switching and Master Clock Oscillator calibration.

4.1 ZL30407 Mode Switching - Examples

The ZL30407 is designed to transition from one mode to the other driven by the internal State Machine or by

manual control. The following examples present a couple of typical scenarios of how the ZL30407 can be employed

in network synchronization equipment (e.g. timing modules, line cards or stand alone synchronizers).

4.1.1 System Start-up Sequence: FREE-RUN --> HOLDOVER --> NORMAL

The FREE-RUN to HOLDOVER to NORMAL transition represents a sequence of steps that will most likely occur

during a new system installation or scheduled maintenance of timing cards. The process starts from the RESET

state and then transitions to Free-run mode where the system (card) is being initialized. At the end of this process

the ZL30407 should be switched into Normal mode (with MS2, MS1 set to 00) instead of Holdover mode. If the

reference clock is available, the ZL30407 will transition briefly into Holdover to acquire synchronization and switch

automatically to Normal mode. If the reference clock is not available at this time, as it may happen during new

system installation, then the ZL30407 will stay in Holdover indefinitely. While in Holdover mode, the Core PLL will

continue generating clocks with the same accuracy as in the Free-run mode, waiting for a good reference clock.

When the system is connected to the network (or timing card switched to a valid reference) the Acquisition PLL will

quickly synchronize and clear its own Holdover status (PAH bit). This will enable the Core PLL to start the

synchronization process. After acquiring lock, the ZL30407 will automatically switch from Holdover into Normal

mode without system intervention. This transition to the Normal mode will be flagged by the LOCK status bit and

pin.

Ref: FAIL-->OK AND

MS2,MS1=00 AND

MS2,MS1=01 OR

RefSel change

AHRD=1 AND MHR=1

{MANUAL}

NORMAL

00

OR

Ref: FAIL-->OK AND

MS2,MS1=00 AND

AHRD=0

Ref: OK AND

MS2,MS1=00

{AUTO}

Ref: OK-->FAIL AND

MS2,MS1=00

{AUTO}

MS2,MS1=00

{AUTO}

RESET=1

OR

MS2,MS1=01

HOLD-

OVER

01

AUTO

HOLD-

OVER

FREE-

RESET

RUN

10

RefSel Change

AHRD=1 AND

MHR=0

OR

MS2,MS1=01

MS2,MS1=10 forces

unconditional return from

any state to Free-run

Figure 9 - Transition from Free-run to Normal mode

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31

ZL30407

Data Sheet

4.1.2 Single Reference Operation: NORMAL --> AUTO HOLDOVER --> NORMAL

The NORMAL to AUTO-HOLDOVER to NORMAL transition will usually happen when the Network Element loses

its single reference clock unexpectedly. The sequence starts with the reference clock transitioning from OK --> FAIL

at a time when ZL30407 operates in Normal mode (as is shown in Figure 10). This failure is detected by the active

Acquisition PLL based on the following FAIL criteria:

-

Frequency offset on 8 kHz, 1.544 MHz, 2.048 MHz and 19.44 MHz reference clocks exceeds ±30000 ppm

(±3%).

Single phase hit on 1.544 MHz, 2.048 MHz and 19.44 MHz exceeds half of the cycle of the reference clock.

-

After detecting any of these anomalies on a reference clock the Acquisition PLL will switch itself into Holdover mode

forcing the Core PLL to automatically switch into the Auto Holdover state. This condition is flagged by LOCK = 0

and HOLDOVER = 1.

Ref: FAIL-->OK AND

MS2,MS1=00 AND

MS2,MS1=01 OR

RefSel change

AHRD=1 AND MHR=1

{MANUAL}

NORMAL

00

OR

Ref: FAIL-->OK AND

MS2,MS1=00 AND

AHRD=0

Ref: OK AND

MS2,MS1=00

{AUTO}

Ref: OK-->FAIL AND

MS2,MS1=00

{AUTO}

MS2,MS1=00

{AUTO}

RESET=1

OR

MS2,MS1=01

HOLD-

OVER

01

AUTO

HOLD-

OVER

FREE-

RESET

RUN

10

RefSel Change

AHRD=1 AND

MHR=0

OR

MS2,MS1=01

MS2,MS1=10 forces

unconditional return from

any state to Free-run

Figure 10 - Automatic entry into Auto Holdover State and recovery into Normal mode

There are two possible returns to Normal mode after the reference signal is restored:

-

With the AHRD (Automatic Holdover Return Disable) bit set to 0. In this case the Core PLL will automatically

return to the Normal state after the reference signal recovers from failure. This transition is shown on the

state diagram as a FAIL --> OK change. This change becomes effective when the reference is restored and

there have been no phase hits detected for at least 64 clock cycles for the 1.544/2.048 MHz reference, 512

clock cycles for the 19.44 MHz reference and 1 clock cycle for the 8 kHz reference.

With the AHRD bit set to 1 to disable automatic return to Normal and the change of MHR (Manual Holdover

Release) bit from 0 to 1 to trigger the transition from Auto Holdover to Normal. This option is provided to

protect the Core PLL and its stored holdover value against toggling between Normal and Auto Holdover

states in case of an intermittent quality reference clock. In the case when MHR has been changed when the

reference is still not available (Acquisition PLL in Holdover mode) the transition to Normal state will not occur

and MHR 0 to 1 transition must be repeated.

-

This transition from Auto Holdover to Normal mode is performed as “hitless” reference switching.

32

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

4.1.3 Dual Reference Operation: NORMAL --> AUTO HOLDOVER--> HOLDOVER --> NORMAL

The NORMAL to AUTO-HOLDOVER to HOLDOVER to NORMAL sequence represents the most likely operation of

ZL30407 in Network Equipment.

The sequence starts from the Normal state and transitions to Auto Holdover state due to an unforeseen loss of

reference. The failure conditions triggering this transition were described in section 4.1.2. When in the Auto

Holdover state, the ZL30407 can return to Normal mode automatically if the lost reference is restored and the

ADHR bit is set to 0. If the reference clock failure persists for a period of time that exceeds the system design limit,

the system control processor may initiate a reference switch. If the secondary reference is available the ZL30407

will briefly switch into Holdover mode and then transition to Normal mode.

Ref: FAIL-->OK AND

MS2,MS1=00 AND

MS2,MS1=01 OR

RefSel change

AHRD=1 AND MHR=1

{MANUAL}

NORMAL

00

OR

Ref: FAIL-->OK AND

MS2,MS1=00 AND

AHRD=0

Ref: OK AND

MS2,MS1=00

{AUTO}

Ref: OK-->FAIL AND

MS2,MS1=00

{AUTO}

MS2,MS1=00

{AUTO}

RESET=1

OR

MS2,MS1=01

HOLD-

OVER

01

AUTO

HOLD-

OVER

FREE-

RESET

RUN

10

RefSel Change

AHRD=1 AND

MHR=0

OR

MS2,MS1=01

MS2,MS1=10 forces

unconditional return from

any state to Free-run

Figure 11 - Entry into Auto Holdover state and recovery into Normal mode by switching

references

The new reference clock will most likely have a different phase but it may also have a different fractional frequency

offset. In order to lock to a new reference with a different frequency, the Core PLL may be stepped gradually

towards the new frequency. The frequency slope will be limited to less than 2.0 ppm/sec.

Zarlink Semiconductor Inc.

33

ZL30407

Data Sheet

4.1.4 Reference Switching (RefSel): NORMAL --> HOLDOVER --> NORMAL

The NORMAL to HOLDOVER to NORMAL mode switching is usually performed when:

- A reference clock is available but its frequency drifts beyond some specified limit. In a Network Element

with stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than

±12ppm beyond its nominal frequency. The ZL30407 indicates this condition by setting PRIOR or

SECOR status bits or pins to logic high.

- During routine maintenance of equipment when orderly switching of reference clocks is possible. This

may happen when synchronization references must be rearranged or when a faulty line card must be

replaced.

Ref: FAIL-->OK AND

MS2,MS1=00 AND

MS2,MS1=01 OR

RefSel change

AHRD=1 AND MHR=1

{MANUAL}

NORMAL

00

OR

Ref: FAIL-->OK AND

MS2,MS1=00 AND

AHRD=0

Ref: OK AND

MS2,MS1=00

{AUTO}

Ref: OK-->FAIL AND

MS2,MS1=00

{AUTO}

MS2,MS1=00

{AUTO}

RESET=1

OR

MS2,MS1=01

HOLD-

OVER

01

AUTO

HOLD-

OVER

FREE-

RESET

RUN

10

RefSel Change

AHRD=1 AND

MHR=0

OR

MS2,MS1=01

MS2,MS1=10 forces

unconditional return from

any state to Free-run

Figure 12 - Manual Reference Switching

Two types of transitions are possible:

-

Semi-automatic transition, which involves changing RefSel input to select a secondary reference clock

without changing the mode select inputs MS2,MS1=00 (Normal mode). This forces the ZL30407 to

momentarily transition through the Holdover state and automatically return to Normal mode after

synchronizing to a secondary reference clock.

Manual transition, which involves switching into Holdover mode (MS2,MS1=01), changing references with

RefSel, and manual return to the Normal mode (MS2, MS1=00).

-

In both cases, the change of references provides “hitless” switching.

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Zarlink Semiconductor Inc.

Data Sheet

ZL30407

4.2 Programming Master Clock Oscillator Frequency Calibration Register

The Master Crystal Oscillator and its programmable Master Clock Frequency Calibration register (see Table 18,

Table 19, Table 20, and Table 21) are described in Section 2.5 "Master Clock Frequency Calibration Circuit", on

page 16. Programming of this register should be done after the system has been powered long enough for the

Master Crystal Oscillator to reach a steady operating temperature. When the temperature stabilizes the crystal

oscillator frequency should be measured with an accurate frequency meter. The frequency measurement should be

substituted for the f_offsetvariable in the following equation.

MCFC = 45036 * (-f_offset

)

where f_offsetis the crystal oscillator frequency offset from the nominal 20 000 000 Hz frequency expressed in Hz.

Example 1: Calculate the binary value that must be written to the MCFC register to correct a -1 ppm offset of the

Master Crystal Oscillator. The -1 ppm offset for a 20 MHz frequency is equivalent to -20 Hz:

MCFC = 45036 * 20 = 900720 = 00 0D BE 70 H

Note: Correcting the -1ppm crystal oscillator offset requires +1ppm MCFC offset.

Example 2: Calculate the binary value that must be written to the MCFC register to correct a +2 ppm offset of the

Master Crystal Oscillator. The +2 ppm offset for 20 MHz frequency is equivalent to 40 Hz:

MCFC = 45036 * (-40) = -1801440 = FF E4 83 20 H

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35

ZL30407

Data Sheet

5.0 Characteristics

5.1 AC and DC Electrical Characteristics

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

1

2

3

4

5

6

Supply voltage

V_DDR

V_PIN

I_PIN

-0.3

7.0

VDD+0.3

30

V

Voltage on any pin

Current on any pin

mA

°C

mW

V

Storage temperature

Package power dissipation (80 pin LQFP)

ESD rating

T_ST

-55

125

P_PD

1000

1500

V_ESD

* Voltages are with respect to ground (GND) unless otherwise stated

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Recommended Operating Conditions*

Characteristics

Supply voltage

Operating temperature

Symbol

Min

Typ

Max

Units

1

2

V_DD

T_A

3.0

-40

3.3

25

3.6

V

+85

°C

* Voltages are with respect to ground (GND) unless otherwise stated

DC Electrical Characteristics*

Characteristics

Symbol

Min

Max

Units Conditions/Notes

1

2

3

4

5

6

7

8

9

Supply current with C20i = 20MHz

Supply current with C20i = 0V

CMOS high-level input voltage

CMOS low-level input voltage

Input leakage current

I_DD

I_DDS

V_CIH

V_CIL

I_IL

155

3.5

mA Outputs unloaded

0.7V_DD

V

0.3V_DD

15

V

µA V_I=V_DDor GND

High-level output voltage

V_OH

V_OL

V_OD

dV_OD

2.4

V

I_OH=10mA

I_OL=10mA

Low-level output voltage

0.4

450

50

LVDS: Differential output voltage

250

mV Z_T=100Ω

LVDS: Change in VOD between

complementary output states

10

11

LVDS: Offset voltage

V_OS

1.125

260

1.375

50

V

Note 1

LVDS: Change in VOS between

complementary output states

dV_OS

mV

12

13

LVDS: Output short circuit current

LVDS: Output rise and fall times

I_OS

24

mA Pin short to GND

ps Note 2

T_RF

900

* Voltages are with respect to ground (GND) unless otherwise stated

Note 1:

Note 2:

VOS is defined as (V

+ V ) / 2

OH OL

Rise and fall times are measured at 20% and 80% levels.

36

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

AC Electrical Characteristics - Timing Parameter Measurement - CMOS Voltage Levels*

Characteristics

Symbol

Level

Units

1

2

3

Threshold voltage

V_T

0.5V_DD

0.7V_DD

0.3V_DD

V

Rise and fall threshold voltage High

Rise and fall threshold voltage Low

V_HM

V_LM

* Voltages are with respect to ground (GND) unless otherwise stated

* Supply voltage and operating temperature are as per Recommended Operating Conditions

* Timing for input and output signals is based on the worst case conditions (over T and V

)

DD

A

Timing Reference Points

V

HM

ALL SIGNALS

V

T

LM

t

IF, OF

IR, OR

Figure 13 - Timing Parameters Measurement Voltage Levels

Zarlink Semiconductor Inc.

37

ZL30407

Data Sheet

AC Electrical Characteristics - Microprocessor Timing*

Test

Characteristics

Symbol

Min

Max

Units

Condition

1

2

3

4

5

6

7

8

DS Low

t_DSL

t_DSH

t_CSS

t_CSH

t_RWS

t_RWH

t_ADS

t_ADH

65

100

0

ns

DS High

CS Setup

CS-Hold

R/W Setup

R/W Hold

0

20

5

Address Setup

Address Hold

10

9

Data Read Delay

Data Read Hold

t_DRD

t_DRH

t_DWS

t_DWH

60

10

ns

C_L=90pF

10

11

12

Data Write Setup

Data Write Hold

10

5

ns

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

DSL

DSH

V

T

DS

CS

t

CSH

CSS

V

T

t

RWH

RWS

R/W

t

t_ADS

ADH

VALID ADDRESS

A0-A6

t

DRH

DRD

VALID DATA

D0-D7

READ

V

T

t

DWH

DWS

VALID DATA

D0-D7

V

T

WRITE

Figure 14 - Microport Timing

38

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

AC Electrical Characteristics - ST-BUS and GCI Output Timing*

Characteristics

Test

Symbol

Min

Max

Units

Condition

1

2

t_F16L

t_F16D

t_C16L

t_C16D

t_F8H

t_C8L

56

27

62

33

32

3

ns

F16o pulse width low (nom 61 ns)

F8o to F16o delay

3

26

C16o pulse width low

F8o to C16o delay

4

-3

5

119

56

125

62

3

F8o pulse width high (nom 122 ns)

C8o pulse width low

6

7

t_C8D

t_F0L

t_F0D

t_C4L

t_C4D

t_C2L

-3

F8o to C8o delay

8

241

119

-3

247

125

3

F0o pulse width low (nom 244 ns)

F8o to F0o delay

9

10

11

12

13

C4o pulse width low

F8o to C4o delay

240

-3

246

3

C2o pulse width low

t_C2D

F8o to C2o delay

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

F16L

t

F16D

F16o

C16o

V

T

tc =125µs

t

C16L

t

C16D

V

T

t

F8H

tc = 61.04 ns

F8o

C8o

t

C8L

tc =125µs

t

C8D

V

T

t

tc = 122.07 ns

F0L

t

F0D

F0o

C4o

T

tc =125µs

t

C4L

t

C4D

V

T

tc = 244.14 ns

tc = 488.28 ns

t

C2D

C2L

C2o

V

Figure 15 - ST-BUS and GCI Output Timing

Zarlink Semiconductor Inc.

39

ZL30407

Data Sheet

AC Electrical Characteristics - DS1, DS2 and C19o Clock Timing*

Characteristics

C6o pulse width low

Symbol

Min

Max

Units

Test Condition

1

2

3

4

5

t_C6L

t_C6D

75

-4

83

11

328

11

7

ns

F8o to C6o delay

C1.5o pulse width low

F8o to C1.5o delay

F8o to C19o delay

t_C1.5L

t_C1.5D

t_C19D

320

-4

-5

* Supply voltage and operating temperature are as per Recommended Operating Conditions

V

T

F8o

tc =125µs

t

C6L

C6D

C6o

V

T

tc = 158.43 ns

t

C1.5D

C1.5L

C1.5o

V

T

tc = 647.67 ns

tc = 51.44 ns

t

C19D

C19o

V

T

Figure 16 - DS1, DS2 and C19o Clock Timing

40

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

AC Electrical Characteristics - C155o and C19o Clock Timing

Characteristics

C155o pulse width low

Symbol

Min

Max

Units

Test Condition

1

2

3

4

t_C155L

t_C19DLH

t_C19DHL

t_C19H

2.6

-1

3.8

7

ns

C155o to C19o rising edge delay

C155o to C19o falling edge delay

C19 pulse width high

-2

6

23

29

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

C155L

C155oP

C19o

1.25V

tc = 6.43 ns

t

C19DHL

C19DLH

V

T

t

C19H

tc = 51.44 ns

Note: Delay is measured from the rising edge of C155P clock (single ended) at 1.25V threshold

to the rising and falling edges of C19o clock at V threshold

T

Figure 17 - C155o and C19o Timing

Zarlink Semiconductor Inc.

41

ZL30407

Data Sheet

AC Electrical Characteristics - Input to Output Phase Alignment (after RefAlign change from 1 to 0)*

Characteristics

Symbol

Min

Max

Units

Test Condition

1

2

8 kHz ref pulse width high

t_R8H

t_R8D

100

13

ns

F8o to 8 kHz ref input delay

31

3

1.544 MHz ref pulse width high

1.544 MHz ref input to F8o delay

2.048 MHz ref pulse width high

2.048 MHz ref input to F8o delay

19.44 MHz ref pulse width high

F8o to 19.44 MHz ref input delay

19.44 MHz ref input to C19o delay

Reference input rise and fall time

t_R1.5H

t_R1.5D

t_R2H

100

335

100

255

20

4

350

272

5

6

t_R2D

7

t_R19H

t_R19D

t_R19C19D

t_IR, t_IF

8

21

10

9

6

10

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

R8H

t

R8D

PRI/SEC

8 kHz

V

T

t

R1.5H

tc = 125 µs

t

R1.5D

PRI/SEC

V

T

1.544 MHz

t

R2H

tc = 647.67 ns

tc = 488.28 ns

t

R2D

PRI/SEC

2.048 MHz

t

R19D

R19H

PRI/SEC

V

T

19.44 MHz

tc = 51.44 ns

t

R19C19D

V

T

C19o

F8o

V

tc = 125 µs

Note: Delay time measurements are done with jitter free input reference signals

Figure 18 - Input Reference to Output Clock Phase Alignment

42

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

AC Electrical Characteristics - Input Control Signals*

Characteristics

Symbol

Min

Max

Units

Test Condition

1

2

Input controls Setup time

Input controls Hold time

t_S

t_H

100

ns

* Supply voltage and operating temperature are as per Recommended Operating Conditions

V

T

F8o

t

S

H

MS1, MS2

RefSel, FCS,

RefAlign

V

T

E3/DS3

E3DS3/OC3

Figure 19 - Input Control Signal Setup and Hold Time

AC Electrical Characteristics - E3 and DS3 Output Timing*

Characteristics

Symbol

Min

Max

Units

Test Condition

1

2

3

4

C44o clock pulse width high

C11o clock pulse width high

C34o clock pulse width high

C8.5o clock pulse width high

t_C44H

t_C11H

t_C34H

t_C8.5H

11

5

13

26

16

24

ns

13

9

* Supply voltage and operating temperature are as per Recommended Operating Conditions

t

C44H

V

T

C44o

C11o

tc = 22.35 ns

tc = 89.41 ns

t

C11H

V

T

t

C34H

C34o

tc = 29.10 ns

tc = 116.39 ns

t

C8.5H

C8.5o

V

T

Figure 20 - E3 and DS3 Output Timing

Zarlink Semiconductor Inc.

43

ZL30407

Data Sheet

5.2 Performance Characteristics

Performance Characteristics*

Characteristics

MIN

MAX

Units

Test Condition

1

2

Holdover accuracy

Holdover stability

0.000001

NA

ppm

Determined by stability of

the 20 MHz Master Clock

oscillator

3

4

Capture range

-104

-12

+104

+12

ppm

The 20 MHz Master Clock

oscillator set at 0ppm

Reference Out of Range Threshold

The 20 MHz Master Clock

oscillator set at 0ppm

Lock Time

1.5 Hz Filter

5

6

7

20

75

95

s

±4.6ppm frequency offset

±20ppm frequency offset

0.1 Hz Filter

Output Phase Continuity (MTIE)

8

Reference switching:

PRI ⇒ SEC, SEC ⇒ PRI

50

ns

PRI = SEC = 8 kHz

TDB

PRI or SEC = 1.544 MHz,

2.048 MHz, 19.44 MHz

9

Switching from Normal mode to

Holdover mode

0

ns

10 Switching from Holdover mode to

Normal mode

50

ns

PRI = SEC = 8 kHz

TBD

PRI or SEC = 1.544 MHz,

2.048 MHz, 19.44 MHz

Output Phase Slope

11 G.813 Option 1, GR-1244 stratum 3

41

1.326ms

ns/s

12 G.813 Option 2

885

GR-253 SONET stratum 3

GR-253 SONET SMC

* Supply voltage and operating temperature are as per Recommended Operating Conditions

44

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Performance Characteristics : Measured Output Jitter - GR-253-CORE and T1.105.03 conformance

Telcordia GR-253-CORE and ANSI T1.105.03

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

Jitter

Limit in

UI

limit in

time

Interface

Measurement

Filter

TYP

Units

Notes

domain

C155 Clock Output

1

2

3

OC-3

65kHz to 1.3MHz 0.15 UIpp

0.964

0.325

0.038

0.408

0.048

0.448

0.053

ns_P-P

ns_RMS

ns_P-P

ns_RMS

ns_P-P

ns_RMS

155.52

Mbit/s

12kHz to1.3MHz

(Category II)

0.1 UIpp

0.643

0.064

9.645

0.01 UI_RMS

500Hz to 1.3MHz 1.5 UIpp

C19 Clock Output

4

5

6

OC-3

65kHz to 1.3MHz 0.15 UIpp

0.964

0.390

0.056

0.458

0.061

0.512

0.065

ns_P-P

ns_RMS

ns_P-P

ns_RMS

ns_P-P

ns_RMS

155.52

Mbit/s

12kHz to1.3MHz

(Category II)

0.1 UIpp

0.643

0.064

9.645

0.01 UI_RMS

500Hz to 1.3MHz 1.5 UIpp

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Performance Characteristics : Measured Output Jitter - T1.403 conformance

ANSI T1.403

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

Jitter

Measurement

Filter

Limit in

UI

limit in

time

Interface

TYP

Units

Notes

domain

C1.5 Clock Output

1

2

DS1

8 kHz to 40 kHz

10 Hz to 40 kHz

0.07 UIpp

0.5 UIpp

45.3

324

0.63

0.93

ns_P-P

1.544 Mbit/s

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Zarlink Semiconductor Inc.

45

ZL30407

Data Sheet

Performance Characteristics : Measured Output Jitter - G.747 conformance

ITU-T G.747

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

limit in

time

Jitter

Measurement

Filter

Limit in

UI

Interface

TYP

Units

Notes

domain

C6 Clock Output

0.53 ns_P-P

1

6312 kbit/s

10 Hz to 60kHz

0.05 UIpp

7.92

(DS2)

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Performance Characteristics : Measured Output Jitter - T1.404 conformance

ANSI T1.403

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

Jitter

Measurement

Filter

Interface

Type I

Limit in

UI

limit in

time

TYP

Units

Notes

domain

C44 Clock Output

1

2

DS3

44.736 Mbit/s

30 kHz to 400 kHz

10 Hz to 400 kHz

0.05 UIpp

0.5 UIpp

1.12

11.2

0.30

0.47

ns_P-P

* Supply voltage and operating temperature are as per Recommended Operating Conditions

46

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Performance Characteristics : Measured Output Jitter - G.732, G.735 to G.739 conformance

ITU-T G.732, G.735, G.736, G.737, G.738, G.739

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

Jitter

Measurement

Filter

Limit in

UI

limit in

time

Interface

TYP

Units

Notes

domain

C16, C8, C4 and C2 Clock Outputs

24.4 0.56 ns_P-P

1

E1

20 Hz to 100 kHz

0.05 UIpp

2048 kbit/s

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Performance Characteristics : Measured Output Jitter - G.751 conformance

ITU-T G.751

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

Jitter

Measurement

Filter

Limit in

UI

limit in

time

Interface

TYP

Units

Notes

domain

C34 Clock Output

0.64 ns_P-P

1

E3

100 Hz to 800 kHz

0.05 UIpp

1.45

34368

kbit/s

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Zarlink Semiconductor Inc.

47

ZL30407

Data Sheet

Performance Characteristics : Measured Output Jitter - G.812 conformance

ITU-T G.812

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

limit in

time

Jitter

Measurement

Filter

Limit in

UI

Interface

TYP

Units

Notes

domain

C155 Clock Output

1

2

STM-1

155.52

Mbit/s

optical

65kHz to 1.3MHz

500Hz to 1.3MHz

0.1 UIpp

0.5 UIpp

0.643

3.215

0.325

0.038

0.448

0.053

ns_P-P

ns_RMS

ns_P-P

ns_RMS

C155 Clock Output

3

4

STM-1

155.52

Mbit/s

65kHz to 1.3MHz

500Hz to 1.3MHz

0.075 UIpp

0.5 UIpp

0.482

3.215

0.325

0.038

0.448

0.053

ns_P-P

ns_RMS

ns_P-P

ns_RMS

electrical

C19 Clock Output

5

6

STM-1

155.52

Mbit/s

optical

65kHz to 1.3MHz

500Hz to 1.3MHz

0.1 UIpp

0.5 UIpp

0.643

3.215

0.390

0.056

0.512

0.065

ns_P-P

ns_RMS

ns_P-P

ns_RMS

C19 Clock Output

7

STM-1

155.52

Mbit/s

65kHz to 1.3MHz

500Hz to 1.3MHz

0.075 UIpp

0.5 UIpp

0.482

3.215

0.390

0.056

0.512

0.065

ns_P-P

ns_RMS

ns_P-P

ns_RMS

electrical

8

C16, C8, C4 and C2 Clock Outputs

0.56 ns_P-P

9

E1

20 Hz to 100 kHz

10 Hz to 40 kHz

0.05 UIpp

24.4

32.4

2048 kbit/s

C1.5 Clock Output

0.93 ns_P-P

10 DS1

1.544 Mbit/s

* Supply voltage and operating temperature are as per Recommended Operating Conditions

48

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Performance Characteristics : Measured Output Jitter - G.813 conformance (Option 1 and Option 2)

ITU-T G.813

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

Jitter

Measurement

Filter

Limit in

UI

limit in

time

Interface

TYP

Units

Notes

domain

Option 1

C155 Clock Output

1

2

STM-1

155.52

Mbit/s

65kHz to 1.3MHz

0.1 UIpp

0.5 UIpp

0.643

3.215

0.325

0.038

0.448

0.053

ns_P-P

ns_RMS

ns_P-P

ns_RMS

500Hz to 1.3MHz

C19 Clock Output

3

4

STM-1

155.52

Mbit/s

65kHz to 1.3MHz

500Hz to 1.3MHz

0.1 UIpp

0.5 UIpp

0.643

3.215

0.390

0.056

0.512

0.065

ns_P-P

ns_RMS

ns_P-P

ns_RMS

C16, C8, C4 and C2 Clock Outputs

0.56 ns_P-P

5

6

E1

20 Hz to 100 kHz

0.05 UIpp

0.1 UIpp

24.4

2048 kbit/s

Option 2

C155 Clock Output

STM-1

155.52

Mbit/s

12kHz to1.3MHz

0.643

0.408

0.048

ns_P-P

ns_RMS

C19 Clock Output

7

STM-1

155.52

Mbit/s

12kHz to1.3MHz

0.1 UIpp

0.643

0.458

0.061

ns_P-P

ns_RMS

* Supply voltage and operating temperature are as per Recommended Operating Conditions

Zarlink Semiconductor Inc.

49

ZL30407

Data Sheet

Performance Characteristics : Measured Output Jitter - EN 300 462-7-1 conformance

ETSI EN 300 462-7-1

ZL30407 Jitter Generation Performance

Jitter Generation Requirements

Equivalent

limit in

time

Jitter

Measurement

Filter

Limit in

UI

Interface

TYP

Units

Notes

domain

C155 Clock Output

1

2

STM-1

155.52

Mbit/s

optical

65kHz to 1.3MHz

500Hz to 1.3MHz

0.1 UIpp

0.5 UIpp

0.643

3.215

0.325

0.038

0.448

0.053

ns_P-P

ns_RMS

ns_P-P

ns_RMS

C155 Clock Output

3

4

STM-1

155.52

Mbit/s

65kHz to 1.3MHz

500Hz to 1.3MHz

0.075 UIpp

0.5 UIpp

0.482

3.215

0.325

0.038

0.448

0.053

ns_P-P

ns_RMS

ns_P-P

ns_RMS

electrical

C19 Clock Output

5

6

STM-1

155.52

Mbit/s

optical

65kHz to 1.3MHz

500Hz to 1.3MHz

0.1 UIpp

0.5 UIpp

0.643

3.215

0.390

0.056

0.512

0.065

ns_P-P

ns_RMS

ns_P-P

ns_RMS

C19 Clock Output

7

STM-1

155.52

Mbit/s

65kHz to 1.3MHz

500Hz to 1.3MHz

0.075 UIpp

0.5 UIpp

0.482

3.215

0.390

0.056

0.512

0.065

ns_P-P

ns_RMS

ns_P-P

ns_RMS

electrical

8

* Supply voltage and operating temperature are as per Recommended Operating Conditions

50

Zarlink Semiconductor Inc.

Data Sheet

ZL30407

Performance Characteristics - Measured Output Jitter - Unfiltered*

TYP

Characteristics

Test Condition

(Ul_PP

)

(ns_PP)

1

2

0.0042

0.0019

0.0037

0.0179

0.0081

0.0222

0.0295

0.0161

0.0125

0.0433

0.0546

0.0867

NA

2.71

0.95

0.92

2.84

0.99

2.58

2.64

0.98

0.64

1.26

1.22

0.56

0.44

0.46

0.45

C1.5o (1.544MHz)

C2o (2.048MHz)

C4o (4.096MHz)

C6o (6.312MHz)

C8o (8.192MHz)

C8.5o (8.592MHz)

C11o (11.184MHz)

C16o (16.384MHz)

C19o (19.44MHz)

C34o (34.368MHz)

C44o (44.736MHz)

C155o (155.52MHz)

F0o (8kHz)

3

4

5

6

7

8

9

10

11

12

13

45

15

NA

F8o (8kHz)

NA

F16o (8kHz)

Zarlink Semiconductor Inc.

51

ZL30407

Data Sheet

52

Zarlink Semiconductor Inc.


型号：	ZL30407/QCC
厂家：	Microsemi
描述：	ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, LQFP-80 ATM 异步传输模式电信电信集成电路
文件：	总54页 (文件大小：768K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZL30407/QCC [MICROSEMI]

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