ZL30407 [ZARLINK]
SONET/SDH Clock Multiplier PLL; SONET / SDH时钟倍频PLL
| 型号： | ZL30407 |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | SONET/SDH Clock Multiplier PLL |
| 文件： | 总22页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZL30416
SONET/SDH Clock Multiplier PLL
Data Sheet
November 2004
Features
•
•
•
Low jitter clock outputs suitable for OC-192, OC-
48, OC-12, OC-3 and OC-1 SONET applications
as defined in Telcordia GR-253-CORE
Ordering Information
ZL30416GGG
64 Ball CABGA
Low jitter clock outputs suitable for STM-64, STM-
16, STM-4 and STM-1 applications as defined in
ITU-T G.813
-40°C to +85°C
Provides one differential LVPECL output clock
selectable to 19.44, 38.88, 77.76, 155.52 or
622.08 MHz
Description
The ZL30416 is an Analog Phase-Locked Loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30416 generates low
jitter output clocks suitable for Telcordia GR-253-
CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and
ITU-T G.813 STM-64, STM-16, STM-4 and STM-1
applications.
•
•
Provides a single-ended CMOS output clock at
19.44 MHz
Accepts a single-ended CMOS reference at
19.44 MHz or a differential LVDS, LVPECL or
CML reference at 19.44 or 77.76 MHz
•
•
•
Provides a LOCK indication
8 mm x 8 mm CABGA package
3.3 V supply
The ZL30416 accepts a CMOS compatible reference
at 19.44 MHz or a differential LVDS, LVPECL or CML
reference at 19.44 or 77.76 MHz and generates a
differential LVPECL output clock selectable to 19.44,
38.88, 77.76, 155.52 or 622.08 MHz and a single-
ended CMOS clock at 19.44 MHz. The ZL30416
provides a lock indication.
Applications
•
SONET/SDH line cards
LPF
REF_SEL
FS3 FS2 FS1
C19o, C38o, C77o,
C155o, C622o,
LVPECL output
C19i
Frequency
& Phase
Detector
Loop
Filter
VCO
Reference
Selection
MUX
OC-CLKoP/N
C19o
Frequency
Dividers
and
Clock
Drivers
REFinP/N
19.44 MHz and 77.76 MHz
Reference
and
Bias Circuit
C19i or C77i
CML, LVDS,
LVPECL input
State
Machine
REF_FREQ LOCK
BIAS
VCC GND VDD
C19oEN
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30416
Data Sheet
1
2
3
4
5
6
7
8
1
A
NC
NC
NC
NC OC-CLKoP OC-CLKoN GND
NC
GND
VDD
GND
NC
NC
VCC
B
NC
VCC2
LPF
NC
VCC1
GND
NC
GND
GND
GND
FS2
NC
GND
NC
C
D
E
F
GND
BIAS
LOCK
NC
GND
VCC
VCC
GND
VCC
VDD
C19o
GND
VDD
GND
NC
REFinN
REFinP
VDD
NC REF_FREQ C19oEN C19i
GND
VDD
GND
G
H
GND
NC
VDD REF_SEL FS3
GND
FS1
NC
NC
VDD
GND
1
- A1 corner is identified by metallized markings.
8 mm x 8 mm
Ball Pitch 0.8mm
Figure 2 - BGA 64 Ball Package (Top View)
1.0 Ball Description
Ball Description Table
Ball #
Name
Description
A1, A2
A3
No internal bonding Connection. Leave unconnected.
NC
A4
A5
OC-CLKoP
OC-CLKoN
SONET/SDH Clock (LVPECL Output). These outputs provide a selectable
differential LVPECL clock at 19.44 Hz, 38.88 MHz, 77.76 MHz, 155.52 MHz,
and 622.08 MHz. The output frequency is selected with FS3, FS2 and FS1
inputs.
A6
Ground. 0 volt
GND
NC
A7, A8
B1, B2
No internal bonding Connection. Leave unconnected.
B3
B4
Positive Analog Power Supply. +3.3 V +/-10%
Ground. 0 volt
VCC1
GND
NC
B5
No internal bonding Connection. Leave unconnected.
Ground. 0 volt
B6, B7
GND
2
Zarlink Semiconductor Inc.
ZL30416
Data Sheet
Ball Description Table (continued)
Ball #
Name
VCC
Description
B8
Positive Analog Power Supply. +3.3 V ±10%
Ground. 0 volt
C1
C2
GND
VCC2
Positive Analog Power Supply. +3.3 V ±10%
Ground. 0 volt
C3, C4
C5
GND
C6
C7
C8
No internal bonding Connection. Leave unconnected.
Positive Digital Power Supply. +3.3 V ±10%
Ground. 0 volt
NC
VDD
GND
BIAS
Bias Circuit.
D1
D2
LPF
External Low-Pass Filter (Analog). Connect external RC network for the low-
pass filter.
D3
D4
NC
No internal bonding Connection. Leave unconnected.
Ground. 0 volt
GND
D5, D6
D7, D8
E1
Positive Analog Power Supply. +3.3 V ±10%
Ground. 0 volt
VCC
GND
LOCK
Lock Indicator (CMOS Output). This output goes high when the PLL is
frequency locked to the selected input reference.
E2, E3
No internal bonding Connection. Leave unconnected.
NC
G4
E4
H5
FS3
FS2
FS1
Frequency Select 3-1 (CMOS Input). These inputs select the clock frequency
on the OC-CLKo output. The possible output frequencies are:
19.44 MHz (000), 38.88 MHz (001), 77.76 MHz (010), 155.52 MHz (011),
622.08 (100)
E5
E6
E7
Positive Analog Power Supply. +3.3 V ±10%
Positive Digital Power Supply. +3.3 V ±10%
No internal bonding Connection. Leave unconnected.
VCC
VDD
NC
E8
F8
REFinN
REFinP
Differential Reference Clock Input (CML/LVDS/LVPECL Compatible Input).
These inputs accept a differential clock at 77.76 MHz or 19.44 MHz as the
reference for synchronization. These inputs do not have on-chip AC coupling
capacitors.
F1, F2
F3
No internal bonding Connection. Leave unconnected.
NC
REF_FREQ
Reference Frequency (CMOS Input). This input selects the rate of the
differential input clock (REFinP/N) to be either 77.76 MHz or 19.44 MHz.
F4
F5
C19oEN
C19o Output Enable (CMOS Input). If tied high this control input enables the
C19o output clock. Pulling this pin low forces the output driver into a high
impedance state.
C19 Reference Input (CMOS Input). This is a single-ended input reference
source used for synchronization. This input accepts 19.44 MHz.
C19i
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
Ball Description Table (continued)
Ball #
Name
Description
F6
Clock 19.44 MHz (CMOS Output). This output provides a single-ended CMOS
clock at 19.44 MHz.
C19o
F7, G1
G2
GND
VDD
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
G3
REF_SEL
Reference Select (CMOS Input). If tied low then the C19i single-ended
reference is used as the input reference source. If tied high then the REFinP/N
differential pair is used as the input reference source.
G4
FS3
See E4 ball description.
G5, G6
G7, G8
GND
Ground. 0 volt
Positive Digital Power Supply. +3.3 V ±10%
VDD
NC
H1, H2
H3
No internal bonding Connection. Leave unconnected.
H4
H5
Positive Digital Power Supply. +3.3 V ±10%
See E4 ball description.
VDD
FS1
H6
Positive Digital Power Supply. +3.3 V ±10%
Ground. 0 volt.
VDD
GND
H7, H8
2.0 Functional Description
The ZL30416 is an analog phased-locked loop which provides rate conversion and jitter attenuation for
SONET/SDH OC-192/STM-64, OC-48/STM-16, OC-12/STM-4 and OC-3/STM-1 applications. A functional block
diagram of the ZL30416 is shown in Figure 1 and a brief description is presented in the following sections.
2.1 Reference Selection Multiplexer
The ZL30416 accepts two types of input reference clocks:
-
-
differential: operating at 19.44 MHz or 77.76 MHz, compatible with LVDS/LVPECL/CML threshold levels
single-ended: operating at 19.44 MHz, compatible with CMOS switching levels
The REF_SEL input determines whether the single-ended CMOS reference input (REFin) or the differential
reference inputs (REFinP/N) are used as input reference clocks. The REF_FREQ input selects the rate of the
differential input clock to be either 19.44 MHz or 77.76 MHz. See Table 1 for details.
REF_SEL
REF_FREQ
Selected Input Reference
Reference Frequency
0
1
1
x
0
1
C19i
19.44 MHz (CMOS)
77.76 MHz (Differential)
19.44 MHz (Differential)
REFin
REFin
Table 1 - Input Reference Selection
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
2.2 Frequency/Phase Detector
The Frequency/Phase Detector compares the frequency/phase of the input reference signal with the feedback
signal from the Frequency Divider circuit and provides an error signal equal to the frequency/phase
difference between the two. This error signal is passed to the Loop Filter circuit.
2.3 Lock Indicator
The ZL30416 has a built-in LOCK detector that measures frequency difference between input reference clock C19i
and the VCO frequency. When the VCO frequency is less than ±300 ppm apart from the input reference frequency
then the LOCK output is set high. The LOCK output is pulled low if the frequency difference exceeds ±1000 ppm.
2.4 Loop Filter
The Loop Filter is a low-pass filter. This low-pass filter eliminates high frequency spectral components from a phase
error signal produced by the Phase Detector. This ensures low output jitter that meets network jitter requirements.
The corner frequency of the Loop Filter is configurable with an external capacitor and resistor connected to the LPF
ball and ground as shown in Figure 3.
ZL30416
Frequency
and Phase
Detector
LPF
Loop
Filter
RF=8.2 kΩ, CF=470 nF
fTYP=14.4 kHz
RF
CF
VCO
Figure 3 - Loop Filter Elements
2.5 VCO
The voltage-controlled oscillator (VCO) receives the filtered error signal from the Loop Filter and based on the
voltage of the error signal generates a primary frequency. The VCO output is connected to the "Frequency Dividers
and Clock Drivers" block that divides VCO frequency and buffer generated clocks.
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
2.6 Frequency Dividers and Clock Drivers
The output of the VCO feeds the high frequency clock to the "Frequency Dividers and Clock Drivers" circuit to
provide one differential LVPECL compatible clock with selectable frequency and one single-ended 19.44 MHz C19o
output clock. The C19o clock can be enabled or disabled with the associated C19oEN Output Enable ball.
Internally, this block provides a feedback clock that closes the PLL loop.
The frequency of the OC-CLKo differential output clock is selected with FS3, FS2 and FS1 inputs as is shown in the
following table.
OC-CLKo
FS3
FS2
FS1
Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
19.44 MHz
38.88 MHz
77.76 MHz
155.52 MHz
622.08 MHz
Reserved
Reserved
Reserved
Table 2 - OC-CLKo Clock Frequency Selection
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
3.0 ZL30416 Performance
The following are some of the ZL30416 performance indicators that complement results listed in the Characteristics
section of this data sheet.
3.1 Input Jitter Tolerance
Jitter tolerance is a measure of the PLL’s ability to operate properly (i.e., remain in lock and/or regain lock in the
presence of large jitter magnitudes at various jitter frequencies) in the presence of jitter applied to its input
reference. The input jitter tolerance of the ZL30416 is shown in Figure 4. On this graph, the single line at the top
represents the input jitter tolerance and the three overlapping lines below represent the specification for minimum
input jitter tolerance for OC-192, OC-48 and OC-12 network interfaces. The jitter tolerance is expressed in
picoseconds (pk-pk) to accommodate requirements for interfaces operating at different rates.
Figure 4 - Input Jitter Tolerance
3.2 Jitter Transfer Characteristic
Jitter Transfer Characteristic represents a ratio of the jitter at the output of a PLL to the jitter applied to the input of a
PLL. This ratio is expressed in dB and it characterizes the PLL’s ability to attenuate (filter) jitter. The ZL30416 jitter
transfer characteristic complies with the maximum 0.1 dB jitter gain specified in Telcordia’s GR-253-CORE.
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
4.0 Applications
4.1 Generation of Low Jitter SONET/SDH Equipment Clocks
The functionality and performance of the ZL30416 complements the entire family of the Zarlink’s advanced network
synchronization PLL’s. Its jitter filtering characteristics exceed requirements of SONET/SDH optical interfaces
operating up to OC-192/STM-64. The ZL30416 in combination with the MT90401 or the ZL30407 (SONET/SDH
Network Element PLL’s) provides the core building blocks for high quality equipment clocks suitable for network
synchronization (see Figure 5).
622.08 MHz
155.52 MHz
77.76 MHz
38.88 MHz
19.44 MHz
OC-CLKoP/N LVPECL
REFinP/N
C19i
ZL30416
C19o
CMOS
19.44 MHz
LPF
CF
R
F = 1 kΩ
CF = 470 nF
R
F
C19o
C155o
C34o/C44o
C16o
C8o
CMOS
19.44 MHz
PRI
LVDS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
155.52 MHz
34.368 MHz or 44.736 MHz
16.384 MHz
8.192 MHz
SEC
Synchronization
Reference
Clocks
RefSel
RefAlign
C6o
6.312 MHz
C4o
ZL30407
4.096 MHz
PRIOR
SECOR
C2o
2.048 MHz
C1.5o
F16o
F8o
1.544 MHz
8 kHz
LOCK
HOLDOVER
8 kHz
8 kHz
F0o
CMOS
20 MHz
OCXO
Data Port
uP
Controller Port
Note: Only main functional connections are shown
Figure 5 - SONET/SDH Equipment Clock
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
4.2 Recommended Interface Circuit
4.2.1 Interfacing to REFin Receiver
4.2.1.1 Interfacing REFin Receiver to LVPECL Driver
The ZL30416 REFin differential receiver can be connected to LVPECL compatible driver with an interface circuit, as
shown in Figure 7. The R1s and R2s terminating resistors should be placed close to the REFin input balls.
ZL30416
VCC=+3.3V
VDD/2
Receiver
R1
R1
Cc
Cc
Z=50 Ω
Z=50 Ω
REFinP
REFinN
LVPECL
Driver
R2
R2
Typical resistor values: R1 = 127
Ω, R2 =82.5 Ω Typical capacitor values: Cc = 0.1 µF
Figure 6 - Interfacing to LVPECL Driver
4.2.1.2 Interfacing REFin Receiver to LVDS or CML Drivers
The ZL30416 REFin differential receiver can be connected to LVDS or CML driver with an interface circuit, as
shown in Figure 7. The 100
Ω
terminating resistors should be placed close to the REFin input balls.
ZL30416
VDD/2
Receiver
Cc
Z=50 Ω
REFinP
LVDS
or
100Ω
CML
Driver
REFinN
Z=50 Ω
Cc
Typical capacitor values: Cc = 0.1 µF
Figure 7 - Interfacing to LVDS or CML Driver
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
4.2.2 Interfacing to OC-CLKo Output
4.2.2.1 LVPECL to LVPECL Interface
The OC-CLKo outputs provide differential LVPECL clocks at 622.08 MHz, 155.52 MHz, 77.76 MHz, 38.88 MHz and
19.44 MHz selectable with FS3, FS2 and FS1 frequency select inputs. The LVPECL output drivers require a 50 Ω
termination connected to the Vcc-2V source for each output terminal at the terminating end as shown below. The
terminating resistors should be placed close to the LVPECL receiver.
Typical resistor values: R1 = 127 Ω, R2 =82.5 Ω
+3.3 V
0.1 uF
VCC=+3.3 V
R1
ZL30416
VCC
LVPECL
Receiver
R1
R2
Z=50 Ω
Z=50 Ω
LVPECL
Driver
OC-CLKoP
OC-CLKoN
R2
GND
Figure 8 - LVPECL to LVPECL Interface
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
4.3 Power supply and BIAS Circuit Filtering Recommendations
Figure 9 presents a complete filtering arrangement that is recommended for applications requiring maximum jitter
performance. The level of required filtering is subject to further optimization and simplification. Please check
Zarlink’s web site for updates.
Ferrite Bead
1
2
3
4
5
6
7
8
0.1 uF
0.1 uF
10 uF
1
A
4.7 Ω
33 uF
NC
NC
NC
NC OC-CLKoP OC-CLKoN GND
NC
GND
VDD
GND
NC
NC
VCC
B
NC
VCC2
LPF
NC
VCC1
GND
NC
GND
GND
GND
FS2
NC
GND
NC
0.1 uF 0.1 uF
C
33 uF
GND
BIAS
LOCK
NC
GND
VCC
VCC
GND
220 Ω
33 uF
0.1 uF
0.1 uF
D
VCC
VDD
C19o
GND
VDD
GND
0.1 uF
E
F
NC
REFinN
REFinP
VDD
0.1 uF 0.1 uF
0.1 uF 0.1 uF
NC REF_FREQ C19oEN C19i
GND
VDD
GND
G
H
+3.3 V Power Rail
GND
NC
VDD REF_SEL FS3
GND
FS1
0.1 uF
NC
NC
VDD
GND
0.1 uF
0.1 uF
0.1 uF
0.1 uF
Notes:
1. All the ground pins (GND) are connected to the same ground plane.
2. Select Ferrite Bead with IDC > 400 mA and RDC in a range from 0.10
Ω
to 0.15 Ω.
Figure 9 - Power Supply and BIAS Circuit Filtering
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
5.0 Characteristics
Absolute Maximum Ratings†
Characteristics
Sym.
DDR, VCCR
VBALL
Min.‡
Max.‡
Units
1
2
Supply voltage
V
TBD
-0.5
TBD
V
V
Voltage on any ball
VCC + 0.5
V
DD + 0.5
3
4
5
6
Current on any ball
ESD rating
IBALL
VESD
TST
-0.5
-55
30
mA
V
1250
125
Storage temperature
Package power dissipation
°C
W
PPD
1.0
† Voltages are with respect to ground unless otherwise stated.
‡ Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions†
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
2
Operating temperature
Positive supply
TOP
-40
3.0
25
+85
3.6
°C
VDD, VCC
3.3
V
† Voltages are with respect to ground unless otherwise stated.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics†
Characteristics
Supply current
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
I
DD+ICC
185
mA
Note 1
Note 2
2
3
4
CMOS: High-level input
voltage
VIH
VIL
IIL
0.7 VDD
0
VDD
0.3 VDD
5
V
V
CMOS: Low-level input
voltage
CMOS: Input leakage current
1
uA
VI = VDD
or 0 V
5
CMOS: Input bias current for
pulled-down inputs: FS1, FS2
and FS3
IB-PU
300
uA
VI = VDD
6
7
CMOS: Input bias current for
pulled-up inputs: C19oEN
IB-PD
VOH
90
uA
V
VI = 0 V
CMOS: High-level output
voltage
2.4
IOH = 8 mA
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
DC Electrical Characteristics† (continued)
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
8
9
CMOS: Low-level output
voltage
VOL
0.4
V
IOL = 4 mA
CMOS: C19o output rise time
TR
TF
1.8
1.1
3.3
1.4
ns
ns
V
18 pF load
18 pF load
10 CMOS: C19o output fall time
11 LVPECL: Differential output
voltage
IVOD_LVPEC
LI
VOS_LVPECL
1.30
for 622 MHz
Note 2
12 LVPECL: Offset voltage
Vcc-
1.38
Vcc-
1.27
Vcc-
1.15
V
for 622 MHz
Note 2
13 LVPECL: Output rise/fall times
TRF
260
ps
for 622 MHz
Note 2
† Voltages are with respect to ground unless otherwise stated.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Note 1: The ILVPECL current is determined by the external termination network connected to LVPECL outputs. More than 25% of this
current (10 mA) flows outside the chip and it does not contribute to the internal power dissipation. The Supply Current value
listed in the table includes this current to reflect total current consumption of the ZL30416 and the attached LVPECL
termination network.
Note 2: LVPECL outputs terminated with ZT = 50 Ω resistors biased to VCC-2V (see Figure 8).
AC Electrical Characteristics† - Output Timing Parameters Measurement Voltage Levels
Characteristics
Threshold voltage
Sym.
CMOS
LVPECL
Units
1
2
3
VT-CMOS
0.5 VDD
0.5 VOD_LVPECL
V
VT-LVPECL
Rise and fall threshold voltage high
Rise and fall threshold voltage low
VHM
0.7 VDD
0.3 VDD
0.8 VOD_LVPECL
V
V
VLM
0.2 VOD_LVPECL
† Voltages are with respect to ground unless otherwise stated.
Timing Reference Points
VHM
VT
VLM
All Signals
tIF, tOF
tIR, tOR
Figure 10 - Output Timing Parameter Measurement Voltage Levels
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
AC Electrical Characteristics† - C19i Input to C19o Output Timing
Characteristics
C19i to C19o delay
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
tC19D
4.4
6.7
9.4
ns
†
Supply voltage and operating temperature are as per Recommended Operating Conditions.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i
VT-CMOS
(19.44 MHz)
tC19D
C19o
VT-CMOS
(19.44 MHz)
Note: All output clocks have nominal 50% duty cycle.
Figure 11 - C19i Input to C19o Output Timing
AC Electrical Characteristics† - REFin to C19o Output Timings
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
ns
Notes
1
2
REFin (19.44 MHz) to C19o
(19.44 MHz) delay
tR19OC19D
1.4
7.8
10
REFin (77.76 MHz) to C19o
(19.44 MHz) delay
tR77OC77D
7.9
9.9
13
ns
tR19OC19D
REFin
VT-LVPECL
(19.44 MHz)
tR77OC77D
tRW
REFin
VT-LVPECL
(77.76 MHz)
VT-CMOS
C19o
(19.44 MHz)
Figure 12 - REFin Input to C19o Output Timing
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Zarlink Semiconductor Inc.
ZL30416
Data Sheet
AC Electrical Characteristics† - C19i Input to OC-CLKo Output Timing
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
2
3
4
5
6
C19i(CMOS) to C19o(LVPECL) delay
C19i(CMOS) to OC-CLKo(38) delay
C19i(CMOS) to OC-CLKo(77) delay
C19i(CMOS) to OC-CLKo(155) delay
C19i(CMOS) to OC-CLKo(622) delay
All Output Clock duty cycle
tC19D
tC38D
tC77D
tC155D
tC622D
dC
1.4
1.2
0.9
0.6
0
3.3
3.0
2.6
2.3
0.8
50
5.1
4.8
4.4
4.1
1.6
52
ns
ns
ns
ns
ns
%
48
†
Supply voltage and operating temperature are as per Recommended Operating Conditions.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
C19i
VT-CMOS
(19.44 MHz)
tC19D
OC-CLKo(19)
VT-LVPECL
VT-LVPECL
VT-LVPECL
(19.44 MHz)
tC38D
OC-CLKo(38)
(38.88 MHz)
tC77D
OC-CLKo(77)
(77.76 MHz)
tC155D
OC-CLKo(155)
VT-LVPECL
(155.52 MHz)
tC622D
OC-CLKo(622)
VT-LVPECL
(622.08 MHz)
Note: All output clocks have nominal 50% duty cycle.
Figure 13 - C19i Input to OC-CLKo Output Timing
15
Zarlink Semiconductor Inc.
ZL30416
Data Sheet
AC Electrical Characteristics† - REFin (19.44 MHz) Input to OC-CLKo Output Timing
Characteristics
Sym.
Min.
Typ.‡
Max. Units
Notes
1
2
3
4
5
REFin(19.44 MHz) to OC-CLKo(19) delay
REFin(19.44 MHz) to OC-CLKo(38) delay
REFin(19.44 MHz) to OC-CLKo(77) delay
REFin(19.44 MHz) to OC-CLKo(155) delay
REFin(19.44 MHz) to OC-CLKo(622) delay
tC19-19D
tC19-38D
tC19-77D
tC19-155D
tC19-622D
2.4
1.9
1.7
1.4
0
4.3
4.0
3.7
3.4
0.8
6.2
6.0
5.6
5.3
1.6
ns
ns
ns
ns
ns
†
Supply voltage and operating temperature are as per Recommended Operating Conditions.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
VT-LVPECL
REFin
(19.44 MHz)
tC19-19D
OC-CLKo(19)
VT-LVPECL
(19.44 MHz)
tC19-38D
OC-CLKo(38)
VT-LVPECL
(38.88 MHz)
tC19-77D
OC-CLKo(77)
VT-LVPECL
(77.76 MHz)
tC19-155D
OC-CLKo(155)
VT-LVPECL
(155.52 MHz)
tC19-622D
OC-CLKo(622)
VT-LVPECL
(622.08 MHz)
Note: All output clocks have nominal 50% duty cycle.
Figure 14 - REFin (19.44 MHz) Input to OC-CLKo Output Timing
16
Zarlink Semiconductor Inc.
ZL30416
Data Sheet
AC Electrical Characteristics† - REFin (77.76 MHz) Input to OC-CLKo Output Timing
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Notes
1
2
3
4
5
REFin(77.76 MHz) to OC-CLKo(19) delay
REFin(77.76 MHz) to OC-CLKo(38) delay
REFin(77.76 MHz) to OC-CLKo(77) delay
REFin(77.76 MHz) to OC-CLKo(155) delay
REFin(77.76 MHz) to OC-CLKo(622) delay
tC77-19D
tC77-38D
tC77-77D
tC77-155D
tC77-622D
3.5
3.2
2.9
2.6
0
6.5
6.2
5.9
5.6
0.8
9.5
9.2
8.8
8.6
1.6
ns
ns
ns
ns
ns
†
Supply voltage and operating temperature are as per Recommended Operating Conditions.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
VT-LVPECL
REFin
(77.76 MHz)
tC77-19D
OC-CLKo(19)
VT-LVPECL
VT-LVPECL
VT-LVPECL
(19.44 MHz)
tC77-38D
OC-CLKo(38)
(38.88 MHz)
tC77-77D
OC-CLKo(77)
(77.76 MHz)
tC77-155D
OC-CLKo(155)
VT-LVPECL
(155.52 MHz)
tC77-622D
OC-CLKo(622)
VT-LVPECL
(622.08 MHz)
Note: All output clocks have nominal 50% duty cycle.
Figure 15 - REFin (77.76 MHz) Input to OC-CLKo Output Timing
17
Zarlink Semiconductor Inc.
ZL30416
Data Sheet
Performance Characteristics - Functional - (VCC = 3.3 V ±10%; TA = -40 to 85°C)
Characteristics
Pull-in range
Min.
Typ.
Max.
Units
Notes
1
2
±1000
ppm
At nominal input
reference frequency
C19i = 19.44 MHz
Lock Time
300
ms
Performance Characteristics: Output Jitter Generation - GR-253-CORE conformance (VCC = 3.3 V ±10%;
TA = -40 to 85°C)
ZL30416 Jitter Generation
GR-253-CORE Jitter Generation Requirements
Performance
Jitter
Equivalent
limit in time
domain
Interface
Limit in
UI
Measurement
Filter
Typ.†
Max.‡
Units
(Category II)
1
2
3
OC-192
STS-192
50 kHz - 80 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.1 UIPP
10.0
1.0
-
7.31
0.94
7.32
0.83
4.37
0.60
psP-P
0.01 UIRMS
0.1 UIPP
0.52
-
psRMS
psP-P
OC-48
STS-48
40.2
4.02
161
16.1
0.01 UIRMS
0.1 UIPP
0.58
-
psRMS
psP-P
OC-12
STS-12
0.01 UIRMS
0.34
psRMS
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF.
18
Zarlink Semiconductor Inc.
ZL30416
Data Sheet
Performance Characteristics: Output Jitter Generation - G.813 conformance (Option 1 and 2) (VCC = 3.3 V
±10%; TA = -40 to 85°C)
ZL30416 Jitter Generation
G.813 Jitter Generation Requirements
Performance
Jitter
Equivalent
Limit in
Interface
Measurement
Filter
limit in time
domain
Typ.†
Max.‡
Units
UI
Option 1
1
2
3
STM-64
4 MHz to 80 MHz
0.1 UIpp
0.5 UIpp
0.1 UIpp
0.5 UIpp
0.1 UIpp
0.5 UIpp
10.0
50.2
40.2
201
161
804
-
0.49
-
6.95
0.89
11.5
1.04
6.40
0.68
8.67
1.06
3.33
0.42
19.1
2.88
psP-P
psRMS
psP-P
20 kHz to 80 MHz
1 MHz to 20 MHz
5 kHz to 20 MHz
250 kHz to 5 MHz
1 kHz to 5 MHz
0.82
-
psRMS
psP-P
STM-16
STM-4
0.50
-
psRMS
psP-P
0.68
-
psRMS
psP-P
0.26
-
psRMS
psP-P
1.51
psRMS
Option 2
5
STM-64
4 MHz to 80 MHz
0.1 UIpp
0.3 UIpp
0.1 UIpp
0.1 UIpp
10.0
30.1
40.2
161
-
0.49
-
6.95
0.89
11.5
1.04
7.32
0.83
4.37
0.60
psP-P
psRMS
psP-P
psRMS
psP-P
psRMS
psP-P
psRMS
20 kHz to 80 MHz
12 kHz - 20 MHz
12 kHz - 5 MHz
0.82
-
6
7
STM-16
STM-4
0.58
-
0.34
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF.
19
Zarlink Semiconductor Inc.
ZL30416
Data Sheet
Performance Characteristics: Output Jitter Generation - ETSI EN 300 462-7-1conformance (VCC = 3.3 V ±10%;
TA = -40 to 85°C)
ZL30416 Jitter Generation
EN 300 462-7-1 Jitter Generation Requirements
Performance
Jitter
Equivalent
Limit in
Interface
Measurement
Filter
limit in time
domain
Typ.†
Max.‡
Units
UI
1
2
STM-16
1 MHz to 20 MHz
0.1 UIpp
40.2
201
161
804
-
0.50
-
6.40
0.68
8.67
1.06
3.33
0.42
19.1
2.88
psP-P
psRMS
psP-P
5 kHz to 20 MHz
0.5UIpp
0.68
-
psRMS
psP-P
STM-4
250 kHz to 5 MHz 0.1 UIpp
0.26
-
psRMS
psP-P
1 kHz to 5 MHz
0.5 UIpp
1.51
psRMS
† Typical figures are for design aid only: not guaranteed and not subject to production testing.
‡ Loop Filter components: RF=8.2 kΩ, CF=470 nF
20
Zarlink Semiconductor Inc.
Package Code
c
Zarlink Semiconductor 2003 All rights reserved.
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ACN
DATE
APPRD.
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