SP5730A/KG/QP2T [ZARLINK]
1.3 GHz Low Phase Noise Frequency Synthesiser; 1.3 GHz的低相噪频率合成器
| 型号： | SP5730A/KG/QP2T |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 1.3 GHz Low Phase Noise Frequency Synthesiser |
| 文件： | 总12页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5730
1.3 GHz Low Phase Noise Frequency Synthesiser
Data Sheet
November 2004
Features
Ordering Information
• Complete 1·3 GHz Single Chip System for Digital
SP5730A/KG/QP1T 16 Pin QSOP Tape & Reel
SP5730A/KG/QP1S 16 Pin QSOP Tubes
SP5730A/KG/MP1S 16 Pin SOIC Tubes
SP5730A/KG/MP2S 16 Pin SOIC* Tubes
SP5730A/KG/QP2T 16 Pin QSOP* Tape & Reel
SP5730A/KG/MP1T 16 Pin SOIC Tape & Reel
SP5730A/KG/MP2T 16 Pin SOIC* Tape & Reel
SP5730A/KG/QP2S 16 Pin QSOP* Tubes
*Pb Free Matte Tin
Terrestrial Television Applications
• Selectable Reference Division Ratio, Compatible with
DTT Requirements
• Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
• No RF Prescaler
• Selectable Reference/Comparison Frequency Output
prescaler phase noise degradation over the full RF
operating range. The comparison frequency is obtained
either from an on-chip crystal controlled oscillator, or from
an external source. The oscillator frequency, fREF, or phase
comparator frequency, fCOMP, can be switched to the REF/
COMP output providing a reference for a second
frequency synthesiser. The synthesiser is controlled via
an 12C bus and is fast mode compliant. It can be hard
wired to respond to one of four addresses to enable two
or more synthesisers to be used on a common bus. The
device contains four switching ports P0 - P3.
• Four Selectable I2C Addresses
• I2C Fast Mode Compliant with 3·3V and 5V Logic
Levels
• Four Switching Ports
• Functional Replacement for SP5659 (except ADC)
• Pin Compatible with SP5655
• Power Consumption 120mW with VCC = 5·5V, all Ports off
• ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Applications
• Digital Satellite, Cable and TerrestrialTuning Systems
Absolute Maximum Ratings
All voltages are referred to VEE = 0V
• Communications Systems
Supply voltage, VCC
RF differential input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance
Chip to ambient, θJA
Chip to case, θJC
-0·3V to +7V
2·5Vp-p
-0·3 to VCC +0·3V
-0·3 to 6V
-55°C to +150°C
+150°C
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1·3GHz and is
optimised for digital terrestrial applications. The RF
preamplifier interfaces direct with the RF programmable
divider, which is of MN1A construction so giving a step
size equal to the loop comparison frequency and no
80°C/W
20°C/W
11
REF/COMP
2
3
CRYSTAL CAP
CRYSTAL
12-BIT
COUNT
REFERENCE
DIVIDER
13
RF
INPUT
48/9
ENABLE/
SELECT
14
3-BIT
COUNT
1
CHARGE PUMP
DRIVE
LOCK
16
PUMP
f
PD
/2
CP MODE
DISABLE
2 BIT
5 BIT
2 BIT
2 BIT
15-BIT LATCH
10
4
ADDRESS
SDA
2
I C BUS
TRANSCEIVER
5
SCL
f /2 SELECT
PD
4-BIT LATCH AND
PORT INTERFACE
6
7
8
9
P3 P2
P1 P0
Figure 1 - SP5730 block diagram
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2001-2004, Zarlink Semiconductor Inc. All Rights Reserved.
SP5730 Datasheet
1
16
15
14
13
12
11
10
9
CHARGE PUMP
DRIVE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CHARGE PUMP
CRYSTAL CAP
CRYSTAL
DRIVE
2
CRYSTAL CAP
V
EE
V
EE
3
CRYSTAL
RF INPUT
RFINPUT
RF INPUT
RFINPUT
4
SDA
SP
5730
SDA
SP
5730
5
SCL
V
CC
SCL
V
CC
6
PORT P3/LOGLEV
REF/COMP
ADDRESS
PORTP0
PORT P3/LOGLEV
PORT P2
REF/COMP
ADDRESS
PORTP0
7
PORT P2
8
PORT P1
PORT P1
MP16
QP16
Figure 2 - Pin connections - top view
Table 1 - Electrical Characteristics
Test Conditions: TAMB = -40°C to +85°C, VCC = 4·5V to 5·5V. These characteristics are guaranteed by either
production test or design. They apply within the specified ambient temperature and supply voltage ranges unless
otherwise stated.
Value
Characteristic
Supply current
Pin
Units
Conditions
Typ. Max.
Min.
12
13,14
16
22
mA
RF input
Input voltage
12·5
40
300
300
100MHz to 1·3GHz, see Figure 3
50MHz to 100MHz, see Figure 3
See Figure 4
mVrms
mVrms
Input impedance
SDA, SCL
4,5
Input high voltage
3
2·3
0
5·5
3·5
1·5
1
10
-10
10
5V I2C logic selected
3·3V I2C logic selected
5V I2C logic selected
3·3V I2C logic selected
Input voltage = VCC
Input voltage = VEE
VCC = VEE
V
V
V
Input low voltage
0
V
Input high current
Input low current
Leakage current
Input hysteresis
SDA output voltage
µA
µA
µA
V
V
V
0·4
4
5
0·4
0·6
400
ISINK = 3mA
ISINK = 6mA
SCL clock rate
Charge pump
kHz
Output current
Output leakage
Drive output current
Crystal
Frequency
1
1
16
2,3
See Table 7, VPIN1 = 2V
VPIN1 = 2V, VCC = 15·0V, TAMB = 25°C
VPIN16 = 0·7V
±3
±10
nA
mA
0·5
2
See Figure 5 for application
20
MHz
External reference
Input frequency
Drive level
Buffered REF/COMP
Output amplitude
Output impedance
Phase Detector
Comparison frequency
Equivalent phase noise at
phase detector
3
2
0·2
20
0·5
Sinewave coupled via 10nF blocking capacitor
Sinewave coupled via 10nF blocking capacitor
AC coupled, see Note 2
0·5 to 20MHz
Enabled by bit RE = 1
MHz
Vp-p
11
0.35
250
Vp-p
Ω
4
-152
-158
MHz
dBc/Hz
dBc/Hz
fCOMP = 2MHz, SSB, See Note 4
fCOMP = 125kHz, SSB, See Note 4
RF division ratio
Reference division ratio
56
32767
See Table 2
cont…
2
Datasheet SP5730
Table 1 - Electrical Characteristics (continued)
Value
Characteristic
Pin
Units
Conditions
Typ.
Max.
Min.
Output Ports P3 - P0
Sink current
6-9
2
mA
VPORT = 0·7V
Leakage current
Address select
Input high current
Input low current
Logic level select
Input high level
Input low level
10
µA
VPORT = VCC See Note 1
See Table 5
VIN = VCC
10
6
1
-0·5
mA
µA
VIN = VEE
See Note 3
3
0
-10
VCC
1·5
10
V
V
µA
5V I2C logic level selected
3·3V I2C logic level selected
VIN = VEE to VCC
Input current
NOTES
1. Output ports high impedance on power-up, with SDA and SCL at logic ‘0’.
2. If the REF/COMP output is not used, the output should be left open circuit or connected to VCC and disabled by setting RE = ‘0’.
3. Bi-dectional port. When used as an output, the input logic state is ignored. When used as an input, the port should be switched
into high impedance (off) state.
4. Figures measured at 2kHz deviation, SSB (within loop bandwidth).
Functional Description
The SP5730 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varactor tuned
local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
good phase noise performance. It can also be operated
with comparison frequencies appropriate for frequency
offsets as required in digital terrestrial television (DTT)
receivers.
Programming
The SP5730 is controlled by an I2C data bus and is
compatible with both standard and fast mode formats and
with I2C data generated from nominal 3·3V and 5V
sources. TheI2C logic level is selected by the bi-directional
port P3/ LOGLEV. 5V logic levels are selected by
connecting P3/ LOGLEV to VCC or leaving it open circuit;
3·3V logic levels are set by connecting P3/LOGLEV to
ground. If this port is used as an input the P3 data should
be programmed to high impedance. If used as an output
only 5V logic levels can be used, in which case the logic
state imposed by the port on the input is ignored.
The RF input signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier interfaces with the
15-bit fully programmable divider which is of MN1A
architecture, where the dual modulus prescaler is 48/9,
the A counter is 3 bits, and the M counter is 12 bits.
Data and clock are fed in on the SDA and SCL lines
respectively as defined by I2C bus format . The synthesiser
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the device
into write mode if it is low, and read mode if it is high.
Tables 3 and 4 illustrate the format of the data.The device
can be programmed to respond to several addresses,
which enables the use of more than one synthesiser in
an I2C bus system. Table 5 shows how the address is
selected by applying a voltage to the address input.
The output of the programmable divider is applied to the
phase comparator where it is compared in both phase
and frequency domains with the comparison frequency.
This frequency is derived either from the on-chip crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into 1 of 29 ratios as detailed inTable 2.
When the device receives a valid address byte, it pulls
the SDA line low during the acknowledge period, and
during following acknowledge periods after further data
bytes are received.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter, integrates
the current pulses into the varactor line voltage.
The programmable divider output fPD/2 can be switched
to port P0 by programming the device into test mode.
The test modes are described inTable 6.
When the device is programmed into read mode, the
controller accepting the data must be pulled low during
all status byte acknowledge periods to read another status
byte. If the controller fails to pull the SDA line low during
this period, the device generates an internal STOP
condition, which inhibits further reading.
3
SP5730 Datasheet
4, a logic ‘0’ indicating byte 2, and a logic ‘1’ indicating
byte 4. Having interpreted this byte as either byte 2 or 4,
the following data byte will be interpreted as byte 3 or 5
respectively. Having received two complete data bytes,
additional data bytes can be entered, where byte
interpretation follows the same procedure, without re-
addressing the device. This procedure continues until a
STOP condition is received. The STOP condition can be
generated after any data byte; if, however, it occurs during
a byte transmission, the previous byte data is retained.
To facilitate smooth fine tuning, the frequency data bytes
are only accepted by the device after all 15 bits of
frequency data have been received, or after the generation
of a STOP condition.
Table 2 - Reference division ratios
R4
R2 R1 R0
Division ratio
R3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
Illegal state
5
10
20
40
80
160
320
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 4.
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the VCC supply to the device has dropped
below 3V (at 25°C ), e.g. when the device is initially turned
on. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates the programmed information may be
corrupted and the device reset to power up condition.
Illegal state
6
12
24
48
96
192
384
Illegal state
7
Bit 2 (FL) indicates whether the device is phase locked, a
logic’1’is present if the device is locked, and a logic ‘0’ if it
is not.
14
28
56
112
224
448
Programable features
• RF programmable divider Function as described
above.
• Reference programmable divider Function as
described above.
• Charge pump current The charge pump current can
be programmed by bits C1 and C0 within data byte 5,
as defined in Table 7.
Write mode
With reference to Table 3, bytes 2 and 3 contain frequency
information bits 214-20 inclusive. Bytes 4 and 5 control
the reference divider ratio (see Table 2), charge pump
setting (see Table 7), REF/COMP output (see Table 8),
output ports and test modes (see Table 6).
• Test mode The test modes are invoked by setting bits
RE, RS, T1 and T0 as described in Table 6.
• Reference/Comparison frequency output The
reference frequency fREF or comparison frequency
fCOMP can be switched to the REF/COMP output,
function as defined in Table 8. RE and RS default to
logic’1’during device power up, thus enabling the
comparison frequency fCOMP at the REF/COMP output.
After reception and acknowledgement of a correct
address (byte 1), the first bit of the following byte
determines whether the byte is interpreted as a byte 2 or
4
Datasheet SP5730
Table 3 - Write data format (MSB transmitted first)
MSB
LSB
Address
1
0
27
1
1
214
26
T1
C0
0
213
25
T0
RE
0
212
24
R4
RS
0
211
23
R3
P3
MA1
210
22
R2
P2
MA0
29
0
A
A
A
A
A
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Programmable divider
Programmable divider
Control data
28
20
R0
P0
21
R1
P1
Control data
C1
Key to Table 3.
A
Acknowledge bit
MA1, MA0 Variable address bits (see Table 5)
214-20
R4-R0
C1, C0
RE
Programmable division ratio control bits
Reference division ratio select (see Table 2)
Charge pump current select (see Table 7)
Reference oscillator output enable
RS
REF/COMP output select when RE=1 (see Table 8)
Test mode control bits (see Table 6)
P3, P2, P1 and P0 port output states
T1-T0
P3-P0
Table 4 - Read data format (MSB transmitted first)
MSB
LSB
Address
Status byte
1
POR
1
FL
0
0
0
0
0
0
MA1
0
MA0
0
1
0
A
A
Byte 1
Byte 2
Key to table 4,
A
Acknowledge bit
MA1, MA0 Variable address bits (see Table 5)
POR
Power On Reset indicator
FL
Phase lock flag
Table 5 - Address selection
Table 6 - Test modes
RE•RS T1 T0
MA1
MA0
Address input voltage level
Test mode description
Normal operation
Normal operation, P0 = fPD/2
Charge pump sink*, FL = ‘0’
Charge pump source*, FL = ‘0’
Charge pump disabled*, FL = ‘1’
0
1
X
X
X
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
0
1
0 to 0·1VCC
Open circuit
0·4VCC to 0·6VCC *
0·9VCC to VCC
*Programmed by connecting a 15kΩ resistor from pin 10 to VCC
*Clocks need to be present on crystal and RF inputs to enable
charge pump test modes and to toggle Status byte bit FL.
X = don’t care
Table 7 - Charge pump current
Table 8 - REF/COMP output
Current (µA)
C1 C0
Min.
Typ.
Max.
RE RS
REF/COMP output
0
0
1
1
0
1
0
1
±116
±247
±517
±1087
±155
±330
±690
±194
±412
±862
±1812
0
1
1
X
0
1
High impedance
fREF selected
fCOMP selected
±1450
X = don’t care
5
SP5730 Datasheet
300
40
25
OPERATING WINDOW
12.5
50 100
500
1000
1300
FREQUENCY (MHz)
Figure 3 - Typical RF input sensitivity
j1
j0.5
j2
j0.2
j5
0.5
5
0.2
1
2
0
50MHz
500MHz
2j5
2j0.2
1GHz
1·3GHz
2j2
2j0.5
S11: ZO = 50Ω
Normalised to 50Ω
2j1
Figure 4 - RF input impedance
2
18p
39p
SP5730
3
Figure 5 - Crystal oscillator application
6
J1 POWER
CONNECTOR
1
2
3
4
5
15V V
CC
C7
C9
C16
C8
130V
18V
RF2
EXT REF
C22
C23
130V
C3
R7
R8
C2
2
1
J2
VARACTOR
C6
R9
R10
C14
R12
C1
X1
T1
1
2
3
4
5
6
7
8
16
VT
V
CC
RF INPUT
RF1
18V
C19
VCO
15
14
13
12
11
10
9
C20
R11
C18
C5
C4
J5
3
RF
OUT
V
SDA5
5V
CC
SP
5730
R13
4
5
6
VCO tuning range
= 500MHz to 900MHz
C10
18V
S1
R1
R4
R5
R6
ADD
LED1
LED2
LED3
LED4
C21
SCL5
CON1
C15
C13
C12
R14
C17
C24
LK1
RF3 COMP
OUTPUT
J4
4
3
2
1
PORT
OUTPUTS
SP5730 Datasheet
Component
Value/type
Component
Value/type
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
18pF
2·2nF
68pF
1nF
C22
C23
C24
LED 1
LED 2
R1
R4
R5
R6
R7
100pF
4·7µF
1nF
HLMPK-150
HLMPK-150
4·7kΩ
1nF
10nF
100nF
4·7µF
100nF
100pF
1nF
100pF
100pF
4·7nF
100pF
4·7µF
10nF
39pF
100pF
1nF
4·7kΩ
4·7kΩ
4·7kΩ
13·3kΩ
22kΩ
1kΩ
0Ω
16Ω
16Ω
16Ω
68Ω
SW DIP-2
BCW31
POS_900
4MHz
R8
R9
R10
R11
R12
R13
R14
S1
T1
VCO
X1
1nF
Table 9 - Component values for Figure 6
8
Datasheet SP5730
Top view
Bottom view
Figure 7 - SP5730 evaluation board layout
9
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相关型号：
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