SP5730QP1S [MITEL]
1.3GHz Low Phase Noise Frequency Synthesiser; 1.3GHz的低相噪频率合成器
| 型号： | SP5730QP1S |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | 1.3GHz Low Phase Noise Frequency Synthesiser |
| 文件： | 总14页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5730
1.3GHz Low Phase Noise Frequency Synthesiser
Preliminary Information
DS4877
issue 1.9
July 1999
Features
● Complete 1.3GHz single chip system for
Digital Terrestrial Television applications
● Selectable reference division ratio, compatible
with (DTT) requirements
● Optimised for low phase noise, with
comparison frequencies up to 4MHz
● No RF prescaler
Ordering Information
SP5730A/KG/MP1S Sticks
SP5730A/KG/MP1T Tape and Reel
SP5730A/KG/QP1S Sticks
SP5730A/KG/QP1T Tape amd Reel
● Selectable reference/comparison frequency
output
● Four selectable I2C bus address
● I2C fast mode compliant and compatible with
3.3 and 5V logic levels
Description
The SP5730 is a single chip frequency synthesiser
designed for tuning systems up to 1.3GHz and is
optimised for digital terrestrial applications.
● Four switching ports
● ESD protection, (Normal ESD Handling
procedures should be observed)
The RF preamplifier interfaces direct with the RF
programmable divider, which is of MN+A construction
so giving a step size equal to the loop comparison
frequency and no prescaler phase noise degradation
over the RF operating range.
The comparison frequency is obtained either from an
on-chip crystal controlled oscillator, or from an external
source. The oscillator frequency, Fref, or phase
comparator frequency, Fcomp, can be switched to the
REF/COMP output providing a reference frequency for
a second frequency synthesiser.
Applications
● Digital Satellite ,Cable and Terrestrial tuning
systems
● Communications systems
The synthesiser is controlled via an I2C bus and is fast
mode compliant. It can be hard wired to respond to one
of four addresses to enable two or more synthesisers to
be used on a common bus.
The device contains four switching ports P0-P3.
SP5730
Preliminary Information
RF/COMP
enable/select
CRYSTAL
Osc
12 BIT
COUNT
REF DIVIDER
CRYSTAL CAP
RF INPUT
8/9
3 BIT
COUNT
CHARGE PUMP
DRIVE
PUMP
2 BIT
Lock
fpd/2
disable
c/p
mode
15 BIT LATCH
5 BIT
2 BIT
2 BIT
fpd/2 select
ADDRESS
SDA
4 BIT LATCH & PORT
INTERFACE
I2C BUS
TRANSCEIVER
SCL
PORT P3
PORT P1
PORT P2
PORT P0
Figure 1 Block diagram
1
16
DRIVE
CHARGE PUMP
V
CRYSTAL CAP
EE
RF INPUT
CRYSTAL
RF INPUT
SDA
VCC
SCL
REF/COMP
PORT P3/LOGLEV
ADDRESS
PORT P2
PORT P0
PORT P1
MP16 & QP16
Figure 2 Pin connections top view
2
Preliminary Information
Electrical Characteristics
SP5730
o
o
Tamb= -40 C to 85 C, V = 4.5 to 5.5V
CC
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
Characteristic
Supply current
Pin
Value
Typ
Units
Conditions
Min
Max
20
mA
RF input voltage
RF input voltage
RF input impedance
SDA, SCL
13,14
13,14
13,14
4, 5
12.5
40
300
300
mVrms 100 MHz – 1.3GHz, see Figure. 4
mVrms 50MHz - 100MHz, see Figure 4
See Figure. 5
Input high voltage
Input low voltage
Input high voltage
Input low voltage
Input high current
Input low current
Leakage current
3
0
5.5
1.5
3.5
1
V
V
5V I2C logic selected
5V I2C logic selected
3V3 I2C logic selected
3V3 I2C logic selected
Input voltage =Vcc
Input voltage = Vee
Vee = Vcc
2.3
0
V
V
10
10
10
µA
µA
µA
Hysteresis
SDA output voltage
0.4
V
V
V
4
0.4
0.6
Isink = 3mA
Isink = 6mA
SCL clock rate
5
1
400
kH
Charge pump output
current
See Table 6 Vpin1 = 2V
Vpin1 = 2V, Vcc = 5V, +25°C
Vpin16 = 0.7V
Charge pump output
leakage
1
3
10
nA
Charge pump drive
output current
16
2,3
0.5
mA
Crystal frequency
Recommended crystal
series resistance
2
10
20
200
MHz
Ω
See Figure 3 for application
4 MHz “parallel resonant”
crystal.
External reference input
Frequency
3
3
2
20
MHz
Vpp
Sinewave coupled through
10 nF blocking capacitor
External reference drive
level
0.2
0.5
Sinewave coupled through
10 nF blocking capacitor
3
SP5730
Preliminary Information
Electrical Characteristics (continued)
o
o
Tamb= -40 C to 85 C, Vcc= 4.5 to 5.5V
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
Characteristic
Pin
Value
Typ
Units
Conditions
Min
Max
Buffered REF/COMP output
output amplitude
11
AC coupled 0.5-20MHz
Enabled by bit RE= 1
See note 2
0.35
250
Vpp
Ω
output impedance
Phase detector Comparison
frequency
4
MHz
Equivalent phase noise at phase
detector
dBc/Hz
SSB, within loop bandwidth
Fcomp = 2MHz
Fcomp = 125kHz
-152
-158
56
RF division ratio
32767
Reference division ratio
See Table 1
Output ports P0 - P3
sink current
6-9
10
6
See Note 1
Vport = 0.7
Vport = Vcc
2
mA
µA
Leakage current
10
Address Select
Input high current
Input low current
See Figure 4 Table 3
Vin = Vcc
Vin = Vee
1
-0.5
mA
mA
Logic level select
Input high level
See note 3
3
Vcc
V
5V I2C logic selected, or
open circuit
Input low level
Input current
0
-10
1.5
10
V
µA
3V3 I2C logic selected
Vin = Vee to Vcc
Notes:
1. Output ports high impedance on power up, with data, clock, and enable at logic ‘0’
2. If the REF/COMP output is not used, the output should be left open circuit or connected to Vcc, and disabled by
setting RE = 0
3. Bi-directional port. When used as an output, the input logic state is ignored. When used as an input the port should
be switched in to high impedance (off) state.
4
Preliminary Information
SP5730
Absolute Maximum Ratings
All voltages are referred to Vee at 0V
Characteristic
Supply voltage, Vcc
RF input voltage
All I/O port DC offsets
SDA and SCL DC offset
Storage temperature
Junction temperature
QP16 thermal resistance,
chip to ambient
Min
-0.3
Max
7
2.5
Vcc+0.3
6V
+150
150
Units
V
Vpp
V
Conditions
Transient
Differential
-0.3
-0.3
-55
V
o
C
o
C
80
20
83
°C/W
°C/W
mW
chip to case
Power consumption at
Vcc = 5.5V
All ports off
ESD protection
2
kV
mil std 883 latest revision method 3015
class 1
Functional Description
The programmable divider output Fpd divided by two
can be switched to port P0 by programming the device
into test mode. The test modes are described in Table 4.
The SP5730 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varicap
tuned local oscillator, so forming a complete PLL
frequency synthesised source. The device allows for
operation with a high comparison frequency and is
fabricated in high speed logic, which enables the
generationofaloopwithgoodphasenoiseperformance.
It can also be operated with comparison frequencies
appropriate for frequency offsets as required in digital
terrestrial (DTT) receivers The block diagram is shown
in Figure 2.
Programming
The SP5730 is controlled by an I2C data bus and is
compatible with both standard and fast mode formats
and with I2C data generated from nominal 3.3V and 5V
sources.TheI2Clogiclevelisselectedbythebi-directional
port P3/LOGLEV. 5V logic levels are selected by
connecting P3/LOGLEV to Vcc or leaving open circuit
and 3.3V by connecting to ground. If this port is used as
an input the P3 data should be programmed to high
impedance. If used as an output 5V logic only levels can
be used and in this case the logic state imposed by the
port on the input is ignored.
The RF input signal is fed to an internal preamplifier,
which provides gain and reverse isolation from the
divider signals. The output of the preamplifier interfaces
direct with the 15-bit fully programmable divider, which
is of MN+A architecture, where the dual modulus
prescaler is 8/9, the A counter is 3-bits, and the M
counter is 12 bits.
Data and Clock are fed in on the SDA and SCL lines
respectivelyasdefinedbyI2Cbusformat.Thesynthesiser
can either accept data (write mode), or send data (read
mode). The LSB of the address byte (R/W) sets the
device into write mode if it is low, and read mode if it is
high. Table 2 illustrates the format of the data. The
device can be programmed to respond to several
addresses, which enables the use of more than one
synthesiserinanI2Cbussystem. Table3showshowthe
addressisselectedbyapplyingavoltagetothe‘address’
input.
The output of the programmable divider is fed to the
phase comparator where it is compared in both phase
and frequency domain with the comparison frequency.
This frequency is derived either from the on-board
crystalcontrolledoscillatororfromanexternalreference
source. In both cases the reference frequency is divided
down to the comparison frequency by the reference
divider which is programmable into 1 of 29 ratios as
detailed in Table 1.
The output of the phase detector feeds a charge pump
and loop amplifier section, which when used with an
externalhighvoltagetransistorandloopfilter, integrates
the current pulses into the varactor line voltage.
5
SP5730
Preliminary Information
When the device receives a valid address byte, it pulls
the SDA line low during the acknowledge period, and
during following acknowledge periods after further data
bytes are received. When the device is programmed into
readmode,thecontrolleracceptingthedatamustpullthe
SDA line low during all status byte acknowledge periods
toreadanotherstatusbyte.Ifthecontrollerfailstopullthe
SDA line low during this period, the device generates an
internal STOP condition, which inhibits further reading.
Programmable features
RF programmable
divider
Function as described above
Reference programmable
divider
Function as described above.
Write mode
With reference to Table 2, bytes 2 and 3 contain
Charge pump current
The charge pump current can be pro
14
0
frequency information bits 2 -2 inclusive. Byte 4 and
byte 5 control the reference divider ratio, see Table 1,
charge pump setting, see Table 6, REF/COMP output,
seeTable 7, output ports and test modes, see Table 4.
grammed by bits C1-C0 within data byte
5, as defined in Table 6.
After reception and acknowledgement of a correct ad-
dress(byte1),thefirstbitofthefollowingbytedetermines
whether the byte is interpreted as a byte 2 or 4, a logic ‘0’
indicating byte 2, and a logic ‘1’ indicating byte 4. Having
interpreted this byte as either byte 2 or 4 the following
data byte will be interpreted as byte 3 or 5 respectively.
Having received two complete data bytes, additional
data bytes can be entered, where byte interpretation
follows the same procedure, without readdressing the
device. This procedure continues until a STOP condition
is received. The STOP condition can be generated after
anydatabyte,ifhoweveritoccursduringabytetransmis-
sion, the previous byte data is retained. To facilitate
smooth fine tuning, the frequency data bytes are only
accepted by the device after all 15 bits of frequency data
have been received, or after the generation of a STOP
condition.
Test mode
ThetestmodesareinvokedbybitsREB.
RS, T1 and T0 as described in Table 4.
Reference/Comparison
frequency output
The reference frequency Fref or
comparison frequency Fcomp can be
switched to the REF/COMP output,
function as defined in Table 7.
RE and RS default to logic ‘I’ during
device power up, thus enabling the
comparison frequency Fcomp at the
REF/COMP output.
Read mode
When the device is in read mode, the status byte read
from the device takes the form shown in Table 2.
Bit 1 (POR) is the power-on reset indicator, and this is set
to a logic ‘1’ if the Vcc supply to the device has dropped
below3V(at25°C),e.g.whenthedeviceisinitiallyturned
ON. The POR is reset to ‘0’ when the read sequence is
terminated by a STOP command. When POR is set high
this indicates that the programmed information may
have been corrupted and the device reset to power up
condition.
Bit 2 (FL) indicates whether the device is phase locked,
a logic ‘1’ is present if the device is locked, and a logic ‘0’
if the device is unlocked.
6
Preliminary Information
SP5730
R4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ratio
2
4
8
16
32
64
128
256
Illegal state
5
10
20
40
80
160
320
Illegal state
6
12
24
48
96
192
384
Illegal State
7
14
28
56
112
224
448
X = don’t care
Table 1 Reference division ratio
MSB
LSB
Address
1
0
1
0
0
0
11
MA1 MA0
0
A
A
A
A
A
Byte 1
14
13
12
10
9
8
Programmable divider
Programmable divider
Control Data
2
2
2
2
2
2
2
2
2
Byte 2
Byte 3
Byte 4
Byte 5
7
6
5
4
3
2
1
0
2
2
2
2
2
2
1
T1
C0
T0
R4
RS
R3
P3
R2
P2
R1
P1
R0
P0
Control Data
C1
RE
Table 2 Write data format (MSB is transmitted first)
7
SP5730
Preliminary Information
MSB
1
POR
LSB
1
0
Address
Status byte
1
FL
0
0
0
0
0
0
MA1 MA0
A
A
Byte 1
Byte 2
0
0
Table 2 Read data format (MSB is transmitted first)
A
:
:
:
:
:
:
:
:
:
:
:
Acknowledge bit
MA1,MA0
Variable address bits (see Table 3)
Programmable division ratio control bits
Reference division ratio select (see Figure 3)
Charge pump current select (see Figure 6)
REF/COMP output enable
REF/COMP output select when RE=1 (see Figure 2)
Test mode control bits
P3 - P0 port output states
14
0
2
- 2
R4-R0
C1, C0
RE
RS
T1-T0
P3-P0
POR
FL
Power on reset indicator
Phase lock flag
MA1
MA0
Address input voltage level
0 - 0.1Vcc
0
0
1
1
0
1
0
1
Open circuit
0.4Vcc - 0.6Vcc #
0.9Vcc - Vcc
# Programmed by connecting a 30kΩ ± 5% resistor between pin 10 and Vcc
Table 3 Address selection
RE.RS
T1
0
0
T0
0
0
Test mode description
Normal operation
Normal operation Port P0 = Fpd/2
0
1
X
X
X
0
1
1
1
0
1
Charge pump sink.* Status byte FL set to logic ‘0’
Charge pump source * Status byte FL set to logic ‘0’
Charge pump disabled * Status byte FL set to logic ‘1’
*clocks need to be present on crystal and RF inputs to enable charge pump test modes and to toggle
Status byte bit FL
X = Dont Care
Table 4 Test modes
8
Preliminary Information
SP5730
C1
C0
Current in µA
byte 5, bit 1
byte 5, bit 2
Min
Typ
Max
0
0
1
1
0
1
0
1
+- 116
+- 247
+- 517
+- 1087
+- 155
+- 330
+- 690
+- 1450
+- 194
+- 412
+- 862
+- 1812
Table 6 Charge pump current
2
150pF
68pF
SP5730
3
Figure 3 XTAL oscillator application
RE
RS
REF/COMP OUTPUT
0
0
1
1
0
1
0
1
High impedance
High impedance Test mode enabled, see Figure 5
Fref selected
Fcomp selected
X = don’t care
Table 7; REF/COMP output
9
SP5730
Preliminary Information
300
37.5
25
12.5
50
100
500
1000
1300
1500
Frequency (MHz)
Figure 4 Typical RF input sensitivity
+j1
+j0.5
+j2
+j0.2
+j5
0
0.2
0.5
1
2
5
X
–j5
–j0.2
–j2
–j0.5
FREQUENCY MARKERS
AT
–j1
50MHz, 500Mhz, 1GHz 1.3GHz
Figure 5 RF input impedance
10
Preliminary Information
SP5730
11
SP5730
Preliminary Information
Figure 7 Evaluation board (top view)
Figure 8 Evaluation board (bottom view)
12
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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