SP5748/KG/MP1S [ZARLINK]
PLL Frequency Synthesizer, BIPolar, PDSO14, 0.150 INCH, PLASTIC, MS-012-AB, SOIC-14;
| 型号： | SP5748/KG/MP1S |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | PLL Frequency Synthesizer, BIPolar, PDSO14, 0.150 INCH, PLASTIC, MS-012-AB, SOIC-14 光电二极管 |
| 文件： | 总12页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5748
2.4GHz Very Low Phase Noise PLL
Datasheet
DS4875
ISSUE 2.3
November 2001
Features
Ordering Information
SP5748/KG/MP1S (Tubes)
SP5748/KG/MP1T (Tape and Reel)
(14 lead minature plastic package)
SP5748/KG/QP1S (Tubes)
• Complete 2.4 GHz Single Chip System
(for faster device refer to SP5768)
• Optimised for Low Phase Noise, with Comparison
Frequencies up to 4 MHz
SP5748/KG/QP1T (Tape and Reel)
(16 lead QSOP plastic Package)
• No RF Prescaler
• Selectable Reference Division Ratio
• Reference Frequency Output
• Selectable Charge Pump Current
• Integrated Loop Amplifier
and allows for coarse tuning in the up-converter application
and fine tuning in the down-converter.
Comparison frequencies are obtained either from a crystal
controlled on-chip oscillator or from an external source.
A buffered reference frequency output is also available to
driveasecondSP5748. Thedevicealsocontains2switching
ports.
• Two Switching Ports
• Low Power Replacement for SP5658 and SP5668
• Power Consumption 110mW with VCC = 5·5V and all
Ports off
• Downwards Software Compatible with SP5658
• ESD Protection 2kV min., MIL-STD-883B Method 3015
Cat.1 (Normal ESD handling procedures should be
observed)
Absolute Maximum Ratings
-0·3V to +7V
2·5V
Supply voltage, VCC
RF differential input voltage
RF input DC offset
Applications
-0·3 to VCC +0·3V
-0·3 to VCC +0·3V
-0·3 to VCC +0·3V
-0·3 to VCC +0·3V
-0·3 to VCC +0·3V
-0·3 to VCC +0·3V
-0·3 to VCC +0·3V
-55°C to +125°C
+150°C
Port voltage
• TV, VCR and Cable Tuning Systems
• Communications Systems
Charge pump DC offset
Varactor drive DC offset
Crystal DC offset
Buffered reference output
Data, clock and enable DC offset
Storage temperature
Junction temperature
MP14 thermal resistance
Chip to ambient, θJA
Chip to case, θJC
Description
The SP5748 is a single chip frequency synthesiser designed
for tuning systems up to 2.4 GHz and is optimized for low
phase noise with comparison frequencies up to 4 MHz. It is
designed to be downwards software compatible with the
SP5658. The RF programmable divider contains a front end
dual-modulus 416/17functioningoverthefulloperatingrange
81°C/W
27°C/W
2
CRYSTAL
CAP
13-BIT
COUNT
REFERENCE
DIVIDER
11
RF
INPUT
416/17
12
3
1
4-BIT
COUNT
CRYSTAL
PUMP
14
CHARGE
PUMP
DRIVE
9
REF
17-BIT LATCH
6-BIT LATCH
5
6
4
DATA
CLOCK
DATA
INTERFACE
ENABLE
7
8
3-BIT
PORT P1/OC
PORT P0/OP
LATCH AND
PORT/TEST MODE
INTERFACE
Figure 1 SP5748 Block Diagram (MP14 pinout)
SP5748 Datasheet
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CHARGE PUMP
CRYSTAL CAP
CRYSTAL
DRIVE
1
14
13
12
11
10
9
CHARGE PUMP
DRIVE
V
EE
2
CRYSTAL CAP
V
EE
NC
3
CRYSTAL
RF INPUT
RFINPUT
ENABLE
RF INPUT
RF INPUT
NC
SP
5748
SP
5748
4
ENABLE
DATA
5
DATA
V
CC
CLOCK
6
CLOCK
REF
PORT P1/OC
PORT P0/OP
V
CC
7
8
PORT P1/OC
PORTP0/OP
REF
MP14
QP16
Figure 2 - Pin connections - top view
Electrical Characteristics
Test conditions (unless otherwise stated): Tamb = -40°C to +80°C, VCC = 4·5V to 5·5V. These characteristics are
guaranteed by either production test or design. They apply within the specified ambient temperature and supply
voltage ranges unless otherwise stated.
Note:
Pin numbers refer to MP14 package.
Value
Characteristic
Supply current
Conditions
Pin
Units
Typ. Max.
Min.
10
13
0·8
±3
mA
20
RF input
Frequency range
Input voltage
11,12
80
30
40
MHz
-400
300 mVrms 150MHz to 2400MHz, see Figure 6
300 mVrms 80MHz to 150MHz, see Figure 6
See Figure 3
Input impedance
Data, clock and enable
Input high voltage
Input low voltage
Input current
Hysteresis
Clock rate
Bus timing
Data set up
5,6,4
3
0
-10
VCC
0·7
10
V
V
µA
Vp-p
kHz
All input conditions
6
5,6,4
500
300
600
300
600
300
ns
ns
ns
ns
ns
Data hold
Enable set up
Enable hold
Clock to enable
Charge pump
Output current
Output leakage
Drive output current
Crystal frequency
External reference
Input frequency
Drive level
1
1
14
2,3
2
µA
nA
mA
VPIN1 = 2V, See Table 1
VPIN1 = 2V, VCC = 15·0V, TAMB = 25°C
VPIN14 = 0·7V
±10
0·5
2
20
MHz See Figure 5 for application
2
0·2
20
0·5
MHz Sinewave coupled via 10nF blocking capacitor
Vp-p Sinewave coupled via 10nF blocking capacitor
Buffered reference output
Output amplitude
Output impedance
9
AC coupled, see Note 1
Vp-p 2-20MHz
0·35
250
Ω
cont…
2
Datasheet SP5748
Electrical Characteristics (continued)
Value
Typ.
Characteristic
Pin
Units
Conditions
Max.
Min.
Comparison frequency
Equivalent phase noise at
phase detector
4
MHz
-148
dBc/Hz At 10kHz SSB with 2MHz comparison
from 4MHz crystal
RF division ratio
240
2
131071
320
Reference division ratio
Output Ports P0 and P1
Sink current
See Table 2
See Note 2
7,8
2
mA
µA
VPORT = 0·7V
VPORT = VCC
Leakage current
10
NOTES
1. Reference output disabled by connecting to VCC
.
2. Output ports high impedance on power-up, with data, clock and enable at logic ‘0’.
Functional description
The SP5748 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varicap tuned
local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with
a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with
excellent phase noise performance, even with high
comparison frequencies.
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier is fed to the 17-bit
fully programmable counter, which is of MN+A
architecture. The M counter is 13 bits and the Acounter 4
bits.
The output of the programmable divider is fed to the phase
comparator where it is compared in both phase and
frequency domain with the comparison frequency. This
frequency is derived either from the on-chip crystal
controlled oscillator or from an external reference source.
In both cases the reference frequency is divided down to
the comparison frequency by the reference divider which
is programmable into1 of 16 ratios as described in Table 2.
The block diagram is shown in Figure 1 and packages
and pin allocations in Figure 2.
The SP5748 is controlled by a standard 3-wire bus
comprising data, clock and enable inputs. The
programming word contains 26 bits, two of which are used
for port selection, 17 to set the programmable divider ratio,
4 bits to select the reference division ratio (bits RD and
R0-R2, seeTable 2), two bits to set charge pump current,
bits C0 and C1 (see Table 1) and the remaining bit to
access test modes (bit T0, see Table 3)). The
programming data format is shown in Figure 4.
The output of the phase detector feeds the charge pump
and loop amplifier section, which when used with an
external high voltage transistor and loop fiIter integrates
the current pulses into the varactor line voltage. The
charge pump current setting is described in Table 1.
Abuffered crystal reference frequency suitable for driving
further synthesisers is available from pin 9. If not required
The clock input is disabled by an enable low signal, data
is therefore only loaded into the internal shift registers
during an enable high and is clocked into the controlling
buffers by an enable high to low transition. This load is
also synchronised with the programmable divider so giving
smooth fine tuning.
this output can be disabled by connecting to VCC
.
The programmable divider output divided by 2, fPD/2 and
comparison frequency, fCOMP, can be switched to ports
P0 and P1 respectively by switching the device into test
mode. The test modes are described in Table 3.
3
SP5748 Datasheet
j1
j0.5
j2
j0.2
j5
0.5
5
0.2
1
2
0
0·5GHz
1GHz
2j5
2j0.2
2·4GHz
S11: ZO = 50Ω
Normalised to 50Ω
2j2
2j0.5
2j1
Figure 3 - RF input impedance
CLOCK
ENABLE
225
P1
224
P0
223
T0
222
C1
221
C0
220
R2
219
R1
218
R0
217
RD
216
MSB
20
DATA
LSB
FREQUENCY
DATA
216 to 20
Programmable divider ratio control bits
R2, R1, R0 Reference divider control bits (see Table 2)
RD
Reference divider mode select (see Table 2)
Port control bits (see Table 3)
Charge pump current bits (see Table 1)
Test mode enable bit
P1, P0
C1, C0
T0
Figure 4 - Data format
C1
C0
Charge pump current (µA)
2
3
18pF
39pF
SP5748
0
0
1
1
0
1
0
1
±230
±1000
±115
±500
Table 1 - Charge pump current
Figure 5 - Crystal oscillator application
4
Datasheet SP5748
Test mode description
P1
P0
T0
R2 R1 R0
Division ratio
RD
X
0
0
1
1
Normal operation
Charge pump sink
Charge pump source
Charge pump disable
Port P1= fCOMP, P0 = fPD/2
X
0
1
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
64
128
256
Table 3 - Test modes
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
5
300
10
20
40
80
160
320
OPERATING WINDOW
40
30
Table 2 - Reference divider control
10
80150
1000
2400
FREQUENCY (MHz)
Figure 6 - Typical input sensitivity
38.9MHz
1.6GHz
50-900MHz
1650-2400MHz
2
SP5748
SP5748
3
VCO
10n
10
3
Figure 7 - Example of double conversion from VHF/UHF frequencies to TV IF
130V
68p
22k
18p
39p
112V
15n
13.3k
16k
47k
Optional application using
on-chip crystal controlled
oscillator
BCW31
2.2n
1
2
3
4
5
6
7
14
13
12
11
10
9
TUNER
REFERENCE
1n
1n
OSCILLATOR
OUTPUT
ENABLE
DATA
SL
5748
15V
CONTROL
MICRO
CLOCK
8
P0
P1
Figure 8 - Typical application of SP5748
5
SP5748 Datasheet
Applications
A generic set of Application Notes AN168 for designing
with synthesisers such as the SP5748 has been written,
covering aspects such as loop filter design and
decoupling. This application note is published on the
Zarlink Semiconductor web site http:/www.zarlink.com.A
generic test/demonstration board has been produced
which can be used for the SP5748; the circuit diagram is
shown in Figure 9, with component values in Table 4.
There are two ways of achieving a higher phase
comparator sampling frequency:
(1) Reduce the division ratio between the reference
source and the phase comparator
(2) use a higher reference source frequency.
Approach (2) may be preferred for best performance since
it is possible that the noise floor of the reference osciliator
may degrade the phase comparator performance if the
reference division ratio is very small.
The board can be used for the following purposes:
● Measuring RF sensitivity performance.
● Indicating port function.
Loop bandwidth
● Synthesising the voltage controlled oscillator.
● Testing of external reference.
● Measurement of phase noise performance.
The majority of applications for which the SP5748 is
intended require a loop filter bandwidth of between 2kHz
and10kHz.
Reference source
Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange
the loop filter bandwidth such that the 1kHz figure lies
within the loop bandwidth. Thus the phase noise depends
on the synthesiser comparator noise floor, rather than
the VCO.
The SP5748 offers optimal LO phase noise performance
when operated with a large step size. This is due to the
fact that the LO phase comparator noise within the loop
bandwidth is:
LO frequency
+20log10
(
)
Phase comparator frequency
The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.
Assuming the phase comparator noise floor is flat
irrespective of sampling frequency, this means that the
best performance will be achieved when the overall LO
Component
Value/type
Component
Value/type
C1
C2
C3
C4
C5
18pF
2·2nF
68pF
1nF
C20
C21
LED 1
LED 2
R1
1nF
1nF
HLMPK-150
HLMPK-150
4·7kΩ
1nF
C6
C7
C8
C9
10nF
100nF
4·7µF
100nF
10pF
1nF
100pF
100pF
4·7nF
100pF
4·7µF
10nF
39pF
100pF
R4
R6
R7
R8
4·7kΩ
13·3kΩ
22kΩ
1kΩ
0Ω
16Ω
16Ω
16Ω
68Ω
SW DIP-2
BCW31
POS_2000
4MHz
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
R9
R10
R11
R12
R13
R14
S1
T1
VCO
X1
Table 4 - Component values for Figure 9
6
Datasheet SP5748
C 1 8
Figure 9 - SP5748 evaluation board
7
SP5748 Datasheet
Top view
Bottom view
Figure 10 - SP5748 evaluation board layout
8
Datasheet SP5748
V
CC
V
CC
500
500
CHARGE PUMP
RF
INPUTS
200
DRIVE
Figure 11b Loop amplifier
Figure 11a RF inputs
V
CC
PORT
25k
Figure 11c Enable, Data and Clock inputs
Figure 11d Output ports
V
CC
V
CC
CRYSTAL
REF
CRYSTAL CAP
1·2mA
Figure 11e Reference oscillator
Figure 11f Reference output
Figure 11 - Input/output interface circuits
9
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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