SP5748GBK0AVKU6R_技术文档

Document Number MPC5748G

Rev. 6, 11/2018

NXP Semiconductors

Data Sheet: Technical Data

MPC5748G

MPC5748G Microcontroller

Data Sheet

Features

• Boot Assist Flash (BAF) supports internal flash

programming via a serial link (LIN / SCI)

• 2 x 160 MHz Power Architecture® e200Z4 Dual issue,

32-bit CPU

• Analog

– Single precision floating point operations

– 8 KB instruction cache and 4 KB data cache

– Variable length encoding (VLE) for significant code

density improvements

– Two analog-to-digital converters (ADC), one 10-bit

and one 12-bit

– Three analogue comparators

– Cross Trigger Unit to enable synchronization of

ADC conversions with a timer event from the

eMIOS or from the PIT

• 1 x 80 MHz Power Architecture® e200Z2 Single issue,

32-bit CPU

– Using variable length encoding (VLE) for

significant code size footprint reduction

• Communication

– Four Deserial Peripheral Interface (DSPI)

– Six Serial Peripheral interface (SPI)

– 18 serial communication interface (LIN) modules

– Eight enhanced FlexCAN3 with FD support

– Four inter-IC communication interface (IIC)

– One USB OTG Controller (USB_0) and One USB

SPH Controller (USB_1) with ULPI Interface.

– ENET complex (10/100 Ethernet) that supports

Multi queue with AVB support, 1588, and MII/

RMII

• End to end ECC

– All bus masters, for example, cores generate single

error correction, double error detection (SECDED)

code for every bus transaction

– SECDED covers 64-bit data and 29-bit address

• Memory interfaces

– 6 MB on-chip flash supported with the flash

controller

– 3 x flash page buffers (3 port flash controller)

– 768 KB on-chip SRAM across three RAM ports

– 2 x ENET with L2 switch

– Secure Digital Hardware Controller (uSDHC)

– Dual-channel FlexRay Controller

• Clock interfaces

– 8-40 MHz external crystal (FXOSC)

– 16 MHz IRC (FIRC)

– 128 KHz IRC (SIRC)

– 32 KHz external crystal (SXOSC)

– Clock Monitor Unit (CMU)

– Frequency modulated phase-locked loop (FMPLL)

– Real Time Counter (RTC)

• Audio

– 3 x Synchronous Audio Interface (SAI)

– Fractional clock dividers (FCD) operating in

conjunction with the SAIs

• Configurable I/O domains supporting FLEXCAN,

LINFlex, Ethernet, USB, MLB, uSDHC and general

I/O

• 2x System Memory Protection Unit (SMPU) each with

16 region descriptors and 16-byte region granularity

• Supports wake-up from low power modes via the

WKPU controller

• 16 Semaphores to manage access to shared resource

• On-chip voltage regulator (VREG)

• Interrupt controller (INTC) capable of routing

interrupts to any CPU

• Debug functionality

– e200Z2 core:NDI per IEEE-ISTO 5001-2008

• Multiple crossbar switch architecture for concurrent

access to peripherals, flash, and RAM from multiple

bus masters

Class3+

– e200Z4 core(s): NDI per IEEE-ISTO 5001-2008

Class 3+

• 32-channels eDMA controller with multiple transfer

request sources using DMAMUX

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

• Timer

– 16 Periodic Interrupt Timers (PITs)

– Three System Timer Module (STM)

– Four Software WatchDog Timers (SWT)

– 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels

• Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and

1149.7 (cJTAG)

• Security

– Hardware Security Module (HSMv2)

– Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management

– One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts

• Functional Safety

– ISO26262 ASIL compliance

• Multiple operating modes

– Includes enhanced low power operation

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

2

NXP Semiconductors

Table of Contents

1

2

3

Block diagram.................................................................................... 4

6.3.5 Flash memory AC timing specifications................... 40

6.3.6 Flash read wait state and address pipeline control

settings ......................................................................41

Family comparison.............................................................................4

Ordering parts.....................................................................................9

3.1 Determining valid orderable parts ..........................................9

3.2 Ordering Information ............................................................. 9

General............................................................................................... 10

4.1 Absolute maximum ratings..................................................... 10

4.2 Recommended operating conditions....................................... 11

4.3 Voltage regulator electrical characteristics............................. 13

4.4 Voltage monitor electrical characteristics...............................16

4.5 Supply current characteristics................................................. 18

4.6 Electrostatic discharge (ESD) characteristics......................... 21

4.7 Electromagnetic Compatibility (EMC) specifications............ 22

I/O parameters....................................................................................22

5.1 AC specifications @ 3.3 V Range...........................................22

5.2 DC electrical specifications @ 3.3V Range............................23

5.3 AC specifications @ 5 V Range..............................................24

5.4 DC electrical specifications @ 5 V Range..............................25

5.5 Reset pad electrical characteristics..........................................26

5.6 PORST electrical specifications..............................................28

Peripheral operating requirements and behaviours............................28

6.1 Analog..................................................................................... 28

6.1.1 ADC electrical specifications....................................28

6.1.2 Analog Comparator (CMP) electrical specifications 32

6.2 Clocks and PLL interfaces modules........................................33

6.2.1 Main oscillator electrical characteristics................... 33

6.2.2 32 kHz Oscillator electrical specifications ...............35

6.2.3 16 MHz RC Oscillator electrical specifications........ 35

6.2.4 128 KHz Internal RC oscillator Electrical

6.4 Communication interfaces.......................................................41

6.4.1 DSPI timing...............................................................41

6.4.2 FlexRay electrical specifications...............................47

4

6.4.2.1

6.4.2.2

6.4.2.3

6.4.2.4

FlexRay timing...................................... 47

TxEN......................................................48

TxD........................................................49

RxD........................................................50

6.4.3 uSDHC specifications............................................... 51

6.4.4 Ethernet switching specifications..............................52

6.4.5 MediaLB (MLB) electrical specifications.................54

5

6.4.5.1

6.4.5.2

MLB 3-pin interface DC characteristics54

MLB 3-pin interface electrical

specifications......................................... 54

6.4.6 USB electrical specifications.....................................56

6.4.6.1

6.4.6.2

USB electrical specifications.................56

ULPI timing specifications....................56

6.4.7 SAI electrical specifications .....................................58

6.5 Debug specifications............................................................... 60

6.5.1 JTAG interface timing ..............................................60

6.5.2 Nexus timing............................................................. 62

6.5.3 WKPU/NMI timing...................................................64

6.5.4 External interrupt timing (IRQ pin)...........................65

Thermal attributes.............................................................................. 65

7.1 Thermal attributes................................................................... 65

Dimensions.........................................................................................67

8.1 Obtaining package dimensions ...............................................67

Pinouts................................................................................................68

9.1 Package pinouts and signal descriptions................................. 68

6

7

8

9

specifications ............................................................ 36

6.2.5 PLL electrical specifications .................................... 36

6.3 Memory interfaces...................................................................37

6.3.1 Flash memory program and erase specifications.......37

6.3.2 Flash memory Array Integrity and Margin Read

10 Reset sequence................................................................................... 68

10.1 Reset sequence duration..........................................................68

10.2 BAF execution duration.......................................................... 68

10.3 Reset sequence description......................................................69

11 Revision History.................................................................................71

specifications............................................................. 38

6.3.3 Flash memory module life specifications..................39

6.3.4 Data retention vs program/erase cycles.....................39

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

3

Block diagram

1 Block diagram

System bus masters

80 MHz e200z2

160 MHz e200z4

uSDHC

MLB150

HSM

Ethernet(ENET)

Ethernet Switch

64-bit AHB

E2 E-ECC

Nexus 3+

System

3 x STM

8 KB i-cache 4 KB d-cache

WKPU

BAF

eDMA

Flexray

SPFP-APU

E2 E-ECC

Nexus 3+

PMC

HS_USBSPH HS_USBOTG

64-bit AHB

FMPLL

16 MHz FIRC

RTC/API

DEBUG/

JTAG

4 x SWTs

16 x SEMA4

16 x PIT-RTI

FCCU

PASS

SSCM

64-bit data

E2 E-ECC

SMPU

3 x DSMC

2 x DSMC

32 KHz

SXOSC

MC_CGM,

MC_PCU,

MC_ME,

Peripheral

Flash

3xRAM

E2 E-ECC

bridge

Low power

unit interface

MC_RGM

E2 E-ECC

3 x SA-PF buffers

Triple ported

64-bit wide RAM

256 KB array

128 KHz

SIRC

SIUL

8–40 MHz

FXOSC

STCU

(MBIST/

LBIST)

6 MB array (inc EEE)

2 x MEMU

CMU

TDM

Peripheral clusters

Padkeeper

support

80 ch 10-bit ADC0 64 ch 12-bit ADC1 1 x FlexCAN(PN)

1x 18 LinFlex

(mix int and ext)

7 x FlexCAN

Register

protection

LPU_CTL

2

C

4 x I

3 x analog

4 x DSPI

6 x SPI

3 x SAI

3 x FCD

comparator (CMP)

3 x eMIOS + BCTU

3-core INTC

DMA and

2 x chmux

1 x CRC

*All FlexCANs optionally

support CAN FD

Figure 1. MPC5748G block diagram

2 Family comparison

The following table provides a summary of the different members of the MPC5748G

family and their proposed features. This information is intended to provide an

understanding of the range of functionality offered by this family. For full details of all of

the family derivatives please contact your marketing representative.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

4

NXP Semiconductors

Family comparison

NOTE

All optional features (Flash memory, RAM, Peripherals) start

with lowest peripheral number (for example: STM_0) or

memory address and end at the highest available peripheral

number or memory address (for example: MPC574xC have 2

STM, ending with STM_1).

Table 1. MPC5748G Family Comparison1

Feature

MPC5747C

e200z4

MPC5748C

e200z4

MPC5746G

e200z4

MPC5747G

e200z4

MPC5748G

e200z4

CPUs

e200z2

e200z4

e200z2

FPU

e200z4

Maximum

Operating

Frequency²

160MHz (z4)

80MHz (z2)

160MHz (z4)

80MHz (z2)

160MHz (z4)

80MHz (z2)

3 MB

160MHz (z4)

80MHz (z2)

4 MB

160MHz (z4)

80MHz (z2)

6 MB

Flash memory

EEPROM support

RAM

4 MB

6 MB

32 KB to 128 KB emulated

512 KB

32 KB to 192 KB emulated

768 KB

ECC

End to End

SMPU

SMPU_0: 12 entry, SMPU_1: 12 entry

SMPU_0: 16 entry, SMPU_1: 16 entry

32 channels

DMA

10-bit ADC

48 Standard channels

32 External channels

16 Precision channels

16 Standard channels

32 External channels

3

12-bit ADC

AnalogComparator

BCTU

1

SWT

2

4³

3

STM

PIT-RTI

16 channels PIT

1 channels RTI

Yes

RTC/API

Total Timer I/O⁴

96 channels

16-bits

LINFlexD

FlexCAN

DSPI/SPI

1 M/S, 15 M

1 M/S, 17 M

8 with optional CAN FD support

4 x DSPI

6 x SPI

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

5

Family comparison

Table 1. MPC5748G Family Comparison1 (continued)

Feature

I²C

MPC5747C

MPC5748C

MPC5746G

4

MPC5747G

MPC5748G

SAI/I²S

FXOSC

SXOSC

FIRC

3

8 - 40 MHz

32 KHz

16 MHz

128 KHz

Yes

SIRC

FMPLL

LPU

Yes

FlexRay 2.1 (dual

channel)

Yes, 128 MB

MLB150

USB 2.0 SPH

USB 2.0 OTG

SDHC

0

1

Ethernet (RMII, MII

+ 1588, Muti queue

AVB support)

Up to 2

3 Port L2 Ethernet

Switch

Optional

CRC

MEMU

1

2

STCU

1

Optional

Yes

HSM-v2 (security)

Censorship

FCCU

1

Safety level

User MBIST

User LBIST

Specific functions ASIL-B certifiable

Yes

I/O Retention in

Standby

GPI

17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA)

GPIO

Debug

129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA)

JTAGC,

cJTAG

Nexus

Z4 N3+

Z2 N3+

Packages

176 LQFP-EP

256 BGA, 324 BGA

1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package

dependent.

2. Based on 125°C ambient operating temperature and subject to full device characterisation.

3. Additional SWT included when HSM option selected

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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NXP Semiconductors

Family comparison

4. Refer device datasheet and reference manual for information on to timer channel configuration and functions.

Table 2. MPC5748G Family Comparison - NVM Memory Map 1

Start Address

End Address

Flash block

RWW

MPC5746

MPC5747

MPC5748

0x01000000

0x0103FFFF

256 KB code

Flash block 0

6

available

0x01040000

0x01080000

0x010C0000

0x01100000

0x01140000

0x01180000

0x011C0000

0x01200000

0x01240000

0x01280000

0x012C0000

0x01300000

0x01340000

0x01380000

0x013C0000

0x01400000

0x01440000

0x01480000

0x14C0000

0x01500000

0x01540000

0x0107FFFF

0x010BFFFF

0x010FFFFF

0x0113FFFF

0x0117FFFF

0x011BFFFF

0x011FFFFF

0x0123FFFF

0x0127FFFF

0x012BFFFF

0x012FFFFF

0x0133FFFF

0x0137FFFF

0x013BFFFF

0x013FFFFF

0x0143FFFF

0x0147FFFF

0x014BFFFF

0x014FFFFF

0x0153FFFF

0x0157FFFF

256 KB code

Flash block 1

6

7

8

9

available

256 KB code

Flash block 2

256 KB code

Flash block3

available

256 KB code

Flash block 4

available

256 KB code

Flash block 5

available

256 KB code

Flash block 6

available

256 KB code

Flash block 7

available

256 KB code

Flash block 8

available

256 KB code

Flash block 9

available

256 KB code

Flash block 10

not available

available

256 KB code

flash block 11

available

256 KB code

flash block 12

available

256 KB code

flash block 13

available

256 KB code

flash block 14

not available

256 KB code

flash block 15

256 KB code

flash block 16

256 KB code

flash block 17

256 KB code

flash block 18

256 KB code

flash block 19

256 KB code

flash block 20

256 KB code

flash block 21

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

7

Family comparison

Table 3. MPC5748G Family Comparison - NVM Memory Map 2

Start Address

End Address

Flash block

RWW

MPC5747C

MPC5748C

MPC5746G

MPC5747G

MPC5748G

available

0x00F90000

0x00F94000

0x00F98000

0x00F9C000

0x00FA0000

0x00FA4000

0x00FA8000

0x00FAC000

0x00FB0000

0x00FB8000

0x00FC0000

0x00FC8000

0x00FD0000

0x00FD8000

0x00FE0000

0x00FF0000

0x00F93FFF

0x00F97FFF

0x00F9BFFF

0x00F9FFFF

0x00FA3FFF

0x00FA7FFF

0x00FABFFF

0x00FAFFFF

0x00FB7FFF

0x00FBFFFF

0x00FC7FFF

0x00FCFFFF

0x00FD7FFF

0x00FDFFFF

0x00FEFFFF

0x00FFFFFF

16 KB data Flash

32 KB data Flash

32 KB data flash

64 KB data flash

2

3

2

3

0

1

0

1

available

not available

available

Table 4. MPC5748G Family Comparison - RAM Memory Map

Start Address

End Address

Allocated size [KB]

MPC5747C

MPC5748C

MPC5746G

MPC5747G

MPC5748G

available

0x40000000

0x40002000

0x40010000

0x40020000

0x40040000

0x40080000

0x40001FFF

0x4000FFFF

0x4001FFFF

0x4003FFFF

0x4007FFFF

0x400BFFFF

8

available

56

available

64

available

128

256

available

not available

available

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

8

NXP Semiconductors

Ordering parts

3 Ordering parts

3.1 Determining valid orderable parts

To determine the orderable part numbers for this device, go to www.nxp.com and

perform a part number search for the following device number: MPC5748G .

3.2 Ordering Information

R

6

P

PC

57

4

8

G

S

K0

M

MJ

Example Code

Qualification Status

Power Architecture

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Optional fields

Fab and mask indicator

Temperature spec.

Package Code

CPU Frequency

R = Tape & Reel (blank if Tray)

Product Version

Package Code

Qualification Status

KU = 176 LQFP EP

MJ = 256 MAPBGA

MN = 324 MAPBGA

C = Body Control Feature Set

G = Gateway Feature Set

P = Engineering samples

S = Automotive qualified

Optional fields

PC = Power Architecture

CPU Frequency

2 = Each z4 operates up to 120

MHz

Blank = Feature not available

Automotive Platform

S = HSM (Security Module)

F = CAN FD

57 = Power Architecture in 55nm

6 = Each z4 operates up to 160

MHz

B = Both HSM and CAN FD

T = HSM and 2nd Ethernet

G = CAN FD and 2nd Ethernet

Core Version

Shipping Method

R = Tape and reel

Blank = Tray

4 = e200z4 Core Version (highest

core version in the case of multiple

cores)

H = HSM, CAN FD, and 2nd Eternet

Fab and mask version indicator

K=TSMC Fab

#=Version of maskset

0=0N65H

1=1N81M

0A=0N78S

Temperature spec.

C = -40.C to +85.C Ta

V = -40.C to +105.C Ta

M = -40.C to +125.C Ta

Flash Memory Size

6 = 3 MB

7 = 4 MB

8 = 6 MB

,

Note: Not all part number combinations are available as production product

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

9

General

4 General

4.1 Absolute maximum ratings

NOTE

Functional operating conditions appear in the DC electrical

characteristics. Absolute maximum ratings are stress ratings

only, and functional operation at the maximum values is not

guaranteed. See footnotes in Table 5 for specific conditions

Stress beyond the listed maximum values may affect device

reliability or cause permanent damage to the device.

Table 5. Absolute maximum ratings

Symbol

Parameter

Conditions¹

Min

Max

Unit

V_{DD_HV_A}, V_{DD_HV_B}

,

3.3 V - 5. 5V input/output supply voltage

—

–0.3

6.0

V

2

V_{DD_HV_C}

3, 4

V_{DD_HV_FLA}

3.3 V flash supply voltage (when supplying

from an external source in bypass mode)

—

–0.3

3.63

V

5

V_{DD_LP_DEC}

Decoupling pin for low power regulators⁶

3.3 V / 5.0 V ADC1 high reference voltage

3.3 V to 5.5V ADC supply voltage

—

–0.3

1.32

6

V

7

V_{DD_HV_ADC1_REF}

V_{DD_HV_ADC0}

V_{DD_HV_ADC1}

V_{SS_HV_ADC0}

V_{SS_HV_ADC1}

6.0

3.3V to 5.5V ADC supply ground

—

–0.1

0.1

V

8, 9, 10, 11

V_{DD_LV}

Core logic supply voltage

—

–0.3

1.32

V

V_INA

Voltage on analog pin with respect to

Min (V_{DD_HV_x},

ground (V_{SS_HV}

)

V_{DD_HV_ADCx}

V_{DD_ADCx_REF}

+0.3

,

)

V_IN

Voltage on any digital pin with respect to

ground (V_{SS_HV}

Relative to

–0.3

V_{DD_HV_x}+ 0.3

V

)

V_{DD_HV_A}

V_{DD_HV_B}

,

V_{DD_HV_C}

I_INJPAD

I_INJSUM

T_ramp

Injected input current on any pin during

overload condition

Always

–5

5

mA

Absolute sum of all injected input currents

during overload condition

—

–50

50

Supply ramp rate

—

0.5 V / min

-40

100V/ms

125

—

°C

12

T_A

Ambient temperature

Storage temperature

T_STG

–55

165

1. All voltages are referred to VSS_HV unless otherwise specified

2. VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

10

NXP Semiconductors

General

3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V

4. VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V

5. This pin should be decoupled with low ESR 1 µF capacitor.

6. Not available for input voltage, only for decoupling internal regulators

7. 10-bit ADC does not have dedicated reference and its reference is double bonded to 10-bit ADC supply(VDD_HV_ADC0).

8. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum T_J= 150 °C, remaining time as defined in footnotes 10

and 11.

9. Allowed 1.38 – 1.45 V– for 10 hours cumulative time at maximum T_J= 150 °C, remaining time as defined in footnote 11.

10. 1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at

maximum T_J= 150 °C.

11. If HVD on core supply (V_{HVD_LV_x}) is enabled, it will generate a reset when supply goes above threshold.

12. T_J=150°C. Assumes T_A=125°C

• Assumes maximum θJA. SeeThermal attributes

4.2 Recommended operating conditions

The following table describes the operating conditions for the device, and for which all

specifications in the data sheet are valid, except where explicitly noted. The device

operating conditions must not be exceeded in order to guarantee proper operation and

reliability. The ranges in this table are design targets and actual data may vary in the

given range.

NOTE

• For normal device operations, all supplies must be within

operating range corresponding to the range mentioned in

following tables. This is required even if some of the

features are not used.

• If VDD_HV_A is in 5.0V range, VDD_HV_FLA should be

externally supplied using a 3.3V source. If VDD_HV_A is

in 3.3V range, VDD_HV_FLA should be shorted to

VDD_HV_A.

• VDD_HV_A, VDD_HV_B and VDD_HV_C are all

independent supplies and can each be set to 3.3V or 5V.

The following tables: 'Recommended operating conditions

(VDD_HV_x = 3.3 V)' and table 'Recommended operating

conditions (VDD_HV_x = 5 V)' specify their ranges when

configured in 3.3V or 5V respectively.

Table 6. Recommended operating conditions (V_{DD_HV_x}= 3.3 V)

Symbol

V_{DD_HV_A}

V_{DD_HV_B}

V_{DD_HV_C}

V_{DD_HV_FLA}

Parameter

Conditions¹

Min²

Max

Unit

HV IO supply voltage

—

3.15

3.6

V

3

HV flash supply voltage

—

3.15

3.6

V

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

11

General

Table 6. Recommended operating conditions (V_{DD_HV_x}= 3.3 V) (continued)

Symbol

Parameter

Conditions¹

Min²

Max

5.5

Unit

V

V_{DD_HV_ADC1_REF}HV ADC1 high reference voltage

—

3.0

V_{DD_HV_ADC0}

V_{DD_HV_ADC1}

HV ADC supply voltage

HV ADC supply ground

max(VDD_H

V_A,VDD_H

V_B,VDD_H

V_C) - 0.05

3.6

V

V_{SS_HV_ADC0}

V_{SS_HV_ADC1}

—

-0.1

0.1

V

4

V_{DD_LV}

Core supply voltage

—

1.2

3.15

-3.0

1.32

3.6

V

5, 6

V_{IN1_CMP_REF}

I_INJPAD

Analog Comparator DAC reference voltage

Injected input current on any pin during

overload condition

3.0

mA

T_A

T_J

Ambient temperature under bias

f_CPU≤ 160

MHz

–40

125

150

°C

Junction temperature under bias

—

1. All voltages are referred to V_{SS_HV}unless otherwise specified

2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the

point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.

3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V

4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be

left floating.

5. VIN1_CMP_REF ≤ VDD_HV_A

6. This supply is shorted VDD_HV_A on lower packages.

NOTE

If VDD_HV_A is in 5V range, it is necessary to use internal

Flash supply 3.3V regulator. VDD_HV_FLA should not be

supplied externally and should only have decoupling capacitor.

Table 7. Recommended operating conditions (V_{DD_HV_x}= 5 V)

Symbol

V_{DD_HV_A}

V_{DD_HV_B}

V_{DD_HV_C}

V_{DD_HV_FLA}

Parameter

Conditions ¹

Min²

Max

Unit

HV IO supply voltage

—

4.5

5.5

V

3

HV flash supply voltage

—

3.15

3.6

5.5

V

V_{DD_HV_ADC1_REF}HV ADC1 high reference voltage

V_{DD_HV_ADC0}

HV ADC supply voltage

max(VDD_H

V_A,VDD_H

V_B,VDD_H

V_C) - 0.05

V_{DD_HV_ADC1}

V_{SS_HV_ADC0}

V_{SS_HV_ADC1}

HV ADC supply ground

Core supply voltage

—

-0.1

0.1

V

4

V_{DD_LV}

1.2

1.32

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

12

NXP Semiconductors

General

Table 7. Recommended operating conditions (V_{DD_HV_x}= 5 V) (continued)

Symbol

V_{IN1_CMP_REF}

I_INJPAD

Parameter

Conditions ¹

Min²

3.15

-3.0

Max

5.5

Unit

V

5

Analog Comparator DAC reference voltage

—

Injected input current on any pin during

overload condition

3.0

mA

T_A

T_J

Ambient temperature under bias

f_CPU≤ 160

MHz

–40

125

150

°C

Junction temperature under bias

—

1. All voltages are referred to V_{SS_HV}unless otherwise specified

2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the

point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset.

3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with C_{flash_reg}

.

4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be

left floating

5. This supply is shorted VDD_HV_A on lower packages.

4.3 Voltage regulator electrical characteristics

The voltage regulator is composed of the following blocks:

• Choice of generating supply voltage for the core area.

• Control of external NPN ballast transistor

• Connecting an external 1.25 V (nominal) supply directly without the NPN ballast

• Internal generation of the 3.3 V flash supply when device connected in 5V

applications

• External bypass of the 3.3 V flash regulator when device connected in 3.3V

applications

• Low voltage detector - low threshold (LVD_IO_A_LO) for V_{DD_HV_IO_A supply}

• Low voltage detector - high threshold (LVD_IO_A_Hi) for V_{DD_HV_IO_A supply}

• Various low voltage detectors (LVD_LV_x)

• High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV)

• Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV)

• Power on Reset (POR_HV) for 3.3 V to 5 V supply (VDD_HV_A)

The following bipolar transistors¹are supported, depending on the device performance

requirements. As a minimum the following must be considered when determining the

most appropriate solution to maintain the device under its maximum power dissipation

capability: current, ambient temperature, mounting pad area, duty cycle and frequency for

Idd, collector voltage, etc

1. BCP56, MCP68 and MJD31are guaranteed ballasts.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

13

General

LPPREG

V_{DD_LP_DEC}

V_{DD_HV_BALLAST}

ULPPREG

C_LP/ULPREG

VRC_CTRL

V_{SS_HV}

FPREG

C

BE_FPREG

Flash

voltage

regulator

VDD_HV_FLA

V

DD_LV

C_{FLASH_REG}

C_{FP_REG}

V_{SS_HV}

DEVICE

Figure 2. Voltage regulator capacitance connection

Table 8. Voltage regulator electrical specifications

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

1

C_{fp_reg}

External decoupling / stability

capacitor

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1.32

2.2²

3

µF

Combined ESR of external

capacitor

—

0.001

0.8

—

1

0.03

1.4

Ohm

µF

C_{lp/ulp_reg}External decoupling / stability

capacitor for internal low power

regulators

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

Combined ESR of external

capacitor

—

0.001

—

0.1

Ohm

nF

3

C_{be_fpreg}

Capacitor in parallel to base-

emitter

BCP68 and BCP56

MJD31

3.3

4.7

2.2

4

C_{flash_reg}

External decoupling / stability

capacitor for internal Flash

regulators

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1.32

3

µF

Combined ESR of external

capacitor

—

0.001

—

0.03

Ohm

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

14

NXP Semiconductors

General

Table 8. Voltage regulator electrical specifications (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

C_{HV_VDD_A}

VDD_HV_A supply capacitor

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

—

µF

C_{HV_VDD_B}

VDD_HV_B supply capacitor⁵

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

—

µF

V

C_{HV_VDD_C}VDD_HV_C supply capacitor⁵

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

C_{HV_ADC0}HV ADC supply decoupling

capacitances

C_{HV_ADC1}

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

1

—

6

C_{HV_ADR}

HV ADC SAR reference supply

decoupling capacitances

Min, max values shall be granted

with respect to tolerance, voltage,

temperature, and aging

variations.

0.47

2.25

—

V_{DD_HV_BALL}FPREG Ballast collector supply

When collector of NPN ballast is

directly supplied by an on board

supply source (not shared with

VDD_HV_A supply pin) without

any series resistance, that is,

R_{C_BALLAST}less than 0.01 Ohm.

5.5

7

voltage

AST

R_{C_BALLAST}Series resistor on collector of

FPREG ballast

When VDD_HV_BALLAST is

shorted to VDD_HV_A on the

board

—

0.1

—

Ohm

t_SU

Start-up time after main supply

stabilization

Cfp_reg = 3 μF

74

μs

µs

t_ramp

Load current transient

Iload from 15% to 55%

C_{fp_reg}= 3 µF

1.0

1. Split capacitance on each pair VDD_LV pin should sum up to a total value of C_{fp_reg}

2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and

maximum values.

3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is

recommended. The tolerance +/-20% is acceptable.

4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing

inductance should be less than 1nH.

5.

1. For VDD_HV_A, VDD_HV_B, and VDD_HV_C, 1µf on each side of the chip

a. 0.1 µf close to each VDD/VSS pin pair.

b. 10 µf near for each power supply source

c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation

mode, this amount of capacitance will need to be subtracted from the total capacitance required by the

regulator for e.g., as specified by CFP_REG parameter.

2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this

amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as

specified by CFP_REG parameter

6. Only applicable to ADC1

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

15

General

7. In external ballast configuration the following must be ensured during power-up and power-down (Note: If V_{DD_HV_BALLAST}

is supplied from the same source as VDD_HV_A this condition is implicitly met):

• During power-up, V_{DD_HV_BALLAST}must have met the min spec of 2.25V before VDD_HV_A reaches the

POR_HV_RISE min of 2.75V.

• During power-down, V_{DD_HV_BALLAST}must not drop below the min spec of 2.25V until VDD_HV_A is below

POR_HV_FALL min of 2.7V.

NOTE

For a typical configuration using an external ballast transistor

with separate supply for VDD_HV_A and the ballast collector,

a bulk storage capacitor (as defined in Table 8) is required on

VDD_HV_A close to the device pins to ensure a stable supply

voltage.

Extra care must be taken if the VDD_HV_A supply is also

being used to power the external ballast transistor or the device

is running in internal regulation mode. In these modes, the

inrush current on device Power Up or on exit from Low Power

Modes is significant and may cause the VDD_HV_A voltage to

drop resulting in an LVD reset event. To avoid this, the board

layout should be optimized to reduce common trace resistance

or additional capacitance at the ballast transistor collector (or

VDD_HV_A pins in the case of internal regulation mode) is

required. NXP recommends that customers simulate the

external voltage supply circuitry.

In all circumstances, the voltage on VDD_HV_A must be

maintained within the specified operating range (see

Recommended operating conditions) to prevent LVD events.

4.4 Voltage monitor electrical characteristics

Table 9. Voltage monitor electrical characteristics

Symbol

Parameter

State Conditions

Configuration

Threshold

Typ Max

Unit

V

Powe Mas

Reset Type

Min

r Up ¹

k

Opt

V_{POR_LV}

LV supply

power on

reset detector

Fall

Untrimmed

Trimmed

Yes

No

POR

0.930 0.979 1.028

0.959 0.979 0.999

0.980 1.029 1.078

1.009 1.029 1.049

V

Rise

Untrimmed

Trimmed

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

16

NXP Semiconductors

General

Table 9. Voltage monitor electrical characteristics (continued)

Symbol

Parameter

State Conditions

Configuration

Threshold

Typ Max

Unit

V

Powe Mas

Reset Type

Min

r Up ¹

k

Opt

V_{HVD_LV_cold}

LV supply high Fall

voltage

Untrimmed

Trimmed

No

Yes Functional

Disabled at Start

1.325 1.345 1.375

Disabled at Start

V

monitoring,

detecting at

Rise

Untrimmed

Trimmed

the device pin

1.345 1.365 1.395

1.080 1.120 1.160

1.125 1.143 1.160

1.100 1.140 1.180

1.145 1.163 1.180

V

V_{LVD_LV_PD2_hot}

V_{LVD_LV_PD1_hot}

V_{LVD_LV_PD0_hot}

V_{POR_HV}

LV supply low Fall

voltage

Untrimmed

Trimmed

Yes

No

POR

monitoring,

Rise

Untrimmed

Trimmed

detecting in

the PD2 core

(hot) area

LV supply low Fall

voltage

Untrimmed

Trimmed

1.080 1.120 1.160

1.114 1.137 1.160

1.100 1.140 1.180

1.134 1.157 1.180

V

monitoring,

Rise

Untrimmed

Trimmed

detecting in

the PD1 core

(hot) area

LV supply low Fall

voltage

Untrimmed

Trimmed

1.080 1.120 1.160

1.114 1.137 1.160

1.100 1.140 1.180

1.134 1.157 1.180

V

monitoring,

Rise

Untrimmed

Trimmed

detecting in

the PD0 core

(hot) area

HV supply

power on

reset detector

Fall

Untrimmed

Yes

No

POR

2.700 2.850 3.000

2.750 2.900 3.050

V

Rise

, 2

V_{LVD_IO_A_LO}

HV IO_A

supply low

voltage

monitoring -

low range

Fall

Untrimmed

Trimmed

Untrimmed

Trimmed

2.750 2.923 3.095

2.978 3.039 3.100

2.780 2.953 3.125

3.008 3.069 3.130

Disabled at Start

V

Rise

Fall

2

V_{LVD_IO_A_HI}

HV IO_A

No

Yes Functional

supply low

voltage

monitoring -

high range

4.060 4.151 4.240

Disabled at Start

V

Rise

Trimmed

4.115 4.201 4.3

Disabled at Start

V_{LVD_LV_PD2_cold}

LV supply low Fall

voltage

Untrimmed

Trimmed

1.14

Disabled at Start

1.16 1.178 1.195

1.158 1.175

monitoring,

detecting at

Rise

Untrimmed

Trimmed

the device pin

1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until the

minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active

will always generate a POR reset.

2. There is no voltage monitoring on the V_{DD_HV_ADC0}, V_{DD_HV_ADC1}, V_{DD_HV_B}and V_{DD_HV_C}I/O segments. For applications

requiring monitoring of these segments, either connect these to V_{DD_HV_A}at the PCB level or monitor externally.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

17

General

4.5 Supply current characteristics

Current consumption data is given in the following table. These specifications are design

targets and are subject to change per device characterization.

NOTE

The ballast must be chosen in accordance with the ballast

transistor supplier operating conditions and recommendations.

Table 10. Current consumption characteristics

Symbol

I_{DD_FULL}

2, 3

Parameter

Conditions¹

LV supply + HV supply + HV Flash supply +

2 x HV ADC supplies

T_a= 85°C

Min Typ

219

Max Unit

RUN Full Mode

Operating current

—

292

mA

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 160MHz

T_a= 105°C

—

230

249

183

328

400

260

mA

T_a= 125 °C

—

I_{DD_GWY}

5, 6

RUN Gateway

Mode Operating

current

LV supply + HV supply + HV Flash supply + 2 x HV

ADC supplies

—

T_a= 85°C

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 160MHz

T_a= 105°C

—

196

215

294

348

223

mA

T_a= 125°C⁴

I_{DD_BODY_1}

7, 8

RUN Body Mode LV supply + HV supply + HV Flash supply + 2 x HV

Profile Operating ADC supplies

—

149

current

T_a= 85 °C

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 120MHz

T_a= 105 °C

—

158

175

270

310

174

mA

T_a= 125°C ⁴

IDD_BODY_2^{9, 10}RUN Body Mode LV supply + HV supply + HV Flash supply + 2 x HV

Profile Operating ADC supplies

—

105

current

T_a= 85 °C

V_{DD_LV}= 1.25 V

VDD_HV_A = 5.5V

SYS_CLK = 80MHz

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

18

NXP Semiconductors

General

Table 10. Current consumption characteristics (continued)

Symbol

Parameter

Conditions¹

Min Typ

Max Unit

T_a= 105 °C

T_a= 125 °C ⁴

—

114

131

11

206

277

—

mA

—

I_{DD_STOP}

STOP mode

T_a= 25 °C

—

Operating current

V_{DD_LV}= 1.25 V

T_a= 85 °C

—

19.8

29

105

145

160

400

V_{DD_LV}= 1.25 V

T_a= 105 °C

V_{DD_LV}= 1.25 V

T_a= 125 °C ⁴

V_{DD_LV}= 1.25 V

T_a= 25 °C

—

45

11, 12

I_{DD_HV_ADC_REF}

ADC REF

Operating current

—

200

µA

mA

2 ADCs operating at 80 MHz

V_{DD_HV_ADC_REF}= 3.6 V

T_a= 125 °C ⁴

—

200

1

400

2

2 ADCs operating at 80 MHz

V_{DD_HV_ADC_REF}= 5.5 V

T_a= 25 °C

12

I_{DD_HV_ADCx}

ADC HV

Operating current

—

ADC operating at 80 MHz

V_{DD_HV_ADC}= 3.6 V

T_a= 125 °C ⁴

—

1.2

40

2

ADC operating at 80 MHz

V_{DD_HV_ADC}= 5.5 V

T_a= 125 °C ⁴

I_{DD_HV_FLASH}

Flash Operating

current during

read access

—

45

3.3 V supplies

x MHz frequency

1. The content of the Conditions column identifies the components that draw the specific current.

2. ALL Modules enabled at maximum frequency: 2 x e200Z4 @160 MHz, e200Z2 at 80 MHz, Platform @160MHz, DMA

(SRAM to SRAM), all SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled), HSM

reading from flash at regular intervals (500 pll clock cycles), ENET0 transmitting, MLB transmitting, FlexRay transmitting,

USB-SPH transmitting (USB-OTG only clocked), 2 x I2C transmitting (rest clocked), 1 x SAI transmitting (rest clocked),

ADC0 converting using BCTU triggers triggered through PIT (other ADC clocked), RTC running, 3 x STM running, 2 x

DSPI transmitting (rest clocked), 2 x SPI transmitting (rest clocked), 4 x CAN state machines working(rest clocked), 9 x

LINFlexD transmitting (rest clocked), 1 x eMIOS clocked (used OPWFMB mode) (Others clock gated), SDHC,3 x CMP

only clocked, FIRC, SIRC, FXOSC, SXOSC, PLL running. All others modules clock gated if not specifically mentioned. I/O

supply current excluded.

3. Recommended Transistors:MJD31 @ 85°C, 105°C and 125°C.

4. Tj=150°C. Assumes Ta=125°C

• Assumes maximum θJA. SeeThermal attributes

5. Enabled Modules in Gateway mode: 2 x e200Z4 @160 MHz (Instruction and Data cache enabled), Platform @160MHz,

e200Z2 at 80 MHz(Instruction cache enabled), all SRAMs accessed in parallel, Flash access(prefetch is disabled while

buffers are enabled), HSM reading from flash at regular intervals(500 pll clock cycles), ENET0 transmitting, MLB

transmitting, FlexRay transmitting, USB-SPH Transmitting, USB-OTG clocked, 2 x I2C transmitting, (2 x I2C clock gated),

1 x SAI transmitting (2 x SAI clock gated), ADC0 converting in continuous mode (ADC1 clock gated), PIT clocked, RTC

clocked, 3 x STM clocked, 2 x DSPI transmitting(Other DSPS clock gated), 2 x SPI transmitting(Other SPIs clock gated), 4

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

19

General

x FlexCAN state machines clocked(other FLEXCAN clock gated), 4 x LINFlexD transmitting (Other clock gated), 1x eMIOS

clocked(used OPWFMB mode) (Others clock gated), FIRC, SIRC, FXOSC, SXOSC, PLL running, BCTU, DMAMUX,

ACMP clock gated. All others modules clock gated if not specifically mentioned. I/O supply current excluded

6. Recommended Transistors:MJD31@85°C, 105°C and 125°C.

7. Enabled Modules in Body mode enabled at maximum frequency: 2 x e200Z4 @120Mhz(Instruction and Data cache

enabled),Platform@120MHz, SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled),

HSM reading from flash at regular intervals(500 pll clock cycles), DMA (SRAM to SRAM), ADC0 converting using BCTU

triggers which are triggered through PIT(ADC1 clocked), RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(others

DSPIs clocked), 2 x SPI transmitting(others clocked), 4 x FlexCAN state machines working(others clocked), 9xLINFlexD

transmitting (others clocked), 1xeMIOS operational (used OPWFMB mode) (others clocked), FIRC, SIRC, FXOSC,

SXOSC, PLL running, MEMU, FCCU, SIUL, SDHC,CMP clocked, e200Z2, ENET, MLB, SAI, I2C, FlexRay, USB clock

gated. All others modules clock gated if not specifically mentioned I/O supply current excluded

8. Recommended Transistors:BCP56, BCP68 or MJD31@85°C, BCP56, BCP68 or MJD31@105°C and MJD31@125°C.

9. Enabled Modules in Body mode enabled at maximum frequency:2 x e200Z4 @80Mhz(Instruction and Data cache

enabled),Platform@80MHz, SRAMs accessed in parallel, Flash access(prefetch is disabled while buffers are enabled),

HSM reading from flash at regular intervals(500 pll clock cycles), DMA (SRAM to SRAM), ADC0 converting using BCTU

triggers which are triggered through PIT(ADC1 clocked), RTC clocked, 3 x STM clocked, 2 x DSPI transmitting(others

DSPIs clocked), 2 x SPI transmitting(others clocked), 4 x FlexCAN state machines working(others clocked), 9xLINFlexD

transmitting (others clocked), 1xeMIOS operational (used OPWFMB mode) (others clocked), FIRC, SIRC, FXOSC,

SXOSC, PLL running, MEMU, FCCU, SIUL, SDHC,CMP clocked, e200Z2, ENET, MLB, SAI, I2C, FlexRay, USB clock

gated. All others modules clock gated if not specifically mentioned I/O supply current excluded

10. Recommended Transistors:BCP56, BCP68 or MJD31@85°C, 105°C and 125°C

11. Internal structures hold the input voltage less than V_{DD_HV_ADC_REF}+ 1.0 V on all pads powered by V_DDAsupplies, if the

maximum injection current specification is met (3 mA for all pins) and V_DDAis within the operating voltage specifications.

12. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max.

Table 11. Low Power Unit (LPU) Current consumption characteristics

Symbol

Parameter

Conditions¹

Min Typ

Max Unit

LPU_RUN

with 256K RAM,

but only one RAM

being accessed

T_a= 25 °C

—

8.9

mA

SYS_CLK = 16MHz

ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF

T_a= 25 °C

10.2

SYS_CLK = 16MHz

ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON

T_a= 85 °C

—

12.5

14.5

16

22

24

26

T_a= 105 °C

T_a= 125 °C ^{, 2}

—

SYS_CLK = 16MHz

ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON

LPU_STOP

with 256K RAM

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C ²

—

0.535

0.72

1

mA

—

6

8

1.6

10.6

1. The content of the Conditions column identifies the components that draw the specific current.

2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum θJA of 2s2p board. SeeThermal

attributes

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

20

NXP Semiconductors

General

Table 12. STANDBY Current consumption characteristics

Symbol

Parameter

Conditions¹

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C

T_a= 25 °C

T_a= 85 °C

T_a= 105 °C

T_a= 125 °C

T_a= 25 °C

Min Typ Max Unit

STANDBY0

STANDBY with

8K RAM

—

71

—

µA

175

800

338 1725

750 2775

STANDBY1

STANDBY2

STANDBY3

STANDBY with

64K RAM

72

—

176

815

350 1775

825 3000

STANDBY with

128K RAM

75

—

182

830

366 1825

900 3250

STANDBY with

256K RAM

80

—

197

860

400 1875

975 3500

FIRC ON

500

—

1. The content of the Conditions column identifies the components that draw the specific current.

NOTE

For the Precision channel Analog inputs, SIUL2_MSCRn[PUS]

must be configured to 0 before entering STANDBY. An

increase in current would be observed when

SIUL2_MSCRn[PUS] is configured to be 1, irrespective of the

state of IBE or PUE. The current numbers would increase

irrespective of whether the pad is pulled low/high externally.

4.6 Electrostatic discharge (ESD) characteristics

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This

test conforms to the AEC-Q100-002/-003/-011 standard.

NOTE

A device will be defined as a failure if after exposure to ESD

pulses the device no longer meets the device specification

requirements. Complete DC parametric and functional testing

shall be performed per applicable device specification at room

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

21

I/O parameters

temperature followed by hot temperature, unless specified

otherwise in the device specification.

Table 13. ESD ratings

Symbol

Parameter

Electrostatic discharge

(Human Body Model)

Conditions¹

Class

Max value²

Unit

V_ESD(HBM)

T_A= 25 °C

H1C

2000

V

conforming to AEC-

Q100-002

V_ESD(CDM)

Electrostatic discharge

(Charged Device Model)

T_A= 25 °C

C3A

500

V

conforming to AEC-

Q100-011

750 (corners)

1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

2. Data based on characterization results, not tested in production.

4.7 Electromagnetic Compatibility (EMC) specifications

EMC measurements to IC-level IEC standards are available from NXP on request.

5 I/O parameters

5.1 AC specifications @ 3.3 V Range

Table 14. Functional Pad AC Specifications @ 3.3 V Range

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)

Drive Load

(pF)

SIUL2_MSCRn[SRC 1:0]

L>H/H>L

Min

Max

6/6

Min

Max

1.9/1.5

3.25/3

12/12

3.9/3.5

1.1

MSB,LSB

pad_sr_hv

(output)

25

50

11

2.5/2.5

6.4/5

8.25/7.5

19.5/19.5

8/8

0.8/0.6

3.5/2.5

0.55/0.5

0.035

1/1

200

2.2/2.5

0.090

2.9/3.5

11/8

25

10

1.1

asymmetry²

12.5/11

35/31

45/45

65/65

75/75

100/100

2/2

7/6

50

7.7/5

25/21

25/25

30/30

40/40

51/51

0.5/0.5

200

8.3/9.6

13.5/15

13/13

21/22

4/3.5

50

01

00³

NA

6.3/6.2

6.8/6

200

50

11/11

200

pad_i_hv/

pad_sr_hv

0.5

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

22

NXP Semiconductors

I/O parameters

Table 14. Functional Pad AC Specifications @ 3.3 V Range

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)

Drive Load

(pF)

SIUL2_MSCRn[SRC 1:0]

L>H/H>L

Min

Max

Min

Max

MSB,LSB

(input)⁴

1. As measured from 50% of core side input to Voh/Vol of the output

2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF

load. Required for the Flexray spec.

3. Slew rate control modes

4. Input slope = 2ns

NOTE

The specification given above is based on simulation data into

an ideal lumped capacitor. Customer should use IBIS models

for their specific board/loading conditions to simulate the

expected signal integrity and edge rates of their system.

NOTE

The specification given above is measured between 20% / 80%.

5.2 DC electrical specifications @ 3.3V Range

Table 15. DC electrical specifications @ 3.3V Range

Symbol

Parameter

Value

Unit

Min

1.08

3.15

Max

1.32

3.63

VDD

LV (core) Supply Voltage

V

VDD_HV_x

Vih (pad_i_hv)

I/O Supply Voltage

pad_i_hv Input Buffer High Voltage

0.72*VDD_HV_ VDD_HV_x +

0.3

x

Vil (pad_i_hv)

Vhys (pad_i_hv)

Vih_hys

Vil_hys

pad_i_hv Input Buffer Low Voltage

pad_i_hv Input Buffer Hysteresis

VSS_LV - 0.3 0.45*VDD_HV_

x

V

0.11*VDD_HV_

x

CMOS Input Buffer High Voltage (with hysteresis

enabled)

0.67*VDD_HV_ VDD_HV_x +

x

0.3

CMOS Input Buffer Low Voltage (with hysteresis

enabled)

VSS_LV - 0.3 0.35*VDD_HV_

x

Vih

CMOS Input Buffer High Voltage (with hysteresis

disabled)

0.57 *

VDD_HV_x

VDD_HV_x +

0.3

Vil

CMOS Input Buffer Low Voltage (with hysteresis

disabled)

VSS_LV - 0.3

0.4 *

VDD_HV_x

Vhys

CMOS Input Buffer Hysteresis

0.09 *

VDD_HV_x

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

23

I/O parameters

Symbol

Table 15. DC electrical specifications @ 3.3V Range (continued)

Parameter

Value

Unit

Min

Max

Pull_IIH (pad_i_hv) Weak Pullup Current Low

Pull_IIH (pad_i_hv) Weak Pullup Current High

Pull_IIL (pad_i_hv) Weak Pulldown Current²Low

Pull_IIL (pad_i_hv) Weak Pulldown Current¹High

15

µA

V

55

28

85

Pull_Ioh

Pull_Iol

Iinact_d

Voh

Weak Pullup Current³

Weak Pulldown Current⁴

15

50

Digital Pad Input Leakage Current (weak pull inactive)

Output High Voltage⁵

-2.5

2.5

0.8 *VDD_HV_x

—

Vol

Output Low Voltage⁶

0.2 *VDD_HV_x

V

Output Low Voltage⁷

0.1 *VDD_HV_x

Ioh_f

Iol_f

Full drive Ioh⁸(SIUL2_MSCRn[SRC 1:0]= 11)

Full drive Iol⁸(SIUL2_MSCRn[SRC 1:0]= 11)

Half drive Ioh⁸(SIUL2_MSCRn[SRC 1:0]= 10)

Half drive Iol⁸(SIUL2_MSCRn[SRC 1:0]= 10)

18

21

70

120

35

mA

Ioh_h

Iol_h

9

10.5

60

1. Measured when pad=0.69*VDD_HV_x

2. Measured when pad=0.49*VDD_HV_x

3. Measured when pad = 0 V

4. Measured when pad = VDD_HV_x

5. Measured when pad is sourcing 2 mA

6. Measured when pad is sinking 2 mA

7. Measured when pad is sinking 1.5 mA

8. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.

5.3 AC specifications @ 5 V Range

Table 16. Functional Pad AC Specifications @ 5 V Range

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)

Drive Load (pF)

SIUL2_MSCRn[SRC 1:0]

L>H/H>L

Min

Max

4.5/4.5

6/6

Min

Max

1.3/1.2

2.5/2

9/9

MSB,LSB

pad_sr_hv

(output)

25

50

11

13/13

5.25/5.25

9/8

200

25

3/2

10

5/4

50

22/22

27/27

40/40

18/16

13/13

24/24

200

50

01²

00²

200

50

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

24

NXP Semiconductors

I/O parameters

Table 16. Functional Pad AC Specifications @ 5 V Range (continued)

Symbol

Prop. Delay (ns)¹

Rise/Fall Edge (ns)

Drive Load (pF)

SIUL2_MSCRn[SRC 1:0]

L>H/H>L

Min

Max

65/65

1.5/1.5

Min

Max

40/40

0.5/0.5

MSB,LSB

200

0.5

pad_i_hv/

pad_sr_hv

NA

(input)

1. As measured from 50% of core side input to Voh/Vol of the output

2. Slew rate control modes

NOTE

The above specification is based on simulation data into an

ideal lumped capacitor. Customer should use IBIS models for

their specific board/loading conditions to simulate the expected

signal integrity and edge rates of their system.

NOTE

The above specification is measured between 20% / 80%.

5.4 DC electrical specifications @ 5 V Range

Table 17. DC electrical specifications @ 5 V Range

Symbol

Parameter

Value

Unit

Min

1.08

4.5

Max

1.32

5.5

VDD_LV

VDD_HV_x

Vih (pad_i_hv)

LV (core) Supply Voltage

V

I/O Supply Voltage

pad_i_hv Input Buffer High Voltage

0.7*VDD_HV_x VDD_HV_x +

0.3

Vil (pad_i_hv)

pad_i_hv Input Buffer Low Voltage

pad_i_hv Input Buffer Hysteresis

VSS_LV- 0.3 0.45*VDD_HV_

x

V

Vhys (pad_i_hv)

0.09*VDD_HV_

x

Vih

Vil

CMOS Input Buffer High Voltage (with hysteresis

disabled)

0.55 *

VDD_HV_x

VDD_HV_x +

0.3

CMOS Input Buffer Low Voltage (with hysteresis

disabled)

VSS_LV - 0.3

0.4 *

VDD_HV_x

Vhys

Vih_hys

CMOS Input Buffer Hysteresis

0.09 *

VDD_HV_x

CMOS Input Buffer High Voltage (with hysteresis

enabled)

0.65*

VDD_HV_x

VDD_HV_x +

0.3

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

25

I/O parameters

Table 17. DC electrical specifications @ 5 V Range (continued)

Symbol

Parameter

Value

Unit

Min

Max

Vil_hys

CMOS Input Buffer Low Voltage (with hysteresis

enabled)

VSS_LV - 0.3 0.35*VDD_HV_

x

V

Pull_IIH (pad_i_hv) Weak Pullup Current Low

Pull_IIH (pad_i_hv) Weak Pullup Current High

Pull_IIL (pad_i_hv) Weak Pulldown Current²Low

Pull_IIL (pad_i_hv) Weak Pulldown Current¹High

23

µA

V

82

40

130

Pull_Ioh

Pull_Iol

Iinact_d

Voh

Weak Pullup Current³

Weak Pulldown Current⁴

30

80

2.5

—

Digital Pad Input Leakage Current (weak pull inactive)

Output High Voltage⁵

-2.5

0.8 *

VDD_HV_x

Vol

Output Low Voltage⁶

Output Low Voltage⁷

—

0.2 *

VDD_HV_x

V

0.1*VDD_HV_x

Ioh_f

Iol_f

Full drive Ioh⁸(SIUL2_MSCRn[SRC 1:0]= 11)

Full drive Iol⁸(SIUL2_MSCRn[SRC 1:0]= 11)

Half drive Ioh⁸(SIUL2_MSCRn[SRC 1:0]= 10)

Half drive Iol⁸(SIUL2_MSCRn[SRC 1:0]= 10)

38

48

19

24

132

220

66

mA

Ioh_h

Iol_h

110

1. Measured when pad=0.69*VDD_HV_x

2. Measured when pad=0.49*VDD_HV_x

3. Measured when pad = 0 V

4. Measured when pad = VDD_HV_x

5. Measured when pad is sourcing 2 mA

6. Measured when pad is sinking 2 mA

7. Measured when pad is sinking 1.5 mA

8. Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test.

5.5 Reset pad electrical characteristics

The device implements a dedicated bidirectional RESET pin.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

26

NXP Semiconductors

I/O parameters

V

DD_HV_IOx

A

V

DDMIN

PORST

V

IH

V

IL

device reset forced by PORST

device start-up phase

Figure 3. Start-up reset requirements

V_PORST

hw_rst

‘1’

V

DD_HV_IO

A

V

IH

V

IL

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

W

FRST

W

NFRST

Figure 4. Noise filtering on reset signal

Table 18. Functional reset pad electrical specifications

Symbol

Parameter

Conditions

Value

Unit

Min

2.0

Typ

Max

V_IH

Input high level TTL (Schmitt Trigger)

—

V_{DD_HV_A}

+0.4

V

V_IL

Input low level TTL (Schmitt Trigger)

Input hysteresis TTL (Schmitt Trigger)

—

–0.4

300

—

0.8

—

V

V_HYS

mV

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

27

Peripheral operating requirements and behaviours

Table 18. Functional reset pad electrical specifications (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Typ

Max

V_{DD_POR}

I_{OL_R}

Minimum supply for strong pull-down

activation

Strong pull-down current ¹

—

1.2

V

Device under power-on reset

V_{DD_HV_IO}= V _{DD_POR}

V_OL= 0.35*V_{DD_HV_IO}

Device under power-on reset

3.0 V < V_{DD_HV_IO}< 5.5 V

V_OL= 0.35*V_{DD_HV_IO}

—

0.2

11

—

mA

—

mA

W_FRST

RESET input filtered pulse

—

500

—

ns

µA

W_NFRST

RESET input not filtered pulse

Weak pull-up current absolute value

—

2000

23

|I_WPU

|

RESET pin V_IN= V_DD

82

1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET.

5.6 PORST electrical specifications

Table 19. PORST electrical specifications

Symbol

Parameter

Value

Unit

Min

—

Typ

Max

W_FPORST

W_NFPORST

V_IH

PORST input filtered pulse

PORST input not filtered pulse

Input high level

—

200

—

ns

1000

—

ns

V

0.65 x V_{DD_HV_A}

0.35 x V_{DD_HV_A}

—

V_IL

Input low level

—

V

6 Peripheral operating requirements and behaviours

6.1 Analog

6.1.1 ADC electrical specifications

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-

Digital Converter.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

28

NXP Semiconductors

Analog

Offset Error OSE Gain Error GE

4095

4094

4093

4092

4091

4090

(2)

1 LSB ideal =(VrefH-VrefL)/ 4096 =

3.3V/ 4096 = 0.806 mV

Total Unadjusted Error

TUE = +/- 6 LSB = +/- 4.84mV

code out₇

(1)

6

5

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer

curve

(5)

4

3

(4)

(3)

2

1

1 LSB (ideal)

0

1

2

3

4

5

6

7

4089 4090 4091 4092 4093 4094 4095

V_in(A)(LSB_ideal

)

Offset Error OSE

Figure 5. ADC characteristics and error definitions

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

29

Analog

6.1.1.1 Input equivalent circuit and ADC conversion characteristics

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

V

DD_IO

Channel

Sampling

Selection

Source

Filter

Current Limiter

R

S

F

L

SW1

AD

C

V

C

P1

C

S

A

F

P2

R

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

S

F

L

R

C

R

C

SW1

AD

P

Pin Capacitance (two contributions, C and C

Sampling Capacitance

)

P1

P2

S

Figure 6. Input equivalent circuit

NOTE

The ADC performance specifications are not guaranteed if two

ADCs simultaneously sample the same shared channel.

Table 20. ADC conversion characteristics (for 12-bit)

Symbol

Parameter

Conditions

Min

Typ¹

Max

Unit

f_CK

ADC Clock frequency (depends on —

ADC configuration) (The duty cycle

depends on AD_CK²frequency)

15.2

80

MHz

f_s

Sampling frequency

Sample time³

80 MHz

—

1.00

—

MHz

ns

t_sample

80 MHz@ 100 ohm source

impedance

250

t_conv

Conversion time⁴

80 MHz

700

1.5⁵

—

ns

µs

t_{total_conv}

Total Conversion time t_sample+

t_conv(for standard and extended

channels)

Total Conversion time t_sample

t_conv(for precision channels)

+

1

—

C_S

ADC input sampling capacitance

ADC input pin capacitance 1

ADC input pin capacitance 2

—

3

5

pF

kΩ

Ω

6

C_P1

—

6

C_P2

—

0.8

0.3

875

6

R_SW1

Internal resistance of analog

source

V_REFrange = 4.5 to 5.5 V

V_REFrange = 3.15 to 3.6 V

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

30

NXP Semiconductors

Analog

Table 20. ADC conversion characteristics (for 12-bit) (continued)

Symbol

Parameter

Conditions

Min

Typ¹

Max

Unit

6

R_AD

Internal resistance of analog

source

—

825

Ω

INL

Integral non-linearity (precise

channel)

–2

–3

—

2

3

LSB

Integral non-linearity (standard

channel)

DNL

OFS

GNE

Differential non-linearity

Offset error

—

–1

–6

–4

—

1

6

LSB

nA

—

Gain error

—

4

ADC Analog Pad Max leakage (precision channel)

(pad going to one

150 °C

—

250

2500

250

5

Max leakage (standard channel)

—

nA

ADC)

Max leakage (standard channel)

105 °C _TA

5

nA

Max positive/negative injection

–5

–6

—

mA

LSB

µs

TUE_{precision channels}Total unadjusted error for precision Without current injection

+/-4

+/-5

+/-6

+/-8

6

channels

With current injection

TUE_{standard/extended}Total unadjusted error for standard/ Without current injection

–8

8

extended channels

With current injection⁷

channels

t_recovery

STOP mode to Run mode recovery

time

< 1

1. Active ADC input, VinA < [min(ADC_VrefH, ADC_ADV, VDD_HV_IOx)]. VDD_HV_IOx refers to I/O segment supply

voltage. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolute

maximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' for required

relation between IO_supply_A,B,C and ADC_Supply.

2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral

clock based on register configuration in the ADC.

3. During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_sample. After the end of the

sample time t_sample, changes of the analog input voltage have no effect on the conversion result. Values for the sample

clock t_sampledepend on programming.

4. This parameter does not include the sample time t_sample, but only the time for determining the digital result and the time to

load the result register with the conversion result.

5. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from the

ADC is lower.

6. See Figure 2.

7. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being

performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum

voltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here

NOTE

The ADC input pins sit across all three I/O segments,

VDD_HV_A, VDD_HV_B and VDD_HV_C.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

31

Analog

6.1.2 Analog Comparator (CMP) electrical specifications

Table 21. Comparator and 6-bit DAC electrical specifications

Symbol

I_DDHS

I_DDLS

Description

Min.

—

Typ.

—

Max.

250

11

Unit

μA

V

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

5

V_AIN

V_SS

—

V_{IN1_CMP_RE}

F

V_AIO

V_H

Analog input offset voltage ¹

Analog comparator hysteresis ²

• CR0[HYSTCTR] = 00

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

-42

—

42

mV

—

1

25

50

mV

20

40

60

70

105

t_DHS

t_DLS

Propagation Delay, High Speed Mode (Full Swing) ^{1, 3}

Propagation Delay, Low power Mode (Full Swing) ^{1, 3}

—

5

250

21

ns

μs

Analog comparator initialization delay, High speed

mode⁴

4

Analog comparator initialization delay, Low speed

mode ⁴

—

100

μs

I_DAC6b

6-bit DAC current adder (when enabled)

3.3V Reference Voltage

—

6

9

μA

LSB⁵

5V Reference Voltage

10

—

16

0.5

0.8

INL

6-bit DAC integral non-linearity

6-bit DAC differential non-linearity

–0.5

–0.8

DNL

LSB

1. Measured with hysteresis mode of 00

2. Typical hysteresis is measured with input voltage range limited to 0.6 to V_{DD_HV_A}-0.6V

3. Full swing = VIH, VIL

4. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN,

VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.

5. 1 LSB = V_reference/64

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

32

NXP Semiconductors

Clocks and PLL interfaces modules

6.2 Clocks and PLL interfaces modules

6.2.1 Main oscillator electrical characteristics

This device provides a driver for oscillator in pierce configuration with amplitude

control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this

way the EMI. Other benefits arises by reducing the power consumption. This Loop

Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of

traces between crystal and MCU.

An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also

available in case of parasitic capacitances and cannot be reduced by using crystal with

high equivalent series resistance. For this mode, a special care needs to be taken

regarding the serial resistance used to avoid the crystal overdrive.

Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For

EXT Wave, the drive is disabled and an external source of clock within CMOS level

based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240

Kohms resistor and the feedback resistor remains active connecting XTAL through

EXTAL by 1M resistor.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

33

Clocks and PLL interfaces modules

Figure 7. Oscillator connections scheme

Table 22. Main oscillator electrical characteristics

Symbol

f_XOSCHS

Parameter

Mode

Conditions

Min

Typ

Max

Unit

Oscillator

frequency

FSP/LCP

8

40

MHz

g_mXOSCHS

Driver

Transconduct

ance

LCP

FSP

23

33

mA/V

V_XOSCHS

Oscillation

Amplitude

LCP

8 MHz

1.0

0.8

2

V_PP

ms

16 MHz

40 MHz

8 MHz

T_XOSCHSSU

Startup time

FSP/LCP

FSP

16 MHz

40 MHz

8 MHz

1

0.5

2.2

3.2

Oscillator

Analog Circuit

supply current

mA

16 MHz

40 MHz

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

34

NXP Semiconductors

Clocks and PLL interfaces modules

Table 22. Main oscillator electrical characteristics (continued)

Symbol

Parameter

Mode

Conditions

8 MHz

Min

Typ

Max

Unit

LCP

141

252

518

uA

16 MHz

40 MHz

V_IH

V_IL

Input High

level CMOS

Schmitt trigger

EXT Wave

Oscillator

supply=3.3

1.95

V

Input low level EXT Wave

CMOS

Oscillator

supply=3.3

1.25

Schmitt trigger

6.2.2 32 kHz Oscillator electrical specifications

Table 23. 32 kHz oscillator electrical specifications

Symbol

f_{osc_lo}

Parameter

Condition

Min

Typ

Max

Unit

Oscillator crystal

or resonator

frequency

32

40

2

KHz

t_cst

Crystal Start-up

Time^{1, 2}

s

1. This parameter is characterized before qualification rather than 100% tested.

2. Proper PC board layout procedures must be followed to achieve specifications.

6.2.3 16 MHz RC Oscillator electrical specifications

Table 24. 16 MHz RC Oscillator electrical specifications

Symbol

Parameter

Conditions

Value

Typ

16

Unit

Min

—

Max

F_Target

PTA

IRC target frequency

—

5

MHz

%

IRC frequency variation after trimming

Startup time

-5

—

T_startup

T_STJIT

T_LTJIT

—

1.5

0.2

us

%

Cycle to cycle jitter

—

Long term jitter

—

%

NOTE

The above start up time of 1 us is equivalent to 16 cycles of 16

MHz.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

35

Clocks and PLL interfaces modules

6.2.4 128 KHz Internal RC oscillator Electrical specifications

Table 25. 128 KHz Internal RC oscillator electrical specifications

Symbol

Parameter

Condition

Calibrated

Min

Typ

Max

Unit

1

F_oscu

Oscillator

frequency

119

128

136.5

600

18

KHz

Temperature

dependence

ppm/C

%/V

Supply

dependence

Supply current

Clock running

Clock stopped

2.75

200

µA

nA

1. Vdd=1.2 V, 1.32V, T_a=-40 C, 125 C

6.2.5 PLL electrical specifications

Table 26. PLL electrical specifications

Parameter

Input Frequency

Min

Typ

Max

Unit

MHz

Comments

8

40

VCO Frequency Range

Duty Cycle at pllclkout

600

48%

1280

52%

MHz

This specification is guaranteed

at PLL IP boundary

Period Jitter

TIE

See Table 27

ps

NON SSCG mode

at 960 M Integrated over 1MHz

offset not valid in SSCG mode

Modulation Depth (Center Spread) +/- 0.25%

Modulation Frequency

+/- 3.0%

32

KHz

µs

Lock Time

60

Calibration mode

Table 27. Jitter calculation

Type of jitter

Jitter due to

Supply

Jitter due to

Fractional Mode

J_SSCG(ps) ³

1 Sigma

Total Period Jitter (ps)

Fractional Mode

Random

Jitter J_RJ

(ps) ⁴

2

Noise (ps)

(ps) J_SDM

1

J_SN

Period Jitter

60 ps

3% of pllclkout1,2

Modulation depth

0.1% of

+/-(J_SN+J_SDM+J_SSCG+N^[4]

pllclkout1,2

×J_RJ)

Long Term Jitter

(Integer Mode)

40

+/-(N x J_RJ

)

Long Term jitter

100

+/-(N x J_RJ

(Fractional Mode)

1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value

is valid for inductor value of 5nH or less each on VDD_LV and VSS_LV.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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NXP Semiconductors

Memory interfaces

2. This jitter component is added when the PLL is working in the fractional mode.

3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0.

4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding

specified value of jitter table

Table 28. Percentage of sample exceeding specified value of jitter

N

Percentage of samples exceeding specified value of jitter

(%)

1

2

3

4

5

6

7

31.73

4.55

0.27

6.30 × 1e-03

5.63 × 1e-05

2.00 × 1e-07

2.82 × 1e-10

6.3 Memory interfaces

6.3.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this

section are defined for a single embedded flash memory within

an SoC, and represent average currents for given supplies and

operations.

Table 29 shows the estimated Program/Erase times.

Table 29. Flash memory program and erase specifications

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C ≤150°C ≤150°C cycles cycles

t_dwpgm

Doubleword (64 bits) program time 43

100 150 55 500

μs

t_ppgm

Page (256 bits) program time

73

200

800

300

108

396

500

μs

t_qppgm

Quad-page (1024 bits) program

time

268

1,200

2,000

t_16kers

16 KB Block erase time

168

34

290

45

320

50

250

40

1,000

ms

t_16kpgm

16 KB Block program time

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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37

Memory interfaces

Table 29. Flash memory program and erase specifications (continued)

Symbol

Characteristic¹

Typ²

Factory

Field Update

Unit

Programming^{3, 4}

Initial

Max

Initial

Max, Full

Temp

Typical

End of

Life⁵

Lifetime Max⁶

20°C ≤T_A-40°C ≤T_J-40°C ≤T_J≤ 1,000 ≤ 250,000

≤30°C

≤150°C

cycles

1,200

1,600

4,000

cycles

t_32kers

t_32kpgm

t_64kers

32 KB Block erase time

32 KB Block program time

64 KB Block erase time

64 KB Block program time

256 KB Block erase time

256 KB Block program time

217

360

390

310

ms

69

100

110

90

315

138

884

552

490

590

420

170

1,080

650

t_64kpgm

t_256kers

t_256kpgm

180

210

1,520

720

2,030

880

—

1. Program times are actual hardware programming times and do not include software overhead. Block program times

assume quad-page programming.

2. Typical program and erase times represent the median performance and assume nominal supply values and operation at

25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 150 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤ T_J≤ 150°C, full spec voltage.

6.3.2 Flash memory Array Integrity and Margin Read specifications

Table 30. Flash memory Array Integrity and Margin Read specifications

Symbol

Characteristic

Min

Typical

Max

Units

t_ai16kseq

Array Integrity time for sequential sequence on 16 KB block.

—

512 x

Tperiod x

Nread

—

t_ai32kseq

Array Integrity time for sequential sequence on 32 KB block.

Array Integrity time for sequential sequence on 64 KB block.

Array Integrity time for sequential sequence on 256 KB block.

—

1024 x

Tperiod x

Nread

—

t_ai64kseq

2048 x

Tperiod x

Nread

8192 x

Tperiod x

Nread

tai256kseq

t_mr16kseq

t_mr32kseq

t_mr64kseq

t_mr256kseq

Margin Read time for sequential sequence on 16 KB block.

Margin Read time for sequential sequence on 32 KB block.

Margin Read time for sequential sequence on 64 KB block.

Margin Read time for sequential sequence on 256 KB block.

73.81

128.43

237.65

893.01

—

110.7

192.6

μs

356.5

1,339.5

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NXP Semiconductors

Memory interfaces

6.3.3 Flash memory module life specifications

Table 31. Flash memory module life specifications

Symbol

Characteristic

Conditions

Min

Typical

Units

P/E

Array P/E

cycles

Number of program/erase cycles per block

for 16 KB, 32 KB and 64 KB blocks.

—

250,000

—

cycles

Number of program/erase cycles per block

for 256 KB blocks.

1,000

250,000

P/E

cycles

Data

retention

Minimum data retention.

Blocks with 0 - 1,000 P/E 50

cycles.

—

Years

Blocks with 100,000 P/E

cycles.

20

Blocks with 250,000 P/E

cycles.

10

6.3.4 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the

following figure. The spec window represents qualified limits. The extrapolated dotted

line demonstrates technology capability, however is beyond the qualification limits.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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39

Memory interfaces

6.3.5 Flash memory AC timing specifications

Table 32. Flash memory AC timing specifications

Symbol

Characteristic

Min

Typical

Max

Units

t_psus

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

to a 1.

—

9.4

11.5

μs

plus four

system

clock

plus four

system

clock

periods

t_esus

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

to a 1.

—

16

20.8

μs

plus four

system

clock

plus four

system

clock

periods

t_res

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

until DONE goes low.

—

16

100

ns

μs

t_done

t_dones

Time from 0 to 1 transition on the MCR-EHV bit initiating a

program/erase until the MCR-DONE bit is cleared.

5

Time from 1 to 0 transition on the MCR-EHV bit aborting a

program/erase until the MCR-DONE bit is set to a 1.

20.8

plus four

system

clock

plus four

system

clock

periods

t_drcv

Time to recover once exiting low power mode.

16

—

45

μs

plus seven

system

clock

plus seven

system

clock

periods.

periods

t_aistart

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

or Array Integrity until the UT0-AID bit is cleared. This time also

applies to the resuming from a suspend or breakpoint by

clearing AISUS or clearing NAIBP

—

5

ns

t_aistop

Time from 1 to 0 transition of UT0-AIE initiating an Array

Integrity abort until the UT0-AID bit is set. This time also applies

to the UT0-AISUS to UT0-AID setting in the event of a Array

Integrity suspend request.

—

80

plus fifteen

system

clock

periods

t_mrstop

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read

abort until the UT0-AID bit is set. This time also applies to the

UT0-AISUS to UT0-AID setting in the event of a Margin Read

suspend request.

10.36

—

20.42

μs

plus four

system

clock

plus four

system

clock

periods

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

40

NXP Semiconductors

Communication interfaces

6.3.6 Flash read wait state and address pipeline control settings

The following table describes the recommended RWSC and APC settings at various

operating frequencies based on specified intrinsic flash access times of the flash module

controller array at 125 °C.

Table 33. Flash Read Wait State and Address Pipeline Control Combinations

Flash frequency

0 MHz < fFlash <= 33 MHz

33 MHz < fFlash <= 100 MHz

100 MHz < fFlash <= 133 MHz

133 MHz < fFlash <= 160 MHz

RWSC setting

APC setting

0

2

3

4

0

1

6.4 Communication interfaces

6.4.1 DSPI timing

Table 34. DSPI electrical specifications

No

Symbol

Parameter

Conditions

High Speed Mode¹

low Speed mode

Unit

Min

25

Max

—

Min

50

Max

—

1

t_SCK

DSPI cycle

time

Master

Slave (MTFE = 0)

—

ns

40

—

60

—

2

3

4

5

6

7

8

9

t_CSC

t_ASC

t_SDC

t_A

PCS to SCK

delay

16

—

ns

After SCK

delay

—

16

—

SCK duty

cycle

t_SCK/2 - 10

t_SCK/2 + 10

Slave access SS active to SOUT

time valid

—

13

40

10

—

t_DIS

Slave SOUT _SSinactive to SOUT

disable time

High-Z or invalid

t_PCSC

t_PASC

t_SUI

PCSx to

PCSS time

—

PCSS to

PCSx time

—

Data setup

time for

inputs

Master (MTFE = 0)

Slave

NA

2

—

20

2

8²

—

Master (MTFE = 1,

CPHA = 0)

15

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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41

Communication interfaces

Table 34. DSPI electrical specifications (continued)

No

Symbol

Parameter

Conditions

High Speed Mode¹

low Speed mode

Unit

Min

Max

Min

Max

Master (MTFE = 1,

CPHA = 1)

15

—

20

—

10

t_HI

Data hold

time for

inputs

Master (MTFE = 0)

Slave

NA

4

—

–5

4

11²

—

ns

Master (MTFE = 1,

CPHA = 0)

0

Master (MTFE = 1,

CPHA = 1)

0

—

-5

—

11

12

t_SUO

Data valid

(after SCK

edge)

Master (MTFE = 0)

Slave

—

NA

15

4

—

4

ns

23

16²

Master (MTFE = 1,

CPHA = 0)

Master (MTFE = 1,

CPHA = 1)

—

4

—

4

t_HO

Data hold

time for

outputs

Master (MTFE = 0)

NA

—

–2

—

Slave

4

—

6

10²

—

Master (MTFE = 1,

CPHA = 0)

-2

Master (MTFE = 1,

CPHA = 1)

–2

—

–2

—

1. Only one {SIN,SOUT and SCK} group per DSPI/SPI will support high frequency mode. See Table 3.

2. SMPL_PTR should be set to 1

NOTE

Restriction For High Speed modes

• DSPI2, DSPI3, SPI1 and SPI2 will support 40MHz Master

mode SCK

• DSPI2, DSPI3, SPI1 and SPI2 will support 25MHz Slave

SCK frequency

• Only one {SIN,SOUT and SCK} group per DSPI/SPI will

support high frequency mode. See Table 36.

• For Master mode MTFE will be 1 for high speed mode

• For high speed slaves, their master have to be in MTFE=1

mode or should be able to support 15ns tSUO delay

NOTE

For numbers shown in the following figures, see Table 34

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Communication interfaces

Table 35. Continuous SCK timing

Spec

Characteristics

Pad Drive/Load

Value

Min

100 ns

-

Max

tSCK

SCK cycle timing

PCS valid after SCK

strong/50 pF

-

15 ns

-

-4 ns

Table 36. DSPI high speed mode I/Os

DSPI

High speed SCK

GPIO[78]

High speed SIN

GPIO[76]

High speed SOUT

DSPI2

DSPI3

SPI1

GPIO[77]

GPIO[100]

GPIO[173]

GPIO[79]

GPIO[101]

GPIO[175]

GPIO[110]

GPIO[98]

GPIO[176]

GPIO[111]

SPI2

2

3

PCSx

1

4

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

10

9

Last Data

SIN

First Data

Data

12

11

First Data

Data

Last Data

SOUT

Figure 8. DSPI classic SPI timing — master, CPHA = 0

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

43

Communication interfaces

PCSx

SCK Output

(CPOL=0)

10

SCK Output

(CPOL=1)

9

Data

First Data

Last Data

SIN

12

11

SOUT

Last Data

First Data

Figure 9. DSPI classic SPI timing — master, CPHA = 1

3

2

SS

1

4

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

5

11

12

Data

6

First Data

Last Data

SOUT

SIN

9

10

Data

Last Data

First Data

Figure 10. DSPI classic SPI timing — slave, CPHA = 0

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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NXP Semiconductors

Communication interfaces

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

Data

SOUT

SIN

First Data

10

9

Last Data

First Data

Figure 11. DSPI classic SPI timing — slave, CPHA = 1

3

PCSx

4

1

2

SCK Output

(CPOL=0)

4

SCK Output

(CPOL=1)

9

10

SIN

First Data

12

Last Data

Data

11

SOUT

First Data

Data

Figure 12. DSPI modified transfer format timing — master, CPHA = 0

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

45

Communication interfaces

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

10

9

SIN

Last Data

First Data

Data

12

Data

11

First Data

Last Data

SOUT

Figure 13. DSPI modified transfer format timing — master, CPHA = 1

3

2

SS

1

SCK Input

(CPOL=0)

4

SCK Input

(CPOL=1)

12

11

6

5

First Data

9

Data

Last Data

10

SOUT

SIN

Last Data

First Data

Figure 14. DSPI modified transfer format timing – slave, CPHA = 0

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

46

NXP Semiconductors

FlexRay electrical specifications

SS

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11

5

6

12

Last Data

First Data

10

Data

SOUT

SIN

9

First Data

Last Data

Figure 15. DSPI modified transfer format timing — slave, CPHA = 1

8

7

PCSS

PCSx

Figure 16. DSPI PCS strobe (PCSS) timing

6.4.2 FlexRay electrical specifications

6.4.2.1 FlexRay timing

This section provides the FlexRay Interface timing characteristics for the input and output

signals. It should be noted that these are recommended numbers as per the FlexRay EPL

v3.0 specification, and subject to change per the final timing analysis of the device.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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47

FlexRay electrical specifications

6.4.2.2 TxEN

TxEN

80 %

20 %

dCCTxEN

FALL

RISE

Figure 17. TxEN signal

Table 37. TxEN output characteristics¹

Name

Description

Min

—

Max

Unit

ns

dCCTxEN_RISE25

dCCTxEN_FALL25

dCCTxEN₀₁

Rise time of TxEN signal at CC

Fall time of TxEN signal at CC

9

—

ns

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

—

25

ns

dCCTxEN₁₀

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

—

25

ns

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, + 10%, TJ = –40 °C / 150 °C, TxEN pin load maximum 25 pF

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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NXP Semiconductors

FlexRay electrical specifications

PE_Clk

TxEN

dCCTxEN

10

01

Figure 18. TxEN signal propagation delays

6.4.2.3 TxD

TxD

dCCTxD

50%

80 %

50 %

20 %

dCCTxD

RISE

FALL

Figure 19. TxD Signal

Table 38. TxD output characteristics

Name

Description¹

Min

Max

Unit

dCCT_xAsym

Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100

ns)

–2.45

2.45

ns

dCCTxD_RISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output

D_FALL25

—

9²

ns

Table continues on the next page...

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FlexRay electrical specifications

Table 38. TxD output characteristics (continued)

Name

Description¹

Min

Max

Unit

dCCTxD₀₁

Sum of delay between Clk to Q of the last FF and the final

output buffer, rising edge

—

25

ns

dCCTxD₁₀

Sum of delay between Clk to Q of the last FF and the final

output buffer, falling edge

—

25

ns

1. All parameters specified for V_{DD_HV_IOx}= 3.3 V -5%, + 10%, TJ = –40 °C / 150 °C, TxD pin load maximum 25 pF.

2. For 3.3 V 10% operation, this specification is 10 ns.

PE_Clk*

TxD

dCCTxD

10

dCCTxD

01

*FlexRay Protocol Engine Clock

Figure 20. TxD Signal propagation delays

6.4.2.4 RxD

Table 39. RxD input characteristic

Name

Description¹

Min

Max

Unit

C_CCRxD

Input capacitance on

RxD pin

—

7

pF

uCCLogic_1

uCCLogic_0

dCCRxD₀₁

Threshold for detecting

logic high

35

30

—

70

65

10

%

ns

Threshold for detecting

logic low

Sum of delay from

actual input to the D

input of the first FF,

rising edge

dCCRxD₁₀

Sum of delay from

actual input to the D

input of the first FF,

falling edge

—

10

ns

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NXP Semiconductors

FlexRay electrical specifications

1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, + 10%, TJ = –40 oC / 150 oC.

6.4.3 uSDHC specifications

Table 40. uSDHC switching specifications

Num

Symbol

Description

Min.

Max.

Unit

Card input clock

Clock frequency (Identification mode)

SD1

fpp

f_OD

t_WL

t_WH

t_TLH

t_THL

0

400

25

40

20

40

—

3

kHz

MHz

ns

Clock frequency (SD\SDIO full speed)

Clock frequency (SD\SDIO high speed)

Clock frequency (MMC full speed)

Clock low time

0

SD2

SD3

SD4

SD5

7

Clock high time

7

ns

Clock rise time

—

ns

Clock fall time

3

ns

SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SDHC output delay (output valid) -5 6.5

SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)

SD6

t_OD

ns

SD7

SD8

t_ISU

t_IH

SDHC input setup time

SDHC input hold time

5

0

—

ns

SD3

SD6

SD2

SD1

SDHC_CLK

Output SDHC_CMD

Output SDHC_DAT[3:0]

Input SDHC_CMD

SD7

SD8

Input SDHC_DAT[3:0]

Figure 21. uSDHC timing

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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51

FlexRay electrical specifications

6.4.4 Ethernet switching specifications

The following timing specs are defined at the chip I/O pin and must be translated

appropriately to arrive at timing specs/constraints for the physical interface.

6.4.4.1 MII signal switching specifications

The following timing specs meet the requirements for MII style interfaces for a range of

transceiver devices.

NOTE

ENET0 supports the following xMII interfaces: MII, MII_Lite

and RMII. ENET1 supports the following xMII interfaces:

MII_Lite.

NOTE

It is only possible to use ENET0 and ENET1 simultaneously

when both are configured for MII_Lite.

NOTE

In certain pinout configurations ENET1 MII-Lite signals can be

across multiple VDD_HV_A/B/C domains. If these

configuration are used, VDD_HV IO domains need to be at the

same voltage (for example: 3.3V)

Table 41. MII signal switching specifications

Symbol

—

Description

Min.

—

Max.

25

Unit

MHz

RXCLK frequency

RXCLK pulse width high

MII1

35%

65%

RXCLK

period

RXCLK

period

ns

MII2

RXCLK pulse width low

35%

65%

MII3

MII4

—

RXD[3:0], RXDV, RXER to RXCLK setup

RXCLK to RXD[3:0], RXDV, RXER hold

TXCLK frequency

5

—

ns

—

25

MHz

MII5

TXCLK pulse width high

35%

65%

TXCLK

period

TXCLK

period

ns

MII6

TXCLK pulse width low

35%

65%

MII7

MII8

TXCLK to TXD[3:0], TXEN, TXER invalid

TXCLK to TXD[3:0], TXEN, TXER valid

2

—

25

ns

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NXP Semiconductors

FlexRay electrical specifications

MII6

MII5

MII7

TXCLK (input)

TXD[n:0]

TXEN

MII8

Valid data

TXER

Figure 22. RMII/MII transmit signal timing diagram

MII2

MII1

RXCLK (input)

RXD[n:0]

RXDV

MII3

MII4

Valid data

RXER

Figure 23. RMII/MII receive signal timing diagram

6.4.4.2 RMII signal switching specifications

The following timing specs meet the requirements for RMII style interfaces for a range of

transceiver devices.

Table 42. RMII signal switching specifications

Num

—

Description

Min.

—

Max.

50

Unit

EXTAL frequency (RMII input clock RMII_CLK)

RMII_CLK pulse width high

MHz

RMII1

35%

65%

RMII_CLK

period

RMII2

RMII_CLK pulse width low

35%

65%

RMII_CLK

period

RMII3

RMII4

RMII7

RMII8

RXD[1:0], CRS_DV, RXER to RMII_CLK setup

RMII_CLK to RXD[1:0], CRS_DV, RXER hold

RMII_CLK to TXD[1:0], TXEN invalid

4

2

—

15

ns

4

RMII_CLK to TXD[1:0], TXEN valid

—

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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53

MediaLB (MLB) electrical specifications

Connecting two MPC5748G MCUs via ENET without a PHY

To connect two MPC5748G MCUs for an application together through ENET without a

PHY, the following steps should be followed:

1. MCU #1 ENET_0 should be connected to MCU #2 ENET_0

2. MCU #1 ENET_1 should be connected to MCU #2 ENET_1

This ensures conformity to ENET set-up and hold times. Note that the MPC5748G

datasheet quotes worst case set-up and hold times when connecting MCU #1 ENET_0 to

MCU #2 ENET_1.

6.4.5 MediaLB (MLB) electrical specifications

6.4.5.1 MLB 3-pin interface DC characteristics

The section lists the MLB 3-pin interface electrical characteristics.

Table 43. MediaLB 3-Pin Interface Electrical DC Specifications

Parameter

Maximum input voltage

Low level input threshold

High level input threshold

Low level output threshold

High level output threshold

Input leakage current

Symbol

Test Conditions

Min

Max

3.6

Unit

—

V

V_IL

—

0.7

—

V_IH

V_OL

V_OH

See Note¹

1.8

—

I_OL= –6 mA

I_OH= –6 mA

0 < Vin < VDD

0.4

—

2.0

—

10

μA

IL

1. Higher V_IHthresholds can be used; however, the risks associated with less noise margin in the system must be evaluated

and assumed by the customer.

6.4.5.2 MLB 3-pin interface electrical specifications

This section describes the timing electrical information of the MLB module.

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MediaLB (MLB) electrical specifications

Figure 24. MediaLB 3-Pin Timing

Ground = 0.0 V; Load Capacitance = 60 pF, input transition= 1 ns ; MediaLB speed =

256/512 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold

as listed below; unless otherwise noted.

Table 44. MLB 3-Pin 256/512 Fs Timing Parameters

Parameter

Symbol

Min

Max

25.6

Unit

MHz

Comment

MLBCLK operating frequency

f_mck

11.264

256xFs at 44.0 kHz,

512xFs at 50.0 kHz

MLBCLK rise time

MLBCLK fall time

MLBCLK low time¹

t_mck

r

f

l

3

ns

V_{IL to V}

IH

3

V_{IH to V}

IL

30

14

30

14

1

—

256xFs

512xFs

256xFs

512xFs

—

MLBCLK high time

t_mck

h

—

ns

MLBSIG/MLBDAT receiver input setup to

MLBCLK falling

t_dsmcf

t_dhmcf

t_mcfdz

t_mdzh

—

ns

MLBSIG/MLBDAT receiver input hold from

MLBCLK low

t_mcfdz

—

2

MLBSIG/MLBDAT output valid from

MLBCLK low

0

4

t_mck

—

l

Bus output hold from MLBCLK low

2

1. MLBCLK low/high time includes the pluse width variation.

2. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final

driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the

maximum load capacitance listed.

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55

USB electrical specifications

Ground = 0.0 V; Load Capacitance = 40 pF, input transition= 1 ns; MediaLB speed =

1024 Fs; Fs = 48 kHz; all timing parameters specified from the valid voltage threshold as

listed below; unless otherwise noted.

Table 45. MLB 3-Pin 1024 Fs Timing Parameters

Parameter

Symbol

Min

45.056

-

Max

Unit

MHz

Comment

MLBCLK Operating Frequency¹

f_mck

-

1024 x fs at 44.0 kHz

51.2

1

MHz

ns

1024 x fs at 50.0 kHz

MLBCLK rise time

MLBCLK fall time

MLBCLK low time

MLBCLK high time

f_mckr

f_mckf

t_mckl

t_mckh

t_dsmcf

V_{IL to}V_IH

1

ns

V_{IH to}V_IL

6.1

9.3

1

—

ns

2

ns

MLBSIG/MLBDAT receiver input

setup to MLBCLK falling

ns

MLBSIG/MLBDAT receiver input hold t_dhmcf

from MLBCLK low

t_mcfdz

—

ns

MLBSIG/MLBDAT output valid from

MLBCLK low

t_mcfdz

0

2

t_mckl

—

3

Bus Hold from MLBCLK low

t_mdzh

1. The controller can shut off MLBCLK to place MediaLB in a low-power state. Depending on the time the clock is shut off, a

runt pulse can occur on MLBCLK.

2. MLBCLK low/high time includes the pluse width variation.

3. The MediaLB driver can release the MLBDAT/MLBSIG line as soon as MLBCLK is low; however, the logic state of the final

driven bit on the line must remain on the bus for tmdzh. Therefore, coupling must be minimized while meeting the

maximum load capacitance listed.

6.4.6 USB electrical specifications

6.4.6.1 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards

documented by the Universal Serial Bus Implementers Forum. For the most up-to-date

standards, visit http://www.usb.org.

6.4.6.2 ULPI timing specifications

The ULPI interface is fully compliant with the industry standard UTMI+ Low Pin

Interface. Control and data timing requirements for the ULPI pins are given in the

following table. These timings apply to synchronous mode only. All timings are

measured with respect to the clock as seen at the USB_CLKIN pin.

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USB electrical specifications

Table 46. ULPI timing specifications

Num

Description

Min.

Typ.

Max.

Unit

USB_CLKIN

operating

—

60

—

MHz

frequency

USB_CLKIN duty

cycle

—

5

50

16.67

—

9.5

—

%

ns

U1

U2

U3

U4

U5

USB_CLKIN clock

period

Input setup (control

and data)

Input hold (control

and data)

1

—

Output valid

(control and data)

—

1

—

Output hold (control

and data)

—

U1

USB_CLKIN

U2

U3

ULPI_DIR/ULPI_NXT

(control input)

ULPI_DATAn (input)

U5

U4

ULPI_STP

(control output)

ULPI_DATAn (output)

Figure 25. ULPI timing diagram

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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57

USB electrical specifications

6.4.7 SAI electrical specifications

All timing requirements are specified relative to the clock period or to the minimum

allowed clock period of a device

Table 47. Master mode SAI Timing

no

Parameter

Value

Unit

Min

2.7

Max

3.6

-

Operating Voltage

V

S1

S2

SAI_MCLK cycle time

SAI_MCLK pulse width high/low

40

ns

45%

55%

MCLK

period

S3

SAI_BCLK cycle time

80

-

BCLK

period

S4

S5

S6

S7

S8

S9

S10

SAI_BCLK pulse width high/low

45%

55%

ns

SAI_BCLK to SAI_FS output valid

SAI_BCLK to SAI_FS output invalid

SAI_BCLK to SAI_TXD valid

-

0

15

-

15

-

SAI_BCLK to SAI_TXD invalid

0

SAI_RXD/SAI_FS input setup before SAI_BCLK

SAI_RXD/SAI_FS input hold after SAI_BCLK

28

0

-

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USB electrical specifications

Figure 26. Master mode SAI Timing

Table 48. Slave mode SAI Timing

No

Parameter

Value

Unit

Min

2.7

80

45%

10

2

Max

Operating Voltage

3.6

V

S11

S12

S13

S14

S15

S16

S17

S18

SAI_BCLK cycle time (input)

-

ns

SAI_BCLK pulse width high/low (input)

SAI_FS input setup before SAI_BCLK

SAI_FS input hold after SAI_BCLK

SAI_BCLK to SAI_TXD/SAI_FS output valid

SAI_BCLK to SAI_TXD/SAI_FS output invalid

SAI_RXD setup before SAI_BCLK

SAI_RXD hold after SAI_BCLK

55%

BCLK period

-

ns

-

28

-

0

10

2

-

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59

Debug specifications

Figure 27. Slave mode SAI Timing

6.5 Debug specifications

6.5.1 JTAG interface timing

Table 49. JTAG pin AC electrical characteristics ¹

#

1

Symbol

t_JCYC

Characteristic

Min

62.5

40

—

5

Max

—

Unit

ns

%

TCK Cycle Time ²

2

t_JDC

TCK Clock Pulse Width

TCK Rise and Fall Times (40% - 70%)

60

3

t_TCKRISE

3

ns

4

t_TMSS, t_TDISTMS, TDI Data Setup Time

t_TMSH, t_TDIHTMS, TDI Data Hold Time

—

5

—

20³

6

t_TDOV

t_TDOI

TCK Low to TDO Data Valid

—

0

7

TCK Low to TDO Data Invalid

TCK Low to TDO High Impedance

TCK Falling Edge to Output Valid

—

8

t_TDOHZ

t_BSDV

t_BSDVZ

—

15

600⁴

11

12

TCK Falling Edge to Output Valid out of High

Impedance

600

13

14

15

t_BSDHZ

t_BSDST

t_BSDHT

TCK Falling Edge to Output High Impedance

Boundary Scan Input Valid to TCK Rising Edge

TCK Rising Edge to Boundary Scan Input Invalid

—

15

600

—

ns

—

1. These specifications apply to JTAG boundary scan only.

2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions.

Refer to pad specification for allowed transition frequency

3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

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Debug specifications

TCK

2

3

2

1

Figure 28. JTAG test clock input timing

TCK

4

5

TMS, TDI

6

8

7

TDO

Figure 29. JTAG test access port timing

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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61

Debug specifications

TCK

11

13

Output

Signals

12

Output

Signals

14

15

Input

Signals

Figure 30. JTAG boundary scan timing

6.5.2 Nexus timing

Table 50. Nexus debug port timing ¹

No.

Symbol

Parameter

Condition

s

Min

Max

Unit

1

2

3

4

5

6

7

8

t_MCYC

t_MDC

t_MDOV

t_EVTIPW

MCKO Cycle Time

—

15.6

40

–0.1

4

—

60

0.25

—

ns

%

MCKO Duty Cycle

MCKO Low to MDO, MSEO, EVTO Data Valid²

tMCYC

tTCYC

tMCYC

ns

EVTI Pulse Width

t_EVTOPWEVTO Pulse Width

1

—

t_TCYC

t_TDC

TCK Cycle Time³

62.5

40

8

—

TCK Duty Cycle

60

—

%

t_NTDIS

,

TDI, TMS Data Setup Time

ns

t_NTMSS

Table continues on the next page...

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Debug specifications

Table 50. Nexus debug port timing ¹(continued)

No.

Symbol

Parameter

Condition

s

Min

5

Max

—

Unit

ns

9

t_NTDIH

,

TDI, TMS Data Hold Time

TCK Low to TDO/RDY Data Valid

—

t_NTMSH

10

t_JOV

—

0

25

ns

1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured

from 50% of MCKO and 50% of the respective signal.

2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

3. The system clock frequency needs to be four times faster than the TCK frequency.

1

2

MCKO

3

MDO

MSEO

EVTO

Output Data Valid

5

Figure 31. Nexus output timing

4

EVTI

Figure 32. Nexus EVTI Input Pulse Width

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63

Debug specifications

6

7

TCK

8

9

TMS, TDI

10

TDO/RDY

Figure 33. Nexus TDI, TMS, TDO timing

6.5.3 WKPU/NMI timing

Table 51. WKPU/NMI glitch filter

No.

1

Symbol

Parameter

Min

—

Typ

—

Max

20

Unit

ns

W_FNMI

NMI pulse width that is rejected

NMI pulse width that is passed

2

W_NFNMI

D

400

—

ns

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Thermal attributes

6.5.4 External interrupt timing (IRQ pin)

Table 52. External interrupt timing specifications

No.

1

Symbol

t_IPWL

Parameter

Conditions

Min

3

Max

Unit

t_CYC

IRQ pulse width low

IRQ pulse width high

IRQ edge to edge time

—

2

t_IPWH

3

t_ICYC

6

These values applies when IRQ pins are configured for rising edge or falling edge events,

but not both.

IRQ

1

2

3

Figure 34. External interrupt timing

7 Thermal attributes

7.1 Thermal attributes

Board

type

Symbol

Description

176LQFP

45.5

Unit

Notes

Single-layer R_θJA

(1s)

Thermal resistance, junction to ambient (natural

convection)

°C/W

1, 2

Four-layer

(2s2p)

R_θJA

Thermal resistance, junction to ambient (natural

convection)

23.1

°C/W

1, 2, 3

1,3

Single-layer R_θJMA

(1s)

Thermal resistance, junction to ambient (200 ft./min. 34.8

air speed)

Four-layer

(2s2p)

R_θJMA

Thermal resistance, junction to ambient (200 ft./min. 16

air speed)

1,3

—

R_θJB

Thermal resistance, junction to board

Thermal resistance, junction to case top

Thermal resistance, junction to case bottom

9.4

9.5

0.2

°C/W

4

5

6

R_θJCtop

R_θJCbotttom

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

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65

Thermal attributes

Board

type

Symbol

Description

176LQFP

Unit

Notes

—

Ψ_JT

Thermal characterization parameter, junction to

package top

0.2

°C/W

7

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any

interface resistance.

7. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

Board

type

Symbol

Description

324

Unit

°C/W

Notes

MAPBGA

Single-

layer (1s)

R_θJA

Thermal resistance, junction to ambient (natural

convection)

25.5

19.0

18.1

14.8

1, 2

1,23

1, 3

1,3

Four-layer R_θJA

(2s2p)

Thermal resistance, junction to ambient (natural

convection)

Single-

layer (1s)

R_θJMA

Thermal resistance, junction to ambient (200 ft./

min. air speed)

Four-layer R_θJMA

(2s2p)

Thermal resistance, junction to ambient (200 ft./

min. air speed)

—

R_θJB

R_θJC

Ψ_JT

Thermal resistance, junction to board

Thermal resistance, junction to case

10.4

8.4

°C/W

4

5

6

Thermal characterization parameter, junction to

package top natural convection)

0.45

—

Ψ_JB

Thermal characterization parameter, junction to

package top natural convection)

2.65

°C/W

7

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.,

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JB.

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NXP Semiconductors

Dimensions

Notes

Board

type

Symbol

Description

256

MAPBGA

Unit

°C/W

Single-

layer (1s)

R_θJA

Thermal resistance, junction to ambient (natural 39.5

convection)

1, 2

1,23

1,3

Four-layer R_θJA

(2s2p)

Thermal resistance, junction to ambient (natural 22.9

convection)

Single-

layer (1s)

R_θJMA

Thermal resistance, junction to ambient (200 ft./ 28.5

min. air speed)

Four-layer R_θJMA

(2s2p)

Thermal resistance, junction to ambient (200 ft./ 18.3

min. air speed)

1,3

—

R_θJB

R_θJC

Ψ_JT

Thermal resistance, junction to board

Thermal resistance, junction to case

9.5

5.8

0.2

°C/W

4

5

6

Thermal characterization parameter, junction to

package top outside center (natural convection)

—

Ψ_JB

Thermal characterization parameter, junction to

package bottom outside center (natural

convection)

6.4

°C/W

7

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.,

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction

temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JB.

8 Dimensions

8.1 Obtaining package dimensions

Package dimensions are provided in package drawing.

To find a package drawing, go to www.nxp.com and perform a keyword search for the

drawing’s document number:

Package

NXP Document Number

176-pin LQFP-EP

256 MAPBGA

324 MAPBGA

98ASA00673D

98ASA00346D

98ASA10582D

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67

Pinouts

9 Pinouts

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

10 Reset sequence

This section describes different reset sequences and details the duration for which the

device remains in reset condition in each of those conditions.

10.1 Reset sequence duration

Table 53 specifies the minimum and the maximum reset sequence duration for the five

different reset sequences described in Reset sequence description.

Table 53. RESET sequences

No. Symbol

Parameter

T_Reset

Min Typ ¹Max

5.730 7.796

0.111 0.182

5.729 7.793

0.110 0.179

0.007 0.009

Unit

1

2

3

4

5

T_DRB

T_DR

Destructive Reset Sequence, BIST enabled

Destructive Reset Sequence, BIST disabled

ms

T_ERLBExternal Reset Sequence Long, Unsecure Boot

T_FRL

T_FRS

Functional Reset Sequence Long, Unsecure Boot

Functional Reset Sequence Short, Unsecure Boot

1. The Typ value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET_B by

an external reset generator.

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NXP Semiconductors

Reset sequence

10.2 BAF execution duration

Following table specifies the typical BAF execution time in case BAF boot header is

present at first location (Typical) and last location (worst case). Total Boot time is the

sum of reset sequence duration and BAF execution time.

Table 54. BAF execution duration

BAF execution

duration

Min

Typ

Max

Unit

BAF execution time

(boot header at first

location)

-

200

320

-

μs

BAF execution time

(boot header at last

location)

10.3 Reset sequence description

The figures in this section show the internal states of the device during the five different

reset sequences. The dotted lines in the figures indicate the starting point and the end

point for which the duration is specified in Table 53.

With the beginning of DRUN mode, the first instruction is fetched and executed. At this

point, application execution starts and the internal reset sequence is finished.

The following figures show the internal states of the device during the execution of the

reset sequence and the possible states of the RESET_B signal pin.

NOTE

RESET_B is a bidirectional pin. The voltage level on this pin

can either be driven low by an external reset generator or by the

device internal reset circuitry. A high level on this pin can only

be generated by an external pullup resistor which is strong

enough to overdrive the weak internal pulldown resistor. The

rising edge on RESET_B in the following figures indicates the

time when the device stops driving it low. The reset sequence

durations given in Table 53 are applicable only if the internal

reset sequence is not prolonged by an external reset generator

keeping RESET_B asserted low beyond the last Phase3.

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69

Reset sequence

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE0

PHASE1,2

PHASE3

BIST

PHASE1,2

PHASE3

DRUN

BAF+

Flash

Init

Device

Config

Establish

IRC and

PWR

Flash

Init

Device

Config

Self

Test

Setup

Application

MBIST

LBIST

Ex ecut ion

T

< T

RESET DRB, max

DRB, min

Figure 35. Destructive reset sequence, BIST enabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE0

PHASE1,2

PHASE3

DRUN

BAF+

Establish

IRC and

PWR

Flash

Init

Device

Config

Application

Execution

T

< T

RESET DR, max

DR, min

Figure 36. Destructive reset sequence, BIST disabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE1,2

PHASE3

BIST

PHASE1,2

PHASE3

DRUN

BAF+

Flash

Init

Device

Config

Flash

Init

Device

Config

Self

Test

Setup

Application

MBIST

LBIST

Execut ion

T

< T

RESET

< T

ERLB, max

ERLB, min

Figure 37. External reset sequence long, BIST enabled

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE1,2

PHASE3

DRUN

BAF+

Application

Ex ecut ion

Flash

Init

Device

Config

T

< T

RESET FRL, max

FRL, min

Figure 38. Functional reset sequence long

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Revision History

Reset Sequence Trigger

Reset Sequence Start Condition

RESET_B

PHASE3

DRUN

BAF+

Application

Execution

T

< T

RESET FRS, max

FRS, min

Figure 39. Functional reset sequence short

The reset sequences shown in Figure 38 and Figure 39 are triggered by functional reset

events. RESET_B is driven low during these two reset sequences only if the

corresponding functional reset source (which triggered the reset sequence) was enabled to

drive RESET_B low for the duration of the internal reset sequence. See the RGM_FBRE

register in the device reference manual for more information.

11 Revision History

The following table provides a revision history for this document.

Table 55. Revision History

Rev. No.

Date

Substantial Changes

1

14 March 2013

16 May 2013

22 May 2014

Initial Release

1.1

2

Updated Pinouts section

• Removed Category (SR, CC, P, T, D, B) column from all the table of the Datasheet

• Revised the feature list.

• Revised Introduction section to remove classification information.

• Updated optional information in the ordering information figure.

• Revised Absolute maximum rating section:

• Removed category column from table

• Added footnote at Ta

• Revised Recommended operating conditions section

• Added notes

• Updated table: Recommended operating conditions (VDD_HV_x = 3.3 V)

• Updated table: Recommended operating conditions (VDD_HV_x = 5 V)

• Revised Voltage regulator electrical characteristics

• Updated text describing bipolar transistors

• Updated figure: Voltage regulator capacitance connection

• Updated table: Voltage regulator electrical specifications

• Removed Brownout information

• Revised Voltage monitor electrical characteristics table

• Revised Supply current characteristics section

• Updated table: Current consumption characteristics

• Updated table: Low Power Unit (LPU) Current consumption characteristics

• STANDBY Current consumption characteristics

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

71

Revision History

Rev. No.

Table 55. Revision History (continued)

Date

Substantial Changes

• Revised Electromagnetic Interference (EMI) characteristics section

• Revised DC electrical specifications @ 3.3V Range table for naming convections.

• Revised DC electrical specifications @ 5 V Range table for naming conventions

• Deleted MLB 6-pin Electrical Specifications

• Removed PORST characteristics from Functional reset pad electrical characteristics

table

• Added section PORST electrical characteristics

• Revised Input impedance and ADC accuracy section to remove SNR, THD, SINAD,

ENOB,

• Revised 32 kHz oscillator electrical specifications table to remove 'Vpp' row.

• Updated 16 MHz RC Oscillator electrical specifications table for statuptime, cycle to

cycle jitter, and lonf term jitter

• Updated 128 KHz Internal RC oscillator electrical specifications table.

• Updated PLL electrical specifications table

• Added Jitter Calculation table

• Added Percentage of Sample exceeding specified value of jitter table

• Revised Memory interfaces section

• Revised Communication interfaces section

• Updated note

• Added Continuous SCK timing table

• Added DSPI high speed mode I/Os table

• Updated input transition value in section MLB 3-pin interface electrical specifications

• Deleted MLB 6-pin interface DC characteristics section

• Deleted MLB 6-pin interface AC characteristics section

• Updated JTAG pin AC electrical characteristics table

• Revised table under Thermal attributes section

• Updated Obtaining package dimensions section for Freescale Document numbers

3

12 May 2015

• Editorial updates throughout the sections

• Renamed '176 LQFP' package to '176 LQFP-EP'

• Added following sections:

• Block diagram

• Family comparison

• Ordering Information

• In table: Absolute maximum ratings as follows:

• Removed row for symbol: 'V_{SS_HV}

'

• Added symbol: 'V_{DD_LV}

'

• Updated 'Max' column for symbol 'V_INA

• Added footnote to 'Conditions' column

• Removed footnote from 'Max' column

'

• In section: Recommended operating conditions

• Added opening text: ''The following table describes the operating conditions ... "

• Added note: "V_{DD_HV_A}, V_{DD_HV_B}and V_{DD_HV_C}are all ... "

• In table: Recommended operating conditions (V_{DD_HV_x}= 3.3 V)

• Added footnote to 'Conditions' cloumn

• Updated footnote for 'Min' column

• Removed footnote from symbols 'V_{DD_HV_A}', 'V_{DD_HV_B}', and 'V_{DD_HV_C}

• Removed row for symbol: 'V_{SS_HV}

• Updated 'Parameter' column for symbol 'V_{DD_HV_FLA}', 'V_{DD_HV_ADC1_REF}',

'V_{DD_LV}

• Updated 'Min' column for symbol 'V_{DD_HV_ADC0}' and 'V_{DD_HV_ADC1}

• Updated 'Parameter' 'Min' 'Max' column for symbol 'V_{SS_HV_ADC0}' and

'V_{SS_HV_ADC1}

• Added footnote to symbol 'V_{DD_LV}

'

• Removed footnote from symbol 'V_{IN1_CMP_REF}

'

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

72

NXP Semiconductors

Revision History

Table 55. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Removed row for symbol 'V_{SS_LV}

• Removed footnote from 'Max' column of symbols 'V_{DD_HV_ADC0}' and

'V_{DD_HV_ADC1}

'

• In section: Recommended operating conditions

• In table: Recommended operating conditions (V_{DD_HV_x}= 5 V)

• Added footnote to 'Conditions' cloumn

• Updated footnote for 'Min' column

• Removed footnote from symbols 'V_{DD_HV_A', 'VDD_HV_B}', and 'V_{DD_HV_C}

'

• Removed row for symbol: 'V_{SS_HV}

• Updated 'Parameter' column for symbol 'V_{DD_HV_ADC1_REF}

'V_{DD_HV_ADC1_REF}', 'V_{DD_LV}

• Updated 'Min' columnn of symbol 'V_{DD_HV_ADC0}' and 'V_{DD_HV_ADC1}

• Updated 'Parameter', 'Min' 'Max' column for symbol 'V_{SS_HV_ADC0}' and

'V_{SS_HV_ADC1}

• Added footnote to symbol 'V_{DD_LV}

• Removed row for symbol 'V_{SS_LV}

'

• Added row for symbol 'V_{IN1_CMP_REF}' and corresponding footnotes to the

symbol

• In section: Voltage regulator electrical characteristics

• In table: Voltage regulator electrical specifications

• Added note to symbol 'Cbe_fpreg'

• In section: Voltage monitor electrical characteristics

• In table: Voltage monitor electrical characteristics

• Updated column 'Parameter', 'Min' and 'Max' (of fall/rise trimmed condition)

for symbol 'V_{HVD_LV_cold}' and 'V_{LVD_IO_A_HI'}

• Updated column 'Parameter', 'Min' and 'Typ' (of fall/rise trimmed condition)

for symbol) 'V_{LVD_LV_PD2_hot',}'V_{LVD_LV_PD2_cold LV}

• Updated column 'Parameter' for symbol 'V_{LVD_LV_PD0_hot}

• Updated column 'Typ' and 'Max' (of fall/rise trimmed condition) for symbol)

'V_{LVD_FLASH}

• Updated footnote on symbol 'V_{LVD_IO_A_LO}' and 'V_{LVD_IO_A_HI'}

'

• In section: Supply current characteristics

• In table: Current consumption characteristics

• Updated column 'Typ' for symbol 'I_{DD_FULL}' for temperature 85, 105, 125

• Updated column 'Typ' for symbol 'I_{DD_GWY}' for temperature 85, 105, 125 and

column 'Max' for temperature 105

• Updated column 'Typ' for symbol 'I_{DD_BODY1}' for temperature 85, 105, 125

• Updated column 'Typ' for symbol 'I_{DD_BODY2}' for temperature 85, 105, 125

and 'Max' for temperature 125

• Added 'Typ' value for temperature 25 for symbol 'I_{DD_STOP}

'

• Updated column 'Typ' and 'Max' for symbol 'I_{DD_STOP}' for temperature 85,

105, 125

• In table: Low Power Unit (LPU) Current consumption characteristics

• Updated column 'Typ' for symbol 'LPU_RUN' for tempeature 25 and 125

• Added 'Typ' and 'Max' value for temperature 85 and 105 for symbol

'LPU_RUN'

• Updated column 'Typ' for symbol 'LPU_STOP' for tempeature 25 and 125

• Added 'Typ' and 'Max' value for temperature 85 and 105 for symbol

'LPU_STOP'

• In table: STANDBY Current consumption characteristics

• Updated to have one STANDBY

• In section: I/O parameters

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

73

Revision History

Rev. No.

Table 55. Revision History (continued)

Date

Substantial Changes

• In table: Functional Pad AC Specifications @ 3.3 V Range

• Updated values for symbol 'pad_sr_hv (output)'

• In table: DC electrical specifications @ 3.3V Range

• Updtaed values for VDD_HV_x, Vih, Vhys

• Added Vih (pad_i_hv), Vil (pad_i_hv), Vhys (pad_i_hv), Vih_hys, Vil_hys

• In table: Functional Pad AC Specifications @ 5 V Range

• Updated values for symbol 'pad_sr_hv (output)'

• In table DC electrical specifications @ 5 V Range

• Added Vih (pad_i_hv), Vil (pad_i_hv), Vhys (pad_i_hv), Vih_hys, Vil_hys

• In section: PORST electrical specifications

• In table: PORST electrical specifications

• Updated 'Min' value for W_NFPORST

• Corrected 'Unit' for V_IHand V_IL

• In section: Peripheral operating requirements and behaviours

• Revised table: ADC conversion characteristics (for 12-bit) and ADC conversion

characteristics (for 10-bit)

• In section: Analogue Comparator (CMP) electrical specifications

• In table: Comparator and 6-bit DAC electrical specifications

• Updated 'Max' value of I_DDLS

• Updated 'Min' and 'Max' for V_AIOand DNL

• Updated 'Descripton' 'Min' 'Max' od V_H

• Updated row for tDHS

• Added row for tDLS

• Removed row for VCMPOh and VCMPOl

• In section: Clocks and PLL interfaces modules

• Revised table: Main oscillator electrical characteristics

• In table: 16 MHz RC Oscillator electrical specifications

• Updated 'Max' of Tstartup

• In table: 128 KHz Internal RC oscillator electrical specifications

• Removed Uncaliberated 'Condition' for Fosc

• Updated 'Min' and 'Max' of Caliberated Fosc

• Updated 'Temperature dependence' and 'Supply dependence'

• In table: PLL electrical specifications

• Removed Input Clock Low Level, Input Clock High Level, Power

consumption, Regulator Maximum Output Current, Analog Supply, Digital

Supply (VDD_LV), Modulation Depth (Down Spread), PLL reset assertion

time, and Power Consumption

• Removed 'Typ' value of Duty Cycle at pllclkout

• Removed 'Min' from calibration mode of Lock Time

• In table: Jitter calculation

• Added 1 Sigma Random Jitter value for Long term jitter

• In section Flash read wait state and address pipeline control settings

• Revised table: Flash Read Wait State and Address Pipeline Control

• Removed section: On-chip peripherals

• Added section: 'Reset sequence'

Rev4

Feb 10 2017

• Added VDD_HV_BALLAST footnote in Voltage regulator electrical characteristics

• Added Note to clarify In-Rush current and pin capacitance in Voltage regulator electrical

characteristics

• Updated SIUL2_MSCRn[SRC 1:0]=11@25pF max value; SIUL2_MSCRn[SRC

1:0]=11@50pF min value; SIUL2_MSCRn[SRC 1:0]=10@25pF min and max values in

AC specifications @ 3.3 V Range

Table continues on the next page...

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

74

NXP Semiconductors

Revision History

Table 55. Revision History (continued)

Rev. No.

Date

Substantial Changes

• Updated VIH min and VIL max values in Main oscillator electrical characteristics

• Replaced ipp_sre[1:0] by SIUL2_MSCRn[SRC 1:0] in AC specifications @ 3.3 V Range,

DC electrical specifications @ 3.3V Range

• Functional reset sequence short, unsecure boot corrected Reset sequence duration

• Added NVM memory map and RAM memory map Family comparison

• Added BAF execution duration section BAF execution duration

• Supply names (VDD_LV, VSS_LV replace dvss, avss, dvdd, avdd) corrected in Jitter

calculation table PLL electrical specifications

• Updated Ordering information: Fab and Mask version indicator

• Updated tpsus typical and max values Flash memory AC timing specifications

• Added Notes on IBIS models use in AC specifications @3.3 V Range AC specifications

@ 3.3 V Range

• Updated Vol value in DC electrical specifications @ 3.3V Range DC electrical

specifications @ 3.3V Range

• Added Notes on IBIS models in Functional Pad AC Specifications @ 5 V Range AC

specifications @ 5 V Range

• Updated Vol values in DC electrical specifications @5V Range DC electrical

specifications @ 5 V Range

• Updated IDD Current values Supply current characteristics

• Updated STANDBY current consumption with FIRC ON Supply current characteristics

• Thermal numbers update for 256MAPBGA Thermal attributes

• POR_HV Trim values removed Voltage monitor electrical characteristics

• ADC analog pad leakage for 105 C added ADC electrical specifications

• IDD STANDBY0, 1, 2 and 3 added Supply current characteristics

Rev5

Rev6

July 31 2017

Nov 23 2018

• Updated Standby2 value to 125 C in Standby current consumption characteristics

• Corrected typo in Note from "case" to "cause" Voltage regulator electrical characteristics

• Updated propagation delay from 14 to 21 in ACMP electrical specifications

• Added text "Connecting two MPC5748G MCUs.......connecting MCU #1 ENET_0 to

MCU #2 ENET_1" under "RMII signal switching specifications" section in Ethernet

switching specifications.

• Removed the footnote "Max power supply ramp rate is 500 V / ms" from Table 17 and

Table 15.

• Changed "V_{DD_HV_A}" to "V_{DD_HV_IO}" and changed the condition from "V_{DD_HV_A}

V_{DD_POR}" to "3.0 V < V_{DD_HV_IO}< 5.5 V" in Table 18.

• Added footnote to V_{DD_LV}in Table 5.

=

• Corrected the number of SMPU descriptors from 32 to 16 in Features and table

"MPC5748G Family Comparison" in Family comparison.

• Updated the second bullet point from "If VDD_HV_A is in 3.3V range......should be

shorted to VDD_HV_A" to "If VDD_HV_A is in 5.0V range.......should be shorted to

VDD_HV_A " in Recommended operating conditions.

• Added footnote in "High Speed Mode" column and for Parameter "DSPI cycle time"

changed the Condition from "Master (MTFE=0)" to "Master" in DSPI timing.

• Added 32 and 64 KB flash blocks in Table 3.

• Added note "For the Precision channel Analog inputs...pulled low/high externally" in

Supply current characteristics.

• Changed Powerup to POR under the column "Reset Type" in table Voltage monitor

electrical characteristics in Voltage monitor electrical characteristics.

MPC5748G Microcontroller Data Sheet, Rev. 6, 11/2018

NXP Semiconductors

75

How to Reach Us:

Information in this document is provided solely to enable system and software implementers to use

NXP products. There are no express or implied copyright licenses granted hereunder to design or

fabricate any integrated circuits based on the information in this document. NXP reserves the right to

make changes without further notice to any products herein.

Home Page:

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NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any

particular purpose, nor does NXP assume any liability arising out of the application or use of any

product or circuit, and specifically disclaims any and all liability, including without limitation

consequential or incidental damages. “Typical” parameters that may be provided in NXP data sheets

and/or specifications can and do vary in different applications, and actual performance may vary over

time. All operating parameters, including “typicals,” must be validated for each customer application

by customerʼs technical experts. NXP does not convey any license under its patent rights nor the

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vulnerabilities. Customers are responsible for the design and operation of their applications and

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NXP accepts no liability for any vulnerability that is discovered. Customers should implement

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and products.

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Document Number MPC5748G

Revision 6, 11/2018


型号：	SP5748GBK0AVKU6R
厂家：	NXP
描述：	RISC Microcontroller 微控制器外围集成电路
文件：	总76页 (文件大小：1232K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP5748GBK0AVKU6R [NXP]

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