SP5748/KG/QP1T_技术文档

SP5748

2·4GHz Very Low Phase Noise PLL

DS4875 Issue 2.0 October 1999

Features

Ordering Information

G Complete 2.4 GHz Single Chip System

(for faster device refer to SP5768)

G Optimised for Low Phase Noise, with Comparison

Frequencies up to 4 MHz

SP5748/KG/MP1S (Tubes)

SP5748/KG/MP1T (Tape and Reel)

SP5748/KG/QP1S (Tubes)

SP5748/KG/QP1T (Tape and Reel)

G No RF Prescaler

G Selectable Reference Division Ratio

G Reference Frequency Output

G Selectable Charge Pump Current

G Integrated Loop Amplifier

and allows for coarse tuning in the up-converter application

and fine tuning in the down-converter.

Comparison frequencies are obtained either from a crystal

controlled on-chip oscillator or from an external source.

Abuffered referencefrequencyoutputisalsoavailabletodrive

asecondSP5748.Thedevicealsocontains2switchingports.

G Two Switching Ports

G Low Power Replacement for SP5658 and SP5668

G Power Consumption 72mW with V_CC= 5·5V and all Ports

off

G Downwards Software Compatible with SP5658

G ESD Protection 2kV min., MIL-STD-883B Method 3015

Cat.1 (Normal ESD handling procedures should be

observed)

Absolute Maximum Ratings

Supply voltage, V_CC

RF differential input voltage

RF input DC offset

20·3V to 17V

2·5V

20·3 to V_CC10·3V

255°C to 1125°C

1150°C

Port voltage

Applications

Charge pump DC offset

Varactor drive DC offset

Crystal DC offset

Buffered reference output

Data, clock and enable DC offset

Storage temperature

Junction temperature

MP14 thermal resistance

Chip to ambient, θ_JA

Chip to case, θ_JC

G TV, VCR and Cable Tuning Systems

G Communications Systems

The SP5748 is a single chip frequency synthesiser designed

for tuning systems up to 2.4 GHz and is optimized for low

phase noise with comparison frequencies up to 4 MHz. It is

designed to be downwards software compatible with the

SP5658. The RF programmable divider contains a front end

dual-modulus 416/17functioningoverthefulloperatingrange

81°C/W

27°C/W

2

CRYSTAL

CAP

13-BIT

COUNT

REFERENCE

DIVIDER

11

RF

INPUT

416/17

12

3

1

4-BIT

COUNT

CRYSTAL

PUMP

14

CHARGE

PUMP

DRIVE

9

REF

17-BIT LATCH

6-BIT LATCH

5

6

4

DATA

CLOCK

DATA

INTERFACE

ENABLE

7

8

3-BIT

PORT P1/OC

PORT P0/OP

LATCH AND

PORT/TEST MODE

INTERFACE

Figure 1 SP5748 block diagram (MP14 pinout)

SP5748

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CHARGE PUMP

CRYSTAL CAP

CRYSTAL

DRIVE

1

2

3

4

5

6

7

14

13

12

11

10

9

CHARGE PUMP

CRYSTAL CAP

CRYSTAL

ENABLE

DRIVE

V

EE

V

EE

NC

RF INPUT

RFINPUT

ENABLE

RF INPUT

NC

SP

5748

SP

5748

DATA

V

CC

CLOCK

REF

PORT P1/OC

PORT P0/OP

V

CC

8

PORT P1/OC

PORTP0/OP

REF

MP14

QP16

Figure 2 Pin connections - top view

Electrical Characteristics

Test conditions (unless otherwise stated): Tamb = 240°C to 180°C, V_CC= 4·5V to 5·5V. These characteristics are

guaranteed by either production test or design. They apply within the specified ambient temperature and supply

voltage ranges unless otherwise stated.

Value

Characteristic

Supply current

Conditions

Units

Typ. Max.

Min.

10

13

0·8

63

mA

20

RF input

Frequency range

Input voltage

11,12

80

30

40

MHz

mVrms

2400

300

150MHz to 2400MHz

80MHz to 150MHz

See Figure 3

Input impedance

Data, clock and enable

Input high voltage

Input low voltage

Input current

Hysteresis

Clock rate

Bus timing

Data set up

5,6,4

3

0

210

V

µA

Vp-p

kHz

V_CC

0·7

10

All input conditions

6

5,6,4

500

300

600

300

600

300

ns

Data hold

Enable set up

Enable hold

Clock to enable

Charge pump

Output current

Output leakage

Drive output current

Crystal frequency

External reference

Input frequency

Drive level

1

14

2,3

2

µA

nA

mA

MHz

V_PIN1= 2V, See Table 1

V_PIN1= 2V, V_CC= 15·0V, T_AMB= 25°C

V_PIN14= 0·7V

610

0·5

2

20

See Figure 5 for application

2

0·2

MHz

Vp-p

Sinewave coupled via 10nF blocking capacitor

AC coupled, see Note 1

20

0·5

Buffered reference output

Output amplitude

Output impedance

9

0·35

250

Vp-p

Ω

2-20MHz

cont…

2

SP5748

Electrical Characteristics (continued)

Value

Typ.

Characteristic

Units

Conditions

Min.

Max.

Comparison frequency

Equivalent phase noise at

phase detector

MHz

4

2148

dBc/Hz At 10kHz SSB with 2MHz comparison

from 4MHz crystal

RF division ratio

240

2

131071

320

Reference division ratio

Output Ports P0 and P1

Sink current

See Table 2

See Note 2

7,8

2

mA

V_PORT= 0·7V

Leakage current

µA

V_PORT= V_CC

10

NOTES

1. Reference output disabled by connecting to V_CCif required.

2. Output ports high impedance on power-up, with data, clock and enable at logic ‘0’.

Functional description

The SP5748 contains all the elements necessary, with the

exception of a frequency reference, loop filter and external

high voltage transistor, to control a varicap tuned local

oscillator, so forming a complete PLL frequency

synthesised source. The device allows for operation with

a high comparison frequency and is fabricated in high

speed logic, which enables the generation of a loop with

excellent phase noise performance, even with high

comparison frequencies.

The RF signal is fed to an internal preamplifier, which

provides gain and reverse isolation from the divider signals.

The output of the preamplifier is fed to the 17-bit fully

programmable counter, which is of MN+Aarchitecture. The

M counter is 13 bits and the A counter 4 bits.

The output of the programmable divider is fed to the phase

comparator where it is compared in both phase and

frequency domain with the comparison frequency. This

frequency is derived either from the on-chip crystal

controlled oscillator or from an external reference source.

In both cases the reference frequency is divided down to

the comparison frequency by the reference divider which

is programmable into1 of 16 ratios as described in Table 2.

The block diagram is shown in Figure 1 and packages

and pin allocations in Figure 2.

The SP5748 is controlled by a standard 3-wire bus

comprising data, clock and enable inputs. The

programming word contains 26 bits, two of which are used

for port selection, 17 to set the programmable divider ratio,

4 bits to select the reference division ratio (bits RD and

R0-R2, see Table 2), two bits to set charge pump current,

bits C0 and C1 (seeTable 1) and the remaining bit to access

test modes (bit T0, see Table 3)). The programming data

format is shown in Figure 4.

The output of the phase detector feeds the charge pump

and loop amplifier section, which when used with an

external high voltage transistor and loop fiIter integrates

the current pulses into the varactor line voltage. The charge

pump current setting is described in Table 1.

A buffered crystal reference frequency suitable for driving

further synthesisers is available from pin 9. If not required

The clock input is disabled by an enable low signal, data is

therefore only loaded into the internal shift registers during

an enable high and is clocked into the controlling buffers

by an enable high to low transition. This load is also

synchronised with the programmable divider so giving

smooth fine tuning.

this output can be disabled by connecting to V_CC

.

The programmable divider output divided by 2, f_PD/2 and

comparison frequency, f_COMP, can be switched to ports P0

and P1 respectively by switching the device into test mode.

The test modes are described in Table 3.

3

SP5748

j1

j0.5

j2

j0.2

j5

0.5

5

0.2

1

2

0

0·5GHz

1GHz

2j5

2j0.2

2·4GHz

S11: Z_O= 50Ω

2j2

2j0.5

Normalised to 50Ω

2j1

Figure 3 RF input impedance

CLOCK

ENABLE

DATA

2²⁵

P1

2²⁴

P0

2²³

T0

2²²

C1

2²¹

C0

2²⁰

R2

2¹⁹

R1

2¹⁸

R0

2¹⁷

RD

2¹⁶

MSB

2⁰

LSB

FREQUENCY

DATA

2¹⁶to 2⁰

Programmable divider ratio control bits

R2, R1, R0 Reference divider control bits (see Table 2)

RD

Reference divider mode select (see Table 2)

Port control bits (see Table 3)

Charge pump current bits (see Table 1)

Test mode enable bit

P1, P0

C1, C0

T0

Figure 4 Data format

C1

C0

Charge pump current (µA)

2

68p

150p

SP5748

0

1

0

1

0

1

6230

61000

6115

3

6500

Table 1 Charge pump current

Figure 5 Crystal oscillator application

4

SP5748

P2

Test mode description

P1

P0

RD R2 R1 R0

Division ratio

X

0

1

X

0

1

0

1

0

1

Normal operation

Charge pump sink

Charge pump source

Charge pump disable

Port P1= f_COMP, P0 = f_PD/2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Table 3 Test modes

300

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3

5

10

20

40

80

160

320

OPERATING WINDOW

40

30

Table 2 Reference divider control

10

80150

1000

2400

FREQUENCY (MHz)

Figure 6 Typical input sensitivity

1·6GHz

50-900MHz

38·9MHz

1650-2400MHz

2

SP5748

3

VCO

10n

10

3

Figure 7 Example of double conversion from VHF/UHF frequencies to TV IF

130V

68p

22k

18p

68p

112V

15n

13·3k

16k

47k

Optional application using

on-chip crystal controlled

oscillator

BCW31

2·2n

1

2

3

4

5

6

7

14

13

12

11

10

9

TUNER

REFERENCE

1n

OSCILLATOR

OUTPUT

ENABLE

DATA

SL

5748

15V

CONTROL

MICRO

CLOCK

8

P0

P1

Figure 8 Typical application of SP5748

5

SP5748

Applications

best performance will be achieved when the overall LO to

phase comparator division ratio is a minimum.

A generic set of Application Notes AN168 for designing

with synthesisers such as the SP5748 has been written,

covering aspects such as loop filter design and decoupling.

This application note is published on the Mitel

Semiconductor web site http:/www.Mitelsemi.com. A

generic test/demonstration board has been produced

which can be used for the SP5748; the circuit diagram is

shown in Figure 9, with component values in Table 4.

There are two ways of achieving a higher phase

comparator sampling frequency:

(1) Reduce the division ratio between the reference source

and the phase comparator

(2) use a higher reference source frequency.

Approach (2) may be preferred for best performance since

it is possible that the noise floor of the reference osciliator

may degrade the phase comparator performance if the

reference division ratio is very small.

The board can be used for the following purposes:

G Measuring RF sensitivity performance.

G Indicating port function.

G Synthesising the voltage controlled oscillator.

G Testing of external reference.

G Measurement of phase noise performance.

Loop bandwidth

The majority of applications for which the SP5748 is

intended require a loop filter bandwidth of between 2kHz

and10kHz.

Reference source

The SP5748 offers optimal LO phase noise performance

when operated with a large step size. This is due to the

fact that the LO phase comparator noise within the loop

bandwidth is:

Typically the VCO phase noise will be specified at both

1kHz and10kHz offset. It is common practice to arrange

the loop filter bandwidth such that the 1kHz figure lies within

the loop bandwidth. Thus the phase noise depends on the

synthesiser comparator noise floor, rather than the VCO.

LO frequency

Phase comparator frequency

120log₁₀

(

)

The 10kHz offset figure should depend on the VCO

providing the loop is designed correctly, and is not

underdamped.

Assuming the phase comparator noise floor is flat

irrespective of sampling frequency, this means that the

Component

Value/type

Component

Value/type

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

18pF

2·2nF

68pF

1nF

C20

C21

LED 1

LED 2

R1

R4

R6

R7

R8

1nF

HLMPK-150

4·7kΩ

1nF

10nF

100nF

4·7µF

100nF

10pF

1nF

100pF

4·7nF

100pF

4·7µF

10nF

39pF

100pF

4·7kΩ

13·3kΩ

22kΩ

R9

1kΩ

R10

R11

R12

R13

R14

S1

T1

VCO

X1

0Ω

16Ω

68Ω

SW DIP-2

BCW31

POS_2000

4MHz

Table 4 Component values for Figure 9

6

SP5748

Figure 9 SP5748 evaluation board

7

SP5748

Top view

Bottom view

Figure 10 SP5748 evaluation board layout

8

SP5748

V

CC

V

CC

500

CHARGE PUMP

RF

INPUTS

200

DRIVE

Figure 11b Loop amplifier

Figure 11a RF inputs

V

CC

PORT

25k

Figure 11c Enable, Data and Clock inputs

Figure 11d Output ports

V

CC

V

CC

CRYSTAL

REF

CRYSTAL CAP

1·2mA

Figure 11f Reference output

Figure 11e Reference oscillator

Figure 11 Input/output interface circuits

9


型号：	SP5748/KG/QP1T
厂家：	Microsemi
描述：	PLL Frequency Synthesizer, BIPolar, PDSO16, QP-16 光电二极管
文件：	总9页 (文件大小：125K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP5748/KG/QP1T [MICROSEMI]

相关型号：

SP5748GBK0AMMJ6R

SP5748GBK0AVKU6R

SP5748KG

SP5748KGMP1S

SP5748KGMP1T

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SP574BA

SP574BAP

SP574BB

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SP574BBP