SP5748 [MITEL]
2.4GHz Very Low Phase Noise PLL; 2.4GHz的超低相位噪声PLL
| 型号： | SP5748 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | 2.4GHz Very Low Phase Noise PLL |
| 文件： | 总15页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SP5748
2.4GHz Very Low Phase Noise PLL
Advance Information
DS4875 - 1.3 November 1998
The SP5748 is a single chip frequency synthesiser
designed for tuning systems up to 2.4 GHz and is
optimized for low phase noise with comparison
frequenciesupto4MHz.Itisdesignedtobedownwards
software compatible with the SP5658.
14
CHARGE PUMP
CRYSTAL CAP
CRYSTAL
ENABLE
DRIVE
VEE
RF INPUT
RF INPUT
VCC
The RF programmable divider contains a front end dual
modulus 16/17 functioning over the full operating range
and allows for coarse tuning in the upconverter
application and fine tuning in the downconverter.
DATA
CLOCK
REF
PORT P1/OC
PORT P0/OP
Comparison frequencies are obtained either from a
crystal controlled on-chip oscillator or from an external
source. a buffered reference frequency output is also
available to drive a second SP5748.
MP14
Figure1 Pin connections - top view
The device also contains 2 switching ports.
APPLICATIONS
FEATURES
● TV, VCR and Cable tuning systems
● Communications systems
● Complete 2.4 GHz single chip system
(for faster device refer to to SP5768)
● Optimised for low phase noise, with comparison
frequencies up to 4 MHz
ORDERING INFORMATION
● No RF prescaler
SP5748/KG/MP1S (Tubes)
SP5748/KG/MP1T (Tape and Reel)
● Selectable reference division ratio
● Reference frequency output
● Selectable charge pump current
● Integrated loop amplifier
● Two switching ports
● Low power replacement for SP5658 and 5668
● Downwards software compatible with SP5658
● ESD protection, (Normal ESD handling
procedures should be observed)
SP5748 Advance Information
REF
13 BIT
COUNT
REFERENCE
DIVIDER
CRYSTAL
16/17
RF INPUT
4 BIT
COUNT
PUMP
DRIVE
17 BIT LATCH
6 BIT LATCH
DATA
3 BIT
LATCH & PORT/
TEST MODE
INTERFACE
CLOCK
DATA
INTERFACE
ENABLE
PORT P0/OP PORT P1/OC
Figure 2 SP5748 block diagram
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V
Characteristic
Pin
Value
Typ
Units
Conditions
Min
Max
Supply current
10
13
mA
RF input frequency range 11,12
80
30
2400
300
MHz
RF input voltage
11,12
mV rms
RF input impedance
11,12
5,6,4
See Figure 3
Data, clock & enable
input high voltage
input low voltage
input current
3
0
-10
Vcc
0.7
10
V
V
µA
All input conditions
hysterysis
0.8
V
PP
2
SP5748 Advance Information
ELECTRICAL CHARACTERISTICS (continued)
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
TAMB = -40°C to 80°C, VCC =+ 4·5V to +5·5V
Characteristic
Pin
Value
Typ
Units
Conditions
Min
Max
Clock rate
6
500
kHz
Bus timing -
data set up
5,6,4
300
600
300
600
See Figure4
ns
ns
ns
ns
data hold
enable set up
enable hold
clock to enable
300
ns
Charge pump output
current
1
1
See Figure 5,
Vpin1 = 2V
Charge pump output
leakage
+-3
+-10
nA
Vpin1=2V
Charge pump drive
output current
14
2,3
0.5
mA
Vpin 14=0.7V
Crystal frequency
Recommended crystal
2
10
20
200
MHz
Ω
See Figure 6 for application
4 MHz parallel resonant
crystal. series resistance
o
Oscillator temperature
stability
TBC
TBC
20
ppm/ C
Oscillator supply voltage
stability
ppm/V
MHz
External reference input
frequency
2
2
2
Sinewave coupled through
TBA nF blocking capacitor
External reference drive
level
0.2
0.5
V
Sinewave coupled through
TBA nF blocking capacitor
pp
Buffered reference
frequency output *
output amplitude
output impedance
9
AC coupled
2-20MHz
0.35
TBC
Vpp
Ω
3
SP5748 Advance Information
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
TAMB = -40°C to 80°C, VCC = +4·5V to +5·5V
Characteristic
Pin
Value
Typ
Units
Conditions
Min
Max
Comparison frequency
4
MHz
Equivalent phase noise at
phase detector
-148
240
dBc/Hz @10 kHz, SSB, with 2 MHz
comparison from 4 MHz crystal
reference
RF division ratio
131071
Reference division ratio
see figure (7)
Output ports P0-P1#
sink current
7, 8
2
mA
Vport = 0.7V
leakage current
10
µA
Vport = Vcc
* Reference output disabled by connecting to Vcc if not required
’ Output ports high impedance on power up, with data, clock and enable at logic 0
4
SP5748 Advance Information
ABSOLUTE MAXIMUM RATINGS
All voltages are referred to VEE at 0V
Characteristic
Supply voltage, Vcc
RF input voltage
Pin
10
Min
Typ
Max
7
Units
Conditions
-0.3
V
11,12
11,12
7,8
2.5
V
Differential across pins
11 and 12
p-p
V
RF input DC offset
Port voltage
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
V
V
V
V
V
V
V
+0.3
cc
cc
cc
cc
cc
cc
cc
+0.3
+0.3
+0.3
+0.3
+0.3
+0.3
V
V
V
V
V
V
Charge pump DC offset
Varactor drive DC offset
Crystal DC offset
Buffered ref output
1
14
2,3
9
Data, clock & enable
DC offset
5,6,4
Storage temperature
Junction temperature
-55
+125
+150
°C
°C
MP14 thermal resistance,
chip to ambient
81
27
°C/W
°C/W
chip to case
Power consumption at
cc
TBC
mW
All ports off
V
=5.5V
ESD protection
2
kV
Mil-std 883B latest revision
method 3015 cat.1.
Functional description
The RF signal is fed to an internal preamplifier, which
provides gain and reverse isolation from the divider
signals. The output of the preamplifier is fed to the 17 bit
fully programmable counter, which is of MN+A
architecture. The M counter is 13 bit and the A counter
4
The output of the programmable counter is fed to the
phase comparator where it is compared in both phase
and frequency domain with the comparison frequency.
This frequency is derived either from the on board
crystal controlled oscillator or from an external
reference source. In both cases the reference
frequency is divided down to the comparison frequency
by the reference divider which is programmable into1 of
16 ratios as descried in Figure 7.
The SP5748 contains all the elements necessary, with
the exception of a frequency reference, loop filter and
external high voltage transistor, to control a varicap
tuned local oscillator, so forming a complete PLL
frequency synthesised source. The device allows for
operation with a high comparison frequency and is
fabricated in high speed logic, which enables the
generation of a loop with excellent phase noise
performance, even with high comparison frequencies.
ThepackageandpinallocationisshowninFigure1and
the block diagram in Figure 2.
The SP5748 is controlled by a standard 3-wire bus
comprising data, clock and enable inputs. The
programming word contains 26 bits, two of which are
used for port selection, 17 to set the programmable
divider ratio, four bits to select the reference division
ratio, bits RD & R0-R2, see Figure 7, two bits to set
charge pump current, bit C0 and C1, see Figure 5, and
the remaining bit to access test modes, bit T0, see
Figure 8. The programming format is shown in Figure 4.
Theoutputofthephasedetectorfeedsthechargepump
and loop amplifier section, which when used with an
external high voltage transistor and loop filter integrates
the current pulses into the varactor line voltage. The
charge pump current setting is described in Figure 5,
A buffered crystal reference frequency suitable for
driving further synthesisers is available from pin 9. If not
required this output can be disabled by connecting to
Vcc
The clock input is disabled by an enable low signal, data
is therefore only loaded into the internal shift registers
during an enable high and is clocked into the controlling
buffers by an enable high to low transition. This load is
also synchronised with the programmable divider so
giving smooth fine tuning.
The programmable divider output divided by 2, Fpd/2
and comparison frequency, Fcomp can be switched to
ports P0 and P1 respectively by switching the device
into test mode. The test modes are described in Figure
8.
5
SP5748 Advance Information
+j1
+j2
+j0.5
+j0.2
+j5
-j5
0
1
2
-j0.2
3
4
S11
: Zo = 50Ω
Frequency Markers at 500MHz,
1GHz, 1.5GHz and 2.4GHz
-j0.5
Normalised to 50Ω
-j2
-j1
Figure 3 RF input impedance
CLOCK
ENABLE
DATA
216
218
R0
217
RD
20
225
P1
224
P0
223
T0
222
C1
221
C0
220
R2
219
R1
MSB
LSB
Frequency data
TIMING DIAGRAM
TBC
2^16 to 2^0
R2,R1,R0
RD
:
:
:
:
:
:
Programmable divider ratio control bits
Reference divider control bits
Reference divider mode select
Port control bits
P1,P0
C1,C0
T0
Charge pump current select
Test mode enable
Figure 4 Data format
C1
0
C0
0
Current (in mA)
0.2
0.9
.1
0
1
1
0
1
1
.45
Figure 5 Charge pump current
6
SP5748 Advance Information
2
3
SP5748
Figure 6 Crystal oscillator application
RD
0
R2
0
R1
R0
RATIO
2
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
4
0
0
8
0
0
16
0
1
32
0
1
64
0
1
128
256
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
5
10
20
40
80
160
320
Figure 7 Reference division ratio
P1
X
0
P0
X
0
T0
0
FUNCTIONAL DESCRIPTION
Normal operation
1
Charge pump sink
0
1
1
Charge pump source
1
0
1
Charge pump disable
Port P1 = Fcomp, P0 = Fpd/1
1
1
1
X = don't care
Figure 8 Test modes
7
SP5748 Advance Information
300
VIN
(mV RMS
INTO 50Ω)
OPERATING
WINDOW
30
10
1000
2400
80
FREQUENCY (MHz)
Figure 9 Typical input sensitivity
1.6GHz
50 - 900MHz
38.9MHz
1650-2700MHz
1650 -2400MHz
2
3
VCO
VCO
3
10
10nF
Figure 10 Example of double conversion from VHF/UHF frequencies to TV IF
+5V
18pF
+30V
+12V
2
39pF
68pF
13k3
22k
3
15nF
4MHz
16k
47k
2n2
BCW31
Optional application utilising
on–board crystal controlled
oscillator
1
2
3
4
5
6
7
14
13
12
11
10
9
TUNER
1n
1n
REFERENCE
ENABLE
DATA
OSCILLATOR
OUTPUT
CONTROL
MICRO
CLOCK
10n
P1
8
P0
Figure 11 Typical application SP5748
8
SP5748 Advance Information
REFERENCE SOURCE
APPLICATION NOTES
The SP5748 offers optimal LO phase noise
performance when operated with a large step size. This
is due to the fact that the LO phase noise within the loop
bandwidth is:
A generic set of application notes AN168 for designing
withsynthesisers such as the SP5748 has been written.
This covers aspects such as loop filter design and
decoupling. Thisapplication note is also featured in the
Media Data Book, or refer to the Mitel Semiconductor
Internet Site http://www.Mitelsemi.com. A generic test/
demo board has been produced which can be used for
the SP5748. A circuit diagram is shown in Figure 12.
phase comparator
LO frequency
noise floor + 20 log10 phase comparator frequency
(
)
Assuming the phase comparator noise floor is flat
irrespective of sampling frequency, this means that the
best performance will be achieved when the overall LO
to phase comparator division ratio is a minimum.
The board can be used for the following purposes:
(A) Measuring RF sensitivity performance.
(B) Indicating port function.
There are two ways of achieving a higher phase
comparator sampling frequency:–
(C) Synthesising the voltage controlled oscillator.
(D) Testing of external reference.
A) Reduce the division ratio between the reference
source and the phase comparator
(E) Measurement of phase noise performance.
B) use a higher reference source frequency.
Approach B) may be preferred for best performance
since it is possible that the noise floor of the reference
oscillator may degrade the phase comparator
performance if the reference division ratio is very small.
LOOP BANDWIDTH
The majority of applications for which the SP5748 is
intended require a loop filter bandwidth of between
2kHz and10kHz.
Typically the VCO phase noise will be specified at both
1kHz and10kHz offset. It is common practice to arrange
the loop filter bandwidth such that the 1kHz figure lies
within the loop bandwidth. Thus the phase noise
depends on the synthesiser comparator noise floor,
rather than the VCO.
The 10kHz offset figure should depend on the VCO
providing the loop is designed correctly, and is not
underdamped.
9
SP5748 Advance Information
V T
R F O U T
8
2
2
1
W
10
SP5748 Advance Information
Top view
Bottom view
Figure 13
11
SP5748 Advance Information
V
REF
V
CC
500
500
CHARGE
PUMP
RF INPUTS
200
DRIVE
RF inputs
Loop amplifier
VCC
PORT
25K
BIAS
Disable, Enable, Data and Clock inputs
Output Ports
V
CC
V
CC
CRYSTAL
REF
CRYSTAL CAP
1.2mA
Reference output
Reference oscillator
Figure 14 Input/Output interface cicruits
12
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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