MV95308CMP [ZARLINK]
30MHz 8-BIT CMOS VIDEO DAC; 30MHz的8位CMOS视频DAC
| 型号： | MV95308CMP |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 30MHz 8-BIT CMOS VIDEO DAC |
| 文件： | 总9页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
JULY 1994
DS2431-2.1
MV95308
30MHz 8-BIT CMOS VIDEO DAC
The MV95308 is a CMOS 8-bit, 30MHz Digital to
Analog converter, designed for use in both video graphics
and general digital television applications.
20
19
BLANK
CLK
VDD
1
2
3
4
REFWHITE
0VERBR T
A very low external component count has been
achieved by including the loop amplifier and reference
voltage source on chip.
The device contains a data input register and registered
video controls (BLANK, REFWHITE, OVERBRT and SYNC).
These control inputs and associated internal circuitry allows
the MV95308 to be used in video graphics systems by
providing the necessary video pedestal levels. The STRDAC
input allows the video pedestals to be disabled in
conventional DAC applications.
MSB D 7
18
17
16
15
14
13
12
11
D6
D5
SYNC
STRDAC
IOUT
5
6
7
8
D4
D3
GND
IOUT
D2
D1
This device is capable of directly driving 75Ω lines with
standard RS-343A or RS-170 video levels, using the
RSET
VREF
9
LSB D0
DP20
MP20
10
appropriate R
external resistor.
SET
Pull up resistors have been added to tie all unused
control inputs into their inactive (High) states.
Fig.1 Pin connections - top view
FEATURES
APPLICATIONS
■ Low Power Consumption (180mW Typ)
■ 30MHz Pipeline Operation
■ ±1 LSB Differential Linearity Error
■ ±1 LSB Integral Linearity Error
■ RS-343A/RS-170 Compatible Levels
■ On Chip Reference Voltage Source
■ Guaranteed Monotonic
■ Data Conversion (general)
■ Computer Graphics
■ Waveform Synthesis
■ Consumer TV
■ Instrumentation
ABSOLUTE MAXIMUM RATINGS (Reference to GND)
DC Supply Voltage, V
Digital Input Voltage
-0.3 to +7V
■ Drives 75Ω Loads Directly
■ Single 5V Power Supply
DD
-0.3 to V +0.3V
DD
Analog Output Short Circuit Duration
Ambient Operating Temperature A grade -55°C to +125°C
Indefinite
ORDERING INFORMATION
MV95308 ADG (Military - Ceramic DIL Package)
MV95308 CDP (Commercial - Plastic DIL Package)
MV95308 CMP (Commercial - Miniature Plastic DIL
Package)
C grade
0°C to + 70°C
-55°C to +125°C
Storage Temperature Range
Fig.2 Block diagram of MV95308
MV95308
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated):
As specified in recommended operating conditions. Full temperature range: A grade = -55°C to +125°C, C grade = 0 to 70°C
DC CHARACTERISTICS
Temp
(°C)
Value
Typ.
Parameter
Symbol
Units
Conditions
Min.
Max.
Resolution
Full
8
Bits
Integral linearity error
Differential linearity error
Gain error
INL
25
±0.5
±0.5
±1%
LSB
LSB
LSB
LSB
Full
±1
DNL
25
Full
25
±1
±5%
%
Of full scale
Analog output
Grey scale current range
25
25
25
25
8.8
mA
255
27
10
276
100
21
7.5
255
92.5
LSB
LSB
IRE
LSB
IRE
LSB
IRE
LSB
IRE
LSB
IRE
LSB
mV
V
10% Over Bright level relative to
White level
26
275
20
28
277
22
White level relative to Blank level
Black level relative to Blank level
White level relative to Black level
Blank level
75Ω singly
terminated load
R
= 1.8kΩ
SET
(graphics mode)
25
25
107
-0.3
111
40
0
115
Sync level
LSB size
Output compliance
25
25
25
LSB
2.58
V
+1.5
OC
Digital inputs
High level I/P voltage
Low level I/P voltage
High level I/P current
Low level I/P current
V
V
25
25
25
25
3
V
+0.3
1.2
+1
-1
V
V
µA
µA
IH
DD
GND-0.3
IL
I
IH
I
IL
Internal voltage reference (V
)
V
25
Full
0.95
0.90
1.0
40
1.05
1.10
V
V
REF
REF
V
temperature coefficient
ppm/°C
REF
AC CHARACTERISTICS (Refer to Fig. 3)
Parameter Symbol
Max clock rate
Temp
(°C)
Value
Typ.
Units
Conditions
Min.
Max.
f
Full
30
MHz
maximum
guaranteed freq.
MAX
Clock high time
Clock low time
t
t
25
25
10
10
ns
ns
CLKH
CLKL
Data and control setup time
Data and control hold time
t
t
25
25
8
2
ns
ns
SU
H
Analog output delay
Analog output rise/fall time
Analog output settling time
Glitch energy
t
t
25
25
25
25
25
10
3
15
100
30
36
ns
ns
ns
pV-sec
mA
mA
DLY
6
RF
t
S
V
supply current
IDD
fc = 15MHz
fc = 30MHz
DD
THERMAL CHARACTERISTICS
RECOMMENDED OPERATING CONDITIONS
R
(I
and I
)
75Ω
5.0V ± 0.5V
1.8kΩ
Thermal Resistance
DP
20
75
MP
30
LOAD OUT
OUT
V
R
R
DD
Chip to case θ
°C/W
°C/W
jC
(graphics applications)
(straight DAC applications)
SET
SET
Chip to ambient θ
93
jA
1.2kΩ
2
MV95308
CIRCUIT DESCRIPTION
It also ensures synchronisation of the internal data and a
minimal output glitch energy.
The DAC employed by the MV95308 eliminates the need
for precision component ratios by using segmented architecture
As illustrated in the function block diagram, Fig. 2, the
MV95308 contains an 8-bit D-to-A converter, input registers,
a loop amplifier and a voltage reference.
On the falling edge of each clock cycle, as shown in Fig. 3,
eight data bits are latched into the device and passed to the
8-bit D-to-A converter. Also latched on the falling edge of the
clock signal, the SYNC and BLANK inputs add the
necessary weighted currents to the analog outputs to
produce the required output levels for use in video
applications. Table 1 details how the SYNC, BLANK,
REFWHITE and OVERBRT inputs modify the DAC output
levels.
To obtain a high data throughput rate, the decoding logic of
the MV95308 is fully pipelined. This introduces a one clock
cycle delay between the latching of the input data and the
resultant DAC output.
in which equal weight bit currents are either routed to I
or
OUT
I
. The use of identical current sources and current steering
OUT
their outputs means that monotonicity is guaranteed.
The MV95308 eliminates the need for an external voltage
reference by providing a nominally 1.0V reference on chip. An
on-chip loop amplifier also provides stability of the full scale
output current against power supply and temperature
variations. The full scale output current is set by an external
resistor R . By adjustment of this value it is possible to
SET
implement RS-343A or RS-170 video levels as explained in the
application notes.
Fig.3 Timing diagram
OUTPUT
DATA
I
OUT
(LSB)
Description
STRDAC
SYNC
BLANK
REFWHITE OVERBRT
REFWHITE + 10%
REFWHITE
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
X
X
414
387
387
FULL WHITE
$FF
DATA
OVERBRIGHT
DATA +
132 + 27
FULL BLACK
BLANK
1
1
1
1
0
1
1
0
0
X
1
0
1
0
1
1
X
1
1
X
1
$00
X
132
111
DATA-SYNC
SYNC
DATA
X
DATA + 21
0
X
1
X
X
STRDAC MODE
DATA
DATA
Table 1:Video output truth table
3
MV95308
Pin
Name
Description
2
CLK
The clock input. The falling edge of the clock latches the DATA, BLANK, SYNC, OVERBRT and
REFWHITE inputs into the logic pipeline. The decoded data will be latched into the DAC output 1
clock cycle later. The clock frequency determines the update rate of the DAC output.
3-10
D -D
The data inputs. D is the least significant bit (LSB). The coding is in straight binary only.
7
0
0
13,15
I
, I
The current output and its complement. These are the high impedance current source outputs of
the DAC capable of driving a 75Ω load up to a voltage of 1.5V.
OUT OUT
14
20
11
GND
Analog ground for the DAC.
Analog power for the DAC
V
DD
V
The output of the internal voltage reference generator. This output is nominally 1V, and
REF
should be decoupled with a 10nF capacitor.
12
R
The full scale adjust control. The R
resistor is connected from this pin to ground. An internal
SET
SET
loop amplifier adjusts a reference current flowing through the R
resistor so that the voltage
SET
across the resistor is equal to the V
16 LSB’s.
voltage. This reference current has a weighting equal to
REF
1
BLANK
SYNC
The composite blank control input. A logical zero on this input removes the Black pedestal
from the I output, whilst forcing the internal data to the DAC to $00. This input is latched on
the clock falling edge and will override the REFWHITE and OVERBRT inputs. The Black
pedestal is 7.5 IRE units (actually 21 LSB’s). If left open circuit this input is internally tied high.
OUT
17
The composite sync control input. A logical zero on this input removes the Blank pedestal
from the I
output. The Blank pedestal is nominally 40 IRE units (actually 111 LSB’s). The
OUT
SYNC input does not override any other control lines. This input is latched on the clock falling
edge. If left open circuit this input is internally tied high.
19
18
REFWHITE The reference white level control input. A logical zero on this input overrides the input data,
forcing the data to $FF. The BLANK input will override this input. If left open circuit this input is
internally tied high.
OVERBRT
The 10% overbright control input. A logical zero on this input switches the Overbright pedestal
into the I output. The Overbright pedestal is 10 IRE units (actually 27 LSB’s). This input does
OUT
not override any other input. The BLANK input overrides this input. If left open circuit this input is
internally tied high.
16
STRDAC
The straight DAC control input. A logical zero on this input causes the Black, Blank and
Overbright pedestals to be disabled, removing them from both I
and I
. This allows the
OUT
OUT
DAC contribution to the output to be extended to a full 1 Volt. To obtain this extra DAC range, it is
necessary to reduce the R resistor value, see application notes. The BLANK the REFWHITE
SET
inputs may still be used to force the input data to $00 or $FF respectively. With the STRDAC pin
held low the output current can be calculated from:
Output current = Data x 1 LSB
V
REF
Where 1 LSB=
16 x R
SET
Full scale = 255 LSB
V
= 1.0V typ.
REF
The exact value of 1 LSB must be calculated from the full scale output.
If left open circuit this input is internally tied high and the device will be configured for video graphics.
In this mode the output current can be calculated from:
Output current = (DATA + 21 + 111) x 1 LSB
V
= 1.0V typ.
REF
4
MV95308
PCB LAYOUT CONSIDERATIONS
APPLICATIONS INFORMATION
The PCB layout should provide low noise on the
MV95308 power and ground lines by shielding the digital
inputs and providing adequate decoupling. The PCB should
utilise both power and ground planes for best performance,
connecting both planes to their respective regular PCB
planes through a ferrite bead located as close as possible to
the device. For best performance, a 100nF capacitor should
be used to decouple the reference and supply pins.
Decoupling should take place as close to the device as
possible to reduce lead inductance. The digital inputs to the
device should be isolated as much as possible from the
analog outputs and other analog circuitry and should not
overlay the analog ground and power planes.
RS-343A and RS-170 Video Generation
For generation of RS-343A compatible video levels (see
Fig.4) it is recommended that a singly terminated 75Ω load
be used with an R
resistor value of approximately 1.82kΩ
SET
Similarly for the generation of RS-170 video levels a
singly terminated 75Ω load should be used but in association
with an R
value of approximately 1.29kΩ to provide the
SET
increased voltage range.
Non-Video Applications
The MV95308 may be used in non-video applications as
explained in the pin description for STRDAC mode.The
relationship between R
and the full scale output current
SET
To reduce noise pick-up, long clock lines to the device
should be avoided. For best performance the analog output
should have a 75Ω load connected to analog ground.
has been explained previously and for a singly terminated
75Ω load an R
resistor value of approximately 1.19kΩ
SET
should be used.
Fig.4 Composite video output waveform
Fig.5 Applications/test board
5
MV95308
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
• GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55
• ITALY Milan Tel: (02) 66040867 Fax: (02)66040993
Wiltshire, United Kingdom. SN2 2QW
Tel: (01793) 518000
• JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510
Fax: (01793) 518411
• NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023
• SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
• SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36
• TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
• UK, EIRE, DENMARK, FINLAND & NORWAY
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel (408) 438 2900
Swindon Tel: (01793) 518510 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1994 Publication No.DS2431 Issue No. 2.1 July 1994
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
Fax: (408) 438 5576
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The
Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not
constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such
information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
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TECHNICAL DOCUMENTATION - NOT FOR RESALE
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