X24320V14I-2.5T1 [XICOR]
EEPROM, 4KX8, Serial, CMOS, PDSO14, PLASTIC, TSSOP-14;型号: | X24320V14I-2.5T1 |
厂家: | XICOR INC. |
描述: | EEPROM, 4KX8, Serial, CMOS, PDSO14, PLASTIC, TSSOP-14 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
文件: | 总18页 (文件大小:484K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
32K
4Kx 8 Bit
X24320
400KHz 2-Wire Serial E2PROM with Block Lock™
DESCRIPTION
FEATURES
• Save Critical Data with Programmable Block
Lock Protection
The X24320 is a CMOS Serial E2PROM, internally
organized 4K x 8.The device features a serial interface
and software protocol allowing operation on a simple
two wire bus. The bus operates at 400 KHz all the way
down to 1.8V.
—Block lock (0, 1/4, 1/2, or all of E2PROM array)
—Software write protection
—Programmable hardware write protect
• In Circuit Programmable ROM Mode
• 400KHz 2-Wire Serial Interface
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
• Longer Battery Life With Lower Power
—Active read current less than 1mA
—Active write current less than 3mA
—Standby current less than 1µA
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Versions
Three device select inputs (S –S ) allow up to eight
0
2
devices to share a common two wire bus.
A Write Protect Register at the highest address location,
FFFFh, provides three write protection features: Software
Write Protect, Block Lock Protect, and Programmable
Hardware Write Protect. The Software Write Protect
feature prevents any nonvolatile writes to the device
until the WEL bit in the Write Protect Register is set.
The Block Lock Protection feature gives the user four
array block protect options, set by programming two bits
in the Write Protect Register. The Programmable Hard-
ware Write Protect feature allows the user to install the
• 32 Word Page Write Mode
—Minimizes total write time per word
• Internally Organized 4K x 8
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
—Typical write cycle time of 5ms
• High Reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• 8-Lead SOIC
device with WP tied to V , write to and Block Lock the
CC
desired portions of the memory array in circuit, and then
enable the In Circuit Programmable ROM Mode by pro-
gramming the WPEN bit HIGH in the Write Protect Reg-
ister. After this, the Block Locked portions of the array,
including the Write Protect Register itself, are perma-
nently protected from being erased.
Xicor E2PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
• 14-Lead TSSOP
—8-Lead PDIP
BLOCK DIAGRAM
Data Register
Serial E2PROM Data
and Address (SDA)
Y Decode Logic
Serial E2PROM
Command
SCL
Decode
and
Array
Page
Decode
Logic
4K x 8
Control
Logic
1K x 8
1K x 8
Block Lock and
Write Protect
Control Logic
S
S
S
2
1
0
Device
Select
Logic
Write
Protect
Register
2K x 8
Write Voltage
Control
WP
Xicor, Inc. 2000 Patents Pending
7035-1.2 11/4/03 EP
Characteristics subject to change without notice. 1 of 18
X24320
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN CONFIGURATION
8-Lead DIP/SOIC
The SCL input is used to clock all data into and out of
the device.
S
0
1
2
8
7
V
CC
S
S
1
2
WP
Serial Data (SDA)
X24320
3
4
6
5
SCL
SDA
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
V
SS
14-Lead TSSOP
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-up
resistor selection graph at the end of this data sheet.
S
0
14
1
V
CC
S
1
13
12
11
2
WP
NC
NC
NC
NC
NC
3
4
Device Select (S , S , S )
0
1
2
X24320
The device select inputs (S , S , S ) are used to set
0
1
2
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
10
9
5
6
NC
S
2
SCL
SDA
V
SS
7
8
statically they must be tied to V or V
as appropri-
SS
CC
ate. If actively driven, they must be driven with CMOS
levels (driven to V or V ).
CC
SS
DEVICE OPERATION
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write Pro-
tection is disabled. When this input is held HIGH, and
the WPEN bit in the Write Protect Register is set HIGH,
the Write Protect Register is protected, preventing
changes to the Block Lock Protection and WPEN bits.
PIN NAMES
Symbol
Description
Device Select Inputs
Serial Data
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
S , S , S
0
1
2
SDA
SCL
WP
Serial Clock
Write Protect
Ground
Start Condition
V
SS
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
V
Supply Voltage
No Connect
CC
NC
Characteristics subject to change without notice. 2 of 18
X24320
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Stop Condition
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent 8-bit word.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL From
Master
1
8
9
Data Output
From Transmitter
Data Output
From Receiver
START
Acknowledge
Characteristics subject to change without notice. 3 of 18
X24320
DEVICE ADDRESSING
Figure 4. Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing.The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S , S , and S . This allows up to 8
Device Type
Identifier
Device
Select
1
0
1
0
S
2
S
1
S
R/W
0
0
1
2
devices to share a single bus.These bits are compared
to the S , S , and S device select input pins. The last
SLAVE ADDRESS BYTE
0
1
2
bit of the Slave Address Byte defines the operation to
be performed. When the R/W bit is a one, then a read
operation is selected. When it is zero then a write oper-
ation is selected. Refer to figure 4. After loading the
Slave Address Byte from the SDA bus, the device com-
pares the device type bits with the value “1010” and the
device select bits with the status of the device select
input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and
the device returns to the standby mode.
High Order Word Address
0 A11 A10 A9 A8
0
0
0
X24320 WORD ADDRESS BYTE 1
Low Order Address
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word
Address Bytes as shown in Figure 4.
A7
A6
A4 A3
A2 A1
A0
A5
WORD ADDRESS BYTE 0
The internal organization of the E2 array is 128 pages
by 32 bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in
bits 7 through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See Figure 4.
D7 D6 D5
D4 D3
D2 D1 D0
DATA BYTE
Characteristics subject to change without notice. 4 of 18
X24320
WRITE OPERATIONS
Byte Write
operation after the first data word is transferred, the
master can transmit up to thirty-one more words. The
device will respond with an acknowledge after the
receipt of each word, and then the byte address is
internally incremented by one. The page address
remains constant. When the counter reaches the end
of the page, it “rolls over” and goes back to the first
byte of the current page. This means that the master
can write 32 words to the page beginning at any byte. If
the master begins writing at byte 16, and loads 32
words, then the first 16 words are written to bytes 16
through 31, and the last 16 words are written to bytes 0
through 15. Afterwards, the address counter would
point to byte 16. If the master writes more than 32
words, then the previously loaded data is overwritten
by the new data, one byte at a time.
For a write operation, the device requires the Slave
Address Byte, the Word Address Byte 1, and the Word
Address Byte 0, which gives the master access to any
one of the words in the array. Upon receipt of the Word
Address Byte 0, the device responds with an acknowl-
edge, and waits for the first eight bits of data. After
receiving the 8 bits of the data byte, the device again
responds with an acknowledge. The master then termi-
nates the transfer by generating a stop condition, at
which time the device begins the internal write cycle to
the nonvolatile memory. While the internal write cycle
is in progress the device inputs are disabled and the
device will not respond to any requests from the
master. The SDA pin is at high impedance. See
Figure 5.
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 6 for the address,
acknowledge, and data transfer sequence.
Page Write
The device is capable of a thirty-two byte page write
operation. It is initiated in the same manner as the byte
write operation; but instead of terminating the write
Figure 5. Byte Write Sequence
S
S
T
A
R
T
Word Address
Byte 1
Word Address
Byte 0
Signals From
The Master
Slave
Address
T
O
P
Data
SDA Bus
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 6. Page Write Sequence
(0 ≤ n ≤ 31)
S
T
A
R
T
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
Data
(n)
Signals From
The Master
Slave
Address
S
T
O
P
SDA Bus
1 0 1 0
S
0
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Characteristics subject to change without notice. 5 of 18
X24320
Acknowledge Polling
READ OPERATIONS
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 7.
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
Figure 7. Acknowledge Polling Sequence
Byte Load Completed
By Issuing STOP
Enter ACK Polling
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the eight bits of the Data Byte. The mas-
ter terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 8 for
the address, acknowledge, and data transfer
sequence.
Issue
START
Issue Slave
Address Byte
Issue STOP
(Read or Write)
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
ACK
Returned?
NO
YES
Figure 8. Current Address Read Sequence
HIGH
Voltage
Cycle Complete.
Continue
S
NO
Signals From
The Master
T
A
R
T
S
T
O
P
Slave
Address
Sequence?
SDA Bus
S 1 0 1 0
1
P
YES
A
C
K
Signals From
The Slave
Data
Continue Normal
Read or Write
Command Sequence
Issue STOP
PROCEED
Characteristics subject to change without notice. 6 of 18
X24320
Random Read
The next Current Address Read operation will read
from the newly loaded address.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues another
start condition and the Slave Address Byte with the R/W
bit set to one. This is followed by an acknowledge and
then eight bits of data from the device. The master ter-
minates the read operation by not responding with an
acknowledge and then issuing a stop condition. Refer
to figure 9 for the address, acknowledge, and data
transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
it requires additional data. The device continues to out-
put data for each acknowledge received. The master
terminates the read operation by not responding with
an acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h and the device continues to output data for each
acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the sec-
ond start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the address
counter, but no data is output by the device.
Figure 9. Random Read Sequence
S
S
T
A
R
T
A
R
Signals From
The Master
Word Address
Byte 1
Words Address
Byte 0
Slave
Address
S
T
O
P
Slave
Address
T
T
SDA Bus
1
S 1 0 1 0
0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Data
Figure 10. Sequential Read Sequence
Slave
Address
A
C
K
A
C
K
A
C
K
S
T
O
P
Signals From
The Master
SDA Bus
1
P
A
C
K
Signals From
The Slave
Data
(1)
Data
(2)
Data
(n–1)
Data
(n)
(n is any integer greater than 1)
Characteristics subject to change without notice. 7 of 18
X24320
WRITE PROTECT REGISTER (WPR)
Writing to the Write Protect Register
WPEN: Write Protect Enable Bit (Nonvolatile)
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Write Protect Register control
the Programmable Hardware Write Protection feature.
Hardware Write Protection is enabled when the WP pin
is HIGH and the WPEN bit is HIGH, and disabled when
either the WP pin is LOW or the WPEN bit is LOW. Fig-
ure 12 defines the write protect status for each combi-
nation of WPEN and WP. When the chip is Hardware
Write Protected, nonvolatile writes are disabled to the
Write Protect Register, including the Block Lock Pro-
tect bits and the WPEN bit itself, as well as to the Block
Lock protected sections in the memory array. Only the
sections of the memory array that are not Block Lock
protected, and the volatile bits WEL and RWEL, can be
written.
The Write Protect Register can only be modified by
performing a “Byte Write” operation directly to the
address FFFFh as described below.
The Data Byte must contain zeroes where indicated in
the procedural descriptions below; otherwise the oper-
ation will not be performed. Only one Data Byte is
allowed for each register write operation. The part will
not acknowledge any data bytes after the first byte is
entered. The user then has to issue a stop to initiate
the nonvolatile write cycle that writes BL0, BL1, and
WPEN to the nonvolatile bits. A stop must also be
issued after volatile register write operations to put the
device into Standby.
In Circuit Programmable ROM Mode
The state of the Write Protect Register can be read by
performing a random byte read at FFFFh at any time.
The part will reset itself after the first byte is read. The
master should supply a stop condition to be consistent
with the protocol, but a stop is not required to end this
operation. After the read, the address counter contains
0000h.
Note that when the WPEN bit is write protected, it can-
not be changed back to a LOW state; so write protec-
tion is enabled as long as the WP pin is held HIGH.
Thus an In Circuit Programmable ROM function can be
implemented by hardwiring the WP pin to V , writing
to and Block Locking the desired portion of the array to
be ROM, and then programming the WPEN bit HIGH.
CC
Write Protect Register: WPR (ADDR = FFFF )
h
Unused Bit Positions
7
6
5
4
3
2
1
0
Bits 0, 5 & 6 are not used. All writes to the WPR must
have zeros in these bit positions. The data byte output
during a WPR read will contain zeros in these bits.
WPEN
0
0
BL1 BL0
RWEL WEL
0
WEL: Write Enable Latch (Volatile)
0 = Write Enable Latch reset, writes disabled.
Writing to the WEL and RWEL Bits
WEL and RWEL are volatile latches that power up in
the LOW (disabled) state. While the WEL bit is LOW,
writes to any address other than FFFFh will be ignored
(no acknowledge will be issued after the Data Byte).
The WEL bit is set by writing 00000010 to address
FFFFh. Once set, WEL remains HIGH until either it is
reset to 0 (by writing 00000000 to FFFFh) or until the
part powers up again. Writes to WEL and RWEL do not
cause a nonvolatile write cycle, so the device is ready for
the next operation immediately after the stop condition.
1 = Write Enable Latch set, writes enabled.
RWEL: Register Write Enable Latch (Volatile)
0 = Register Write Enable Latch reset, writes to the
Write Protect Register disabled.
1 = Register Write Enable Latch set, writes to the
Write Protect Register enabled.
BL0, BL1: Block Lock Protect Bits (Nonvolatile)
The Block Lock Protect Bits, BL0 and BL1, determine
which blocks of the array are protected. A write to a
protected block of memory is ignored, but will receive
an acknowledge. The master must issue a stop to put
the part into standby, just as it would for a valid write;
but the stop will not initiate an internal nonvolatile write
cycle. See Figure 11.
The RWEL bit controls writes to the Block Lock Protect
bits, BL0 and BL1, and the WPEN bit. If RWEL is 0
then no writes can be performed on BL0, BL1, or
WPEN. RWEL is reset when the device powers up or
after any nonvolatile write, including writes to the Block
Lock Protect bits, WPEN bit, or any bytes in the memory
Characteristics subject to change without notice. 8 of 18
X24320
array. When RWEL is set, WEL cannot be reset, nor
can RWEL and WEL be reset in one write operation.
RWEL can be reset by writing 00000010 to FFFFh; but
this is the same operation as in step 3 described
below, and will result in programing BL0, BL1, and
WPEN.
RWEL is reset to zero in step 3 so that user is required
to perform steps 2 and 3 to make another change.
RWEL must be 0 in step 3. If the RWEL bit in the data
byte for step 3 is a one, then no changes are made to
the Write Protect Register and the device remains at
step 2.
The WP pin must be LOW or the WPEN bit must be
LOW before a nonvolatile register write operation is ini-
tiated. Otherwise, the write operation will abort and the
device will go into standby mode after the master
issues the stop condition in step 3.
Writing to the BL and WPEN Bits
A 3 step sequence is required to change the nonvola-
tile Block Lock Protect or Write Protect Enable bits:
1) Set WEL=1, Write 00000010 to address FFFFh
(Volatile Write Cycle.)
Step 3 is a nonvolatile write operation, requiring t
to
WC
complete (acknowledge polling may be used to reduce
this time requirement). It should be noted that step 3
MUST end with a stop condition. If a start condition is
issued during or at the end of step 3 (instead of a stop
condition) the device will abort the nonvolatile register
write and remain at step 2. If the operation is aborted
with a start condition, the master must issue a stop to
put the device into standby mode.
2) Set RWEL=1, Write 00000110 to address FFFFh
(Volatile Write Cycle.)
3) Set BL1, BL0, and/or WPEN bits, Write u00xy010 to
address FFFFh, where u=WPEN, x=BL1, and
y=BL0. (Nonvolatile Write Cycle.)
The three step sequence was created to make it diffi-
cult to change the contents of the Write Protect Regis-
ter accidentally. If WEL was set to one by a previous
register write operation, the user may start at step 2.
Block Lock Protect Bits and Protected Addresses
BL1
BL0
Protected Addresses
Array Location
No Protect
Upper 1/4
0
0
1
1
0
1
0
1
None
C00h - FFFh
800h - FFFh
000h - FFFh
Upper 1/2
Full Array
WP Pin and WPEN Bit Functionality
Memory Array Not
Memory Array Block
WP
0
WPEN
Lock Block Protected
Lock Protected
Block Lock Bits
WPEN Bit
Unprotected
Unprotected
Protected
X
0
1
Writable
Protected
Unprotected
Unprotected
Protected
X
Writable
Protected
1
Writable
Protected
Characteristics subject to change without notice. 9 of 18
X24320
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under Bias, X24320..........–65 to +135°C
Storage temperature ...............................–6 to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Voltage on any pin with respect to V .......–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X24320
Limits
4.5V to 5.5V
2.5V to 5.5V
1.8V to 3.6V
–40°C
X24320–2.5
X24320–1.8
D.C. OPERATING CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Max.
Units
mA
Test Conditions
I
I
V
V
Supply Current (Read)
Supply Current (Write)
1
3
SCL = V
X 0.1/V X 0.9 Levels
CC1
CC2
CC
CC CC
@ 400KHz, SDA = Open, All Other
Inputs = V or V – 0.3V
mA
CC
SS
CC
(1)
I
I
V
Standby Current
Standby Current
5
1
µA
µA
SCL = SDA = V , All Other Inputs =
CC
SB1
SB2
CC
CC
V
or V – 0.3V, V = 5V 10%
SS
CC CC
(1)
V
SCL = SDA = V , All Other Inputs =
CC
V
or V – 0.3V, V = 2.5V
CC CC
SS
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
= V to V
CC
LI
IN
SS
I
V
= V to V
SS
CC
LO
OUT
(2)
V
–0.5
V
x 0.3
lL
CC
(2)
V
Input HIGH Voltage
Output LOW Voltage
V
x 0.7
CC
V
+ 0.5
V
IH
CC
V
0.4
V
I
= 3mA
OL
OL
(3)
V
Hysteresis of Schmitt Trigger
Inputs
V
x 0.05
V
hys
CC
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Max.
Units
pF
Test Conditions
(3)
C
Input/Output Capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
I/O
(3)
C
Input Capacitance (S , S , S , SCL, WP)
pF
V
IN
IN
0
1
2
Notes: (1) Must perform a stop command prior to measurement.
(2) V min. and V max. are for reference only and are not 100% tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 10 of 18
X24320
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
Input rise and fall times
Input and output timing levels
10ns
V
X 0.5
1.53KΩ
CC
Output
100pF
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
Symbol
Parameter
Min.
0
Max.
Units
KHz
ns
f
SCL Clock Frequency
400
SCL
t
Noise Suppression Time
50
I
Constant at SCL, SDA Inputs
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
t
0.1
1.2
0.6
1.2
0.6
0.6
0
0.9
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
AA
t
BUF
t
t
HD:STA
t
Clock LOW Period
LOW
t
Clock HIGH Period
HIGH
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
SU:STA
HD:DAT
t
t
Data In Setup Time
100
SU:DAT
t
SDA and SCL Rise Time
300
300
R
t
SDA and SCL Fall Time
F
t
Stop Condition Setup Time
Data Out Hold Time
0.6
50
SU:STO
t
300
DH
(4)
t
Output Fall Time
20+0.1C
OF
b
Notes: (4) Cb = Total capacitance of one bus line in pF
POWER-UP TIMING(5)
Symbol
Parameter
Max.
Units
t
Power-up to Read Operation
Power-up to Write Operation
1
5
ms
ms
PUR
t
PUW
Notes: (5) t
and t
are the delays required from the time V is stable until the specified operation can be initiated. These parameters
CC
PUR
PUW
are periodically sampled and not 100% tested.
Characteristics subject to change without notice. 11 of 18
X24320
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
SU:STO
t
HD:STA
HD:DAT
SU:DAT
SU:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(6)
Max.
Units
(7)
t
Write Cycle Time
5
10
ms
WC
Notes: (6) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(7) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WR
time the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X24320 bus interface circuits are disabled, SDA is allowed to remain HIGH, and
the device does not respond to its slave address.
Bus Timing
SCL
ACK
SDA
8th Bit
Word n
t
WC
STOP
Condition
START
Condition
Characteristics subject to change without notice. 12 of 18
X24320
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
120
Must be
steady
Will be
steady
VCC MAX
RMIN
=
=1.8KΩ
IOL MIN
100
80
May change
from Low to
High
Will change
from Low to
High
tR
RMAX
Max.
=
CBUS
May change
from High to
Low
Will change
from High to
Low
60
Resistance
40
20
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
Min.
Resistance
N/A
Center Line
is High
Impedance
0
20
40
60
80
0
100
120
Bus Capacitance (Pf)
Characteristics subject to change without notice. 13 of 18
X24320
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 14 of 18
X24320
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050"Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 15 of 18
X24320
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 16 of 18
X24320
Ordering Information
X24320
X
X
-X
V
Range
Device
CC
Blank = 5V 10%
2.5 = 2.5V to 5.5V
1.8 = 1.8V to 3.6V
Temperature Range
Blank = 0 to +70°C
I = –40 to +85°C
Package
X24320
S8 = 8-Lead SOIC
V14 = 14-Lead TSSOP
P = 8-Lead PDIP
Characteristics subject to change without notice. 17 of 18
X24320
Part Mark Convention
X24320
X
X
Blank = 8-Lead SOIC
V = 14-Lead TSSOP
P = 8-Lead PDIP
Blank = 4.5V to 5.5V, 0 to +70°C
I = 4.5V to 5.5V, –40 to +85°C
AE = 2.5V to 5.5V, 0 to +70°C
AF = 2.5V to 5.5V, –40 to +85°C
AG = 1.8V to 3.6V, 0 to +70°C
AH = 1.8V to 3.6V, –40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 18 of 18
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