X24321S8 [XICOR]
400 KHz 2-Wire Serial E2PROM; 400 KHz的2线串行E2PROM
| 型号： | X24321S8 |
| 厂家： | 
XICOR INC. |
| 描述： | 400 KHz 2-Wire Serial E2PROM |
| 文件： | 总13页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32K
4K x 8 Bit
X24321
2
400 KHz 2-Wire Serial E PROM
FEATURES
DESCRIPTION
2
The X24321 is a CMOS Serial E PROM Memory,
internally organized 4K x 8. The device features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus. The bus operates at
400KHz all the way down to 1.8V.
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Operation
• Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• 400KHz Fast Mode 2-Wire Serial Interface
—Down to 1.8V
Three device select inputs (S –S ) allow up to eight
devices to share a common two wire bus.
0
2
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
Hardware Write Protection is provided through a Write
Protect (WP) input pin on the X24321. When the WP
pin is HIGH, the upper quadrant of the Serial E PROM
2
• Internally Organized 4K x 8 Bit
• 32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
• Hardware Write Protect
array is protected against any nonvolatile write
attempts.
2
Xicor Serial E PROM Memories are designed and
tested for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
—Typical Write Cycle Time of 5ms
• High Reliability
—Endurance: 1,000,000 Cycles
—Data Retention: 100Years
• 8-Lead SOIC
FUNCTIONAL DIAGRAM
DATA REGISTER
Y DECODE LOGIC
SERIAL E2PROM DATA
AND ADDRESS (SDA)
COMMAND
DECODE
SCL
PAGE
DECODE
LOGIC
AND
CONTROL
LOGIC
E2PROM
ARRAY
4K x 8
S2
DEVICE
SELECT
LOGIC
WRITE
PROTECT
LOGIC
S1
S0
WRITE VOLTAGE
CONTROL
WP
7040 FM 01
Xicor, 1995, 1996 Patents Pending
7040 3/27/97 T0/C0/D0 SH
Characteristics subject to change without notice
1
X24321
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN NAMES
Symbol
Description
Device Select Inputs
Serial Data
The SCL input is used to clock all data into and out of
the device.
S0, S1, S2
SDA
Serial Data (SDA)
SCL
Serial Clock
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
WP
Write Protect
Ground
VSS
VCC
Supply Voltage
7040 FRM T01
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
PIN CONFIGURATION
8-LEAD SOIC
Device Select (S , S , S )
0
1
2
S
S
S
1
2
8
7
V
CC
0
1
2
The device select inputs (S , S , S ) are used to set
0
1
2
WP
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
X24321
3
4
6
5
SCL
SDA
V
SS
statically they must be tied to V or V
priate. If actively driven, they must be driven with
CMOS levels.
as appro-
SS
CC
7040 FM 02
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write
Protection is disabled and the device can be written
normally. When this input is held HIGH, Write Protec-
tion is enabled, and nonvolatile writes are disabled to
2
the upper quadrant of the E PROM array.
2
X24321
DEVICE OPERATION
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
The device supports a bidirectional, bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data trans-
fers, and provide the clock for both transmit and
receive operations. Therefore, the device will be
considered a slave in all applications.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
7040 FM 03
Figure 2. Definition of Start and Stop
SCL
SDA
STARTBIT
STOP BIT
7040 FM 04
3
X24321
Stop Condition
The device will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a Write Operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
7040 FM 05
4
X24321
DEVICE ADDRESSING
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
device select bits S , S , and S . This allows up to 8
0
1
2
devices to share a single bus. These bits are
compared to the S , S , and S device select input
0
1
2
2
The internal organization of the E PROM array is 128
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a Read Operation is selected. When it is zero
then a Write Operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
pages by 32 bytes per page. The page address is
partially contained in the Address Byte 1 and partially in
bits 7 through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Refer to figure 4.
Figure 4. Device Addressing
DEVICE TYPE
IDENTIFIER
DEVICE
SELECT
1
0
1
0
S
2
S
1
S
R/W
0
SLAVE ADDRESS BYTE
HIGH ORDER ADDRESS
0
0
0
A0
A11 A10 A9
A8
ADDRESS BYTE 1
LOW ORDER ADDRESS
A7
A6
A4 A3
A2 A1
A0
A5
ADDRESS BYTE 0
D7 D6 D5
D4 D3
D2 D1 D0
DATA BYTE
7040 FM 06
5
X24321
WRITE OPERATIONS
Byte Write
Page Write Operation
The device executes a thirty-two byte Page Write
Operation. For a Page Write Operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the page to be written. Upon receipt of Address
Byte 0, the device responds with an acknowledge, and
waits for the first eight bits of data. After receiving the 8
bits of the first data byte, the device again responds
with an acknowledge. The device will respond with an
acknowledge after the receipt of each of 31 more
bytes. Each time the byte address is internally incre-
mented by one, while page address remains constant.
When the counter reaches the end of the page, the
master terminates the data loading by issuing a stop
condition, which causes the device to begin the
nonvolatile write cycle. All inputs are disabled until
completion of the nonvolatile write cycle. The SDA pin
is at high impedance. Refer to figure 5 for the address,
acknowledge, and data transfer sequence.
For a Byte Write Operation, the device requires the
Slave Address Byte, the Word Address Byte 1, and the
Word Address Byte 0, which gives the master access to
any one of the bytes in the array. Upon receipt of the
Word Address Byte 0, the device responds with an
acknowledge, and waits for the first eight bits of data.
After receiving the 8 bits of the data byte, the device
again responds with an acknowledge. The master then
terminates the transfer by generating a stop condition,
at which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write cycle
is in progress the device inputs are disabled and the
device will not respond to any requests from the master.
The SDA pin is at high impedance. See figure 4.
Figure 4. Byte Write Sequence
S
SIGNALS
FROMTHE
MASTER
S
T
A
R
T
WORDADDRESS WORD ADDRESS
BYTE 1
SLAVE
ADDRESS
T
O
P
BYTE 0
DATA
SDA BUS
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROMTHE
SLAVE
7040 FM 07
Figure 5. Page Write Sequence
S
SIGNALS
WORDADDRESS WORD ADDRESS
BYTE 1
S
T
SLAVE
FROMTHE
T
A
ADDRESS
BYTE 0
DATA
MASTER
O
P
R
T
SDA BUS
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROMTHE
SLAVE
7040 FM 07
6
X24321
READ OPERATIONS
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the
nonvolatile write cycle, then no ACK will be returned. If
the device has completed the nonvolatile write opera-
tion, an ACK will be returned and the host can then
proceed with the read or write operation. Refer to
figure 6.
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last byte read or written,
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address of the same page.
Figure 6. Acknowledge Polling Sequence
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the byte at the current address. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 7 for
the address, acknowledge, and data transfer
sequence.
ISSUE
START
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
ISSUE SLAVE
ADDRESS BYTE
(READ OR PROGRAM)
ISSUE STOP
ACK
RETURNED?
NO
YES
Figure 7. Current Address Read Sequence
S
SIGNALS
FROM THE
MASTER
T
A
R
T
S
T
NONVOLATILE
WRITE
SLAVE
NO
ADDRESS
O
P
CYCLE COMPLETE.
CONTINUE
SEQUENCE?
SDA BUS
S 1 0 1 0
1
P
A
C
K
SIGNALS
FROM THE
SLAVE
YES
DATA
CONTINUE NORMAL
READ OR PROGRAM
COMMAND SEQUENCE
7040 FM 10
ISSUE STOP
PROCEED
7040 FM 09
7
X24321
Random Read
The next Current Address Read operation will read
from the newly loaded address.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues Address Byte 1, receives
another acknowledge, then issues Address Byte 0
containing the address of the byte to be read. After the
device acknowledges receipt of Address Byte 0, the
master issues another start condition and the Slave
Address Byte with the R/W bit set to one. This is
followed by an acknowledge and then eight bits of data
from the device. The master terminates the read oper-
ation by not responding with an acknowledge and then
issuing a stop condition. Refer to figure 8 for the
address, acknowledge, and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first byte is trans-
mitted as with the other modes; however, the master
now responds with an acknowledge, indicating it
requires additional data. The device continues to
output data for each acknowledge received. The
master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all byte
addresses, allowing the entire memory contents to be
read during one operation. At the end of the address
space the counter “rolls over” to address 0000h and the
device continues to output data for each acknowledge
received. Refer to figure 9 for the acknowledge and data
transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the
second start shown in figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the
address counter, but no data is output by the device.
Figure 8. Random Read Sequence
S
S
SIGNALS
FROMTHE
MASTER
T
A
R
T
A
R
ADDRESS
BYTE 1
ADDRESS
BYTE 0
SLAVE
ADDRESS
S
T
O
P
SLAVE
ADDRESS
T
T
1
SDA BUS
S 1 0 1 0
0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROMTHE
SLAVE
DATA
7040 FM 11
Figure 9. Sequential Read Sequence
SIGNALS
FROM THE
MASTER
A
C
K
A
C
K
A
C
K
S
T
O
P
SLAVE
ADDRESS
SDA BUS
1
P
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
(1)
DATA
(2)
DATA
(n–1)
DATA
(n)
7040 FM 12
8
X24321
*COMMENT
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
X24321.......................................–65°C to +135°C
Storage Temperature........................–65°C to +150°C
Voltage on any Pin with
Respect to V ....................................–1V to +7V
SS
D.C. Output Current ..............................................5mA
Lead Temperature
(Soldering, 10 seconds) ..............................300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X24321
Limits
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
4.5V to 5.5V
2.5V to 5.5V
1.8V to 3.6V
X24321–2.5
X24321–1.8
–40°C
7040 FRM T04
7040 FRM T05
D.C. OPERATING CHARACTERISTICS
Limits
Symbol
ICC1
Parameter
Min.
Max.
Units
Test Conditions
VCC Supply Current (Read)
1
3
mA SCL = VCC X 0.1/VCC X 0.9 Levels
@ 400KHz, SDA = Open, All Other
ICC2
VCC Supply Current
(Write)
mA
Inputs = V or VCC – 0.3V
SS
(1)
ISB1
VCC Standby Current
3
1
µA
µA
SCL = SDA = VCC – 0.3V,
All Other Inputs = V or VCC – 0.3V,
SS
V
CC = 5V ± 10%
SCL = SDA = VCC – 0.1V,
All Other Inputs = V or VCC – 0.1V,
(1)
ISB2
VCC Standby Current
SS
VCC = 1.8V
ILI
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
VIN = V to VCC
SS
ILO
VOUT = V to VCC
SS
(2)
VlL
–0.5
VCC x 0.3
VCC + 0.5
0.4
(2)
VIH
Input HIGH Voltage
Output LOW Voltage
VCC x 0.7
V
VOL
V
IOL = 3mA
(3)
Vhys
Hysteresis of Schmitt
Trigger Inputs
VCC x 0.05
V
7040 FRM T06.1
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
pF
Test Conditions
(3)
CI/O
Input/Output Capacitance (SDA)
8
6
VI/O = 0V
VIN = 0V
(3)
CIN
Input Capacitance (S0, S1, S2, SCL,WP)
pF
7040 FRM T07
Notes: (1) Must perform a stop command prior to measurement.
(2) V min. and V max. are for reference only and are not 100% tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
9
X24321
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
10ns
5V
Input Rise and
Fall Times
1.53KΩ
Input and Output
Timing Levels
OUTPUT
VCC X 0.5
7040 FRM T08
100pF
7040 FM 13
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Program Cycle Limits
Symbol
fSCL
Parameter
SCL Clock Frequency
Min.
0
Max.
Units
KHz
ns
400
TI
Noise Suppression Time
50
Constant at SCL, SDA Inputs
(6)
tAA
SCL LOW to SDA Data Out Valid
0.1
1.2
0.9
µs
µs
tBUF
Time the Bus Must Be Free Before a
New Transmission Can Start
tHD:STA
tLOW
Start Condition Hold Time
Clock LOW Period
0.6
1.2
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock HIGH Period
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
tR
Data In Hold Time
0
100
µs
ns
ns
ns
µs
ns
Data In Setup Time
(5)
(5)
20+0.1XCb
20+0.1XCb
0.6
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Output Fall Time
300
300
tF
tSU:STO
tDH
50
(5)
tOF
20 + 0.1Cb
250
ns
7040 FRM T09
(4)
POWER-UP TIMING
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
5
tPUW
ms
7040 FRM T10
Notes: (4)
t
and t
are the delays required from the time V is stable until the specified operation can be initiated.These parameters
PUW CC
PUR
are periodically sampled and not 100% tested.
(5) C = total capacitance of one bus line in pF
b
(6) t = 1.1µs Max below V = 2.5V.
AA
CC
10
X24321
Bus Timing
t
t
t
t
HIGH
LOW
R
F
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
7040 FM 14
Program Cycle Limits
Symbol
(7)
Parameter
Min.
Typ.
Max.
Units
ms
(8)
TWR
Program Cycle Time
5
10
7040 FRM T11
Notes: (7) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(8) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WR
time the device requires to automatically complete the nonvolatile write operation.
The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal
erase/program cycle. During the program cycle, the X24321 bus interface circuits are disabled, SDA is allowed to
remain HIGH, and the device does not respond to its slave address.
Bus Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
STOP
CONDITION
START
CONDITION
7040 FM 15
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
CC MAX
R
=
=1.8KΩ
Must be
steady
Will be
steady
MIN
I
100
80
OL MIN
t
R
R
=
May change
from Low to
High
Will change
from Low to
High
MAX
C
BUS
MAX.
60
40
20
0
RESISTANCE
May change
from High to
Low
Will change
from High to
Low
MIN.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
RESISTANCE
20 40 60 80
0
100 120
N/A
Center Line
is High
Impedance
BUS CAPACITANCE (pF)
7040 FM 16
7040 FM 17
11
X24321
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45°
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
7040 FM 19
12
X24321
ORDERING INFORMATION
X24321
X
X
-X
V
Range
Device
CC
Blank = 5V ±10%
2.5 = 2.5V to 5.5V
1.8 = 1.8V to 3.6V
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
Package
X24321
S8= 8-Lead SOIC
Part Mark Convention
X24321
Blank = 8-Lead SOIC
X
X
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
AE = 2.5V to 5.5V, 0°C to +70°C
AF = 2.5V to 5.5V, –40°C to +85°C
AG = 1.8V to 3.6V, 0°C to +70°C
AH = 1.8V to 3.6V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
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